src/gallium/drivers/radeonsi/si_perfcounter.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *  Nicolai Hähnle <nicolai.haehnle@amd.com>
  25  *
  26  */
  27
  28 #include "radeon/r600_cs.h"
  29 #include "radeon/r600_query.h"
  30 #include "radeon/r600_pipe_common.h"
  31 #include "util/u_memory.h"
  32
  33 #include "si_pipe.h"
  34 #include "sid.h"
  35
  36 enum si_pc_reg_layout {
  37         /* All secondary selector dwords follow as one block after the primary
  38          * selector dwords for the counters that have secondary selectors.
  39          */
  40         SI_PC_MULTI_BLOCK = 0,
  41
  42         /* Each secondary selector dword follows immediately afters the
  43          * corresponding primary.
  44          */
  45         SI_PC_MULTI_ALTERNATE = 1,
  46
  47         /* All secondary selector dwords follow as one block after all primary
  48          * selector dwords.
  49          */
  50         SI_PC_MULTI_TAIL = 2,
  51
  52         /* Free-form arrangement of selector registers. */
  53         SI_PC_MULTI_CUSTOM = 3,
  54
  55         SI_PC_MULTI_MASK = 3,
  56
  57         /* Registers are laid out in decreasing rather than increasing order. */
  58         SI_PC_REG_REVERSE = 4,
  59
  60         SI_PC_FAKE = 8,
  61 };
  62
  63 struct si_pc_block_base {
  64         const char *name;
  65         unsigned num_counters;
  66         unsigned flags;
  67
  68         unsigned select_or;
  69         unsigned select0;
  70         unsigned counter0_lo;
  71         unsigned *select;
  72         unsigned *counters;
  73         unsigned num_multi;
  74         unsigned num_prelude;
  75         unsigned layout;
  76 };
  77
  78 struct si_pc_block {
  79         struct si_pc_block_base *b;
  80         unsigned selectors;
  81         unsigned instances;
  82 };
  83
  84 /* The order is chosen to be compatible with GPUPerfStudio's hardcoding of
  85  * performance counter group IDs.
  86  */
  87 static const char * const si_pc_shader_type_suffixes[] = {
  88         "", "_ES", "_GS", "_VS", "_PS", "_LS", "_HS", "_CS"
  89 };
  90
  91 static const unsigned si_pc_shader_type_bits[] = {
  92         0x7f,
  93         S_036780_ES_EN(1),
  94         S_036780_GS_EN(1),
  95         S_036780_VS_EN(1),
  96         S_036780_PS_EN(1),
  97         S_036780_LS_EN(1),
  98         S_036780_HS_EN(1),
  99         S_036780_CS_EN(1),
 100 };
 101
 102 static struct si_pc_block_base cik_CB = {
 103         .name = "CB",
 104         .num_counters = 4,
 105         .flags = R600_PC_BLOCK_SE | R600_PC_BLOCK_INSTANCE_GROUPS,
 106
 107         .select0 = R_037000_CB_PERFCOUNTER_FILTER,
 108         .counter0_lo = R_035018_CB_PERFCOUNTER0_LO,
 109         .num_multi = 1,
 110         .num_prelude = 1,
 111         .layout = SI_PC_MULTI_ALTERNATE,
 112 };
 113
 114 static unsigned cik_CPC_select[] = {
 115         R_036024_CPC_PERFCOUNTER0_SELECT,
 116         R_036010_CPC_PERFCOUNTER0_SELECT1,
 117         R_03600C_CPC_PERFCOUNTER1_SELECT,
 118 };
 119 static struct si_pc_block_base cik_CPC = {
 120         .name = "CPC",
 121         .num_counters = 2,
 122
 123         .select = cik_CPC_select,
 124         .counter0_lo = R_034018_CPC_PERFCOUNTER0_LO,
 125         .num_multi = 1,
 126         .layout = SI_PC_MULTI_CUSTOM | SI_PC_REG_REVERSE,
 127 };
 128
 129 static struct si_pc_block_base cik_CPF = {
 130         .name = "CPF",
 131         .num_counters = 2,
 132
 133         .select0 = R_03601C_CPF_PERFCOUNTER0_SELECT,
 134         .counter0_lo = R_034028_CPF_PERFCOUNTER0_LO,
 135         .num_multi = 1,
 136         .layout = SI_PC_MULTI_ALTERNATE | SI_PC_REG_REVERSE,
 137 };
 138
 139 static struct si_pc_block_base cik_CPG = {
 140         .name = "CPG",
 141         .num_counters = 2,
 142
 143         .select0 = R_036008_CPG_PERFCOUNTER0_SELECT,
 144         .counter0_lo = R_034008_CPG_PERFCOUNTER0_LO,
 145         .num_multi = 1,
 146         .layout = SI_PC_MULTI_ALTERNATE | SI_PC_REG_REVERSE,
 147 };
 148
 149 static struct si_pc_block_base cik_DB = {
 150         .name = "DB",
 151         .num_counters = 4,
 152         .flags = R600_PC_BLOCK_SE | R600_PC_BLOCK_INSTANCE_GROUPS,
 153
 154         .select0 = R_037100_DB_PERFCOUNTER0_SELECT,
 155         .counter0_lo = R_035100_DB_PERFCOUNTER0_LO,
 156         .num_multi = 3, // really only 2, but there's a gap between registers
 157         .layout = SI_PC_MULTI_ALTERNATE,
 158 };
 159
 160 static struct si_pc_block_base cik_GDS = {
 161         .name = "GDS",
 162         .num_counters = 4,
 163
 164         .select0 = R_036A00_GDS_PERFCOUNTER0_SELECT,
 165         .counter0_lo = R_034A00_GDS_PERFCOUNTER0_LO,
 166         .num_multi = 1,
 167         .layout = SI_PC_MULTI_TAIL,
 168 };
 169
 170 static unsigned cik_GRBM_counters[] = {
 171         R_034100_GRBM_PERFCOUNTER0_LO,
 172         R_03410C_GRBM_PERFCOUNTER1_LO,
 173 };
 174 static struct si_pc_block_base cik_GRBM = {
 175         .name = "GRBM",
 176         .num_counters = 2,
 177
 178         .select0 = R_036100_GRBM_PERFCOUNTER0_SELECT,
 179         .counters = cik_GRBM_counters,
 180 };
 181
 182 static struct si_pc_block_base cik_GRBMSE = {
 183         .name = "GRBMSE",
 184         .num_counters = 4,
 185
 186         .select0 = R_036108_GRBM_SE0_PERFCOUNTER_SELECT,
 187         .counter0_lo = R_034114_GRBM_SE0_PERFCOUNTER_LO,
 188 };
 189
 190 static struct si_pc_block_base cik_IA = {
 191         .name = "IA",
 192         .num_counters = 4,
 193
 194         .select0 = R_036210_IA_PERFCOUNTER0_SELECT,
 195         .counter0_lo = R_034220_IA_PERFCOUNTER0_LO,
 196         .num_multi = 1,
 197         .layout = SI_PC_MULTI_TAIL,
 198 };
 199
 200 static struct si_pc_block_base cik_PA_SC = {
 201         .name = "PA_SC",
 202         .num_counters = 8,
 203         .flags = R600_PC_BLOCK_SE,
 204
 205         .select0 = R_036500_PA_SC_PERFCOUNTER0_SELECT,
 206         .counter0_lo = R_034500_PA_SC_PERFCOUNTER0_LO,
 207         .num_multi = 1,
 208         .layout = SI_PC_MULTI_ALTERNATE,
 209 };
 210
 211 static struct si_pc_block_base cik_PA_SU = {
 212         .name = "PA_SU",
 213         .num_counters = 4,
 214         .flags = R600_PC_BLOCK_SE,
 215
 216         .select0 = R_036400_PA_SU_PERFCOUNTER0_SELECT,
 217         .counter0_lo = R_034400_PA_SU_PERFCOUNTER0_LO,
 218         .num_multi = 2,
 219         .layout = SI_PC_MULTI_ALTERNATE,
 220 };
 221
 222 static struct si_pc_block_base cik_SPI = {
 223         .name = "SPI",
 224         .num_counters = 6,
 225         .flags = R600_PC_BLOCK_SE,
 226
 227         .select0 = R_036600_SPI_PERFCOUNTER0_SELECT,
 228         .counter0_lo = R_034604_SPI_PERFCOUNTER0_LO,
 229         .num_multi = 4,
 230         .layout = SI_PC_MULTI_BLOCK,
 231 };
 232
 233 static struct si_pc_block_base cik_SQ = {
 234         .name = "SQ",
 235         .num_counters = 16,
 236         .flags = R600_PC_BLOCK_SE | R600_PC_BLOCK_SHADER,
 237
 238         .select0 = R_036700_SQ_PERFCOUNTER0_SELECT,
 239         .select_or = S_036700_SQC_BANK_MASK(15) |
 240                         S_036700_SQC_CLIENT_MASK(15) |
 241                         S_036700_SIMD_MASK(15),
 242         .counter0_lo = R_034700_SQ_PERFCOUNTER0_LO,
 243 };
 244
 245 static struct si_pc_block_base cik_SX = {
 246         .name = "SX",
 247         .num_counters = 4,
 248         .flags = R600_PC_BLOCK_SE,
 249
 250         .select0 = R_036900_SX_PERFCOUNTER0_SELECT,
 251         .counter0_lo = R_034900_SX_PERFCOUNTER0_LO,
 252         .num_multi = 2,
 253         .layout = SI_PC_MULTI_TAIL,
 254 };
 255
 256 static struct si_pc_block_base cik_TA = {
 257         .name = "TA",
 258         .num_counters = 2,
 259         .flags = R600_PC_BLOCK_SE | R600_PC_BLOCK_INSTANCE_GROUPS | R600_PC_BLOCK_SHADER_WINDOWED,
 260
 261         .select0 = R_036B00_TA_PERFCOUNTER0_SELECT,
 262         .counter0_lo = R_034B00_TA_PERFCOUNTER0_LO,
 263         .num_multi = 1,
 264         .layout = SI_PC_MULTI_ALTERNATE,
 265 };
 266
 267 static struct si_pc_block_base cik_TD = {
 268         .name = "TD",
 269         .num_counters = 2,
 270         .flags = R600_PC_BLOCK_SE | R600_PC_BLOCK_INSTANCE_GROUPS | R600_PC_BLOCK_SHADER_WINDOWED,
 271
 272         .select0 = R_036C00_TD_PERFCOUNTER0_SELECT,
 273         .counter0_lo = R_034C00_TD_PERFCOUNTER0_LO,
 274         .num_multi = 1,
 275         .layout = SI_PC_MULTI_ALTERNATE,
 276 };
 277
 278 static struct si_pc_block_base cik_TCA = {
 279         .name = "TCA",
 280         .num_counters = 4,
 281         .flags = R600_PC_BLOCK_INSTANCE_GROUPS,
 282
 283         .select0 = R_036E40_TCA_PERFCOUNTER0_SELECT,
 284         .counter0_lo = R_034E40_TCA_PERFCOUNTER0_LO,
 285         .num_multi = 2,
 286         .layout = SI_PC_MULTI_ALTERNATE,
 287 };
 288
 289 static struct si_pc_block_base cik_TCC = {
 290         .name = "TCC",
 291         .num_counters = 4,
 292         .flags = R600_PC_BLOCK_INSTANCE_GROUPS,
 293
 294         .select0 = R_036E00_TCC_PERFCOUNTER0_SELECT,
 295         .counter0_lo = R_034E00_TCC_PERFCOUNTER0_LO,
 296         .num_multi = 2,
 297         .layout = SI_PC_MULTI_ALTERNATE,
 298 };
 299
 300 static struct si_pc_block_base cik_TCP = {
 301         .name = "TCP",
 302         .num_counters = 4,
 303         .flags = R600_PC_BLOCK_SE | R600_PC_BLOCK_INSTANCE_GROUPS | R600_PC_BLOCK_SHADER_WINDOWED,
 304
 305         .select0 = R_036D00_TCP_PERFCOUNTER0_SELECT,
 306         .counter0_lo = R_034D00_TCP_PERFCOUNTER0_LO,
 307         .num_multi = 2,
 308         .layout = SI_PC_MULTI_ALTERNATE,
 309 };
 310
 311 static struct si_pc_block_base cik_VGT = {
 312         .name = "VGT",
 313         .num_counters = 4,
 314         .flags = R600_PC_BLOCK_SE,
 315
 316         .select0 = R_036230_VGT_PERFCOUNTER0_SELECT,
 317         .counter0_lo = R_034240_VGT_PERFCOUNTER0_LO,
 318         .num_multi = 1,
 319         .layout = SI_PC_MULTI_TAIL,
 320 };
 321
 322 static struct si_pc_block_base cik_WD = {
 323         .name = "WD",
 324         .num_counters = 4,
 325
 326         .select0 = R_036200_WD_PERFCOUNTER0_SELECT,
 327         .counter0_lo = R_034200_WD_PERFCOUNTER0_LO,
 328 };
 329
 330 static struct si_pc_block_base cik_MC = {
 331         .name = "MC",
 332         .num_counters = 4,
 333
 334         .layout = SI_PC_FAKE,
 335 };
 336
 337 static struct si_pc_block_base cik_SRBM = {
 338         .name = "SRBM",
 339         .num_counters = 2,
 340
 341         .layout = SI_PC_FAKE,
 342 };
 343
 344 /* Both the number of instances and selectors varies between chips of the same
 345  * class. We only differentiate by class here and simply expose the maximum
 346  * number over all chips in a class.
 347  *
 348  * Unfortunately, GPUPerfStudio uses the order of performance counter groups
 349  * blindly once it believes it has identified the hardware, so the order of
 350  * blocks here matters.
 351  */
 352 static struct si_pc_block groups_CIK[] = {
 353         { &cik_CB, 226, 4 },
 354         { &cik_CPF, 17 },
 355         { &cik_DB, 257, 4 },
 356         { &cik_GRBM, 34 },
 357         { &cik_GRBMSE, 15 },
 358         { &cik_PA_SU, 153 },
 359         { &cik_PA_SC, 395 },
 360         { &cik_SPI, 186 },
 361         { &cik_SQ, 252 },
 362         { &cik_SX, 32 },
 363         { &cik_TA, 111, 11 },
 364         { &cik_TCA, 39, 2 },
 365         { &cik_TCC, 160, 16 },
 366         { &cik_TD, 55, 11 },
 367         { &cik_TCP, 154, 11 },
 368         { &cik_GDS, 121 },
 369         { &cik_VGT, 140 },
 370         { &cik_IA, 22 },
 371         { &cik_MC, 22 },
 372         { &cik_SRBM, 19 },
 373         { &cik_WD, 22 },
 374         { &cik_CPG, 46 },
 375         { &cik_CPC, 22 },
 376
 377 };
 378
 379 static struct si_pc_block groups_VI[] = {
 380         { &cik_CB, 396, 4 },
 381         { &cik_CPF, 19 },
 382         { &cik_DB, 257, 4 },
 383         { &cik_GRBM, 34 },
 384         { &cik_GRBMSE, 15 },
 385         { &cik_PA_SU, 153 },
 386         { &cik_PA_SC, 397 },
 387         { &cik_SPI, 197 },
 388         { &cik_SQ, 273 },
 389         { &cik_SX, 34 },
 390         { &cik_TA, 119, 16 },
 391         { &cik_TCA, 35, 2 },
 392         { &cik_TCC, 192, 16 },
 393         { &cik_TD, 55, 16 },
 394         { &cik_TCP, 180, 16 },
 395         { &cik_GDS, 121 },
 396         { &cik_VGT, 147 },
 397         { &cik_IA, 24 },
 398         { &cik_MC, 22 },
 399         { &cik_SRBM, 27 },
 400         { &cik_WD, 37 },
 401         { &cik_CPG, 48 },
 402         { &cik_CPC, 24 },
 403
 404 };
 405
 406 static void si_pc_get_size(struct r600_perfcounter_block *group,
 407                         unsigned count, unsigned *selectors,
 408                         unsigned *num_select_dw, unsigned *num_read_dw)
 409 {
 410         struct si_pc_block *sigroup = (struct si_pc_block *)group->data;
 411         struct si_pc_block_base *regs = sigroup->b;
 412         unsigned layout_multi = regs->layout & SI_PC_MULTI_MASK;
 413
 414         if (regs->layout & SI_PC_FAKE) {
 415                 *num_select_dw = 0;
 416         } else if (layout_multi == SI_PC_MULTI_BLOCK) {
 417                 if (count < regs->num_multi)
 418                         *num_select_dw = 2 * (count + 2) + regs->num_prelude;
 419                 else
 420                         *num_select_dw = 2 + count + regs->num_multi + regs->num_prelude;
 421         } else if (layout_multi == SI_PC_MULTI_TAIL) {
 422                 *num_select_dw = 4 + count + MIN2(count, regs->num_multi) + regs->num_prelude;
 423         } else if (layout_multi == SI_PC_MULTI_CUSTOM) {
 424                 assert(regs->num_prelude == 0);
 425                 *num_select_dw = 3 * (count + MIN2(count, regs->num_multi));
 426         } else {
 427                 assert(layout_multi == SI_PC_MULTI_ALTERNATE);
 428
 429                 *num_select_dw = 2 + count + MIN2(count, regs->num_multi) + regs->num_prelude;
 430         }
 431
 432         *num_read_dw = 6 * count;
 433 }
 434
 435 static void si_pc_emit_instance(struct r600_common_context *ctx,
 436                                 int se, int instance)
 437 {
 438         struct radeon_winsys_cs *cs = ctx->gfx.cs;
 439         unsigned value = S_030800_SH_BROADCAST_WRITES(1);
 440
 441         if (se >= 0) {
 442                 value |= S_030800_SE_INDEX(se);
 443         } else {
 444                 value |= S_030800_SE_BROADCAST_WRITES(1);
 445         }
 446
 447         if (instance >= 0) {
 448                 value |= S_030800_INSTANCE_INDEX(instance);
 449         } else {
 450                 value |= S_030800_INSTANCE_BROADCAST_WRITES(1);
 451         }
 452
 453         radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, value);
 454 }
 455
 456 static void si_pc_emit_shaders(struct r600_common_context *ctx,
 457                                unsigned shaders)
 458 {
 459         struct radeon_winsys_cs *cs = ctx->gfx.cs;
 460
 461         radeon_set_uconfig_reg_seq(cs, R_036780_SQ_PERFCOUNTER_CTRL, 2);
 462         radeon_emit(cs, shaders & 0x7f);
 463         radeon_emit(cs, 0xffffffff);
 464 }
 465
 466 static void si_pc_emit_select(struct r600_common_context *ctx,
 467                         struct r600_perfcounter_block *group,
 468                         unsigned count, unsigned *selectors)
 469 {
 470         struct si_pc_block *sigroup = (struct si_pc_block *)group->data;
 471         struct si_pc_block_base *regs = sigroup->b;
 472         struct radeon_winsys_cs *cs = ctx->gfx.cs;
 473         unsigned idx;
 474         unsigned layout_multi = regs->layout & SI_PC_MULTI_MASK;
 475         unsigned dw;
 476
 477         assert(count <= regs->num_counters);
 478
 479         if (regs->layout & SI_PC_FAKE)
 480                 return;
 481
 482         if (layout_multi == SI_PC_MULTI_BLOCK) {
 483                 assert(!(regs->layout & SI_PC_REG_REVERSE));
 484
 485                 dw = count + regs->num_prelude;
 486                 if (count >= regs->num_multi)
 487                         dw += regs->num_multi;
 488                 radeon_set_uconfig_reg_seq(cs, regs->select0, dw);
 489                 for (idx = 0; idx < regs->num_prelude; ++idx)
 490                         radeon_emit(cs, 0);
 491                 for (idx = 0; idx < MIN2(count, regs->num_multi); ++idx)
 492                         radeon_emit(cs, selectors[idx] | regs->select_or);
 493
 494                 if (count < regs->num_multi) {
 495                         unsigned select1 =
 496                                 regs->select0 + 4 * regs->num_multi;
 497                         radeon_set_uconfig_reg_seq(cs, select1, count);
 498                 }
 499
 500                 for (idx = 0; idx < MIN2(count, regs->num_multi); ++idx)
 501                         radeon_emit(cs, 0);
 502
 503                 if (count > regs->num_multi) {
 504                         for (idx = regs->num_multi; idx < count; ++idx)
 505                                 radeon_emit(cs, selectors[idx] | regs->select_or);
 506                 }
 507         } else if (layout_multi == SI_PC_MULTI_TAIL) {
 508                 unsigned select1, select1_count;
 509
 510                 assert(!(regs->layout & SI_PC_REG_REVERSE));
 511
 512                 radeon_set_uconfig_reg_seq(cs, regs->select0, count + regs->num_prelude);
 513                 for (idx = 0; idx < regs->num_prelude; ++idx)
 514                         radeon_emit(cs, 0);
 515                 for (idx = 0; idx < count; ++idx)
 516                         radeon_emit(cs, selectors[idx] | regs->select_or);
 517
 518                 select1 = regs->select0 + 4 * regs->num_counters;
 519                 select1_count = MIN2(count, regs->num_multi);
 520                 radeon_set_uconfig_reg_seq(cs, select1, select1_count);
 521                 for (idx = 0; idx < select1_count; ++idx)
 522                         radeon_emit(cs, 0);
 523         } else if (layout_multi == SI_PC_MULTI_CUSTOM) {
 524                 unsigned *reg = regs->select;
 525                 for (idx = 0; idx < count; ++idx) {
 526                         radeon_set_uconfig_reg(cs, *reg++, selectors[idx] | regs->select_or);
 527                         if (idx < regs->num_multi)
 528                                 radeon_set_uconfig_reg(cs, *reg++, 0);
 529                 }
 530         } else {
 531                 assert(layout_multi == SI_PC_MULTI_ALTERNATE);
 532
 533                 unsigned reg_base = regs->select0;
 534                 unsigned reg_count = count + MIN2(count, regs->num_multi);
 535                 reg_count += regs->num_prelude;
 536
 537                 if (!(regs->layout & SI_PC_REG_REVERSE)) {
 538                         radeon_set_uconfig_reg_seq(cs, reg_base, reg_count);
 539
 540                         for (idx = 0; idx < regs->num_prelude; ++idx)
 541                                 radeon_emit(cs, 0);
 542                         for (idx = 0; idx < count; ++idx) {
 543                                 radeon_emit(cs, selectors[idx] | regs->select_or);
 544                                 if (idx < regs->num_multi)
 545                                         radeon_emit(cs, 0);
 546                         }
 547                 } else {
 548                         reg_base -= (reg_count - 1) * 4;
 549                         radeon_set_uconfig_reg_seq(cs, reg_base, reg_count);
 550
 551                         for (idx = count; idx > 0; --idx) {
 552                                 if (idx <= regs->num_multi)
 553                                         radeon_emit(cs, 0);
 554                                 radeon_emit(cs, selectors[idx - 1] | regs->select_or);
 555                         }
 556                         for (idx = 0; idx < regs->num_prelude; ++idx)
 557                                 radeon_emit(cs, 0);
 558                 }
 559         }
 560 }
 561
 562 static void si_pc_emit_start(struct r600_common_context *ctx,
 563                              struct r600_resource *buffer, uint64_t va)
 564 {
 565         struct radeon_winsys_cs *cs = ctx->gfx.cs;
 566
 567         radeon_add_to_buffer_list(ctx, &ctx->gfx, buffer,
 568                                   RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
 569
 570         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
 571         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
 572                         COPY_DATA_DST_SEL(COPY_DATA_MEM));
 573         radeon_emit(cs, 1); /* immediate */
 574         radeon_emit(cs, 0); /* unused */
 575         radeon_emit(cs, va);
 576         radeon_emit(cs, va >> 32);
 577
 578         radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
 579                                S_036020_PERFMON_STATE(V_036020_DISABLE_AND_RESET));
 580         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 581         radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PERFCOUNTER_START) | EVENT_INDEX(0));
 582         radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
 583                                S_036020_PERFMON_STATE(V_036020_START_COUNTING));
 584 }
 585
 586 /* Note: The buffer was already added in si_pc_emit_start, so we don't have to
 587  * do it again in here. */
 588 static void si_pc_emit_stop(struct r600_common_context *ctx,
 589                             struct r600_resource *buffer, uint64_t va)
 590 {
 591         struct radeon_winsys_cs *cs = ctx->gfx.cs;
 592
 593         if (ctx->screen->chip_class == CIK) {
 594                 /* Workaround for cache flush problems: send two EOP events. */
 595                 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
 596                 radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) |
 597                                 EVENT_INDEX(5));
 598                 radeon_emit(cs, va);
 599                 radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
 600                 radeon_emit(cs, 0); /* immediate data */
 601                 radeon_emit(cs, 0); /* unused */
 602         }
 603
 604         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
 605         radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) |
 606                         EVENT_INDEX(5));
 607         radeon_emit(cs, va);
 608         radeon_emit(cs, (va >> 32) | EOP_DATA_SEL(1));
 609         radeon_emit(cs, 0); /* immediate data */
 610         radeon_emit(cs, 0); /* unused */
 611
 612         radeon_emit(cs, PKT3(PKT3_WAIT_REG_MEM, 5, 0));
 613         radeon_emit(cs, WAIT_REG_MEM_EQUAL | WAIT_REG_MEM_MEM_SPACE(1));
 614         radeon_emit(cs, va);
 615         radeon_emit(cs, va >> 32);
 616         radeon_emit(cs, 0); /* reference value */
 617         radeon_emit(cs, 0xffffffff); /* mask */
 618         radeon_emit(cs, 4); /* poll interval */
 619
 620         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 621         radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PERFCOUNTER_SAMPLE) | EVENT_INDEX(0));
 622         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 623         radeon_emit(cs, EVENT_TYPE(EVENT_TYPE_PERFCOUNTER_STOP) | EVENT_INDEX(0));
 624         radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
 625                                S_036020_PERFMON_STATE(V_036020_STOP_COUNTING) |
 626                                S_036020_PERFMON_SAMPLE_ENABLE(1));
 627 }
 628
 629 static void si_pc_emit_read(struct r600_common_context *ctx,
 630                             struct r600_perfcounter_block *group,
 631                             unsigned count, unsigned *selectors,
 632                             struct r600_resource *buffer, uint64_t va)
 633 {
 634         struct si_pc_block *sigroup = (struct si_pc_block *)group->data;
 635         struct si_pc_block_base *regs = sigroup->b;
 636         struct radeon_winsys_cs *cs = ctx->gfx.cs;
 637         unsigned idx;
 638         unsigned reg = regs->counter0_lo;
 639         unsigned reg_delta = 8;
 640
 641         if (!(regs->layout & SI_PC_FAKE)) {
 642                 if (regs->layout & SI_PC_REG_REVERSE)
 643                         reg_delta = -reg_delta;
 644
 645                 for (idx = 0; idx < count; ++idx) {
 646                         if (regs->counters)
 647                                 reg = regs->counters[idx];
 648
 649                         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
 650                         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_PERF) |
 651                                         COPY_DATA_DST_SEL(COPY_DATA_MEM));
 652                         radeon_emit(cs, reg >> 2);
 653                         radeon_emit(cs, 0); /* unused */
 654                         radeon_emit(cs, va);
 655                         radeon_emit(cs, va >> 32);
 656                         va += 4;
 657                         reg += reg_delta;
 658                 }
 659         } else {
 660                 for (idx = 0; idx < count; ++idx) {
 661                         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
 662                         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
 663                                         COPY_DATA_DST_SEL(COPY_DATA_MEM));
 664                         radeon_emit(cs, 0); /* immediate */
 665                         radeon_emit(cs, 0); /* unused */
 666                         radeon_emit(cs, va);
 667                         radeon_emit(cs, va >> 32);
 668                         va += 4;
 669                 }
 670         }
 671 }
 672
 673 static void si_pc_cleanup(struct r600_common_screen *rscreen)
 674 {
 675         r600_perfcounters_do_destroy(rscreen->perfcounters);
 676         rscreen->perfcounters = NULL;
 677 }
 678
 679 void si_init_perfcounters(struct si_screen *screen)
 680 {
 681         struct r600_perfcounters *pc;
 682         struct si_pc_block *blocks;
 683         unsigned num_blocks;
 684         unsigned i;
 685
 686         switch (screen->b.chip_class) {
 687         case CIK:
 688                 blocks = groups_CIK;
 689                 num_blocks = ARRAY_SIZE(groups_CIK);
 690                 break;
 691         case VI:
 692                 blocks = groups_VI;
 693                 num_blocks = ARRAY_SIZE(groups_VI);
 694                 break;
 695         case SI:
 696         default:
 697                 return; /* not implemented */
 698         }
 699
 700         if (screen->b.info.max_sh_per_se != 1) {
 701                 /* This should not happen on non-SI chips. */
 702                 fprintf(stderr, "si_init_perfcounters: max_sh_per_se = %d not "
 703                         "supported (inaccurate performance counters)\n",
 704                         screen->b.info.max_sh_per_se);
 705         }
 706
 707         pc = CALLOC_STRUCT(r600_perfcounters);
 708         if (!pc)
 709                 return;
 710
 711         pc->num_start_cs_dwords = 14;
 712         pc->num_stop_cs_dwords = 20;
 713         pc->num_instance_cs_dwords = 3;
 714         pc->num_shaders_cs_dwords = 4;
 715
 716         if (screen->b.chip_class == CIK) {
 717                 pc->num_stop_cs_dwords += 6;
 718         }
 719
 720         pc->num_shader_types = ARRAY_SIZE(si_pc_shader_type_bits);
 721         pc->shader_type_suffixes = si_pc_shader_type_suffixes;
 722         pc->shader_type_bits = si_pc_shader_type_bits;
 723
 724         pc->get_size = si_pc_get_size;
 725         pc->emit_instance = si_pc_emit_instance;
 726         pc->emit_shaders = si_pc_emit_shaders;
 727         pc->emit_select = si_pc_emit_select;
 728         pc->emit_start = si_pc_emit_start;
 729         pc->emit_stop = si_pc_emit_stop;
 730         pc->emit_read = si_pc_emit_read;
 731         pc->cleanup = si_pc_cleanup;
 732
 733         if (!r600_perfcounters_init(pc, num_blocks))
 734                 goto error;
 735
 736         for (i = 0; i < num_blocks; ++i) {
 737                 struct si_pc_block *block = &blocks[i];
 738                 unsigned instances = block->instances;
 739
 740                 if (!strcmp(block->b->name, "IA")) {
 741                         if (screen->b.info.max_se > 2)
 742                                 instances = 2;
 743                 }
 744
 745                 r600_perfcounters_add_block(&screen->b, pc,
 746                                             block->b->name,
 747                                             block->b->flags,
 748                                             block->b->num_counters,
 749                                             block->selectors,
 750                                             instances,
 751                                             block);
 752         }
 753
 754         screen->b.perfcounters = pc;
 755         return;
 756
 757 error:
 758         r600_perfcounters_do_destroy(pc);
 759 }