src/gallium/drivers/radeonsi/si_perfcounter.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  */
  24
  25 #include "radeon/r600_cs.h"
  26 #include "radeon/r600_query.h"
  27 #include "util/u_memory.h"
  28
  29 #include "si_pipe.h"
  30 #include "sid.h"
  31
  32 enum si_pc_reg_layout {
  33         /* All secondary selector dwords follow as one block after the primary
  34          * selector dwords for the counters that have secondary selectors.
  35          */
  36         SI_PC_MULTI_BLOCK = 0,
  37
  38         /* Each secondary selector dword follows immediately afters the
  39          * corresponding primary.
  40          */
  41         SI_PC_MULTI_ALTERNATE = 1,
  42
  43         /* All secondary selector dwords follow as one block after all primary
  44          * selector dwords.
  45          */
  46         SI_PC_MULTI_TAIL = 2,
  47
  48         /* Free-form arrangement of selector registers. */
  49         SI_PC_MULTI_CUSTOM = 3,
  50
  51         SI_PC_MULTI_MASK = 3,
  52
  53         /* Registers are laid out in decreasing rather than increasing order. */
  54         SI_PC_REG_REVERSE = 4,
  55
  56         SI_PC_FAKE = 8,
  57 };
  58
  59 struct si_pc_block_base {
  60         const char *name;
  61         unsigned num_counters;
  62         unsigned flags;
  63
  64         unsigned select_or;
  65         unsigned select0;
  66         unsigned counter0_lo;
  67         unsigned *select;
  68         unsigned *counters;
  69         unsigned num_multi;
  70         unsigned num_prelude;
  71         unsigned layout;
  72 };
  73
  74 struct si_pc_block {
  75         struct si_pc_block_base *b;
  76         unsigned selectors;
  77         unsigned instances;
  78 };
  79
  80 /* The order is chosen to be compatible with GPUPerfStudio's hardcoding of
  81  * performance counter group IDs.
  82  */
  83 static const char * const si_pc_shader_type_suffixes[] = {
  84         "", "_ES", "_GS", "_VS", "_PS", "_LS", "_HS", "_CS"
  85 };
  86
  87 static const unsigned si_pc_shader_type_bits[] = {
  88         0x7f,
  89         S_036780_ES_EN(1),
  90         S_036780_GS_EN(1),
  91         S_036780_VS_EN(1),
  92         S_036780_PS_EN(1),
  93         S_036780_LS_EN(1),
  94         S_036780_HS_EN(1),
  95         S_036780_CS_EN(1),
  96 };
  97
  98 static struct si_pc_block_base cik_CB = {
  99         .name = "CB",
 100         .num_counters = 4,
 101         .flags = SI_PC_BLOCK_SE | SI_PC_BLOCK_INSTANCE_GROUPS,
 102
 103         .select0 = R_037000_CB_PERFCOUNTER_FILTER,
 104         .counter0_lo = R_035018_CB_PERFCOUNTER0_LO,
 105         .num_multi = 1,
 106         .num_prelude = 1,
 107         .layout = SI_PC_MULTI_ALTERNATE,
 108 };
 109
 110 static unsigned cik_CPC_select[] = {
 111         R_036024_CPC_PERFCOUNTER0_SELECT,
 112         R_036010_CPC_PERFCOUNTER0_SELECT1,
 113         R_03600C_CPC_PERFCOUNTER1_SELECT,
 114 };
 115 static struct si_pc_block_base cik_CPC = {
 116         .name = "CPC",
 117         .num_counters = 2,
 118
 119         .select = cik_CPC_select,
 120         .counter0_lo = R_034018_CPC_PERFCOUNTER0_LO,
 121         .num_multi = 1,
 122         .layout = SI_PC_MULTI_CUSTOM | SI_PC_REG_REVERSE,
 123 };
 124
 125 static struct si_pc_block_base cik_CPF = {
 126         .name = "CPF",
 127         .num_counters = 2,
 128
 129         .select0 = R_03601C_CPF_PERFCOUNTER0_SELECT,
 130         .counter0_lo = R_034028_CPF_PERFCOUNTER0_LO,
 131         .num_multi = 1,
 132         .layout = SI_PC_MULTI_ALTERNATE | SI_PC_REG_REVERSE,
 133 };
 134
 135 static struct si_pc_block_base cik_CPG = {
 136         .name = "CPG",
 137         .num_counters = 2,
 138
 139         .select0 = R_036008_CPG_PERFCOUNTER0_SELECT,
 140         .counter0_lo = R_034008_CPG_PERFCOUNTER0_LO,
 141         .num_multi = 1,
 142         .layout = SI_PC_MULTI_ALTERNATE | SI_PC_REG_REVERSE,
 143 };
 144
 145 static struct si_pc_block_base cik_DB = {
 146         .name = "DB",
 147         .num_counters = 4,
 148         .flags = SI_PC_BLOCK_SE | SI_PC_BLOCK_INSTANCE_GROUPS,
 149
 150         .select0 = R_037100_DB_PERFCOUNTER0_SELECT,
 151         .counter0_lo = R_035100_DB_PERFCOUNTER0_LO,
 152         .num_multi = 3, // really only 2, but there's a gap between registers
 153         .layout = SI_PC_MULTI_ALTERNATE,
 154 };
 155
 156 static struct si_pc_block_base cik_GDS = {
 157         .name = "GDS",
 158         .num_counters = 4,
 159
 160         .select0 = R_036A00_GDS_PERFCOUNTER0_SELECT,
 161         .counter0_lo = R_034A00_GDS_PERFCOUNTER0_LO,
 162         .num_multi = 1,
 163         .layout = SI_PC_MULTI_TAIL,
 164 };
 165
 166 static unsigned cik_GRBM_counters[] = {
 167         R_034100_GRBM_PERFCOUNTER0_LO,
 168         R_03410C_GRBM_PERFCOUNTER1_LO,
 169 };
 170 static struct si_pc_block_base cik_GRBM = {
 171         .name = "GRBM",
 172         .num_counters = 2,
 173
 174         .select0 = R_036100_GRBM_PERFCOUNTER0_SELECT,
 175         .counters = cik_GRBM_counters,
 176 };
 177
 178 static struct si_pc_block_base cik_GRBMSE = {
 179         .name = "GRBMSE",
 180         .num_counters = 4,
 181
 182         .select0 = R_036108_GRBM_SE0_PERFCOUNTER_SELECT,
 183         .counter0_lo = R_034114_GRBM_SE0_PERFCOUNTER_LO,
 184 };
 185
 186 static struct si_pc_block_base cik_IA = {
 187         .name = "IA",
 188         .num_counters = 4,
 189
 190         .select0 = R_036210_IA_PERFCOUNTER0_SELECT,
 191         .counter0_lo = R_034220_IA_PERFCOUNTER0_LO,
 192         .num_multi = 1,
 193         .layout = SI_PC_MULTI_TAIL,
 194 };
 195
 196 static struct si_pc_block_base cik_PA_SC = {
 197         .name = "PA_SC",
 198         .num_counters = 8,
 199         .flags = SI_PC_BLOCK_SE,
 200
 201         .select0 = R_036500_PA_SC_PERFCOUNTER0_SELECT,
 202         .counter0_lo = R_034500_PA_SC_PERFCOUNTER0_LO,
 203         .num_multi = 1,
 204         .layout = SI_PC_MULTI_ALTERNATE,
 205 };
 206
 207 /* According to docs, PA_SU counters are only 48 bits wide. */
 208 static struct si_pc_block_base cik_PA_SU = {
 209         .name = "PA_SU",
 210         .num_counters = 4,
 211         .flags = SI_PC_BLOCK_SE,
 212
 213         .select0 = R_036400_PA_SU_PERFCOUNTER0_SELECT,
 214         .counter0_lo = R_034400_PA_SU_PERFCOUNTER0_LO,
 215         .num_multi = 2,
 216         .layout = SI_PC_MULTI_ALTERNATE,
 217 };
 218
 219 static struct si_pc_block_base cik_SPI = {
 220         .name = "SPI",
 221         .num_counters = 6,
 222         .flags = SI_PC_BLOCK_SE,
 223
 224         .select0 = R_036600_SPI_PERFCOUNTER0_SELECT,
 225         .counter0_lo = R_034604_SPI_PERFCOUNTER0_LO,
 226         .num_multi = 4,
 227         .layout = SI_PC_MULTI_BLOCK,
 228 };
 229
 230 static struct si_pc_block_base cik_SQ = {
 231         .name = "SQ",
 232         .num_counters = 16,
 233         .flags = SI_PC_BLOCK_SE | SI_PC_BLOCK_SHADER,
 234
 235         .select0 = R_036700_SQ_PERFCOUNTER0_SELECT,
 236         .select_or = S_036700_SQC_BANK_MASK(15) |
 237                         S_036700_SQC_CLIENT_MASK(15) |
 238                         S_036700_SIMD_MASK(15),
 239         .counter0_lo = R_034700_SQ_PERFCOUNTER0_LO,
 240 };
 241
 242 static struct si_pc_block_base cik_SX = {
 243         .name = "SX",
 244         .num_counters = 4,
 245         .flags = SI_PC_BLOCK_SE,
 246
 247         .select0 = R_036900_SX_PERFCOUNTER0_SELECT,
 248         .counter0_lo = R_034900_SX_PERFCOUNTER0_LO,
 249         .num_multi = 2,
 250         .layout = SI_PC_MULTI_TAIL,
 251 };
 252
 253 static struct si_pc_block_base cik_TA = {
 254         .name = "TA",
 255         .num_counters = 2,
 256         .flags = SI_PC_BLOCK_SE | SI_PC_BLOCK_INSTANCE_GROUPS | SI_PC_BLOCK_SHADER_WINDOWED,
 257
 258         .select0 = R_036B00_TA_PERFCOUNTER0_SELECT,
 259         .counter0_lo = R_034B00_TA_PERFCOUNTER0_LO,
 260         .num_multi = 1,
 261         .layout = SI_PC_MULTI_ALTERNATE,
 262 };
 263
 264 static struct si_pc_block_base cik_TD = {
 265         .name = "TD",
 266         .num_counters = 2,
 267         .flags = SI_PC_BLOCK_SE | SI_PC_BLOCK_INSTANCE_GROUPS | SI_PC_BLOCK_SHADER_WINDOWED,
 268
 269         .select0 = R_036C00_TD_PERFCOUNTER0_SELECT,
 270         .counter0_lo = R_034C00_TD_PERFCOUNTER0_LO,
 271         .num_multi = 1,
 272         .layout = SI_PC_MULTI_ALTERNATE,
 273 };
 274
 275 static struct si_pc_block_base cik_TCA = {
 276         .name = "TCA",
 277         .num_counters = 4,
 278         .flags = SI_PC_BLOCK_INSTANCE_GROUPS,
 279
 280         .select0 = R_036E40_TCA_PERFCOUNTER0_SELECT,
 281         .counter0_lo = R_034E40_TCA_PERFCOUNTER0_LO,
 282         .num_multi = 2,
 283         .layout = SI_PC_MULTI_ALTERNATE,
 284 };
 285
 286 static struct si_pc_block_base cik_TCC = {
 287         .name = "TCC",
 288         .num_counters = 4,
 289         .flags = SI_PC_BLOCK_INSTANCE_GROUPS,
 290
 291         .select0 = R_036E00_TCC_PERFCOUNTER0_SELECT,
 292         .counter0_lo = R_034E00_TCC_PERFCOUNTER0_LO,
 293         .num_multi = 2,
 294         .layout = SI_PC_MULTI_ALTERNATE,
 295 };
 296
 297 static struct si_pc_block_base cik_TCP = {
 298         .name = "TCP",
 299         .num_counters = 4,
 300         .flags = SI_PC_BLOCK_SE | SI_PC_BLOCK_INSTANCE_GROUPS | SI_PC_BLOCK_SHADER_WINDOWED,
 301
 302         .select0 = R_036D00_TCP_PERFCOUNTER0_SELECT,
 303         .counter0_lo = R_034D00_TCP_PERFCOUNTER0_LO,
 304         .num_multi = 2,
 305         .layout = SI_PC_MULTI_ALTERNATE,
 306 };
 307
 308 static struct si_pc_block_base cik_VGT = {
 309         .name = "VGT",
 310         .num_counters = 4,
 311         .flags = SI_PC_BLOCK_SE,
 312
 313         .select0 = R_036230_VGT_PERFCOUNTER0_SELECT,
 314         .counter0_lo = R_034240_VGT_PERFCOUNTER0_LO,
 315         .num_multi = 1,
 316         .layout = SI_PC_MULTI_TAIL,
 317 };
 318
 319 static struct si_pc_block_base cik_WD = {
 320         .name = "WD",
 321         .num_counters = 4,
 322
 323         .select0 = R_036200_WD_PERFCOUNTER0_SELECT,
 324         .counter0_lo = R_034200_WD_PERFCOUNTER0_LO,
 325 };
 326
 327 static struct si_pc_block_base cik_MC = {
 328         .name = "MC",
 329         .num_counters = 4,
 330
 331         .layout = SI_PC_FAKE,
 332 };
 333
 334 static struct si_pc_block_base cik_SRBM = {
 335         .name = "SRBM",
 336         .num_counters = 2,
 337
 338         .layout = SI_PC_FAKE,
 339 };
 340
 341 /* Both the number of instances and selectors varies between chips of the same
 342  * class. We only differentiate by class here and simply expose the maximum
 343  * number over all chips in a class.
 344  *
 345  * Unfortunately, GPUPerfStudio uses the order of performance counter groups
 346  * blindly once it believes it has identified the hardware, so the order of
 347  * blocks here matters.
 348  */
 349 static struct si_pc_block groups_CIK[] = {
 350         { &cik_CB, 226, 4 },
 351         { &cik_CPF, 17 },
 352         { &cik_DB, 257, 4 },
 353         { &cik_GRBM, 34 },
 354         { &cik_GRBMSE, 15 },
 355         { &cik_PA_SU, 153 },
 356         { &cik_PA_SC, 395 },
 357         { &cik_SPI, 186 },
 358         { &cik_SQ, 252 },
 359         { &cik_SX, 32 },
 360         { &cik_TA, 111, 11 },
 361         { &cik_TCA, 39, 2 },
 362         { &cik_TCC, 160, 16 },
 363         { &cik_TD, 55, 11 },
 364         { &cik_TCP, 154, 11 },
 365         { &cik_GDS, 121 },
 366         { &cik_VGT, 140 },
 367         { &cik_IA, 22 },
 368         { &cik_MC, 22 },
 369         { &cik_SRBM, 19 },
 370         { &cik_WD, 22 },
 371         { &cik_CPG, 46 },
 372         { &cik_CPC, 22 },
 373
 374 };
 375
 376 static struct si_pc_block groups_VI[] = {
 377         { &cik_CB, 405, 4 },
 378         { &cik_CPF, 19 },
 379         { &cik_DB, 257, 4 },
 380         { &cik_GRBM, 34 },
 381         { &cik_GRBMSE, 15 },
 382         { &cik_PA_SU, 153 },
 383         { &cik_PA_SC, 397 },
 384         { &cik_SPI, 197 },
 385         { &cik_SQ, 273 },
 386         { &cik_SX, 34 },
 387         { &cik_TA, 119, 16 },
 388         { &cik_TCA, 35, 2 },
 389         { &cik_TCC, 192, 16 },
 390         { &cik_TD, 55, 16 },
 391         { &cik_TCP, 180, 16 },
 392         { &cik_GDS, 121 },
 393         { &cik_VGT, 147 },
 394         { &cik_IA, 24 },
 395         { &cik_MC, 22 },
 396         { &cik_SRBM, 27 },
 397         { &cik_WD, 37 },
 398         { &cik_CPG, 48 },
 399         { &cik_CPC, 24 },
 400
 401 };
 402
 403 static struct si_pc_block groups_gfx9[] = {
 404         { &cik_CB, 438, 4 },
 405         { &cik_CPF, 32 },
 406         { &cik_DB, 328, 4 },
 407         { &cik_GRBM, 38 },
 408         { &cik_GRBMSE, 16 },
 409         { &cik_PA_SU, 292 },
 410         { &cik_PA_SC, 491 },
 411         { &cik_SPI, 196 },
 412         { &cik_SQ, 374 },
 413         { &cik_SX, 208 },
 414         { &cik_TA, 119, 16 },
 415         { &cik_TCA, 35, 2 },
 416         { &cik_TCC, 256, 16 },
 417         { &cik_TD, 57, 16 },
 418         { &cik_TCP, 85, 16 },
 419         { &cik_GDS, 121 },
 420         { &cik_VGT, 148 },
 421         { &cik_IA, 32 },
 422         { &cik_WD, 58 },
 423         { &cik_CPG, 59 },
 424         { &cik_CPC, 35 },
 425 };
 426
 427 static void si_pc_emit_instance(struct si_context *sctx,
 428                                 int se, int instance)
 429 {
 430         struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
 431         unsigned value = S_030800_SH_BROADCAST_WRITES(1);
 432
 433         if (se >= 0) {
 434                 value |= S_030800_SE_INDEX(se);
 435         } else {
 436                 value |= S_030800_SE_BROADCAST_WRITES(1);
 437         }
 438
 439         if (instance >= 0) {
 440                 value |= S_030800_INSTANCE_INDEX(instance);
 441         } else {
 442                 value |= S_030800_INSTANCE_BROADCAST_WRITES(1);
 443         }
 444
 445         radeon_set_uconfig_reg(cs, R_030800_GRBM_GFX_INDEX, value);
 446 }
 447
 448 static void si_pc_emit_shaders(struct si_context *sctx,
 449                                unsigned shaders)
 450 {
 451         struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
 452
 453         radeon_set_uconfig_reg_seq(cs, R_036780_SQ_PERFCOUNTER_CTRL, 2);
 454         radeon_emit(cs, shaders & 0x7f);
 455         radeon_emit(cs, 0xffffffff);
 456 }
 457
 458 static void si_pc_emit_select(struct si_context *sctx,
 459                         struct si_perfcounter_block *group,
 460                         unsigned count, unsigned *selectors)
 461 {
 462         struct si_pc_block *sigroup = (struct si_pc_block *)group->data;
 463         struct si_pc_block_base *regs = sigroup->b;
 464         struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
 465         unsigned idx;
 466         unsigned layout_multi = regs->layout & SI_PC_MULTI_MASK;
 467         unsigned dw;
 468
 469         assert(count <= regs->num_counters);
 470
 471         if (regs->layout & SI_PC_FAKE)
 472                 return;
 473
 474         if (layout_multi == SI_PC_MULTI_BLOCK) {
 475                 assert(!(regs->layout & SI_PC_REG_REVERSE));
 476
 477                 dw = count + regs->num_prelude;
 478                 if (count >= regs->num_multi)
 479                         dw += regs->num_multi;
 480                 radeon_set_uconfig_reg_seq(cs, regs->select0, dw);
 481                 for (idx = 0; idx < regs->num_prelude; ++idx)
 482                         radeon_emit(cs, 0);
 483                 for (idx = 0; idx < MIN2(count, regs->num_multi); ++idx)
 484                         radeon_emit(cs, selectors[idx] | regs->select_or);
 485
 486                 if (count < regs->num_multi) {
 487                         unsigned select1 =
 488                                 regs->select0 + 4 * regs->num_multi;
 489                         radeon_set_uconfig_reg_seq(cs, select1, count);
 490                 }
 491
 492                 for (idx = 0; idx < MIN2(count, regs->num_multi); ++idx)
 493                         radeon_emit(cs, 0);
 494
 495                 if (count > regs->num_multi) {
 496                         for (idx = regs->num_multi; idx < count; ++idx)
 497                                 radeon_emit(cs, selectors[idx] | regs->select_or);
 498                 }
 499         } else if (layout_multi == SI_PC_MULTI_TAIL) {
 500                 unsigned select1, select1_count;
 501
 502                 assert(!(regs->layout & SI_PC_REG_REVERSE));
 503
 504                 radeon_set_uconfig_reg_seq(cs, regs->select0, count + regs->num_prelude);
 505                 for (idx = 0; idx < regs->num_prelude; ++idx)
 506                         radeon_emit(cs, 0);
 507                 for (idx = 0; idx < count; ++idx)
 508                         radeon_emit(cs, selectors[idx] | regs->select_or);
 509
 510                 select1 = regs->select0 + 4 * regs->num_counters;
 511                 select1_count = MIN2(count, regs->num_multi);
 512                 radeon_set_uconfig_reg_seq(cs, select1, select1_count);
 513                 for (idx = 0; idx < select1_count; ++idx)
 514                         radeon_emit(cs, 0);
 515         } else if (layout_multi == SI_PC_MULTI_CUSTOM) {
 516                 unsigned *reg = regs->select;
 517                 for (idx = 0; idx < count; ++idx) {
 518                         radeon_set_uconfig_reg(cs, *reg++, selectors[idx] | regs->select_or);
 519                         if (idx < regs->num_multi)
 520                                 radeon_set_uconfig_reg(cs, *reg++, 0);
 521                 }
 522         } else {
 523                 assert(layout_multi == SI_PC_MULTI_ALTERNATE);
 524
 525                 unsigned reg_base = regs->select0;
 526                 unsigned reg_count = count + MIN2(count, regs->num_multi);
 527                 reg_count += regs->num_prelude;
 528
 529                 if (!(regs->layout & SI_PC_REG_REVERSE)) {
 530                         radeon_set_uconfig_reg_seq(cs, reg_base, reg_count);
 531
 532                         for (idx = 0; idx < regs->num_prelude; ++idx)
 533                                 radeon_emit(cs, 0);
 534                         for (idx = 0; idx < count; ++idx) {
 535                                 radeon_emit(cs, selectors[idx] | regs->select_or);
 536                                 if (idx < regs->num_multi)
 537                                         radeon_emit(cs, 0);
 538                         }
 539                 } else {
 540                         reg_base -= (reg_count - 1) * 4;
 541                         radeon_set_uconfig_reg_seq(cs, reg_base, reg_count);
 542
 543                         for (idx = count; idx > 0; --idx) {
 544                                 if (idx <= regs->num_multi)
 545                                         radeon_emit(cs, 0);
 546                                 radeon_emit(cs, selectors[idx - 1] | regs->select_or);
 547                         }
 548                         for (idx = 0; idx < regs->num_prelude; ++idx)
 549                                 radeon_emit(cs, 0);
 550                 }
 551         }
 552 }
 553
 554 static void si_pc_emit_start(struct si_context *sctx,
 555                              struct r600_resource *buffer, uint64_t va)
 556 {
 557         struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
 558
 559         radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs, buffer,
 560                                   RADEON_USAGE_WRITE, RADEON_PRIO_QUERY);
 561
 562         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
 563         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
 564                         COPY_DATA_DST_SEL(COPY_DATA_MEM));
 565         radeon_emit(cs, 1); /* immediate */
 566         radeon_emit(cs, 0); /* unused */
 567         radeon_emit(cs, va);
 568         radeon_emit(cs, va >> 32);
 569
 570         radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
 571                                S_036020_PERFMON_STATE(V_036020_DISABLE_AND_RESET));
 572         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 573         radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_START) | EVENT_INDEX(0));
 574         radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
 575                                S_036020_PERFMON_STATE(V_036020_START_COUNTING));
 576 }
 577
 578 /* Note: The buffer was already added in si_pc_emit_start, so we don't have to
 579  * do it again in here. */
 580 static void si_pc_emit_stop(struct si_context *sctx,
 581                             struct r600_resource *buffer, uint64_t va)
 582 {
 583         struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
 584
 585         si_gfx_write_event_eop(sctx, V_028A90_BOTTOM_OF_PIPE_TS, 0,
 586                                EOP_DATA_SEL_VALUE_32BIT,
 587                                buffer, va, 0, SI_NOT_QUERY);
 588         si_gfx_wait_fence(sctx, va, 0, 0xffffffff);
 589
 590         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 591         radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_SAMPLE) | EVENT_INDEX(0));
 592         radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
 593         radeon_emit(cs, EVENT_TYPE(V_028A90_PERFCOUNTER_STOP) | EVENT_INDEX(0));
 594         radeon_set_uconfig_reg(cs, R_036020_CP_PERFMON_CNTL,
 595                                S_036020_PERFMON_STATE(V_036020_STOP_COUNTING) |
 596                                S_036020_PERFMON_SAMPLE_ENABLE(1));
 597 }
 598
 599 static void si_pc_emit_read(struct si_context *sctx,
 600                             struct si_perfcounter_block *group,
 601                             unsigned count, unsigned *selectors,
 602                             struct r600_resource *buffer, uint64_t va)
 603 {
 604         struct si_pc_block *sigroup = (struct si_pc_block *)group->data;
 605         struct si_pc_block_base *regs = sigroup->b;
 606         struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
 607         unsigned idx;
 608         unsigned reg = regs->counter0_lo;
 609         unsigned reg_delta = 8;
 610
 611         if (!(regs->layout & SI_PC_FAKE)) {
 612                 if (regs->layout & SI_PC_REG_REVERSE)
 613                         reg_delta = -reg_delta;
 614
 615                 for (idx = 0; idx < count; ++idx) {
 616                         if (regs->counters)
 617                                 reg = regs->counters[idx];
 618
 619                         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
 620                         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_PERF) |
 621                                         COPY_DATA_DST_SEL(COPY_DATA_MEM) |
 622                                         COPY_DATA_COUNT_SEL); /* 64 bits */
 623                         radeon_emit(cs, reg >> 2);
 624                         radeon_emit(cs, 0); /* unused */
 625                         radeon_emit(cs, va);
 626                         radeon_emit(cs, va >> 32);
 627                         va += sizeof(uint64_t);
 628                         reg += reg_delta;
 629                 }
 630         } else {
 631                 for (idx = 0; idx < count; ++idx) {
 632                         radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
 633                         radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_IMM) |
 634                                         COPY_DATA_DST_SEL(COPY_DATA_MEM) |
 635                                         COPY_DATA_COUNT_SEL);
 636                         radeon_emit(cs, 0); /* immediate */
 637                         radeon_emit(cs, 0);
 638                         radeon_emit(cs, va);
 639                         radeon_emit(cs, va >> 32);
 640                         va += sizeof(uint64_t);
 641                 }
 642         }
 643 }
 644
 645 static void si_pc_cleanup(struct si_screen *sscreen)
 646 {
 647         si_perfcounters_do_destroy(sscreen->perfcounters);
 648         sscreen->perfcounters = NULL;
 649 }
 650
 651 void si_init_perfcounters(struct si_screen *screen)
 652 {
 653         struct si_perfcounters *pc;
 654         struct si_pc_block *blocks;
 655         unsigned num_blocks;
 656         unsigned i;
 657
 658         switch (screen->info.chip_class) {
 659         case CIK:
 660                 blocks = groups_CIK;
 661                 num_blocks = ARRAY_SIZE(groups_CIK);
 662                 break;
 663         case VI:
 664                 blocks = groups_VI;
 665                 num_blocks = ARRAY_SIZE(groups_VI);
 666                 break;
 667         case GFX9:
 668                 blocks = groups_gfx9;
 669                 num_blocks = ARRAY_SIZE(groups_gfx9);
 670                 break;
 671         case SI:
 672         default:
 673                 return; /* not implemented */
 674         }
 675
 676         if (screen->info.max_sh_per_se != 1) {
 677                 /* This should not happen on non-SI chips. */
 678                 fprintf(stderr, "si_init_perfcounters: max_sh_per_se = %d not "
 679                         "supported (inaccurate performance counters)\n",
 680                         screen->info.max_sh_per_se);
 681         }
 682
 683         pc = CALLOC_STRUCT(si_perfcounters);
 684         if (!pc)
 685                 return;
 686
 687         pc->num_stop_cs_dwords = 14 + si_gfx_write_fence_dwords(screen);
 688         pc->num_instance_cs_dwords = 3;
 689
 690         pc->num_shader_types = ARRAY_SIZE(si_pc_shader_type_bits);
 691         pc->shader_type_suffixes = si_pc_shader_type_suffixes;
 692         pc->shader_type_bits = si_pc_shader_type_bits;
 693
 694         pc->emit_instance = si_pc_emit_instance;
 695         pc->emit_shaders = si_pc_emit_shaders;
 696         pc->emit_select = si_pc_emit_select;
 697         pc->emit_start = si_pc_emit_start;
 698         pc->emit_stop = si_pc_emit_stop;
 699         pc->emit_read = si_pc_emit_read;
 700         pc->cleanup = si_pc_cleanup;
 701
 702         if (!si_perfcounters_init(pc, num_blocks))
 703                 goto error;
 704
 705         for (i = 0; i < num_blocks; ++i) {
 706                 struct si_pc_block *block = &blocks[i];
 707                 unsigned instances = block->instances;
 708
 709                 if (!strcmp(block->b->name, "IA")) {
 710                         if (screen->info.max_se > 2)
 711                                 instances = 2;
 712                 }
 713
 714                 si_perfcounters_add_block(screen, pc,
 715                                             block->b->name,
 716                                             block->b->flags,
 717                                             block->b->num_counters,
 718                                             block->selectors,
 719                                             instances,
 720                                             block);
 721         }
 722
 723         screen->perfcounters = pc;
 724         return;
 725
 726 error:
 727         si_perfcounters_do_destroy(pc);
 728 }