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9ca64b05d63b64aa9202f0e7ba9ef9b888dc090e
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
30 #include "sid.h"
31
32 #include "ac_llvm_util.h"
33 #include "radeon/radeon_uvd.h"
34 #include "util/disk_cache.h"
35 #include "util/u_log.h"
36 #include "util/u_memory.h"
37 #include "util/u_suballoc.h"
38 #include "util/u_tests.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/xmlconfig.h"
41 #include "vl/vl_decoder.h"
42 #include "driver_ddebug/dd_util.h"
43
44 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
45 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
46 #include <xf86drm.h>
47
48 #include <llvm/Config/llvm-config.h>
49
50 static const struct debug_named_value debug_options[] = {
51 /* Shader logging options: */
52 { "vs", DBG(VS), "Print vertex shaders" },
53 { "ps", DBG(PS), "Print pixel shaders" },
54 { "gs", DBG(GS), "Print geometry shaders" },
55 { "tcs", DBG(TCS), "Print tessellation control shaders" },
56 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
57 { "cs", DBG(CS), "Print compute shaders" },
58 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
59 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
60 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
61 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
62
63 /* Shader compiler options the shader cache should be aware of: */
64 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
65 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
66 { "w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders." },
67 { "w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders." },
68 { "w32cs", DBG(W32_CS), "Use Wave32 for computes shaders." },
69 { "w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders." },
70 { "w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders." },
71 { "w64cs", DBG(W64_CS), "Use Wave64 for computes shaders." },
72
73 /* Shader compiler options (with no effect on the shader cache): */
74 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
75 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
76 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
77
78 /* Information logging options: */
79 { "info", DBG(INFO), "Print driver information" },
80 { "tex", DBG(TEX), "Print texture info" },
81 { "compute", DBG(COMPUTE), "Print compute info" },
82 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
83
84 /* Driver options: */
85 { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." },
86 { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
87 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
88 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
89 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
90 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
91
92 /* 3D engine options: */
93 { "nogfx", DBG(NO_GFX), "Disable graphics. Only multimedia compute paths can be used." },
94 { "nongg", DBG(NO_NGG), "Disable NGG and use the legacy pipeline." },
95 { "alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader." },
96 { "pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls." },
97 { "nopd", DBG(NO_PD), "Disable the primitive discard compute shader." },
98 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
99 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
100 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
101 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
102 { "dpbb", DBG(DPBB), "Enable DPBB." },
103 { "dfsm", DBG(DFSM), "Enable DFSM." },
104 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
105 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
106 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
107 { "notiling", DBG(NO_TILING), "Disable tiling" },
108 { "nodcc", DBG(NO_DCC), "Disable DCC." },
109 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
110 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
111 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
112 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
113
114 /* Tests: */
115 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
116 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
117 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
118 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
119 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
120 { "testgds", DBG(TEST_GDS), "Test GDS." },
121 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
122 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
123
124 DEBUG_NAMED_VALUE_END /* must be last */
125 };
126
127 static void si_init_compiler(struct si_screen *sscreen,
128 struct ac_llvm_compiler *compiler)
129 {
130 /* Only create the less-optimizing version of the compiler on APUs
131 * predating Ryzen (Raven). */
132 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
133 sscreen->info.chip_class <= GFX8;
134
135 enum ac_target_machine_options tm_options =
136 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
137 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
138 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
139 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
140 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
141 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
142 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
143
144 ac_init_llvm_once();
145 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
146 compiler->passes = ac_create_llvm_passes(compiler->tm);
147
148 if (compiler->tm_wave32)
149 compiler->passes_wave32 = ac_create_llvm_passes(compiler->tm_wave32);
150 if (compiler->low_opt_tm)
151 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
152 }
153
154 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
155 {
156 ac_destroy_llvm_compiler(compiler);
157 }
158
159 /*
160 * pipe_context
161 */
162 static void si_destroy_context(struct pipe_context *context)
163 {
164 struct si_context *sctx = (struct si_context *)context;
165 int i;
166
167 util_queue_finish(&sctx->screen->shader_compiler_queue);
168 util_queue_finish(&sctx->screen->shader_compiler_queue_low_priority);
169
170 /* Unreference the framebuffer normally to disable related logic
171 * properly.
172 */
173 struct pipe_framebuffer_state fb = {};
174 if (context->set_framebuffer_state)
175 context->set_framebuffer_state(context, &fb);
176
177 si_release_all_descriptors(sctx);
178
179 if (sctx->chip_class >= GFX10 && sctx->has_graphics)
180 gfx10_destroy_query(sctx);
181
182 pipe_resource_reference(&sctx->esgs_ring, NULL);
183 pipe_resource_reference(&sctx->gsvs_ring, NULL);
184 pipe_resource_reference(&sctx->tess_rings, NULL);
185 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
186 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
187 si_resource_reference(&sctx->border_color_buffer, NULL);
188 free(sctx->border_color_table);
189 si_resource_reference(&sctx->scratch_buffer, NULL);
190 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
191 si_resource_reference(&sctx->wait_mem_scratch, NULL);
192
193 si_pm4_free_state(sctx, sctx->init_config, ~0);
194 if (sctx->init_config_gs_rings)
195 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
196 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
197 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
198
199 if (sctx->fixed_func_tcs_shader.cso)
200 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
201 if (sctx->custom_dsa_flush)
202 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
203 if (sctx->custom_blend_resolve)
204 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
205 if (sctx->custom_blend_fmask_decompress)
206 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
207 if (sctx->custom_blend_eliminate_fastclear)
208 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
209 if (sctx->custom_blend_dcc_decompress)
210 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
211 if (sctx->vs_blit_pos)
212 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
213 if (sctx->vs_blit_pos_layered)
214 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
215 if (sctx->vs_blit_color)
216 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
217 if (sctx->vs_blit_color_layered)
218 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
219 if (sctx->vs_blit_texcoord)
220 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
221 if (sctx->cs_clear_buffer)
222 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
223 if (sctx->cs_copy_buffer)
224 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
225 if (sctx->cs_copy_image)
226 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
227 if (sctx->cs_copy_image_1d_array)
228 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
229 if (sctx->cs_clear_render_target)
230 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
231 if (sctx->cs_clear_render_target_1d_array)
232 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
233 if (sctx->cs_dcc_retile)
234 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile);
235
236 for (unsigned i = 0; i < ARRAY_SIZE(sctx->cs_fmask_expand); i++) {
237 for (unsigned j = 0; j < ARRAY_SIZE(sctx->cs_fmask_expand[i]); j++) {
238 if (sctx->cs_fmask_expand[i][j]) {
239 sctx->b.delete_compute_state(&sctx->b,
240 sctx->cs_fmask_expand[i][j]);
241 }
242 }
243 }
244
245 if (sctx->blitter)
246 util_blitter_destroy(sctx->blitter);
247
248 /* Release DCC stats. */
249 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
250 assert(!sctx->dcc_stats[i].query_active);
251
252 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
253 if (sctx->dcc_stats[i].ps_stats[j])
254 sctx->b.destroy_query(&sctx->b,
255 sctx->dcc_stats[i].ps_stats[j]);
256
257 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
258 }
259
260 if (sctx->query_result_shader)
261 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
262 if (sctx->sh_query_result_shader)
263 sctx->b.delete_compute_state(&sctx->b, sctx->sh_query_result_shader);
264
265 if (sctx->gfx_cs)
266 sctx->ws->cs_destroy(sctx->gfx_cs);
267 if (sctx->dma_cs)
268 sctx->ws->cs_destroy(sctx->dma_cs);
269 if (sctx->ctx)
270 sctx->ws->ctx_destroy(sctx->ctx);
271
272 if (sctx->b.stream_uploader)
273 u_upload_destroy(sctx->b.stream_uploader);
274 if (sctx->b.const_uploader)
275 u_upload_destroy(sctx->b.const_uploader);
276 if (sctx->cached_gtt_allocator)
277 u_upload_destroy(sctx->cached_gtt_allocator);
278
279 slab_destroy_child(&sctx->pool_transfers);
280 slab_destroy_child(&sctx->pool_transfers_unsync);
281
282 if (sctx->allocator_zeroed_memory)
283 u_suballocator_destroy(sctx->allocator_zeroed_memory);
284
285 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
286 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
287 sctx->ws->fence_reference(&sctx->last_ib_barrier_fence, NULL);
288 si_resource_reference(&sctx->eop_bug_scratch, NULL);
289 si_resource_reference(&sctx->index_ring, NULL);
290 si_resource_reference(&sctx->barrier_buf, NULL);
291 si_resource_reference(&sctx->last_ib_barrier_buf, NULL);
292 pb_reference(&sctx->gds, NULL);
293 pb_reference(&sctx->gds_oa, NULL);
294
295 si_destroy_compiler(&sctx->compiler);
296
297 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
298
299 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
300 _mesa_hash_table_destroy(sctx->img_handles, NULL);
301
302 util_dynarray_fini(&sctx->resident_tex_handles);
303 util_dynarray_fini(&sctx->resident_img_handles);
304 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
305 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
306 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
307 si_unref_sdma_uploads(sctx);
308 free(sctx->sdma_uploads);
309 FREE(sctx);
310 }
311
312 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
313 {
314 struct si_context *sctx = (struct si_context *)ctx;
315 enum pipe_reset_status status = sctx->ws->ctx_query_reset_status(sctx->ctx);
316
317 if (status != PIPE_NO_RESET && sctx->device_reset_callback.reset) {
318 sctx->device_reset_callback.reset(sctx->device_reset_callback.data,
319 status);
320 }
321 return status;
322 }
323
324 static void si_set_device_reset_callback(struct pipe_context *ctx,
325 const struct pipe_device_reset_callback *cb)
326 {
327 struct si_context *sctx = (struct si_context *)ctx;
328
329 if (cb)
330 sctx->device_reset_callback = *cb;
331 else
332 memset(&sctx->device_reset_callback, 0,
333 sizeof(sctx->device_reset_callback));
334 }
335
336 /* Apitrace profiling:
337 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
338 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
339 * and remember its number.
340 * 3) In Mesa, enable queries and performance counters around that draw
341 * call and print the results.
342 * 4) glretrace --benchmark --markers ..
343 */
344 static void si_emit_string_marker(struct pipe_context *ctx,
345 const char *string, int len)
346 {
347 struct si_context *sctx = (struct si_context *)ctx;
348
349 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
350
351 if (sctx->log)
352 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
353 }
354
355 static void si_set_debug_callback(struct pipe_context *ctx,
356 const struct pipe_debug_callback *cb)
357 {
358 struct si_context *sctx = (struct si_context *)ctx;
359 struct si_screen *screen = sctx->screen;
360
361 util_queue_finish(&screen->shader_compiler_queue);
362 util_queue_finish(&screen->shader_compiler_queue_low_priority);
363
364 if (cb)
365 sctx->debug = *cb;
366 else
367 memset(&sctx->debug, 0, sizeof(sctx->debug));
368 }
369
370 static void si_set_log_context(struct pipe_context *ctx,
371 struct u_log_context *log)
372 {
373 struct si_context *sctx = (struct si_context *)ctx;
374 sctx->log = log;
375
376 if (log)
377 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
378 }
379
380 static void si_set_context_param(struct pipe_context *ctx,
381 enum pipe_context_param param,
382 unsigned value)
383 {
384 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
385
386 switch (param) {
387 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
388 ws->pin_threads_to_L3_cache(ws, value);
389 break;
390 default:;
391 }
392 }
393
394 static struct pipe_context *si_create_context(struct pipe_screen *screen,
395 unsigned flags)
396 {
397 struct si_screen* sscreen = (struct si_screen *)screen;
398
399 /* Don't create a context if it's not compute-only and hw is compute-only. */
400 if (!sscreen->info.has_graphics &&
401 !(flags & PIPE_CONTEXT_COMPUTE_ONLY))
402 return NULL;
403
404 struct si_context *sctx = CALLOC_STRUCT(si_context);
405 struct radeon_winsys *ws = sscreen->ws;
406 int shader, i;
407 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
408
409 if (!sctx)
410 return NULL;
411
412 sctx->has_graphics = sscreen->info.chip_class == GFX6 ||
413 !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
414
415 if (flags & PIPE_CONTEXT_DEBUG)
416 sscreen->record_llvm_ir = true; /* racy but not critical */
417
418 sctx->b.screen = screen; /* this must be set first */
419 sctx->b.priv = NULL;
420 sctx->b.destroy = si_destroy_context;
421 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
422 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
423
424 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
425 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
426
427 sctx->ws = sscreen->ws;
428 sctx->family = sscreen->info.family;
429 sctx->chip_class = sscreen->info.chip_class;
430
431 if (sctx->chip_class == GFX7 ||
432 sctx->chip_class == GFX8 ||
433 sctx->chip_class == GFX9) {
434 sctx->eop_bug_scratch = si_resource(
435 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
436 16 * sscreen->info.num_render_backends));
437 if (!sctx->eop_bug_scratch)
438 goto fail;
439 }
440
441 /* Initialize context allocators. */
442 sctx->allocator_zeroed_memory =
443 u_suballocator_create(&sctx->b, 128 * 1024,
444 0, PIPE_USAGE_DEFAULT,
445 SI_RESOURCE_FLAG_UNMAPPABLE |
446 SI_RESOURCE_FLAG_CLEAR, false);
447 if (!sctx->allocator_zeroed_memory)
448 goto fail;
449
450 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
451 0, PIPE_USAGE_STREAM,
452 SI_RESOURCE_FLAG_READ_ONLY);
453 if (!sctx->b.stream_uploader)
454 goto fail;
455
456 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
457 0, PIPE_USAGE_STAGING, 0);
458 if (!sctx->cached_gtt_allocator)
459 goto fail;
460
461 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
462 if (!sctx->ctx)
463 goto fail;
464
465 if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
466 sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
467 (void*)si_flush_dma_cs,
468 sctx, stop_exec_on_failure);
469 }
470
471 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->dma_cs;
472 sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
473 0, PIPE_USAGE_DEFAULT,
474 SI_RESOURCE_FLAG_32BIT |
475 (use_sdma_upload ?
476 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA : 0));
477 if (!sctx->b.const_uploader)
478 goto fail;
479
480 if (use_sdma_upload)
481 u_upload_enable_flush_explicit(sctx->b.const_uploader);
482
483 sctx->gfx_cs = ws->cs_create(sctx->ctx,
484 sctx->has_graphics ? RING_GFX : RING_COMPUTE,
485 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
486
487 /* Border colors. */
488 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
489 sizeof(*sctx->border_color_table));
490 if (!sctx->border_color_table)
491 goto fail;
492
493 sctx->border_color_buffer = si_resource(
494 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
495 SI_MAX_BORDER_COLORS *
496 sizeof(*sctx->border_color_table)));
497 if (!sctx->border_color_buffer)
498 goto fail;
499
500 sctx->border_color_map =
501 ws->buffer_map(sctx->border_color_buffer->buf,
502 NULL, PIPE_TRANSFER_WRITE);
503 if (!sctx->border_color_map)
504 goto fail;
505
506 sctx->ngg = sscreen->use_ngg;
507
508 /* Initialize context functions used by graphics and compute. */
509 if (sctx->chip_class >= GFX10)
510 sctx->emit_cache_flush = gfx10_emit_cache_flush;
511 else
512 sctx->emit_cache_flush = si_emit_cache_flush;
513
514 sctx->b.emit_string_marker = si_emit_string_marker;
515 sctx->b.set_debug_callback = si_set_debug_callback;
516 sctx->b.set_log_context = si_set_log_context;
517 sctx->b.set_context_param = si_set_context_param;
518 sctx->b.get_device_reset_status = si_get_reset_status;
519 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
520
521 si_init_all_descriptors(sctx);
522 si_init_buffer_functions(sctx);
523 si_init_clear_functions(sctx);
524 si_init_blit_functions(sctx);
525 si_init_compute_functions(sctx);
526 si_init_compute_blit_functions(sctx);
527 si_init_debug_functions(sctx);
528 si_init_fence_functions(sctx);
529 si_init_query_functions(sctx);
530 si_init_state_compute_functions(sctx);
531 si_init_context_texture_functions(sctx);
532
533 /* Initialize graphics-only context functions. */
534 if (sctx->has_graphics) {
535 if (sctx->chip_class >= GFX10)
536 gfx10_init_query(sctx);
537 si_init_msaa_functions(sctx);
538 si_init_shader_functions(sctx);
539 si_init_state_functions(sctx);
540 si_init_streamout_functions(sctx);
541 si_init_viewport_functions(sctx);
542
543 sctx->blitter = util_blitter_create(&sctx->b);
544 if (sctx->blitter == NULL)
545 goto fail;
546 sctx->blitter->skip_viewport_restore = true;
547
548 /* Some states are expected to be always non-NULL. */
549 sctx->noop_blend = util_blitter_get_noop_blend_state(sctx->blitter);
550 sctx->queued.named.blend = sctx->noop_blend;
551
552 sctx->noop_dsa = util_blitter_get_noop_dsa_state(sctx->blitter);
553 sctx->queued.named.dsa = sctx->noop_dsa;
554
555 sctx->discard_rasterizer_state =
556 util_blitter_get_discard_rasterizer_state(sctx->blitter);
557 sctx->queued.named.rasterizer = sctx->discard_rasterizer_state;
558
559 si_init_draw_functions(sctx);
560 si_initialize_prim_discard_tunables(sctx);
561 }
562
563 /* Initialize SDMA functions. */
564 if (sctx->chip_class >= GFX7)
565 cik_init_sdma_functions(sctx);
566 else
567 si_init_dma_functions(sctx);
568
569 if (sscreen->debug_flags & DBG(FORCE_DMA))
570 sctx->b.resource_copy_region = sctx->dma_copy;
571
572 sctx->sample_mask = 0xffff;
573
574 /* Initialize multimedia functions. */
575 if (sscreen->info.has_hw_decode) {
576 sctx->b.create_video_codec = si_uvd_create_decoder;
577 sctx->b.create_video_buffer = si_video_buffer_create;
578 } else {
579 sctx->b.create_video_codec = vl_create_decoder;
580 sctx->b.create_video_buffer = vl_video_buffer_create;
581 }
582
583 if (sctx->chip_class >= GFX9) {
584 sctx->wait_mem_scratch = si_resource(
585 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 8));
586 if (!sctx->wait_mem_scratch)
587 goto fail;
588
589 /* Initialize the memory. */
590 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
591 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
592 }
593
594 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
595 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
596 if (sctx->chip_class == GFX7) {
597 sctx->null_const_buf.buffer =
598 pipe_aligned_buffer_create(screen,
599 SI_RESOURCE_FLAG_32BIT,
600 PIPE_USAGE_DEFAULT, 16,
601 sctx->screen->info.tcc_cache_line_size);
602 if (!sctx->null_const_buf.buffer)
603 goto fail;
604 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
605
606 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
607 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
608 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
609 sctx->b.set_constant_buffer(&sctx->b, shader, i,
610 &sctx->null_const_buf);
611 }
612 }
613
614 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
615 &sctx->null_const_buf);
616 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
617 &sctx->null_const_buf);
618 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
619 &sctx->null_const_buf);
620 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
621 &sctx->null_const_buf);
622 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
623 &sctx->null_const_buf);
624 }
625
626 uint64_t max_threads_per_block;
627 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
628 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
629 &max_threads_per_block);
630
631 /* The maximum number of scratch waves. Scratch space isn't divided
632 * evenly between CUs. The number is only a function of the number of CUs.
633 * We can decrease the constant to decrease the scratch buffer size.
634 *
635 * sctx->scratch_waves must be >= the maximum posible size of
636 * 1 threadgroup, so that the hw doesn't hang from being unable
637 * to start any.
638 *
639 * The recommended value is 4 per CU at most. Higher numbers don't
640 * bring much benefit, but they still occupy chip resources (think
641 * async compute). I've seen ~2% performance difference between 4 and 32.
642 */
643 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
644 max_threads_per_block / 64);
645
646 si_init_compiler(sscreen, &sctx->compiler);
647
648 /* Bindless handles. */
649 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
650 _mesa_key_pointer_equal);
651 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
652 _mesa_key_pointer_equal);
653
654 util_dynarray_init(&sctx->resident_tex_handles, NULL);
655 util_dynarray_init(&sctx->resident_img_handles, NULL);
656 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
657 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
658 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
659
660 sctx->sample_pos_buffer =
661 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
662 sizeof(sctx->sample_positions));
663 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
664 sizeof(sctx->sample_positions), &sctx->sample_positions);
665
666 /* this must be last */
667 si_begin_new_gfx_cs(sctx);
668
669 if (sctx->chip_class == GFX7) {
670 /* Clear the NULL constant buffer, because loads should return zeros.
671 * Note that this forces CP DMA to be used, because clover deadlocks
672 * for some reason when the compute codepath is used.
673 */
674 uint32_t clear_value = 0;
675 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
676 sctx->null_const_buf.buffer->width0,
677 &clear_value, 4, SI_COHERENCY_SHADER, true);
678 }
679 return &sctx->b;
680 fail:
681 fprintf(stderr, "radeonsi: Failed to create a context.\n");
682 si_destroy_context(&sctx->b);
683 return NULL;
684 }
685
686 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
687 void *priv, unsigned flags)
688 {
689 struct si_screen *sscreen = (struct si_screen *)screen;
690 struct pipe_context *ctx;
691
692 if (sscreen->debug_flags & DBG(CHECK_VM))
693 flags |= PIPE_CONTEXT_DEBUG;
694
695 ctx = si_create_context(screen, flags);
696
697 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
698 return ctx;
699
700 /* Clover (compute-only) is unsupported. */
701 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
702 return ctx;
703
704 /* When shaders are logged to stderr, asynchronous compilation is
705 * disabled too. */
706 if (sscreen->debug_flags & DBG_ALL_SHADERS)
707 return ctx;
708
709 /* Use asynchronous flushes only on amdgpu, since the radeon
710 * implementation for fence_server_sync is incomplete. */
711 return threaded_context_create(ctx, &sscreen->pool_transfers,
712 si_replace_buffer_storage,
713 sscreen->info.is_amdgpu ? si_create_fence : NULL,
714 &((struct si_context*)ctx)->tc);
715 }
716
717 /*
718 * pipe_screen
719 */
720 static void si_destroy_screen(struct pipe_screen* pscreen)
721 {
722 struct si_screen *sscreen = (struct si_screen *)pscreen;
723 struct si_shader_part *parts[] = {
724 sscreen->vs_prologs,
725 sscreen->tcs_epilogs,
726 sscreen->gs_prologs,
727 sscreen->ps_prologs,
728 sscreen->ps_epilogs
729 };
730 unsigned i;
731
732 if (!sscreen->ws->unref(sscreen->ws))
733 return;
734
735 simple_mtx_destroy(&sscreen->aux_context_lock);
736
737 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
738 if (aux_log) {
739 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
740 u_log_context_destroy(aux_log);
741 FREE(aux_log);
742 }
743
744 sscreen->aux_context->destroy(sscreen->aux_context);
745
746 util_queue_destroy(&sscreen->shader_compiler_queue);
747 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
748
749 /* Release the reference on glsl types of the compiler threads. */
750 glsl_type_singleton_decref();
751
752 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
753 si_destroy_compiler(&sscreen->compiler[i]);
754
755 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
756 si_destroy_compiler(&sscreen->compiler_lowp[i]);
757
758 /* Free shader parts. */
759 for (i = 0; i < ARRAY_SIZE(parts); i++) {
760 while (parts[i]) {
761 struct si_shader_part *part = parts[i];
762
763 parts[i] = part->next;
764 si_shader_binary_clean(&part->binary);
765 FREE(part);
766 }
767 }
768 simple_mtx_destroy(&sscreen->shader_parts_mutex);
769 si_destroy_shader_cache(sscreen);
770
771 si_destroy_perfcounters(sscreen);
772 si_gpu_load_kill_thread(sscreen);
773
774 simple_mtx_destroy(&sscreen->gpu_load_mutex);
775
776 slab_destroy_parent(&sscreen->pool_transfers);
777
778 disk_cache_destroy(sscreen->disk_shader_cache);
779 sscreen->ws->destroy(sscreen->ws);
780 FREE(sscreen);
781 }
782
783 static void si_init_gs_info(struct si_screen *sscreen)
784 {
785 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
786 sscreen->info.family);
787 }
788
789 static void si_test_vmfault(struct si_screen *sscreen)
790 {
791 struct pipe_context *ctx = sscreen->aux_context;
792 struct si_context *sctx = (struct si_context *)ctx;
793 struct pipe_resource *buf =
794 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
795
796 if (!buf) {
797 puts("Buffer allocation failed.");
798 exit(1);
799 }
800
801 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
802
803 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
804 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
805 SI_COHERENCY_NONE, L2_BYPASS);
806 ctx->flush(ctx, NULL, 0);
807 puts("VM fault test: CP - done.");
808 }
809 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
810 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
811 ctx->flush(ctx, NULL, 0);
812 puts("VM fault test: SDMA - done.");
813 }
814 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
815 util_test_constant_buffer(ctx, buf);
816 puts("VM fault test: Shader - done.");
817 }
818 exit(0);
819 }
820
821 static void si_test_gds_memory_management(struct si_context *sctx,
822 unsigned alloc_size, unsigned alignment,
823 enum radeon_bo_domain domain)
824 {
825 struct radeon_winsys *ws = sctx->ws;
826 struct radeon_cmdbuf *cs[8];
827 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
828
829 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
830 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
831 NULL, NULL, false);
832 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
833 assert(gds_bo[i]);
834 }
835
836 for (unsigned iterations = 0; iterations < 20000; iterations++) {
837 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
838 /* This clears GDS with CP DMA.
839 *
840 * We don't care if GDS is present. Just add some packet
841 * to make the GPU busy for a moment.
842 */
843 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
844 SI_CPDMA_SKIP_BO_LIST_UPDATE |
845 SI_CPDMA_SKIP_CHECK_CS_SPACE |
846 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
847
848 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
849 RADEON_USAGE_READWRITE, 0);
850 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
851 }
852 }
853 exit(0);
854 }
855
856 static void si_disk_cache_create(struct si_screen *sscreen)
857 {
858 /* Don't use the cache if shader dumping is enabled. */
859 if (sscreen->debug_flags & DBG_ALL_SHADERS)
860 return;
861
862 struct mesa_sha1 ctx;
863 unsigned char sha1[20];
864 char cache_id[20 * 2 + 1];
865
866 _mesa_sha1_init(&ctx);
867
868 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
869 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
870 &ctx))
871 return;
872
873 _mesa_sha1_final(&ctx, sha1);
874 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
875
876 /* These flags affect shader compilation. */
877 #define ALL_FLAGS (DBG(SI_SCHED) | DBG(GISEL))
878 uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS;
879
880 /* Add the high bits of 32-bit addresses, which affects
881 * how 32-bit addresses are expanded to 64 bits.
882 */
883 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
884 assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
885 shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
886
887 sscreen->disk_shader_cache =
888 disk_cache_create(sscreen->info.name,
889 cache_id,
890 shader_debug_flags);
891 }
892
893 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen,
894 unsigned max_threads)
895 {
896 struct si_screen *sscreen = (struct si_screen *)screen;
897
898 /* This function doesn't allow a greater number of threads than
899 * the queue had at its creation. */
900 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue,
901 max_threads);
902 /* Don't change the number of threads on the low priority queue. */
903 }
904
905 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen,
906 void *shader,
907 enum pipe_shader_type shader_type)
908 {
909 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
910
911 return util_queue_fence_is_signalled(&sel->ready);
912 }
913
914 static struct pipe_screen *
915 radeonsi_screen_create_impl(struct radeon_winsys *ws,
916 const struct pipe_screen_config *config)
917 {
918 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
919 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i;
920
921 if (!sscreen) {
922 return NULL;
923 }
924
925 sscreen->ws = ws;
926 ws->query_info(ws, &sscreen->info);
927
928 if (sscreen->info.chip_class == GFX10 && LLVM_VERSION_MAJOR < 9) {
929 fprintf(stderr, "radeonsi: Navi family support requires LLVM 9 or higher\n");
930 FREE(sscreen);
931 return NULL;
932 }
933
934 if (sscreen->info.chip_class >= GFX9) {
935 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
936 } else {
937 ac_get_raster_config(&sscreen->info,
938 &sscreen->pa_sc_raster_config,
939 &sscreen->pa_sc_raster_config_1,
940 &sscreen->se_tile_repeat);
941 }
942
943 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
944 debug_options, 0);
945 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
946 debug_options, 0);
947
948 if (sscreen->debug_flags & DBG(NO_GFX))
949 sscreen->info.has_graphics = false;
950
951 /* Set functions first. */
952 sscreen->b.context_create = si_pipe_create_context;
953 sscreen->b.destroy = si_destroy_screen;
954 sscreen->b.set_max_shader_compiler_threads =
955 si_set_max_shader_compiler_threads;
956 sscreen->b.is_parallel_shader_compilation_finished =
957 si_is_parallel_shader_compilation_finished;
958
959 si_init_screen_get_functions(sscreen);
960 si_init_screen_buffer_functions(sscreen);
961 si_init_screen_fence_functions(sscreen);
962 si_init_screen_state_functions(sscreen);
963 si_init_screen_texture_functions(sscreen);
964 si_init_screen_query_functions(sscreen);
965
966 /* Set these flags in debug_flags early, so that the shader cache takes
967 * them into account.
968 */
969 if (driQueryOptionb(config->options,
970 "glsl_correct_derivatives_after_discard"))
971 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
972 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
973 sscreen->debug_flags |= DBG(SI_SCHED);
974
975 if (sscreen->debug_flags & DBG(INFO))
976 ac_print_gpu_info(&sscreen->info);
977
978 slab_create_parent(&sscreen->pool_transfers,
979 sizeof(struct si_transfer), 64);
980
981 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
982 if (sscreen->force_aniso == -1) {
983 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
984 }
985
986 if (sscreen->force_aniso >= 0) {
987 printf("radeonsi: Forcing anisotropy filter to %ix\n",
988 /* round down to a power of two */
989 1 << util_logbase2(sscreen->force_aniso));
990 }
991
992 (void) simple_mtx_init(&sscreen->aux_context_lock, mtx_plain);
993 (void) simple_mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
994
995 si_init_gs_info(sscreen);
996 if (!si_init_shader_cache(sscreen)) {
997 FREE(sscreen);
998 return NULL;
999 }
1000
1001 si_disk_cache_create(sscreen);
1002
1003 /* Determine the number of shader compiler threads. */
1004 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
1005
1006 if (hw_threads >= 12) {
1007 num_comp_hi_threads = hw_threads * 3 / 4;
1008 num_comp_lo_threads = hw_threads / 3;
1009 } else if (hw_threads >= 6) {
1010 num_comp_hi_threads = hw_threads - 2;
1011 num_comp_lo_threads = hw_threads / 2;
1012 } else if (hw_threads >= 2) {
1013 num_comp_hi_threads = hw_threads - 1;
1014 num_comp_lo_threads = hw_threads / 2;
1015 } else {
1016 num_comp_hi_threads = 1;
1017 num_comp_lo_threads = 1;
1018 }
1019
1020 num_comp_hi_threads = MIN2(num_comp_hi_threads,
1021 ARRAY_SIZE(sscreen->compiler));
1022 num_comp_lo_threads = MIN2(num_comp_lo_threads,
1023 ARRAY_SIZE(sscreen->compiler_lowp));
1024
1025 /* Take a reference on the glsl types for the compiler threads. */
1026 glsl_type_singleton_init_or_ref();
1027
1028 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
1029 64, num_comp_hi_threads,
1030 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1031 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
1032 si_destroy_shader_cache(sscreen);
1033 FREE(sscreen);
1034 glsl_type_singleton_decref();
1035 return NULL;
1036 }
1037
1038 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1039 "shlo",
1040 64, num_comp_lo_threads,
1041 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1042 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
1043 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1044 si_destroy_shader_cache(sscreen);
1045 FREE(sscreen);
1046 glsl_type_singleton_decref();
1047 return NULL;
1048 }
1049
1050 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1051 si_init_perfcounters(sscreen);
1052
1053 /* Determine tessellation ring info. */
1054 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
1055 sscreen->info.family != CHIP_CARRIZO &&
1056 sscreen->info.family != CHIP_STONEY;
1057 /* This must be one less than the maximum number due to a hw limitation.
1058 * Various hardware bugs need this.
1059 */
1060 unsigned max_offchip_buffers_per_se;
1061
1062 if (sscreen->info.chip_class >= GFX10)
1063 max_offchip_buffers_per_se = 256;
1064 /* Only certain chips can use the maximum value. */
1065 else if (sscreen->info.family == CHIP_VEGA12 ||
1066 sscreen->info.family == CHIP_VEGA20)
1067 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1068 else
1069 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1070
1071 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1072 sscreen->info.max_se;
1073 unsigned offchip_granularity;
1074
1075 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1076 * around by setting 4K granularity.
1077 */
1078 if (sscreen->info.family == CHIP_HAWAII) {
1079 sscreen->tess_offchip_block_dw_size = 4096;
1080 offchip_granularity = V_03093C_X_4K_DWORDS;
1081 } else {
1082 sscreen->tess_offchip_block_dw_size = 8192;
1083 offchip_granularity = V_03093C_X_8K_DWORDS;
1084 }
1085
1086 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
1087 sscreen->tess_offchip_ring_size = max_offchip_buffers *
1088 sscreen->tess_offchip_block_dw_size * 4;
1089
1090 if (sscreen->info.chip_class >= GFX7) {
1091 if (sscreen->info.chip_class >= GFX8)
1092 --max_offchip_buffers;
1093 sscreen->vgt_hs_offchip_param =
1094 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1095 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1096 } else {
1097 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1098 sscreen->vgt_hs_offchip_param =
1099 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1100 }
1101
1102 sscreen->has_draw_indirect_multi =
1103 (sscreen->info.family >= CHIP_POLARIS10) ||
1104 (sscreen->info.chip_class == GFX8 &&
1105 sscreen->info.pfp_fw_version >= 121 &&
1106 sscreen->info.me_fw_version >= 87) ||
1107 (sscreen->info.chip_class == GFX7 &&
1108 sscreen->info.pfp_fw_version >= 211 &&
1109 sscreen->info.me_fw_version >= 173) ||
1110 (sscreen->info.chip_class == GFX6 &&
1111 sscreen->info.pfp_fw_version >= 79 &&
1112 sscreen->info.me_fw_version >= 142);
1113
1114 sscreen->has_out_of_order_rast = sscreen->info.has_out_of_order_rast &&
1115 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1116 sscreen->assume_no_z_fights =
1117 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1118 sscreen->commutative_blend_add =
1119 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1120
1121 {
1122 #define OPT_BOOL(name, dflt, description) \
1123 sscreen->options.name = \
1124 driQueryOptionb(config->options, "radeonsi_"#name);
1125 #include "si_debug_options.h"
1126 }
1127
1128 sscreen->use_ngg = sscreen->info.chip_class >= GFX10 &&
1129 sscreen->info.family != CHIP_NAVI14 &&
1130 !(sscreen->debug_flags & DBG(NO_NGG));
1131 sscreen->use_ngg_streamout = false;
1132
1133 /* Only enable primitive binning on APUs by default. */
1134 if (sscreen->info.chip_class >= GFX10) {
1135 sscreen->dpbb_allowed = true;
1136 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1137 } else if (sscreen->info.chip_class == GFX9) {
1138 sscreen->dpbb_allowed = !sscreen->info.has_dedicated_vram;
1139 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1140 }
1141
1142 /* Process DPBB enable flags. */
1143 if (sscreen->debug_flags & DBG(DPBB)) {
1144 sscreen->dpbb_allowed = true;
1145 if (sscreen->debug_flags & DBG(DFSM))
1146 sscreen->dfsm_allowed = true;
1147 }
1148
1149 /* Process DPBB disable flags. */
1150 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1151 sscreen->dpbb_allowed = false;
1152 sscreen->dfsm_allowed = false;
1153 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1154 sscreen->dfsm_allowed = false;
1155 }
1156
1157 /* While it would be nice not to have this flag, we are constrained
1158 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1159 */
1160 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9;
1161
1162 sscreen->dcc_msaa_allowed =
1163 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1164
1165 (void) simple_mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1166 sscreen->use_monolithic_shaders =
1167 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1168
1169 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE |
1170 SI_CONTEXT_INV_VCACHE;
1171 if (sscreen->info.chip_class <= GFX8) {
1172 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2;
1173 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2;
1174 }
1175
1176 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1177 sscreen->debug_flags |= DBG_ALL_SHADERS;
1178
1179 /* Syntax:
1180 * EQAA=s,z,c
1181 * Example:
1182 * EQAA=8,4,2
1183
1184 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1185 * Constraints:
1186 * s >= z >= c (ignoring this only wastes memory)
1187 * s = [2..16]
1188 * z = [2..8]
1189 * c = [2..8]
1190 *
1191 * Only MSAA color and depth buffers are overriden.
1192 */
1193 if (sscreen->info.has_eqaa_surface_allocator) {
1194 const char *eqaa = debug_get_option("EQAA", NULL);
1195 unsigned s,z,f;
1196
1197 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1198 sscreen->eqaa_force_coverage_samples = s;
1199 sscreen->eqaa_force_z_samples = z;
1200 sscreen->eqaa_force_color_samples = f;
1201 }
1202 }
1203
1204 for (i = 0; i < num_comp_hi_threads; i++)
1205 si_init_compiler(sscreen, &sscreen->compiler[i]);
1206 for (i = 0; i < num_comp_lo_threads; i++)
1207 si_init_compiler(sscreen, &sscreen->compiler_lowp[i]);
1208
1209 sscreen->ge_wave_size = 64;
1210 sscreen->ps_wave_size = 64;
1211 sscreen->compute_wave_size = 64;
1212
1213 if (sscreen->info.chip_class >= GFX10) {
1214 /* Pixels shaders: Wave64 is recommended.
1215 * Compute shaders: There are piglit failures with Wave32.
1216 */
1217 sscreen->ge_wave_size = 32;
1218
1219 if (sscreen->debug_flags & DBG(W32_GE))
1220 sscreen->ge_wave_size = 32;
1221 if (sscreen->debug_flags & DBG(W32_PS))
1222 sscreen->ps_wave_size = 32;
1223 if (sscreen->debug_flags & DBG(W32_CS))
1224 sscreen->compute_wave_size = 32;
1225
1226 if (sscreen->debug_flags & DBG(W64_GE))
1227 sscreen->ge_wave_size = 64;
1228 if (sscreen->debug_flags & DBG(W64_PS))
1229 sscreen->ps_wave_size = 64;
1230 if (sscreen->debug_flags & DBG(W64_CS))
1231 sscreen->compute_wave_size = 64;
1232 }
1233
1234 /* Create the auxiliary context. This must be done last. */
1235 sscreen->aux_context = si_create_context(&sscreen->b,
1236 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
1237 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
1238 if (sscreen->options.aux_debug) {
1239 struct u_log_context *log = CALLOC_STRUCT(u_log_context);
1240 u_log_context_init(log);
1241 sscreen->aux_context->set_log_context(sscreen->aux_context, log);
1242 }
1243
1244 if (sscreen->debug_flags & DBG(TEST_DMA))
1245 si_test_dma(sscreen);
1246
1247 if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) {
1248 si_test_dma_perf(sscreen);
1249 }
1250
1251 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1252 DBG(TEST_VMFAULT_SDMA) |
1253 DBG(TEST_VMFAULT_SHADER)))
1254 si_test_vmfault(sscreen);
1255
1256 if (sscreen->debug_flags & DBG(TEST_GDS))
1257 si_test_gds((struct si_context*)sscreen->aux_context);
1258
1259 if (sscreen->debug_flags & DBG(TEST_GDS_MM)) {
1260 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1261 32 * 1024, 4, RADEON_DOMAIN_GDS);
1262 }
1263 if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) {
1264 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1265 4, 1, RADEON_DOMAIN_OA);
1266 }
1267
1268 return &sscreen->b;
1269 }
1270
1271 struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config)
1272 {
1273 drmVersionPtr version = drmGetVersion(fd);
1274 struct radeon_winsys *rw = NULL;
1275
1276 switch (version->version_major) {
1277 case 2:
1278 rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl);
1279 break;
1280 case 3:
1281 rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl);
1282 break;
1283 }
1284
1285 drmFreeVersion(version);
1286 return rw ? rw->screen : NULL;
1287 }