src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_shader.h"
  26 #include "si_public.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_llvm_emit.h"
  30 #include "radeon/radeon_uvd.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_suballoc.h"
  33 #include "vl/vl_decoder.h"
  34
  35 #define SI_LLVM_DEFAULT_FEATURES \
  36         "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals"
  37
  38 /*
  39  * pipe_context
  40  */
  41 static void si_destroy_context(struct pipe_context *context)
  42 {
  43         struct si_context *sctx = (struct si_context *)context;
  44         int i;
  45
  46         si_dec_framebuffer_counters(&sctx->framebuffer.state);
  47
  48         si_release_all_descriptors(sctx);
  49
  50         if (sctx->ce_suballocator)
  51                 u_suballocator_destroy(sctx->ce_suballocator);
  52
  53         pipe_resource_reference(&sctx->esgs_ring, NULL);
  54         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  55         pipe_resource_reference(&sctx->tf_ring, NULL);
  56         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  57         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  58         r600_resource_reference(&sctx->border_color_buffer, NULL);
  59         free(sctx->border_color_table);
  60         r600_resource_reference(&sctx->scratch_buffer, NULL);
  61         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  62         sctx->b.ws->fence_reference(&sctx->last_gfx_fence, NULL);
  63
  64         si_pm4_free_state(sctx, sctx->init_config, ~0);
  65         if (sctx->init_config_gs_rings)
  66                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  67         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  68                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  69
  70         if (sctx->fixed_func_tcs_shader.cso)
  71                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  72         if (sctx->custom_dsa_flush)
  73                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  74         if (sctx->custom_blend_resolve)
  75                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  76         if (sctx->custom_blend_decompress)
  77                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  78         if (sctx->custom_blend_fastclear)
  79                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  80         if (sctx->custom_blend_dcc_decompress)
  81                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  82         util_unreference_framebuffer_state(&sctx->framebuffer.state);
  83
  84         if (sctx->blitter)
  85                 util_blitter_destroy(sctx->blitter);
  86
  87         r600_common_context_cleanup(&sctx->b);
  88
  89         LLVMDisposeTargetMachine(sctx->tm);
  90
  91         r600_resource_reference(&sctx->trace_buf, NULL);
  92         r600_resource_reference(&sctx->last_trace_buf, NULL);
  93         radeon_clear_saved_cs(&sctx->last_gfx);
  94
  95         FREE(sctx);
  96 }
  97
  98 static enum pipe_reset_status
  99 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 100 {
 101         struct si_context *sctx = (struct si_context *)ctx;
 102
 103         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 104 }
 105
 106 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 107                                               void *priv, unsigned flags)
 108 {
 109         struct si_context *sctx = CALLOC_STRUCT(si_context);
 110         struct si_screen* sscreen = (struct si_screen *)screen;
 111         struct radeon_winsys *ws = sscreen->b.ws;
 112         LLVMTargetRef r600_target;
 113         const char *triple = "amdgcn--";
 114         int shader, i;
 115
 116         if (!sctx)
 117                 return NULL;
 118
 119         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 120                 flags |= PIPE_CONTEXT_DEBUG;
 121
 122         sctx->b.b.screen = screen; /* this must be set first */
 123         sctx->b.b.priv = priv;
 124         sctx->b.b.destroy = si_destroy_context;
 125         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 126         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 127         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 128
 129         if (!r600_common_context_init(&sctx->b, &sscreen->b))
 130                 goto fail;
 131
 132         if (sscreen->b.info.drm_major == 3)
 133                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 134
 135         si_init_blit_functions(sctx);
 136         si_init_compute_functions(sctx);
 137         si_init_cp_dma_functions(sctx);
 138         si_init_debug_functions(sctx);
 139
 140         if (sscreen->b.info.has_uvd) {
 141                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 142                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 143         } else {
 144                 sctx->b.b.create_video_codec = vl_create_decoder;
 145                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 146         }
 147
 148         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 149                                        si_context_gfx_flush, sctx);
 150
 151         if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib) {
 152                 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
 153                 if (!sctx->ce_ib)
 154                         goto fail;
 155
 156                 if (ws->cs_add_const_preamble_ib) {
 157                         sctx->ce_preamble_ib =
 158                                    ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
 159
 160                         if (!sctx->ce_preamble_ib)
 161                                 goto fail;
 162                 }
 163
 164                 sctx->ce_suballocator =
 165                                 u_suballocator_create(&sctx->b.b, 1024 * 1024,
 166                                                       PIPE_BIND_CUSTOM,
 167                                                       PIPE_USAGE_DEFAULT, FALSE);
 168                 if (!sctx->ce_suballocator)
 169                         goto fail;
 170         }
 171
 172         sctx->b.gfx.flush = si_context_gfx_flush;
 173
 174         /* Border colors. */
 175         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 176                                           sizeof(*sctx->border_color_table));
 177         if (!sctx->border_color_table)
 178                 goto fail;
 179
 180         sctx->border_color_buffer = (struct r600_resource*)
 181                 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
 182                                    SI_MAX_BORDER_COLORS *
 183                                    sizeof(*sctx->border_color_table));
 184         if (!sctx->border_color_buffer)
 185                 goto fail;
 186
 187         sctx->border_color_map =
 188                 ws->buffer_map(sctx->border_color_buffer->buf,
 189                                NULL, PIPE_TRANSFER_WRITE);
 190         if (!sctx->border_color_map)
 191                 goto fail;
 192
 193         si_init_all_descriptors(sctx);
 194         si_init_state_functions(sctx);
 195         si_init_shader_functions(sctx);
 196
 197         if (sctx->b.chip_class >= CIK)
 198                 cik_init_sdma_functions(sctx);
 199         else
 200                 si_init_dma_functions(sctx);
 201
 202         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 203                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 204
 205         sctx->blitter = util_blitter_create(&sctx->b.b);
 206         if (sctx->blitter == NULL)
 207                 goto fail;
 208         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 209
 210         sctx->sample_mask.sample_mask = 0xffff;
 211
 212         /* these must be last */
 213         si_begin_new_cs(sctx);
 214         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 215
 216         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 217          * with a NULL buffer). We need to use a dummy buffer instead. */
 218         if (sctx->b.chip_class == CIK) {
 219                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 220                                                                  PIPE_USAGE_DEFAULT, 16);
 221                 if (!sctx->null_const_buf.buffer)
 222                         goto fail;
 223                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 224
 225                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 226                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 227                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 228                                                               &sctx->null_const_buf);
 229                         }
 230                 }
 231
 232                 /* Clear the NULL constant buffer, because loads should return zeros. */
 233                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 234                                      sctx->null_const_buf.buffer->width0, 0,
 235                                      R600_COHERENCY_SHADER);
 236         }
 237
 238         uint64_t max_threads_per_block;
 239         screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
 240                                   PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 241                                   &max_threads_per_block);
 242
 243         /* The maximum number of scratch waves. Scratch space isn't divided
 244          * evenly between CUs. The number is only a function of the number of CUs.
 245          * We can decrease the constant to decrease the scratch buffer size.
 246          *
 247          * sctx->scratch_waves must be >= the maximum posible size of
 248          * 1 threadgroup, so that the hw doesn't hang from being unable
 249          * to start any.
 250          *
 251          * The recommended value is 4 per CU at most. Higher numbers don't
 252          * bring much benefit, but they still occupy chip resources (think
 253          * async compute). I've seen ~2% performance difference between 4 and 32.
 254          */
 255         sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
 256                                    max_threads_per_block / 64);
 257
 258         /* Initialize LLVM TargetMachine */
 259         r600_target = radeon_llvm_get_r600_target(triple);
 260         sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
 261                                            r600_get_llvm_processor_name(sscreen->b.family),
 262 #if HAVE_LLVM >= 0x0308
 263                                            sscreen->b.debug_flags & DBG_SI_SCHED ?
 264                                                 SI_LLVM_DEFAULT_FEATURES ",+si-scheduler" :
 265 #endif
 266                                                 SI_LLVM_DEFAULT_FEATURES,
 267                                            LLVMCodeGenLevelDefault,
 268                                            LLVMRelocDefault,
 269                                            LLVMCodeModelDefault);
 270
 271         return &sctx->b.b;
 272 fail:
 273         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 274         si_destroy_context(&sctx->b.b);
 275         return NULL;
 276 }
 277
 278 /*
 279  * pipe_screen
 280  */
 281
 282 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 283 {
 284         struct si_screen *sscreen = (struct si_screen *)pscreen;
 285
 286         switch (param) {
 287         /* Supported features (boolean caps). */
 288         case PIPE_CAP_TWO_SIDED_STENCIL:
 289         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 290         case PIPE_CAP_ANISOTROPIC_FILTER:
 291         case PIPE_CAP_POINT_SPRITE:
 292         case PIPE_CAP_OCCLUSION_QUERY:
 293         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 294         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 295         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 296         case PIPE_CAP_TEXTURE_SWIZZLE:
 297         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 298         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 299         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 300         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 301         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 302         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 303         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 304         case PIPE_CAP_SM3:
 305         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 306         case PIPE_CAP_PRIMITIVE_RESTART:
 307         case PIPE_CAP_CONDITIONAL_RENDER:
 308         case PIPE_CAP_TEXTURE_BARRIER:
 309         case PIPE_CAP_INDEP_BLEND_ENABLE:
 310         case PIPE_CAP_INDEP_BLEND_FUNC:
 311         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 312         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 313         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 314         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 315         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 316         case PIPE_CAP_USER_INDEX_BUFFERS:
 317         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 318         case PIPE_CAP_START_INSTANCE:
 319         case PIPE_CAP_NPOT_TEXTURES:
 320         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 321         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 322         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 323         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 324         case PIPE_CAP_TGSI_INSTANCEID:
 325         case PIPE_CAP_COMPUTE:
 326         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 327         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 328         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 329         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 330         case PIPE_CAP_CUBE_MAP_ARRAY:
 331         case PIPE_CAP_SAMPLE_SHADING:
 332         case PIPE_CAP_DRAW_INDIRECT:
 333         case PIPE_CAP_CLIP_HALFZ:
 334         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 335         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 336         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 337         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 338         case PIPE_CAP_TGSI_TEXCOORD:
 339         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 340         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 341         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 342         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 343         case PIPE_CAP_SHAREABLE_SHADERS:
 344         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 345         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 346         case PIPE_CAP_TEXTURE_QUERY_LOD:
 347         case PIPE_CAP_TEXTURE_GATHER_SM5:
 348         case PIPE_CAP_TGSI_TXQS:
 349         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 350         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 351         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 352         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 353         case PIPE_CAP_INVALIDATE_BUFFER:
 354         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 355         case PIPE_CAP_QUERY_MEMORY_INFO:
 356         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 357         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 358         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 359         case PIPE_CAP_GENERATE_MIPMAP:
 360         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 361                 return 1;
 362
 363         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 364                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 365
 366         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 367                 return (sscreen->b.info.drm_major == 2 &&
 368                         sscreen->b.info.drm_minor >= 43) ||
 369                        sscreen->b.info.drm_major == 3;
 370
 371         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 372                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 373                 return sscreen->b.chip_class < CIK ||
 374                        (sscreen->b.info.drm_major == 2 &&
 375                         sscreen->b.info.drm_minor >= 35) ||
 376                        sscreen->b.info.drm_major == 3;
 377
 378         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 379                 return R600_MAP_BUFFER_ALIGNMENT;
 380
 381         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 382         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 383         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 384                 return 4;
 385         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 386                 return HAVE_LLVM >= 0x0309 ? 4 : 0;
 387
 388         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 389                 if (pscreen->get_shader_param(pscreen, PIPE_SHADER_COMPUTE,
 390                                               PIPE_SHADER_CAP_SUPPORTED_IRS) &
 391                     (1 << PIPE_SHADER_IR_TGSI))
 392                         return 430;
 393                 return HAVE_LLVM >= 0x0309 ? 420 :
 394                        HAVE_LLVM >= 0x0307 ? 410 : 330;
 395
 396         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 397                 return MIN2(sscreen->b.info.vram_size, 0xFFFFFFFF);
 398
 399         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 400                 return 0;
 401
 402         /* Unsupported features. */
 403         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 404         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 405         case PIPE_CAP_USER_VERTEX_BUFFERS:
 406         case PIPE_CAP_FAKE_SW_MSAA:
 407         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 408         case PIPE_CAP_VERTEXID_NOBASE:
 409         case PIPE_CAP_CLEAR_TEXTURE:
 410         case PIPE_CAP_DRAW_PARAMETERS:
 411         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 412         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 413         case PIPE_CAP_STRING_MARKER:
 414         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 415         case PIPE_CAP_CULL_DISTANCE:
 416         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 417         case PIPE_CAP_TGSI_VOTE:
 418         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 419                 return 0;
 420
 421         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 422                 return 30;
 423
 424         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 425                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 426
 427         /* Stream output. */
 428         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 429                 return sscreen->b.has_streamout ? 4 : 0;
 430         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 431                 return sscreen->b.has_streamout ? 1 : 0;
 432         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 433         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 434                 return sscreen->b.has_streamout ? 32*4 : 0;
 435
 436         /* Geometry shader output. */
 437         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 438                 return 1024;
 439         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 440                 return 4095;
 441         case PIPE_CAP_MAX_VERTEX_STREAMS:
 442                 return 4;
 443
 444         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 445                 return 2048;
 446
 447         /* Texturing. */
 448         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 449         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 450                 return 15; /* 16384 */
 451         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 452                 /* textures support 8192, but layered rendering supports 2048 */
 453                 return 12;
 454         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 455                 /* textures support 8192, but layered rendering supports 2048 */
 456                 return 2048;
 457
 458         /* Render targets. */
 459         case PIPE_CAP_MAX_RENDER_TARGETS:
 460                 return 8;
 461
 462         case PIPE_CAP_MAX_VIEWPORTS:
 463                 return R600_MAX_VIEWPORTS;
 464
 465         /* Timer queries, present when the clock frequency is non zero. */
 466         case PIPE_CAP_QUERY_TIMESTAMP:
 467         case PIPE_CAP_QUERY_TIME_ELAPSED:
 468                 return sscreen->b.info.clock_crystal_freq != 0;
 469
 470         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 471         case PIPE_CAP_MIN_TEXEL_OFFSET:
 472                 return -32;
 473
 474         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 475         case PIPE_CAP_MAX_TEXEL_OFFSET:
 476                 return 31;
 477
 478         case PIPE_CAP_ENDIANNESS:
 479                 return PIPE_ENDIAN_LITTLE;
 480
 481         case PIPE_CAP_VENDOR_ID:
 482                 return ATI_VENDOR_ID;
 483         case PIPE_CAP_DEVICE_ID:
 484                 return sscreen->b.info.pci_id;
 485         case PIPE_CAP_ACCELERATED:
 486                 return 1;
 487         case PIPE_CAP_VIDEO_MEMORY:
 488                 return sscreen->b.info.vram_size >> 20;
 489         case PIPE_CAP_UMA:
 490                 return 0;
 491         case PIPE_CAP_PCI_GROUP:
 492                 return sscreen->b.info.pci_domain;
 493         case PIPE_CAP_PCI_BUS:
 494                 return sscreen->b.info.pci_bus;
 495         case PIPE_CAP_PCI_DEVICE:
 496                 return sscreen->b.info.pci_dev;
 497         case PIPE_CAP_PCI_FUNCTION:
 498                 return sscreen->b.info.pci_func;
 499         }
 500         return 0;
 501 }
 502
 503 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 504 {
 505         struct si_screen *sscreen = (struct si_screen *)pscreen;
 506
 507         switch(shader)
 508         {
 509         case PIPE_SHADER_FRAGMENT:
 510         case PIPE_SHADER_VERTEX:
 511         case PIPE_SHADER_GEOMETRY:
 512                 break;
 513         case PIPE_SHADER_TESS_CTRL:
 514         case PIPE_SHADER_TESS_EVAL:
 515                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 516                 if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
 517                         return 0;
 518                 break;
 519         case PIPE_SHADER_COMPUTE:
 520                 switch (param) {
 521                 case PIPE_SHADER_CAP_PREFERRED_IR:
 522                         return PIPE_SHADER_IR_NATIVE;
 523
 524                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 525                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 526
 527                         /* Old kernels disallowed some register writes for SI
 528                          * that are used for indirect dispatches. */
 529                         if (HAVE_LLVM >= 0x309 && (sscreen->b.chip_class >= CIK ||
 530                                                    sscreen->b.info.drm_major == 3 ||
 531                                                    (sscreen->b.info.drm_major == 2 &&
 532                                                     sscreen->b.info.drm_minor >= 45)))
 533                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 534
 535                         return ir;
 536                 }
 537                 case PIPE_SHADER_CAP_DOUBLES:
 538                         return HAVE_LLVM >= 0x0307;
 539
 540                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 541                         uint64_t max_const_buffer_size;
 542                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 543                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 544                                 &max_const_buffer_size);
 545                         return max_const_buffer_size;
 546                 }
 547                 default:
 548                         /* If compute shaders don't require a special value
 549                          * for this cap, we can return the same value we
 550                          * do for other shader types. */
 551                         break;
 552                 }
 553                 break;
 554         default:
 555                 return 0;
 556         }
 557
 558         switch (param) {
 559         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 560         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 561         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 562         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 563                 return 16384;
 564         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 565                 return 32;
 566         case PIPE_SHADER_CAP_MAX_INPUTS:
 567                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 568         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 569                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 570         case PIPE_SHADER_CAP_MAX_TEMPS:
 571                 return 256; /* Max native temporaries. */
 572         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 573                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 574         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 575                 return SI_NUM_CONST_BUFFERS;
 576         case PIPE_SHADER_CAP_MAX_PREDS:
 577                 return 0; /* FIXME */
 578         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 579                 return 1;
 580         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 581                 return 1;
 582         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 583                 /* Indirection of geometry shader input dimension is not
 584                  * handled yet
 585                  */
 586                 return shader != PIPE_SHADER_GEOMETRY;
 587         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 588         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 589         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 590                 return 1;
 591         case PIPE_SHADER_CAP_INTEGERS:
 592                 return 1;
 593         case PIPE_SHADER_CAP_SUBROUTINES:
 594                 return 0;
 595         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 596         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 597                 return SI_NUM_SAMPLERS;
 598         case PIPE_SHADER_CAP_PREFERRED_IR:
 599                 return PIPE_SHADER_IR_TGSI;
 600         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 601                 return 0;
 602         case PIPE_SHADER_CAP_DOUBLES:
 603                 return HAVE_LLVM >= 0x0307;
 604         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 605         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 606                 return 0;
 607         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 608         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 609                 return 1;
 610         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 611                 return 32;
 612         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 613                 return HAVE_LLVM >= 0x0309 ? SI_NUM_SHADER_BUFFERS : 0;
 614         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 615                 return HAVE_LLVM >= 0x0309 ? SI_NUM_IMAGES : 0;
 616         }
 617         return 0;
 618 }
 619
 620 static void si_destroy_screen(struct pipe_screen* pscreen)
 621 {
 622         struct si_screen *sscreen = (struct si_screen *)pscreen;
 623         struct si_shader_part *parts[] = {
 624                 sscreen->vs_prologs,
 625                 sscreen->vs_epilogs,
 626                 sscreen->tcs_epilogs,
 627                 sscreen->ps_prologs,
 628                 sscreen->ps_epilogs
 629         };
 630         unsigned i;
 631
 632         if (!sscreen)
 633                 return;
 634
 635         if (!sscreen->b.ws->unref(sscreen->b.ws))
 636                 return;
 637
 638         /* Free shader parts. */
 639         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 640                 while (parts[i]) {
 641                         struct si_shader_part *part = parts[i];
 642
 643                         parts[i] = part->next;
 644                         radeon_shader_binary_clean(&part->binary);
 645                         FREE(part);
 646                 }
 647         }
 648         pipe_mutex_destroy(sscreen->shader_parts_mutex);
 649         si_destroy_shader_cache(sscreen);
 650         r600_destroy_common_screen(&sscreen->b);
 651 }
 652
 653 static bool si_init_gs_info(struct si_screen *sscreen)
 654 {
 655         switch (sscreen->b.family) {
 656         case CHIP_OLAND:
 657         case CHIP_HAINAN:
 658         case CHIP_KAVERI:
 659         case CHIP_KABINI:
 660         case CHIP_MULLINS:
 661         case CHIP_ICELAND:
 662         case CHIP_CARRIZO:
 663         case CHIP_STONEY:
 664                 sscreen->gs_table_depth = 16;
 665                 return true;
 666         case CHIP_TAHITI:
 667         case CHIP_PITCAIRN:
 668         case CHIP_VERDE:
 669         case CHIP_BONAIRE:
 670         case CHIP_HAWAII:
 671         case CHIP_TONGA:
 672         case CHIP_FIJI:
 673         case CHIP_POLARIS10:
 674         case CHIP_POLARIS11:
 675                 sscreen->gs_table_depth = 32;
 676                 return true;
 677         default:
 678                 return false;
 679         }
 680 }
 681
 682 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 683 {
 684         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 685
 686         if (!sscreen) {
 687                 return NULL;
 688         }
 689
 690         /* Set functions first. */
 691         sscreen->b.b.context_create = si_create_context;
 692         sscreen->b.b.destroy = si_destroy_screen;
 693         sscreen->b.b.get_param = si_get_param;
 694         sscreen->b.b.get_shader_param = si_get_shader_param;
 695         sscreen->b.b.is_format_supported = si_is_format_supported;
 696         sscreen->b.b.resource_create = r600_resource_create_common;
 697
 698         si_init_screen_state_functions(sscreen);
 699
 700         if (!r600_common_screen_init(&sscreen->b, ws) ||
 701             !si_init_gs_info(sscreen) ||
 702             !si_init_shader_cache(sscreen)) {
 703                 FREE(sscreen);
 704                 return NULL;
 705         }
 706
 707         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", FALSE))
 708                 si_init_perfcounters(sscreen);
 709
 710         sscreen->b.has_cp_dma = true;
 711         sscreen->b.has_streamout = true;
 712         pipe_mutex_init(sscreen->shader_parts_mutex);
 713         sscreen->use_monolithic_shaders =
 714                 HAVE_LLVM < 0x0308 ||
 715                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
 716
 717         if (debug_get_bool_option("RADEON_DUMP_SHADERS", FALSE))
 718                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 719
 720         /* Create the auxiliary context. This must be done last. */
 721         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 722
 723         if (sscreen->b.debug_flags & DBG_TEST_DMA)
 724                 r600_test_dma(&sscreen->b);
 725
 726         return &sscreen->b.b;
 727 }