2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
32 #include "ac_llvm_util.h"
33 #include "radeon/radeon_uvd.h"
34 #include "gallivm/lp_bld_misc.h"
35 #include "util/disk_cache.h"
36 #include "util/u_log.h"
37 #include "util/u_memory.h"
38 #include "util/u_suballoc.h"
39 #include "util/u_tests.h"
40 #include "util/u_upload_mgr.h"
41 #include "util/xmlconfig.h"
42 #include "vl/vl_decoder.h"
43 #include "driver_ddebug/dd_util.h"
45 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
46 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
49 static const struct debug_named_value debug_options
[] = {
50 /* Shader logging options: */
51 { "vs", DBG(VS
), "Print vertex shaders" },
52 { "ps", DBG(PS
), "Print pixel shaders" },
53 { "gs", DBG(GS
), "Print geometry shaders" },
54 { "tcs", DBG(TCS
), "Print tessellation control shaders" },
55 { "tes", DBG(TES
), "Print tessellation evaluation shaders" },
56 { "cs", DBG(CS
), "Print compute shaders" },
57 { "noir", DBG(NO_IR
), "Don't print the LLVM IR"},
58 { "notgsi", DBG(NO_TGSI
), "Don't print the TGSI"},
59 { "noasm", DBG(NO_ASM
), "Don't print disassembled shaders"},
60 { "preoptir", DBG(PREOPT_IR
), "Print the LLVM IR before initial optimizations" },
62 /* Shader compiler options the shader cache should be aware of: */
63 { "unsafemath", DBG(UNSAFE_MATH
), "Enable unsafe math shader optimizations" },
64 { "sisched", DBG(SI_SCHED
), "Enable LLVM SI Machine Instruction Scheduler." },
65 { "gisel", DBG(GISEL
), "Enable LLVM global instruction selector." },
67 /* Shader compiler options (with no effect on the shader cache): */
68 { "checkir", DBG(CHECK_IR
), "Enable additional sanity checks on shader IR" },
69 { "mono", DBG(MONOLITHIC_SHADERS
), "Use old-style monolithic shaders compiled on demand" },
70 { "nooptvariant", DBG(NO_OPT_VARIANT
), "Disable compiling optimized shader variants." },
72 /* Information logging options: */
73 { "info", DBG(INFO
), "Print driver information" },
74 { "tex", DBG(TEX
), "Print texture info" },
75 { "compute", DBG(COMPUTE
), "Print compute info" },
76 { "vm", DBG(VM
), "Print virtual addresses when creating resources" },
79 { "forcedma", DBG(FORCE_DMA
), "Use asynchronous DMA for all operations when possible." },
80 { "nodma", DBG(NO_ASYNC_DMA
), "Disable asynchronous DMA" },
81 { "nowc", DBG(NO_WC
), "Disable GTT write combining" },
82 { "check_vm", DBG(CHECK_VM
), "Check VM faults and dump debug info." },
83 { "reserve_vmid", DBG(RESERVE_VMID
), "Force VMID reservation per context." },
84 { "zerovram", DBG(ZERO_VRAM
), "Clear VRAM allocations." },
86 /* 3D engine options: */
87 { "alwayspd", DBG(ALWAYS_PD
), "Always enable the primitive discard compute shader." },
88 { "pd", DBG(PD
), "Enable the primitive discard compute shader for large draw calls." },
89 { "nopd", DBG(NO_PD
), "Disable the primitive discard compute shader." },
90 { "switch_on_eop", DBG(SWITCH_ON_EOP
), "Program WD/IA to switch on end-of-packet." },
91 { "nooutoforder", DBG(NO_OUT_OF_ORDER
), "Disable out-of-order rasterization" },
92 { "nodpbb", DBG(NO_DPBB
), "Disable DPBB." },
93 { "nodfsm", DBG(NO_DFSM
), "Disable DFSM." },
94 { "dpbb", DBG(DPBB
), "Enable DPBB." },
95 { "dfsm", DBG(DFSM
), "Enable DFSM." },
96 { "nohyperz", DBG(NO_HYPERZ
), "Disable Hyper-Z" },
97 { "norbplus", DBG(NO_RB_PLUS
), "Disable RB+." },
98 { "no2d", DBG(NO_2D_TILING
), "Disable 2D tiling" },
99 { "notiling", DBG(NO_TILING
), "Disable tiling" },
100 { "nodcc", DBG(NO_DCC
), "Disable DCC." },
101 { "nodccclear", DBG(NO_DCC_CLEAR
), "Disable DCC fast clear." },
102 { "nodccfb", DBG(NO_DCC_FB
), "Disable separate DCC on the main framebuffer" },
103 { "nodccmsaa", DBG(NO_DCC_MSAA
), "Disable DCC for MSAA" },
104 { "nofmask", DBG(NO_FMASK
), "Disable MSAA compression" },
107 { "testdma", DBG(TEST_DMA
), "Invoke SDMA tests and exit." },
108 { "testvmfaultcp", DBG(TEST_VMFAULT_CP
), "Invoke a CP VM fault test and exit." },
109 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA
), "Invoke a SDMA VM fault test and exit." },
110 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER
), "Invoke a shader VM fault test and exit." },
111 { "testdmaperf", DBG(TEST_DMA_PERF
), "Test DMA performance" },
112 { "testgds", DBG(TEST_GDS
), "Test GDS." },
113 { "testgdsmm", DBG(TEST_GDS_MM
), "Test GDS memory management." },
114 { "testgdsoamm", DBG(TEST_GDS_OA_MM
), "Test GDS OA memory management." },
116 DEBUG_NAMED_VALUE_END
/* must be last */
119 static void si_init_compiler(struct si_screen
*sscreen
,
120 struct ac_llvm_compiler
*compiler
)
122 /* Only create the less-optimizing version of the compiler on APUs
123 * predating Ryzen (Raven). */
124 bool create_low_opt_compiler
= !sscreen
->info
.has_dedicated_vram
&&
125 sscreen
->info
.chip_class
<= GFX8
;
127 enum ac_target_machine_options tm_options
=
128 (sscreen
->debug_flags
& DBG(SI_SCHED
) ? AC_TM_SISCHED
: 0) |
129 (sscreen
->debug_flags
& DBG(GISEL
) ? AC_TM_ENABLE_GLOBAL_ISEL
: 0) |
130 (sscreen
->info
.chip_class
>= GFX9
? AC_TM_FORCE_ENABLE_XNACK
: 0) |
131 (sscreen
->info
.chip_class
< GFX9
? AC_TM_FORCE_DISABLE_XNACK
: 0) |
132 (!sscreen
->llvm_has_working_vgpr_indexing
? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH
: 0) |
133 (sscreen
->debug_flags
& DBG(CHECK_IR
) ? AC_TM_CHECK_IR
: 0) |
134 (create_low_opt_compiler
? AC_TM_CREATE_LOW_OPT
: 0);
137 ac_init_llvm_compiler(compiler
, sscreen
->info
.family
, tm_options
);
138 compiler
->passes
= ac_create_llvm_passes(compiler
->tm
);
140 if (compiler
->low_opt_tm
)
141 compiler
->low_opt_passes
= ac_create_llvm_passes(compiler
->low_opt_tm
);
144 static void si_destroy_compiler(struct ac_llvm_compiler
*compiler
)
146 ac_destroy_llvm_passes(compiler
->passes
);
147 ac_destroy_llvm_passes(compiler
->low_opt_passes
);
148 ac_destroy_llvm_compiler(compiler
);
154 static void si_destroy_context(struct pipe_context
*context
)
156 struct si_context
*sctx
= (struct si_context
*)context
;
159 util_queue_finish(&sctx
->screen
->shader_compiler_queue
);
160 util_queue_finish(&sctx
->screen
->shader_compiler_queue_low_priority
);
162 /* Unreference the framebuffer normally to disable related logic
165 struct pipe_framebuffer_state fb
= {};
166 if (context
->set_framebuffer_state
)
167 context
->set_framebuffer_state(context
, &fb
);
169 si_release_all_descriptors(sctx
);
171 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
172 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
173 pipe_resource_reference(&sctx
->tess_rings
, NULL
);
174 pipe_resource_reference(&sctx
->null_const_buf
.buffer
, NULL
);
175 pipe_resource_reference(&sctx
->sample_pos_buffer
, NULL
);
176 si_resource_reference(&sctx
->border_color_buffer
, NULL
);
177 free(sctx
->border_color_table
);
178 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
179 si_resource_reference(&sctx
->compute_scratch_buffer
, NULL
);
180 si_resource_reference(&sctx
->wait_mem_scratch
, NULL
);
182 si_pm4_free_state(sctx
, sctx
->init_config
, ~0);
183 if (sctx
->init_config_gs_rings
)
184 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
185 for (i
= 0; i
< ARRAY_SIZE(sctx
->vgt_shader_config
); i
++)
186 si_pm4_delete_state(sctx
, vgt_shader_config
, sctx
->vgt_shader_config
[i
]);
188 if (sctx
->fixed_func_tcs_shader
.cso
)
189 sctx
->b
.delete_tcs_state(&sctx
->b
, sctx
->fixed_func_tcs_shader
.cso
);
190 if (sctx
->custom_dsa_flush
)
191 sctx
->b
.delete_depth_stencil_alpha_state(&sctx
->b
, sctx
->custom_dsa_flush
);
192 if (sctx
->custom_blend_resolve
)
193 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_resolve
);
194 if (sctx
->custom_blend_fmask_decompress
)
195 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_fmask_decompress
);
196 if (sctx
->custom_blend_eliminate_fastclear
)
197 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_eliminate_fastclear
);
198 if (sctx
->custom_blend_dcc_decompress
)
199 sctx
->b
.delete_blend_state(&sctx
->b
, sctx
->custom_blend_dcc_decompress
);
200 if (sctx
->vs_blit_pos
)
201 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos
);
202 if (sctx
->vs_blit_pos_layered
)
203 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_pos_layered
);
204 if (sctx
->vs_blit_color
)
205 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color
);
206 if (sctx
->vs_blit_color_layered
)
207 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_color_layered
);
208 if (sctx
->vs_blit_texcoord
)
209 sctx
->b
.delete_vs_state(&sctx
->b
, sctx
->vs_blit_texcoord
);
210 if (sctx
->cs_clear_buffer
)
211 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_buffer
);
212 if (sctx
->cs_copy_buffer
)
213 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_buffer
);
214 if (sctx
->cs_copy_image
)
215 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_image
);
216 if (sctx
->cs_copy_image_1d_array
)
217 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_copy_image_1d_array
);
218 if (sctx
->cs_clear_render_target
)
219 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_render_target
);
220 if (sctx
->cs_clear_render_target_1d_array
)
221 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_clear_render_target_1d_array
);
222 if (sctx
->cs_dcc_retile
)
223 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->cs_dcc_retile
);
226 util_blitter_destroy(sctx
->blitter
);
228 /* Release DCC stats. */
229 for (int i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
230 assert(!sctx
->dcc_stats
[i
].query_active
);
232 for (int j
= 0; j
< ARRAY_SIZE(sctx
->dcc_stats
[i
].ps_stats
); j
++)
233 if (sctx
->dcc_stats
[i
].ps_stats
[j
])
234 sctx
->b
.destroy_query(&sctx
->b
,
235 sctx
->dcc_stats
[i
].ps_stats
[j
]);
237 si_texture_reference(&sctx
->dcc_stats
[i
].tex
, NULL
);
240 if (sctx
->query_result_shader
)
241 sctx
->b
.delete_compute_state(&sctx
->b
, sctx
->query_result_shader
);
244 sctx
->ws
->cs_destroy(sctx
->gfx_cs
);
246 sctx
->ws
->cs_destroy(sctx
->dma_cs
);
248 sctx
->ws
->ctx_destroy(sctx
->ctx
);
250 if (sctx
->b
.stream_uploader
)
251 u_upload_destroy(sctx
->b
.stream_uploader
);
252 if (sctx
->b
.const_uploader
)
253 u_upload_destroy(sctx
->b
.const_uploader
);
254 if (sctx
->cached_gtt_allocator
)
255 u_upload_destroy(sctx
->cached_gtt_allocator
);
257 slab_destroy_child(&sctx
->pool_transfers
);
258 slab_destroy_child(&sctx
->pool_transfers_unsync
);
260 if (sctx
->allocator_zeroed_memory
)
261 u_suballocator_destroy(sctx
->allocator_zeroed_memory
);
263 sctx
->ws
->fence_reference(&sctx
->last_gfx_fence
, NULL
);
264 sctx
->ws
->fence_reference(&sctx
->last_sdma_fence
, NULL
);
265 sctx
->ws
->fence_reference(&sctx
->last_ib_barrier_fence
, NULL
);
266 si_resource_reference(&sctx
->eop_bug_scratch
, NULL
);
267 si_resource_reference(&sctx
->index_ring
, NULL
);
268 si_resource_reference(&sctx
->barrier_buf
, NULL
);
269 si_resource_reference(&sctx
->last_ib_barrier_buf
, NULL
);
270 pb_reference(&sctx
->gds
, NULL
);
271 pb_reference(&sctx
->gds_oa
, NULL
);
273 si_destroy_compiler(&sctx
->compiler
);
275 si_saved_cs_reference(&sctx
->current_saved_cs
, NULL
);
277 _mesa_hash_table_destroy(sctx
->tex_handles
, NULL
);
278 _mesa_hash_table_destroy(sctx
->img_handles
, NULL
);
280 util_dynarray_fini(&sctx
->resident_tex_handles
);
281 util_dynarray_fini(&sctx
->resident_img_handles
);
282 util_dynarray_fini(&sctx
->resident_tex_needs_color_decompress
);
283 util_dynarray_fini(&sctx
->resident_img_needs_color_decompress
);
284 util_dynarray_fini(&sctx
->resident_tex_needs_depth_decompress
);
285 si_unref_sdma_uploads(sctx
);
289 static enum pipe_reset_status
si_get_reset_status(struct pipe_context
*ctx
)
291 struct si_context
*sctx
= (struct si_context
*)ctx
;
293 return sctx
->ws
->ctx_query_reset_status(sctx
->ctx
);
296 static void si_set_device_reset_callback(struct pipe_context
*ctx
,
297 const struct pipe_device_reset_callback
*cb
)
299 struct si_context
*sctx
= (struct si_context
*)ctx
;
302 sctx
->device_reset_callback
= *cb
;
304 memset(&sctx
->device_reset_callback
, 0,
305 sizeof(sctx
->device_reset_callback
));
308 bool si_check_device_reset(struct si_context
*sctx
)
310 enum pipe_reset_status status
;
312 if (!sctx
->device_reset_callback
.reset
)
315 status
= sctx
->ws
->ctx_query_reset_status(sctx
->ctx
);
316 if (status
== PIPE_NO_RESET
)
319 sctx
->device_reset_callback
.reset(sctx
->device_reset_callback
.data
, status
);
323 /* Apitrace profiling:
324 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
325 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
326 * and remember its number.
327 * 3) In Mesa, enable queries and performance counters around that draw
328 * call and print the results.
329 * 4) glretrace --benchmark --markers ..
331 static void si_emit_string_marker(struct pipe_context
*ctx
,
332 const char *string
, int len
)
334 struct si_context
*sctx
= (struct si_context
*)ctx
;
336 dd_parse_apitrace_marker(string
, len
, &sctx
->apitrace_call_number
);
339 u_log_printf(sctx
->log
, "\nString marker: %*s\n", len
, string
);
342 static void si_set_debug_callback(struct pipe_context
*ctx
,
343 const struct pipe_debug_callback
*cb
)
345 struct si_context
*sctx
= (struct si_context
*)ctx
;
346 struct si_screen
*screen
= sctx
->screen
;
348 util_queue_finish(&screen
->shader_compiler_queue
);
349 util_queue_finish(&screen
->shader_compiler_queue_low_priority
);
354 memset(&sctx
->debug
, 0, sizeof(sctx
->debug
));
357 static void si_set_log_context(struct pipe_context
*ctx
,
358 struct u_log_context
*log
)
360 struct si_context
*sctx
= (struct si_context
*)ctx
;
364 u_log_add_auto_logger(log
, si_auto_log_cs
, sctx
);
367 static void si_set_context_param(struct pipe_context
*ctx
,
368 enum pipe_context_param param
,
371 struct radeon_winsys
*ws
= ((struct si_context
*)ctx
)->ws
;
374 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE
:
375 ws
->pin_threads_to_L3_cache(ws
, value
);
381 static struct pipe_context
*si_create_context(struct pipe_screen
*screen
,
384 struct si_context
*sctx
= CALLOC_STRUCT(si_context
);
385 struct si_screen
* sscreen
= (struct si_screen
*)screen
;
386 struct radeon_winsys
*ws
= sscreen
->ws
;
388 bool stop_exec_on_failure
= (flags
& PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET
) != 0;
393 sctx
->has_graphics
= sscreen
->info
.chip_class
== GFX6
||
394 !(flags
& PIPE_CONTEXT_COMPUTE_ONLY
);
396 if (flags
& PIPE_CONTEXT_DEBUG
)
397 sscreen
->record_llvm_ir
= true; /* racy but not critical */
399 sctx
->b
.screen
= screen
; /* this must be set first */
401 sctx
->b
.destroy
= si_destroy_context
;
402 sctx
->screen
= sscreen
; /* Easy accessing of screen/winsys. */
403 sctx
->is_debug
= (flags
& PIPE_CONTEXT_DEBUG
) != 0;
405 slab_create_child(&sctx
->pool_transfers
, &sscreen
->pool_transfers
);
406 slab_create_child(&sctx
->pool_transfers_unsync
, &sscreen
->pool_transfers
);
408 sctx
->ws
= sscreen
->ws
;
409 sctx
->family
= sscreen
->info
.family
;
410 sctx
->chip_class
= sscreen
->info
.chip_class
;
412 if (sctx
->chip_class
== GFX7
||
413 sctx
->chip_class
== GFX8
||
414 sctx
->chip_class
== GFX9
) {
415 sctx
->eop_bug_scratch
= si_resource(
416 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
417 16 * sscreen
->info
.num_render_backends
));
418 if (!sctx
->eop_bug_scratch
)
422 /* Initialize context allocators. */
423 sctx
->allocator_zeroed_memory
=
424 u_suballocator_create(&sctx
->b
, 128 * 1024,
425 0, PIPE_USAGE_DEFAULT
,
426 SI_RESOURCE_FLAG_UNMAPPABLE
|
427 SI_RESOURCE_FLAG_CLEAR
, false);
428 if (!sctx
->allocator_zeroed_memory
)
431 sctx
->b
.stream_uploader
= u_upload_create(&sctx
->b
, 1024 * 1024,
432 0, PIPE_USAGE_STREAM
,
433 SI_RESOURCE_FLAG_READ_ONLY
);
434 if (!sctx
->b
.stream_uploader
)
437 sctx
->cached_gtt_allocator
= u_upload_create(&sctx
->b
, 16 * 1024,
438 0, PIPE_USAGE_STAGING
, 0);
439 if (!sctx
->cached_gtt_allocator
)
442 sctx
->ctx
= sctx
->ws
->ctx_create(sctx
->ws
);
446 if (sscreen
->info
.num_sdma_rings
&& !(sscreen
->debug_flags
& DBG(NO_ASYNC_DMA
))) {
447 sctx
->dma_cs
= sctx
->ws
->cs_create(sctx
->ctx
, RING_DMA
,
448 (void*)si_flush_dma_cs
,
449 sctx
, stop_exec_on_failure
);
452 bool use_sdma_upload
= sscreen
->info
.has_dedicated_vram
&& sctx
->dma_cs
;
453 sctx
->b
.const_uploader
= u_upload_create(&sctx
->b
, 256 * 1024,
454 0, PIPE_USAGE_DEFAULT
,
455 SI_RESOURCE_FLAG_32BIT
|
457 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA
:
458 (sscreen
->cpdma_prefetch_writes_memory
?
459 0 : SI_RESOURCE_FLAG_READ_ONLY
)));
460 if (!sctx
->b
.const_uploader
)
464 u_upload_enable_flush_explicit(sctx
->b
.const_uploader
);
466 sctx
->gfx_cs
= ws
->cs_create(sctx
->ctx
,
467 sctx
->has_graphics
? RING_GFX
: RING_COMPUTE
,
468 (void*)si_flush_gfx_cs
, sctx
, stop_exec_on_failure
);
471 sctx
->border_color_table
= malloc(SI_MAX_BORDER_COLORS
*
472 sizeof(*sctx
->border_color_table
));
473 if (!sctx
->border_color_table
)
476 sctx
->border_color_buffer
= si_resource(
477 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
,
478 SI_MAX_BORDER_COLORS
*
479 sizeof(*sctx
->border_color_table
)));
480 if (!sctx
->border_color_buffer
)
483 sctx
->border_color_map
=
484 ws
->buffer_map(sctx
->border_color_buffer
->buf
,
485 NULL
, PIPE_TRANSFER_WRITE
);
486 if (!sctx
->border_color_map
)
489 /* Initialize context functions used by graphics and compute. */
490 sctx
->emit_cache_flush
= si_emit_cache_flush
;
491 sctx
->b
.emit_string_marker
= si_emit_string_marker
;
492 sctx
->b
.set_debug_callback
= si_set_debug_callback
;
493 sctx
->b
.set_log_context
= si_set_log_context
;
494 sctx
->b
.set_context_param
= si_set_context_param
;
495 sctx
->b
.get_device_reset_status
= si_get_reset_status
;
496 sctx
->b
.set_device_reset_callback
= si_set_device_reset_callback
;
498 si_init_all_descriptors(sctx
);
499 si_init_buffer_functions(sctx
);
500 si_init_clear_functions(sctx
);
501 si_init_blit_functions(sctx
);
502 si_init_compute_functions(sctx
);
503 si_init_compute_blit_functions(sctx
);
504 si_init_debug_functions(sctx
);
505 si_init_fence_functions(sctx
);
506 si_init_query_functions(sctx
);
507 si_init_state_compute_functions(sctx
);
509 /* Initialize graphics-only context functions. */
510 if (sctx
->has_graphics
) {
511 si_init_context_texture_functions(sctx
);
512 si_init_msaa_functions(sctx
);
513 si_init_shader_functions(sctx
);
514 si_init_state_functions(sctx
);
515 si_init_streamout_functions(sctx
);
516 si_init_viewport_functions(sctx
);
518 sctx
->blitter
= util_blitter_create(&sctx
->b
);
519 if (sctx
->blitter
== NULL
)
521 sctx
->blitter
->skip_viewport_restore
= true;
523 si_init_draw_functions(sctx
);
524 si_initialize_prim_discard_tunables(sctx
);
527 /* Initialize SDMA functions. */
528 if (sctx
->chip_class
>= GFX7
)
529 cik_init_sdma_functions(sctx
);
531 si_init_dma_functions(sctx
);
533 if (sscreen
->debug_flags
& DBG(FORCE_DMA
))
534 sctx
->b
.resource_copy_region
= sctx
->dma_copy
;
536 sctx
->sample_mask
= 0xffff;
538 /* Initialize multimedia functions. */
539 if (sscreen
->info
.has_hw_decode
) {
540 sctx
->b
.create_video_codec
= si_uvd_create_decoder
;
541 sctx
->b
.create_video_buffer
= si_video_buffer_create
;
543 sctx
->b
.create_video_codec
= vl_create_decoder
;
544 sctx
->b
.create_video_buffer
= vl_video_buffer_create
;
547 if (sctx
->chip_class
>= GFX9
) {
548 sctx
->wait_mem_scratch
= si_resource(
549 pipe_buffer_create(screen
, 0, PIPE_USAGE_DEFAULT
, 8));
550 if (!sctx
->wait_mem_scratch
)
553 /* Initialize the memory. */
554 si_cp_write_data(sctx
, sctx
->wait_mem_scratch
, 0, 4,
555 V_370_MEM
, V_370_ME
, &sctx
->wait_mem_number
);
558 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
559 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
560 if (sctx
->chip_class
== GFX7
) {
561 sctx
->null_const_buf
.buffer
=
562 pipe_aligned_buffer_create(screen
,
563 SI_RESOURCE_FLAG_32BIT
,
564 PIPE_USAGE_DEFAULT
, 16,
565 sctx
->screen
->info
.tcc_cache_line_size
);
566 if (!sctx
->null_const_buf
.buffer
)
568 sctx
->null_const_buf
.buffer_size
= sctx
->null_const_buf
.buffer
->width0
;
570 unsigned start_shader
= sctx
->has_graphics
? 0 : PIPE_SHADER_COMPUTE
;
571 for (shader
= start_shader
; shader
< SI_NUM_SHADERS
; shader
++) {
572 for (i
= 0; i
< SI_NUM_CONST_BUFFERS
; i
++) {
573 sctx
->b
.set_constant_buffer(&sctx
->b
, shader
, i
,
574 &sctx
->null_const_buf
);
578 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
,
579 &sctx
->null_const_buf
);
580 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
,
581 &sctx
->null_const_buf
);
582 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
,
583 &sctx
->null_const_buf
);
584 si_set_rw_buffer(sctx
, SI_PS_CONST_POLY_STIPPLE
,
585 &sctx
->null_const_buf
);
586 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
,
587 &sctx
->null_const_buf
);
590 uint64_t max_threads_per_block
;
591 screen
->get_compute_param(screen
, PIPE_SHADER_IR_TGSI
,
592 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
,
593 &max_threads_per_block
);
595 /* The maximum number of scratch waves. Scratch space isn't divided
596 * evenly between CUs. The number is only a function of the number of CUs.
597 * We can decrease the constant to decrease the scratch buffer size.
599 * sctx->scratch_waves must be >= the maximum posible size of
600 * 1 threadgroup, so that the hw doesn't hang from being unable
603 * The recommended value is 4 per CU at most. Higher numbers don't
604 * bring much benefit, but they still occupy chip resources (think
605 * async compute). I've seen ~2% performance difference between 4 and 32.
607 sctx
->scratch_waves
= MAX2(32 * sscreen
->info
.num_good_compute_units
,
608 max_threads_per_block
/ 64);
610 si_init_compiler(sscreen
, &sctx
->compiler
);
612 /* Bindless handles. */
613 sctx
->tex_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
614 _mesa_key_pointer_equal
);
615 sctx
->img_handles
= _mesa_hash_table_create(NULL
, _mesa_hash_pointer
,
616 _mesa_key_pointer_equal
);
618 util_dynarray_init(&sctx
->resident_tex_handles
, NULL
);
619 util_dynarray_init(&sctx
->resident_img_handles
, NULL
);
620 util_dynarray_init(&sctx
->resident_tex_needs_color_decompress
, NULL
);
621 util_dynarray_init(&sctx
->resident_img_needs_color_decompress
, NULL
);
622 util_dynarray_init(&sctx
->resident_tex_needs_depth_decompress
, NULL
);
624 sctx
->sample_pos_buffer
=
625 pipe_buffer_create(sctx
->b
.screen
, 0, PIPE_USAGE_DEFAULT
,
626 sizeof(sctx
->sample_positions
));
627 pipe_buffer_write(&sctx
->b
, sctx
->sample_pos_buffer
, 0,
628 sizeof(sctx
->sample_positions
), &sctx
->sample_positions
);
630 /* this must be last */
631 si_begin_new_gfx_cs(sctx
);
633 if (sctx
->chip_class
== GFX7
) {
634 /* Clear the NULL constant buffer, because loads should return zeros.
635 * Note that this forces CP DMA to be used, because clover deadlocks
636 * for some reason when the compute codepath is used.
638 uint32_t clear_value
= 0;
639 si_clear_buffer(sctx
, sctx
->null_const_buf
.buffer
, 0,
640 sctx
->null_const_buf
.buffer
->width0
,
641 &clear_value
, 4, SI_COHERENCY_SHADER
, true);
645 fprintf(stderr
, "radeonsi: Failed to create a context.\n");
646 si_destroy_context(&sctx
->b
);
650 static struct pipe_context
*si_pipe_create_context(struct pipe_screen
*screen
,
651 void *priv
, unsigned flags
)
653 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
654 struct pipe_context
*ctx
;
656 if (sscreen
->debug_flags
& DBG(CHECK_VM
))
657 flags
|= PIPE_CONTEXT_DEBUG
;
659 ctx
= si_create_context(screen
, flags
);
661 if (!(flags
& PIPE_CONTEXT_PREFER_THREADED
))
664 /* Clover (compute-only) is unsupported. */
665 if (flags
& PIPE_CONTEXT_COMPUTE_ONLY
)
668 /* When shaders are logged to stderr, asynchronous compilation is
670 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
673 /* Use asynchronous flushes only on amdgpu, since the radeon
674 * implementation for fence_server_sync is incomplete. */
675 return threaded_context_create(ctx
, &sscreen
->pool_transfers
,
676 si_replace_buffer_storage
,
677 sscreen
->info
.is_amdgpu
? si_create_fence
: NULL
,
678 &((struct si_context
*)ctx
)->tc
);
684 static void si_destroy_screen(struct pipe_screen
* pscreen
)
686 struct si_screen
*sscreen
= (struct si_screen
*)pscreen
;
687 struct si_shader_part
*parts
[] = {
689 sscreen
->tcs_epilogs
,
696 if (!sscreen
->ws
->unref(sscreen
->ws
))
699 mtx_destroy(&sscreen
->aux_context_lock
);
701 struct u_log_context
*aux_log
= ((struct si_context
*)sscreen
->aux_context
)->log
;
703 sscreen
->aux_context
->set_log_context(sscreen
->aux_context
, NULL
);
704 u_log_context_destroy(aux_log
);
708 sscreen
->aux_context
->destroy(sscreen
->aux_context
);
710 util_queue_destroy(&sscreen
->shader_compiler_queue
);
711 util_queue_destroy(&sscreen
->shader_compiler_queue_low_priority
);
713 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler
); i
++)
714 si_destroy_compiler(&sscreen
->compiler
[i
]);
716 for (i
= 0; i
< ARRAY_SIZE(sscreen
->compiler_lowp
); i
++)
717 si_destroy_compiler(&sscreen
->compiler_lowp
[i
]);
719 /* Free shader parts. */
720 for (i
= 0; i
< ARRAY_SIZE(parts
); i
++) {
722 struct si_shader_part
*part
= parts
[i
];
724 parts
[i
] = part
->next
;
725 si_shader_binary_clean(&part
->binary
);
729 mtx_destroy(&sscreen
->shader_parts_mutex
);
730 si_destroy_shader_cache(sscreen
);
732 si_destroy_perfcounters(sscreen
);
733 si_gpu_load_kill_thread(sscreen
);
735 mtx_destroy(&sscreen
->gpu_load_mutex
);
737 slab_destroy_parent(&sscreen
->pool_transfers
);
739 disk_cache_destroy(sscreen
->disk_shader_cache
);
740 sscreen
->ws
->destroy(sscreen
->ws
);
744 static void si_init_gs_info(struct si_screen
*sscreen
)
746 sscreen
->gs_table_depth
= ac_get_gs_table_depth(sscreen
->info
.chip_class
,
747 sscreen
->info
.family
);
750 static void si_test_vmfault(struct si_screen
*sscreen
)
752 struct pipe_context
*ctx
= sscreen
->aux_context
;
753 struct si_context
*sctx
= (struct si_context
*)ctx
;
754 struct pipe_resource
*buf
=
755 pipe_buffer_create_const0(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
, 64);
758 puts("Buffer allocation failed.");
762 si_resource(buf
)->gpu_address
= 0; /* cause a VM fault */
764 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_CP
)) {
765 si_cp_dma_copy_buffer(sctx
, buf
, buf
, 0, 4, 4, 0,
766 SI_COHERENCY_NONE
, L2_BYPASS
);
767 ctx
->flush(ctx
, NULL
, 0);
768 puts("VM fault test: CP - done.");
770 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SDMA
)) {
771 si_sdma_clear_buffer(sctx
, buf
, 0, 4, 0);
772 ctx
->flush(ctx
, NULL
, 0);
773 puts("VM fault test: SDMA - done.");
775 if (sscreen
->debug_flags
& DBG(TEST_VMFAULT_SHADER
)) {
776 util_test_constant_buffer(ctx
, buf
);
777 puts("VM fault test: Shader - done.");
782 static void si_test_gds_memory_management(struct si_context
*sctx
,
783 unsigned alloc_size
, unsigned alignment
,
784 enum radeon_bo_domain domain
)
786 struct radeon_winsys
*ws
= sctx
->ws
;
787 struct radeon_cmdbuf
*cs
[8];
788 struct pb_buffer
*gds_bo
[ARRAY_SIZE(cs
)];
790 for (unsigned i
= 0; i
< ARRAY_SIZE(cs
); i
++) {
791 cs
[i
] = ws
->cs_create(sctx
->ctx
, RING_COMPUTE
,
793 gds_bo
[i
] = ws
->buffer_create(ws
, alloc_size
, alignment
, domain
, 0);
797 for (unsigned iterations
= 0; iterations
< 20000; iterations
++) {
798 for (unsigned i
= 0; i
< ARRAY_SIZE(cs
); i
++) {
799 /* This clears GDS with CP DMA.
801 * We don't care if GDS is present. Just add some packet
802 * to make the GPU busy for a moment.
804 si_cp_dma_clear_buffer(sctx
, cs
[i
], NULL
, 0, alloc_size
, 0,
805 SI_CPDMA_SKIP_BO_LIST_UPDATE
|
806 SI_CPDMA_SKIP_CHECK_CS_SPACE
|
807 SI_CPDMA_SKIP_GFX_SYNC
, 0, 0);
809 ws
->cs_add_buffer(cs
[i
], gds_bo
[i
], domain
,
810 RADEON_USAGE_READWRITE
, 0);
811 ws
->cs_flush(cs
[i
], PIPE_FLUSH_ASYNC
, NULL
);
817 static void si_disk_cache_create(struct si_screen
*sscreen
)
819 /* Don't use the cache if shader dumping is enabled. */
820 if (sscreen
->debug_flags
& DBG_ALL_SHADERS
)
823 struct mesa_sha1 ctx
;
824 unsigned char sha1
[20];
825 char cache_id
[20 * 2 + 1];
827 _mesa_sha1_init(&ctx
);
829 if (!disk_cache_get_function_identifier(si_disk_cache_create
, &ctx
) ||
830 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
,
834 _mesa_sha1_final(&ctx
, sha1
);
835 disk_cache_format_hex_id(cache_id
, sha1
, 20 * 2);
837 /* These flags affect shader compilation. */
838 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
842 uint64_t shader_debug_flags
= sscreen
->debug_flags
&
845 /* Add the high bits of 32-bit addresses, which affects
846 * how 32-bit addresses are expanded to 64 bits.
848 STATIC_ASSERT(ALL_FLAGS
<= UINT_MAX
);
849 assert((int16_t)sscreen
->info
.address32_hi
== (int32_t)sscreen
->info
.address32_hi
);
850 shader_debug_flags
|= (uint64_t)(sscreen
->info
.address32_hi
& 0xffff) << 32;
852 if (sscreen
->options
.enable_nir
)
853 shader_debug_flags
|= 1ull << 48;
855 sscreen
->disk_shader_cache
=
856 disk_cache_create(sscreen
->info
.name
,
861 static void si_set_max_shader_compiler_threads(struct pipe_screen
*screen
,
862 unsigned max_threads
)
864 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
866 /* This function doesn't allow a greater number of threads than
867 * the queue had at its creation. */
868 util_queue_adjust_num_threads(&sscreen
->shader_compiler_queue
,
870 /* Don't change the number of threads on the low priority queue. */
873 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen
*screen
,
875 unsigned shader_type
)
877 if (shader_type
== PIPE_SHADER_COMPUTE
) {
878 struct si_compute
*cs
= (struct si_compute
*)shader
;
880 return util_queue_fence_is_signalled(&cs
->ready
);
882 struct si_shader_selector
*sel
= (struct si_shader_selector
*)shader
;
884 return util_queue_fence_is_signalled(&sel
->ready
);
887 static struct pipe_screen
*
888 radeonsi_screen_create_impl(struct radeon_winsys
*ws
,
889 const struct pipe_screen_config
*config
)
891 struct si_screen
*sscreen
= CALLOC_STRUCT(si_screen
);
892 unsigned hw_threads
, num_comp_hi_threads
, num_comp_lo_threads
, i
;
899 ws
->query_info(ws
, &sscreen
->info
);
901 if (sscreen
->info
.chip_class
== GFX10
&& HAVE_LLVM
< 0x0900) {
902 fprintf(stderr
, "radeonsi: Navi family support requires LLVM 9 or higher\n");
907 if (sscreen
->info
.chip_class
>= GFX9
) {
908 sscreen
->se_tile_repeat
= 32 * sscreen
->info
.max_se
;
910 ac_get_raster_config(&sscreen
->info
,
911 &sscreen
->pa_sc_raster_config
,
912 &sscreen
->pa_sc_raster_config_1
,
913 &sscreen
->se_tile_repeat
);
916 sscreen
->debug_flags
= debug_get_flags_option("R600_DEBUG",
918 sscreen
->debug_flags
|= debug_get_flags_option("AMD_DEBUG",
921 /* Set functions first. */
922 sscreen
->b
.context_create
= si_pipe_create_context
;
923 sscreen
->b
.destroy
= si_destroy_screen
;
924 sscreen
->b
.set_max_shader_compiler_threads
=
925 si_set_max_shader_compiler_threads
;
926 sscreen
->b
.is_parallel_shader_compilation_finished
=
927 si_is_parallel_shader_compilation_finished
;
929 si_init_screen_get_functions(sscreen
);
930 si_init_screen_buffer_functions(sscreen
);
931 si_init_screen_fence_functions(sscreen
);
932 si_init_screen_state_functions(sscreen
);
933 si_init_screen_texture_functions(sscreen
);
934 si_init_screen_query_functions(sscreen
);
936 /* Set these flags in debug_flags early, so that the shader cache takes
939 if (driQueryOptionb(config
->options
,
940 "glsl_correct_derivatives_after_discard"))
941 sscreen
->debug_flags
|= DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
942 if (driQueryOptionb(config
->options
, "radeonsi_enable_sisched"))
943 sscreen
->debug_flags
|= DBG(SI_SCHED
);
945 if (sscreen
->debug_flags
& DBG(INFO
))
946 ac_print_gpu_info(&sscreen
->info
);
948 slab_create_parent(&sscreen
->pool_transfers
,
949 sizeof(struct si_transfer
), 64);
951 sscreen
->force_aniso
= MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
952 if (sscreen
->force_aniso
== -1) {
953 sscreen
->force_aniso
= MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
956 if (sscreen
->force_aniso
>= 0) {
957 printf("radeonsi: Forcing anisotropy filter to %ix\n",
958 /* round down to a power of two */
959 1 << util_logbase2(sscreen
->force_aniso
));
962 (void) mtx_init(&sscreen
->aux_context_lock
, mtx_plain
);
963 (void) mtx_init(&sscreen
->gpu_load_mutex
, mtx_plain
);
965 si_init_gs_info(sscreen
);
966 if (!si_init_shader_cache(sscreen
)) {
971 si_disk_cache_create(sscreen
);
973 /* Determine the number of shader compiler threads. */
974 hw_threads
= sysconf(_SC_NPROCESSORS_ONLN
);
976 if (hw_threads
>= 12) {
977 num_comp_hi_threads
= hw_threads
* 3 / 4;
978 num_comp_lo_threads
= hw_threads
/ 3;
979 } else if (hw_threads
>= 6) {
980 num_comp_hi_threads
= hw_threads
- 2;
981 num_comp_lo_threads
= hw_threads
/ 2;
982 } else if (hw_threads
>= 2) {
983 num_comp_hi_threads
= hw_threads
- 1;
984 num_comp_lo_threads
= hw_threads
/ 2;
986 num_comp_hi_threads
= 1;
987 num_comp_lo_threads
= 1;
990 num_comp_hi_threads
= MIN2(num_comp_hi_threads
,
991 ARRAY_SIZE(sscreen
->compiler
));
992 num_comp_lo_threads
= MIN2(num_comp_lo_threads
,
993 ARRAY_SIZE(sscreen
->compiler_lowp
));
995 if (!util_queue_init(&sscreen
->shader_compiler_queue
, "sh",
996 64, num_comp_hi_threads
,
997 UTIL_QUEUE_INIT_RESIZE_IF_FULL
|
998 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY
)) {
999 si_destroy_shader_cache(sscreen
);
1004 if (!util_queue_init(&sscreen
->shader_compiler_queue_low_priority
,
1006 64, num_comp_lo_threads
,
1007 UTIL_QUEUE_INIT_RESIZE_IF_FULL
|
1008 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY
|
1009 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY
)) {
1010 si_destroy_shader_cache(sscreen
);
1015 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1016 si_init_perfcounters(sscreen
);
1018 /* Determine tessellation ring info. */
1019 bool double_offchip_buffers
= sscreen
->info
.chip_class
>= GFX7
&&
1020 sscreen
->info
.family
!= CHIP_CARRIZO
&&
1021 sscreen
->info
.family
!= CHIP_STONEY
;
1022 /* This must be one less than the maximum number due to a hw limitation.
1023 * Various hardware bugs need this.
1025 unsigned max_offchip_buffers_per_se
;
1027 /* Only certain chips can use the maximum value. */
1028 if (sscreen
->info
.family
== CHIP_VEGA12
||
1029 sscreen
->info
.family
== CHIP_VEGA20
)
1030 max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
1032 max_offchip_buffers_per_se
= double_offchip_buffers
? 127 : 63;
1034 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
1035 sscreen
->info
.max_se
;
1036 unsigned offchip_granularity
;
1038 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1039 * around by setting 4K granularity.
1041 if (sscreen
->info
.family
== CHIP_HAWAII
) {
1042 sscreen
->tess_offchip_block_dw_size
= 4096;
1043 offchip_granularity
= V_03093C_X_4K_DWORDS
;
1045 sscreen
->tess_offchip_block_dw_size
= 8192;
1046 offchip_granularity
= V_03093C_X_8K_DWORDS
;
1049 sscreen
->tess_factor_ring_size
= 32768 * sscreen
->info
.max_se
;
1050 assert(((sscreen
->tess_factor_ring_size
/ 4) & C_030938_SIZE
) == 0);
1051 sscreen
->tess_offchip_ring_size
= max_offchip_buffers
*
1052 sscreen
->tess_offchip_block_dw_size
* 4;
1054 if (sscreen
->info
.chip_class
>= GFX7
) {
1055 if (sscreen
->info
.chip_class
>= GFX8
)
1056 --max_offchip_buffers
;
1057 sscreen
->vgt_hs_offchip_param
=
1058 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
1059 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
1061 assert(offchip_granularity
== V_03093C_X_8K_DWORDS
);
1062 sscreen
->vgt_hs_offchip_param
=
1063 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
1066 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1067 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
1068 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.*/
1069 sscreen
->has_clear_state
= sscreen
->info
.chip_class
>= GFX7
&&
1070 sscreen
->info
.is_amdgpu
;
1072 sscreen
->has_distributed_tess
=
1073 sscreen
->info
.chip_class
>= GFX8
&&
1074 sscreen
->info
.max_se
>= 2;
1076 sscreen
->has_draw_indirect_multi
=
1077 (sscreen
->info
.family
>= CHIP_POLARIS10
) ||
1078 (sscreen
->info
.chip_class
== GFX8
&&
1079 sscreen
->info
.pfp_fw_version
>= 121 &&
1080 sscreen
->info
.me_fw_version
>= 87) ||
1081 (sscreen
->info
.chip_class
== GFX7
&&
1082 sscreen
->info
.pfp_fw_version
>= 211 &&
1083 sscreen
->info
.me_fw_version
>= 173) ||
1084 (sscreen
->info
.chip_class
== GFX6
&&
1085 sscreen
->info
.pfp_fw_version
>= 79 &&
1086 sscreen
->info
.me_fw_version
>= 142);
1088 sscreen
->has_out_of_order_rast
= sscreen
->info
.chip_class
>= GFX8
&&
1089 sscreen
->info
.max_se
>= 2 &&
1090 !(sscreen
->debug_flags
& DBG(NO_OUT_OF_ORDER
));
1091 sscreen
->assume_no_z_fights
=
1092 driQueryOptionb(config
->options
, "radeonsi_assume_no_z_fights");
1093 sscreen
->commutative_blend_add
=
1094 driQueryOptionb(config
->options
, "radeonsi_commutative_blend_add");
1097 #define OPT_BOOL(name, dflt, description) \
1098 sscreen->options.name = \
1099 driQueryOptionb(config->options, "radeonsi_"#name);
1100 #include "si_debug_options.h"
1103 sscreen
->has_gfx9_scissor_bug
= sscreen
->info
.family
== CHIP_VEGA10
||
1104 sscreen
->info
.family
== CHIP_RAVEN
;
1105 sscreen
->has_msaa_sample_loc_bug
= (sscreen
->info
.family
>= CHIP_POLARIS10
&&
1106 sscreen
->info
.family
<= CHIP_POLARIS12
) ||
1107 sscreen
->info
.family
== CHIP_VEGA10
||
1108 sscreen
->info
.family
== CHIP_RAVEN
;
1109 sscreen
->has_ls_vgpr_init_bug
= sscreen
->info
.family
== CHIP_VEGA10
||
1110 sscreen
->info
.family
== CHIP_RAVEN
;
1111 sscreen
->has_dcc_constant_encode
= sscreen
->info
.family
== CHIP_RAVEN2
;
1113 /* Only enable primitive binning on APUs by default. */
1114 sscreen
->dpbb_allowed
= sscreen
->info
.family
== CHIP_RAVEN
||
1115 sscreen
->info
.family
== CHIP_RAVEN2
;
1117 sscreen
->dfsm_allowed
= sscreen
->info
.family
== CHIP_RAVEN
||
1118 sscreen
->info
.family
== CHIP_RAVEN2
;
1120 /* Process DPBB enable flags. */
1121 if (sscreen
->debug_flags
& DBG(DPBB
)) {
1122 sscreen
->dpbb_allowed
= true;
1123 if (sscreen
->debug_flags
& DBG(DFSM
))
1124 sscreen
->dfsm_allowed
= true;
1127 /* Process DPBB disable flags. */
1128 if (sscreen
->debug_flags
& DBG(NO_DPBB
)) {
1129 sscreen
->dpbb_allowed
= false;
1130 sscreen
->dfsm_allowed
= false;
1131 } else if (sscreen
->debug_flags
& DBG(NO_DFSM
)) {
1132 sscreen
->dfsm_allowed
= false;
1135 /* While it would be nice not to have this flag, we are constrained
1136 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1139 sscreen
->llvm_has_working_vgpr_indexing
= sscreen
->info
.chip_class
<= GFX8
;
1141 /* Some chips have RB+ registers, but don't support RB+. Those must
1142 * always disable it.
1144 if (sscreen
->info
.family
== CHIP_STONEY
||
1145 sscreen
->info
.chip_class
>= GFX9
) {
1146 sscreen
->has_rbplus
= true;
1148 sscreen
->rbplus_allowed
=
1149 !(sscreen
->debug_flags
& DBG(NO_RB_PLUS
)) &&
1150 (sscreen
->info
.family
== CHIP_STONEY
||
1151 sscreen
->info
.family
== CHIP_VEGA12
||
1152 sscreen
->info
.family
== CHIP_RAVEN
||
1153 sscreen
->info
.family
== CHIP_RAVEN2
);
1156 sscreen
->dcc_msaa_allowed
=
1157 !(sscreen
->debug_flags
& DBG(NO_DCC_MSAA
));
1159 sscreen
->cpdma_prefetch_writes_memory
= sscreen
->info
.chip_class
<= GFX8
;
1161 (void) mtx_init(&sscreen
->shader_parts_mutex
, mtx_plain
);
1162 sscreen
->use_monolithic_shaders
=
1163 (sscreen
->debug_flags
& DBG(MONOLITHIC_SHADERS
)) != 0;
1165 sscreen
->barrier_flags
.cp_to_L2
= SI_CONTEXT_INV_SCACHE
|
1166 SI_CONTEXT_INV_VCACHE
;
1167 if (sscreen
->info
.chip_class
<= GFX8
) {
1168 sscreen
->barrier_flags
.cp_to_L2
|= SI_CONTEXT_INV_L2
;
1169 sscreen
->barrier_flags
.L2_to_cp
|= SI_CONTEXT_WB_L2
;
1172 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1173 sscreen
->debug_flags
|= DBG_ALL_SHADERS
;
1180 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1182 * s >= z >= c (ignoring this only wastes memory)
1187 * Only MSAA color and depth buffers are overriden.
1189 if (sscreen
->info
.has_eqaa_surface_allocator
) {
1190 const char *eqaa
= debug_get_option("EQAA", NULL
);
1193 if (eqaa
&& sscanf(eqaa
, "%u,%u,%u", &s
, &z
, &f
) == 3 && s
&& z
&& f
) {
1194 sscreen
->eqaa_force_coverage_samples
= s
;
1195 sscreen
->eqaa_force_z_samples
= z
;
1196 sscreen
->eqaa_force_color_samples
= f
;
1200 for (i
= 0; i
< num_comp_hi_threads
; i
++)
1201 si_init_compiler(sscreen
, &sscreen
->compiler
[i
]);
1202 for (i
= 0; i
< num_comp_lo_threads
; i
++)
1203 si_init_compiler(sscreen
, &sscreen
->compiler_lowp
[i
]);
1205 /* Create the auxiliary context. This must be done last. */
1206 sscreen
->aux_context
= si_create_context(
1207 &sscreen
->b
, sscreen
->options
.aux_debug
? PIPE_CONTEXT_DEBUG
: 0);
1208 if (sscreen
->options
.aux_debug
) {
1209 struct u_log_context
*log
= CALLOC_STRUCT(u_log_context
);
1210 u_log_context_init(log
);
1211 sscreen
->aux_context
->set_log_context(sscreen
->aux_context
, log
);
1214 if (sscreen
->debug_flags
& DBG(TEST_DMA
))
1215 si_test_dma(sscreen
);
1217 if (sscreen
->debug_flags
& DBG(TEST_DMA_PERF
)) {
1218 si_test_dma_perf(sscreen
);
1221 if (sscreen
->debug_flags
& (DBG(TEST_VMFAULT_CP
) |
1222 DBG(TEST_VMFAULT_SDMA
) |
1223 DBG(TEST_VMFAULT_SHADER
)))
1224 si_test_vmfault(sscreen
);
1226 if (sscreen
->debug_flags
& DBG(TEST_GDS
))
1227 si_test_gds((struct si_context
*)sscreen
->aux_context
);
1229 if (sscreen
->debug_flags
& DBG(TEST_GDS_MM
)) {
1230 si_test_gds_memory_management((struct si_context
*)sscreen
->aux_context
,
1231 32 * 1024, 4, RADEON_DOMAIN_GDS
);
1233 if (sscreen
->debug_flags
& DBG(TEST_GDS_OA_MM
)) {
1234 si_test_gds_memory_management((struct si_context
*)sscreen
->aux_context
,
1235 4, 1, RADEON_DOMAIN_OA
);
1241 struct pipe_screen
*radeonsi_screen_create(int fd
, const struct pipe_screen_config
*config
)
1243 drmVersionPtr version
= drmGetVersion(fd
);
1244 struct radeon_winsys
*rw
= NULL
;
1246 switch (version
->version_major
) {
1248 rw
= radeon_drm_winsys_create(fd
, config
, radeonsi_screen_create_impl
);
1251 rw
= amdgpu_winsys_create(fd
, config
, radeonsi_screen_create_impl
);
1255 drmFreeVersion(version
);
1256 return rw
? rw
->screen
: NULL
;