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radeonsi: use compute for resource_copy_region when possible
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "sid.h"
30
31 #include "ac_llvm_util.h"
32 #include "radeon/radeon_uvd.h"
33 #include "gallivm/lp_bld_misc.h"
34 #include "util/disk_cache.h"
35 #include "util/u_log.h"
36 #include "util/u_memory.h"
37 #include "util/u_suballoc.h"
38 #include "util/u_tests.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/xmlconfig.h"
41 #include "vl/vl_decoder.h"
42 #include "driver_ddebug/dd_util.h"
43
44 static const struct debug_named_value debug_options[] = {
45 /* Shader logging options: */
46 { "vs", DBG(VS), "Print vertex shaders" },
47 { "ps", DBG(PS), "Print pixel shaders" },
48 { "gs", DBG(GS), "Print geometry shaders" },
49 { "tcs", DBG(TCS), "Print tessellation control shaders" },
50 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
51 { "cs", DBG(CS), "Print compute shaders" },
52 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
53 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
54 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
55 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
56
57 /* Shader compiler options the shader cache should be aware of: */
58 { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" },
59 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
60 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
61
62 /* Shader compiler options (with no effect on the shader cache): */
63 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
64 { "nir", DBG(NIR), "Enable experimental NIR shaders" },
65 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
66 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
67
68 /* Information logging options: */
69 { "info", DBG(INFO), "Print driver information" },
70 { "tex", DBG(TEX), "Print texture info" },
71 { "compute", DBG(COMPUTE), "Print compute info" },
72 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
73
74 /* Driver options: */
75 { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." },
76 { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
77 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
78 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
79 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
80 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
81
82 /* 3D engine options: */
83 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
84 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
85 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
86 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
87 { "dpbb", DBG(DPBB), "Enable DPBB." },
88 { "dfsm", DBG(DFSM), "Enable DFSM." },
89 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
90 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
91 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
92 { "notiling", DBG(NO_TILING), "Disable tiling" },
93 { "nodcc", DBG(NO_DCC), "Disable DCC." },
94 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
95 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
96 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
97 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
98
99 /* Tests: */
100 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
101 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
102 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
103 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
104 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
105 { "testgds", DBG(TEST_GDS), "Test GDS." },
106 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
107 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
108
109 DEBUG_NAMED_VALUE_END /* must be last */
110 };
111
112 static void si_init_compiler(struct si_screen *sscreen,
113 struct ac_llvm_compiler *compiler)
114 {
115 /* Only create the less-optimizing version of the compiler on APUs
116 * predating Ryzen (Raven). */
117 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
118 sscreen->info.chip_class <= VI;
119
120 enum ac_target_machine_options tm_options =
121 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
122 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
123 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
124 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
125 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
126 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
127 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
128
129 ac_init_llvm_once();
130 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
131 compiler->passes = ac_create_llvm_passes(compiler->tm);
132
133 if (compiler->low_opt_tm)
134 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
135 }
136
137 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
138 {
139 ac_destroy_llvm_passes(compiler->passes);
140 ac_destroy_llvm_passes(compiler->low_opt_passes);
141 ac_destroy_llvm_compiler(compiler);
142 }
143
144 /*
145 * pipe_context
146 */
147 static void si_destroy_context(struct pipe_context *context)
148 {
149 struct si_context *sctx = (struct si_context *)context;
150 int i;
151
152 /* Unreference the framebuffer normally to disable related logic
153 * properly.
154 */
155 struct pipe_framebuffer_state fb = {};
156 if (context->set_framebuffer_state)
157 context->set_framebuffer_state(context, &fb);
158
159 si_release_all_descriptors(sctx);
160
161 pipe_resource_reference(&sctx->esgs_ring, NULL);
162 pipe_resource_reference(&sctx->gsvs_ring, NULL);
163 pipe_resource_reference(&sctx->tess_rings, NULL);
164 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
165 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
166 r600_resource_reference(&sctx->border_color_buffer, NULL);
167 free(sctx->border_color_table);
168 r600_resource_reference(&sctx->scratch_buffer, NULL);
169 r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
170 r600_resource_reference(&sctx->wait_mem_scratch, NULL);
171
172 si_pm4_free_state(sctx, sctx->init_config, ~0);
173 if (sctx->init_config_gs_rings)
174 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
175 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
176 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
177
178 if (sctx->fixed_func_tcs_shader.cso)
179 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
180 if (sctx->custom_dsa_flush)
181 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
182 if (sctx->custom_blend_resolve)
183 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
184 if (sctx->custom_blend_fmask_decompress)
185 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
186 if (sctx->custom_blend_eliminate_fastclear)
187 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
188 if (sctx->custom_blend_dcc_decompress)
189 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
190 if (sctx->vs_blit_pos)
191 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
192 if (sctx->vs_blit_pos_layered)
193 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
194 if (sctx->vs_blit_color)
195 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
196 if (sctx->vs_blit_color_layered)
197 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
198 if (sctx->vs_blit_texcoord)
199 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
200 if (sctx->cs_clear_buffer)
201 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
202 if (sctx->cs_copy_buffer)
203 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
204 if (sctx->cs_copy_image)
205 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
206 if (sctx->cs_copy_image_1d_array)
207 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
208
209 if (sctx->blitter)
210 util_blitter_destroy(sctx->blitter);
211
212 /* Release DCC stats. */
213 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
214 assert(!sctx->dcc_stats[i].query_active);
215
216 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
217 if (sctx->dcc_stats[i].ps_stats[j])
218 sctx->b.destroy_query(&sctx->b,
219 sctx->dcc_stats[i].ps_stats[j]);
220
221 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
222 }
223
224 if (sctx->query_result_shader)
225 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
226
227 if (sctx->gfx_cs)
228 sctx->ws->cs_destroy(sctx->gfx_cs);
229 if (sctx->dma_cs)
230 sctx->ws->cs_destroy(sctx->dma_cs);
231 if (sctx->ctx)
232 sctx->ws->ctx_destroy(sctx->ctx);
233
234 if (sctx->b.stream_uploader)
235 u_upload_destroy(sctx->b.stream_uploader);
236 if (sctx->b.const_uploader)
237 u_upload_destroy(sctx->b.const_uploader);
238 if (sctx->cached_gtt_allocator)
239 u_upload_destroy(sctx->cached_gtt_allocator);
240
241 slab_destroy_child(&sctx->pool_transfers);
242 slab_destroy_child(&sctx->pool_transfers_unsync);
243
244 if (sctx->allocator_zeroed_memory)
245 u_suballocator_destroy(sctx->allocator_zeroed_memory);
246
247 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
248 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
249 r600_resource_reference(&sctx->eop_bug_scratch, NULL);
250
251 si_destroy_compiler(&sctx->compiler);
252
253 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
254
255 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
256 _mesa_hash_table_destroy(sctx->img_handles, NULL);
257
258 util_dynarray_fini(&sctx->resident_tex_handles);
259 util_dynarray_fini(&sctx->resident_img_handles);
260 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
261 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
262 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
263 FREE(sctx);
264 }
265
266 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
267 {
268 struct si_context *sctx = (struct si_context *)ctx;
269
270 if (sctx->screen->info.has_gpu_reset_status_query)
271 return sctx->ws->ctx_query_reset_status(sctx->ctx);
272
273 if (sctx->screen->info.has_gpu_reset_counter_query) {
274 unsigned latest = sctx->ws->query_value(sctx->ws,
275 RADEON_GPU_RESET_COUNTER);
276
277 if (sctx->gpu_reset_counter == latest)
278 return PIPE_NO_RESET;
279
280 sctx->gpu_reset_counter = latest;
281 return PIPE_UNKNOWN_CONTEXT_RESET;
282 }
283
284 return PIPE_NO_RESET;
285 }
286
287 static void si_set_device_reset_callback(struct pipe_context *ctx,
288 const struct pipe_device_reset_callback *cb)
289 {
290 struct si_context *sctx = (struct si_context *)ctx;
291
292 if (cb)
293 sctx->device_reset_callback = *cb;
294 else
295 memset(&sctx->device_reset_callback, 0,
296 sizeof(sctx->device_reset_callback));
297 }
298
299 bool si_check_device_reset(struct si_context *sctx)
300 {
301 enum pipe_reset_status status;
302
303 if (!sctx->device_reset_callback.reset)
304 return false;
305
306 if (!sctx->b.get_device_reset_status)
307 return false;
308
309 status = sctx->b.get_device_reset_status(&sctx->b);
310 if (status == PIPE_NO_RESET)
311 return false;
312
313 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
314 return true;
315 }
316
317 /* Apitrace profiling:
318 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
319 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
320 * and remember its number.
321 * 3) In Mesa, enable queries and performance counters around that draw
322 * call and print the results.
323 * 4) glretrace --benchmark --markers ..
324 */
325 static void si_emit_string_marker(struct pipe_context *ctx,
326 const char *string, int len)
327 {
328 struct si_context *sctx = (struct si_context *)ctx;
329
330 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
331
332 if (sctx->log)
333 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
334 }
335
336 static void si_set_debug_callback(struct pipe_context *ctx,
337 const struct pipe_debug_callback *cb)
338 {
339 struct si_context *sctx = (struct si_context *)ctx;
340 struct si_screen *screen = sctx->screen;
341
342 util_queue_finish(&screen->shader_compiler_queue);
343 util_queue_finish(&screen->shader_compiler_queue_low_priority);
344
345 if (cb)
346 sctx->debug = *cb;
347 else
348 memset(&sctx->debug, 0, sizeof(sctx->debug));
349 }
350
351 static void si_set_log_context(struct pipe_context *ctx,
352 struct u_log_context *log)
353 {
354 struct si_context *sctx = (struct si_context *)ctx;
355 sctx->log = log;
356
357 if (log)
358 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
359 }
360
361 static void si_set_context_param(struct pipe_context *ctx,
362 enum pipe_context_param param,
363 unsigned value)
364 {
365 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
366
367 switch (param) {
368 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
369 ws->pin_threads_to_L3_cache(ws, value);
370 break;
371 default:;
372 }
373 }
374
375 static struct pipe_context *si_create_context(struct pipe_screen *screen,
376 unsigned flags)
377 {
378 struct si_context *sctx = CALLOC_STRUCT(si_context);
379 struct si_screen* sscreen = (struct si_screen *)screen;
380 struct radeon_winsys *ws = sscreen->ws;
381 int shader, i;
382 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
383
384 if (!sctx)
385 return NULL;
386
387 if (flags & PIPE_CONTEXT_DEBUG)
388 sscreen->record_llvm_ir = true; /* racy but not critical */
389
390 sctx->b.screen = screen; /* this must be set first */
391 sctx->b.priv = NULL;
392 sctx->b.destroy = si_destroy_context;
393 sctx->b.emit_string_marker = si_emit_string_marker;
394 sctx->b.set_debug_callback = si_set_debug_callback;
395 sctx->b.set_log_context = si_set_log_context;
396 sctx->b.set_context_param = si_set_context_param;
397 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
398 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
399
400 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
401 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
402
403 sctx->ws = sscreen->ws;
404 sctx->family = sscreen->info.family;
405 sctx->chip_class = sscreen->info.chip_class;
406
407 if (sscreen->info.has_gpu_reset_counter_query) {
408 sctx->gpu_reset_counter =
409 sctx->ws->query_value(sctx->ws, RADEON_GPU_RESET_COUNTER);
410 }
411
412 sctx->b.get_device_reset_status = si_get_reset_status;
413 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
414
415 si_init_context_texture_functions(sctx);
416 si_init_query_functions(sctx);
417
418 if (sctx->chip_class == CIK ||
419 sctx->chip_class == VI ||
420 sctx->chip_class == GFX9) {
421 sctx->eop_bug_scratch = r600_resource(
422 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
423 16 * sscreen->info.num_render_backends));
424 if (!sctx->eop_bug_scratch)
425 goto fail;
426 }
427
428 sctx->allocator_zeroed_memory =
429 u_suballocator_create(&sctx->b, sscreen->info.gart_page_size,
430 0, PIPE_USAGE_DEFAULT,
431 SI_RESOURCE_FLAG_SO_FILLED_SIZE, true);
432 if (!sctx->allocator_zeroed_memory)
433 goto fail;
434
435 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
436 0, PIPE_USAGE_STREAM,
437 SI_RESOURCE_FLAG_READ_ONLY);
438 if (!sctx->b.stream_uploader)
439 goto fail;
440
441 sctx->b.const_uploader = u_upload_create(&sctx->b, 128 * 1024,
442 0, PIPE_USAGE_DEFAULT,
443 SI_RESOURCE_FLAG_32BIT |
444 (sscreen->cpdma_prefetch_writes_memory ?
445 0 : SI_RESOURCE_FLAG_READ_ONLY));
446 if (!sctx->b.const_uploader)
447 goto fail;
448
449 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
450 0, PIPE_USAGE_STAGING, 0);
451 if (!sctx->cached_gtt_allocator)
452 goto fail;
453
454 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
455 if (!sctx->ctx)
456 goto fail;
457
458 if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
459 sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
460 (void*)si_flush_dma_cs,
461 sctx, stop_exec_on_failure);
462 }
463
464 si_init_buffer_functions(sctx);
465 si_init_clear_functions(sctx);
466 si_init_blit_functions(sctx);
467 si_init_compute_functions(sctx);
468 si_init_compute_blit_functions(sctx);
469 si_init_debug_functions(sctx);
470 si_init_msaa_functions(sctx);
471 si_init_streamout_functions(sctx);
472
473 if (sscreen->info.has_hw_decode) {
474 sctx->b.create_video_codec = si_uvd_create_decoder;
475 sctx->b.create_video_buffer = si_video_buffer_create;
476 } else {
477 sctx->b.create_video_codec = vl_create_decoder;
478 sctx->b.create_video_buffer = vl_video_buffer_create;
479 }
480
481 sctx->gfx_cs = ws->cs_create(sctx->ctx, RING_GFX,
482 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
483
484 /* Border colors. */
485 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
486 sizeof(*sctx->border_color_table));
487 if (!sctx->border_color_table)
488 goto fail;
489
490 sctx->border_color_buffer = r600_resource(
491 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
492 SI_MAX_BORDER_COLORS *
493 sizeof(*sctx->border_color_table)));
494 if (!sctx->border_color_buffer)
495 goto fail;
496
497 sctx->border_color_map =
498 ws->buffer_map(sctx->border_color_buffer->buf,
499 NULL, PIPE_TRANSFER_WRITE);
500 if (!sctx->border_color_map)
501 goto fail;
502
503 si_init_all_descriptors(sctx);
504 si_init_fence_functions(sctx);
505 si_init_state_functions(sctx);
506 si_init_shader_functions(sctx);
507 si_init_viewport_functions(sctx);
508
509 if (sctx->chip_class >= CIK)
510 cik_init_sdma_functions(sctx);
511 else
512 si_init_dma_functions(sctx);
513
514 if (sscreen->debug_flags & DBG(FORCE_DMA))
515 sctx->b.resource_copy_region = sctx->dma_copy;
516
517 sctx->blitter = util_blitter_create(&sctx->b);
518 if (sctx->blitter == NULL)
519 goto fail;
520 sctx->blitter->skip_viewport_restore = true;
521
522 si_init_draw_functions(sctx);
523
524 sctx->sample_mask = 0xffff;
525
526 if (sctx->chip_class >= GFX9) {
527 sctx->wait_mem_scratch = r600_resource(
528 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4));
529 if (!sctx->wait_mem_scratch)
530 goto fail;
531
532 /* Initialize the memory. */
533 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
534 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
535 }
536
537 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
538 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
539 if (sctx->chip_class == CIK) {
540 sctx->null_const_buf.buffer =
541 pipe_aligned_buffer_create(screen,
542 SI_RESOURCE_FLAG_32BIT,
543 PIPE_USAGE_DEFAULT, 16,
544 sctx->screen->info.tcc_cache_line_size);
545 if (!sctx->null_const_buf.buffer)
546 goto fail;
547 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
548
549 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
550 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
551 sctx->b.set_constant_buffer(&sctx->b, shader, i,
552 &sctx->null_const_buf);
553 }
554 }
555
556 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
557 &sctx->null_const_buf);
558 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
559 &sctx->null_const_buf);
560 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
561 &sctx->null_const_buf);
562 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
563 &sctx->null_const_buf);
564 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
565 &sctx->null_const_buf);
566 }
567
568 uint64_t max_threads_per_block;
569 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
570 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
571 &max_threads_per_block);
572
573 /* The maximum number of scratch waves. Scratch space isn't divided
574 * evenly between CUs. The number is only a function of the number of CUs.
575 * We can decrease the constant to decrease the scratch buffer size.
576 *
577 * sctx->scratch_waves must be >= the maximum posible size of
578 * 1 threadgroup, so that the hw doesn't hang from being unable
579 * to start any.
580 *
581 * The recommended value is 4 per CU at most. Higher numbers don't
582 * bring much benefit, but they still occupy chip resources (think
583 * async compute). I've seen ~2% performance difference between 4 and 32.
584 */
585 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
586 max_threads_per_block / 64);
587
588 si_init_compiler(sscreen, &sctx->compiler);
589
590 /* Bindless handles. */
591 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
592 _mesa_key_pointer_equal);
593 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
594 _mesa_key_pointer_equal);
595
596 util_dynarray_init(&sctx->resident_tex_handles, NULL);
597 util_dynarray_init(&sctx->resident_img_handles, NULL);
598 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
599 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
600 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
601
602 sctx->sample_pos_buffer =
603 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
604 sizeof(sctx->sample_positions));
605 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
606 sizeof(sctx->sample_positions), &sctx->sample_positions);
607
608 /* this must be last */
609 si_begin_new_gfx_cs(sctx);
610
611 if (sctx->chip_class == CIK) {
612 /* Clear the NULL constant buffer, because loads should return zeros. */
613 uint32_t clear_value = 0;
614 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
615 sctx->null_const_buf.buffer->width0,
616 &clear_value, 4, SI_COHERENCY_SHADER);
617 }
618 return &sctx->b;
619 fail:
620 fprintf(stderr, "radeonsi: Failed to create a context.\n");
621 si_destroy_context(&sctx->b);
622 return NULL;
623 }
624
625 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
626 void *priv, unsigned flags)
627 {
628 struct si_screen *sscreen = (struct si_screen *)screen;
629 struct pipe_context *ctx;
630
631 if (sscreen->debug_flags & DBG(CHECK_VM))
632 flags |= PIPE_CONTEXT_DEBUG;
633
634 ctx = si_create_context(screen, flags);
635
636 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
637 return ctx;
638
639 /* Clover (compute-only) is unsupported. */
640 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
641 return ctx;
642
643 /* When shaders are logged to stderr, asynchronous compilation is
644 * disabled too. */
645 if (sscreen->debug_flags & DBG_ALL_SHADERS)
646 return ctx;
647
648 /* Use asynchronous flushes only on amdgpu, since the radeon
649 * implementation for fence_server_sync is incomplete. */
650 return threaded_context_create(ctx, &sscreen->pool_transfers,
651 si_replace_buffer_storage,
652 sscreen->info.drm_major >= 3 ? si_create_fence : NULL,
653 &((struct si_context*)ctx)->tc);
654 }
655
656 /*
657 * pipe_screen
658 */
659 static void si_destroy_screen(struct pipe_screen* pscreen)
660 {
661 struct si_screen *sscreen = (struct si_screen *)pscreen;
662 struct si_shader_part *parts[] = {
663 sscreen->vs_prologs,
664 sscreen->tcs_epilogs,
665 sscreen->gs_prologs,
666 sscreen->ps_prologs,
667 sscreen->ps_epilogs
668 };
669 unsigned i;
670
671 if (!sscreen->ws->unref(sscreen->ws))
672 return;
673
674 util_queue_destroy(&sscreen->shader_compiler_queue);
675 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
676
677 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
678 si_destroy_compiler(&sscreen->compiler[i]);
679
680 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
681 si_destroy_compiler(&sscreen->compiler_lowp[i]);
682
683 /* Free shader parts. */
684 for (i = 0; i < ARRAY_SIZE(parts); i++) {
685 while (parts[i]) {
686 struct si_shader_part *part = parts[i];
687
688 parts[i] = part->next;
689 ac_shader_binary_clean(&part->binary);
690 FREE(part);
691 }
692 }
693 mtx_destroy(&sscreen->shader_parts_mutex);
694 si_destroy_shader_cache(sscreen);
695
696 si_destroy_perfcounters(sscreen);
697 si_gpu_load_kill_thread(sscreen);
698
699 mtx_destroy(&sscreen->gpu_load_mutex);
700 mtx_destroy(&sscreen->aux_context_lock);
701 sscreen->aux_context->destroy(sscreen->aux_context);
702
703 slab_destroy_parent(&sscreen->pool_transfers);
704
705 disk_cache_destroy(sscreen->disk_shader_cache);
706 sscreen->ws->destroy(sscreen->ws);
707 FREE(sscreen);
708 }
709
710 static void si_init_gs_info(struct si_screen *sscreen)
711 {
712 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
713 sscreen->info.family);
714 }
715
716 static void si_test_vmfault(struct si_screen *sscreen)
717 {
718 struct pipe_context *ctx = sscreen->aux_context;
719 struct si_context *sctx = (struct si_context *)ctx;
720 struct pipe_resource *buf =
721 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
722
723 if (!buf) {
724 puts("Buffer allocation failed.");
725 exit(1);
726 }
727
728 r600_resource(buf)->gpu_address = 0; /* cause a VM fault */
729
730 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
731 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
732 SI_COHERENCY_NONE, L2_BYPASS);
733 ctx->flush(ctx, NULL, 0);
734 puts("VM fault test: CP - done.");
735 }
736 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
737 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
738 ctx->flush(ctx, NULL, 0);
739 puts("VM fault test: SDMA - done.");
740 }
741 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
742 util_test_constant_buffer(ctx, buf);
743 puts("VM fault test: Shader - done.");
744 }
745 exit(0);
746 }
747
748 static void si_test_gds_memory_management(struct si_context *sctx,
749 unsigned alloc_size, unsigned alignment,
750 enum radeon_bo_domain domain)
751 {
752 struct radeon_winsys *ws = sctx->ws;
753 struct radeon_cmdbuf *cs[8];
754 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
755
756 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
757 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
758 NULL, NULL, false);
759 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
760 assert(gds_bo[i]);
761 }
762
763 for (unsigned iterations = 0; iterations < 20000; iterations++) {
764 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
765 /* This clears GDS with CP DMA.
766 *
767 * We don't care if GDS is present. Just add some packet
768 * to make the GPU busy for a moment.
769 */
770 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
771 SI_CPDMA_SKIP_BO_LIST_UPDATE |
772 SI_CPDMA_SKIP_CHECK_CS_SPACE |
773 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
774
775 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
776 RADEON_USAGE_READWRITE, 0);
777 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
778 }
779 }
780 exit(0);
781 }
782
783 static void si_disk_cache_create(struct si_screen *sscreen)
784 {
785 /* Don't use the cache if shader dumping is enabled. */
786 if (sscreen->debug_flags & DBG_ALL_SHADERS)
787 return;
788
789 struct mesa_sha1 ctx;
790 unsigned char sha1[20];
791 char cache_id[20 * 2 + 1];
792
793 _mesa_sha1_init(&ctx);
794
795 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
796 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
797 &ctx))
798 return;
799
800 _mesa_sha1_final(&ctx, sha1);
801 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
802
803 /* These flags affect shader compilation. */
804 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
805 DBG(SI_SCHED) | \
806 DBG(GISEL) | \
807 DBG(UNSAFE_MATH) | \
808 DBG(NIR))
809 uint64_t shader_debug_flags = sscreen->debug_flags &
810 ALL_FLAGS;
811
812 /* Add the high bits of 32-bit addresses, which affects
813 * how 32-bit addresses are expanded to 64 bits.
814 */
815 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
816 shader_debug_flags |= (uint64_t)sscreen->info.address32_hi << 32;
817
818 sscreen->disk_shader_cache =
819 disk_cache_create(sscreen->info.name,
820 cache_id,
821 shader_debug_flags);
822 }
823
824 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
825 const struct pipe_screen_config *config)
826 {
827 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
828 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i;
829
830 if (!sscreen) {
831 return NULL;
832 }
833
834 sscreen->ws = ws;
835 ws->query_info(ws, &sscreen->info);
836
837 if (sscreen->info.chip_class >= GFX9) {
838 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
839 } else {
840 ac_get_raster_config(&sscreen->info,
841 &sscreen->pa_sc_raster_config,
842 &sscreen->pa_sc_raster_config_1,
843 &sscreen->se_tile_repeat);
844 }
845
846 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
847 debug_options, 0);
848
849 /* Set functions first. */
850 sscreen->b.context_create = si_pipe_create_context;
851 sscreen->b.destroy = si_destroy_screen;
852
853 si_init_screen_get_functions(sscreen);
854 si_init_screen_buffer_functions(sscreen);
855 si_init_screen_fence_functions(sscreen);
856 si_init_screen_state_functions(sscreen);
857 si_init_screen_texture_functions(sscreen);
858 si_init_screen_query_functions(sscreen);
859
860 /* Set these flags in debug_flags early, so that the shader cache takes
861 * them into account.
862 */
863 if (driQueryOptionb(config->options,
864 "glsl_correct_derivatives_after_discard"))
865 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
866 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
867 sscreen->debug_flags |= DBG(SI_SCHED);
868
869
870 if (sscreen->debug_flags & DBG(INFO))
871 ac_print_gpu_info(&sscreen->info);
872
873 slab_create_parent(&sscreen->pool_transfers,
874 sizeof(struct si_transfer), 64);
875
876 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
877 if (sscreen->force_aniso >= 0) {
878 printf("radeonsi: Forcing anisotropy filter to %ix\n",
879 /* round down to a power of two */
880 1 << util_logbase2(sscreen->force_aniso));
881 }
882
883 (void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
884 (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
885
886 si_init_gs_info(sscreen);
887 if (!si_init_shader_cache(sscreen)) {
888 FREE(sscreen);
889 return NULL;
890 }
891
892 si_disk_cache_create(sscreen);
893
894 /* Determine the number of shader compiler threads. */
895 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
896
897 if (hw_threads >= 12) {
898 num_comp_hi_threads = hw_threads * 3 / 4;
899 num_comp_lo_threads = hw_threads / 3;
900 } else if (hw_threads >= 6) {
901 num_comp_hi_threads = hw_threads - 2;
902 num_comp_lo_threads = hw_threads / 2;
903 } else if (hw_threads >= 2) {
904 num_comp_hi_threads = hw_threads - 1;
905 num_comp_lo_threads = hw_threads / 2;
906 } else {
907 num_comp_hi_threads = 1;
908 num_comp_lo_threads = 1;
909 }
910
911 num_comp_hi_threads = MIN2(num_comp_hi_threads,
912 ARRAY_SIZE(sscreen->compiler));
913 num_comp_lo_threads = MIN2(num_comp_lo_threads,
914 ARRAY_SIZE(sscreen->compiler_lowp));
915
916 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
917 64, num_comp_hi_threads,
918 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
919 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
920 si_destroy_shader_cache(sscreen);
921 FREE(sscreen);
922 return NULL;
923 }
924
925 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
926 "shlo",
927 64, num_comp_lo_threads,
928 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
929 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
930 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
931 si_destroy_shader_cache(sscreen);
932 FREE(sscreen);
933 return NULL;
934 }
935
936 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
937 si_init_perfcounters(sscreen);
938
939 /* Determine tessellation ring info. */
940 bool double_offchip_buffers = sscreen->info.chip_class >= CIK &&
941 sscreen->info.family != CHIP_CARRIZO &&
942 sscreen->info.family != CHIP_STONEY;
943 /* This must be one less than the maximum number due to a hw limitation.
944 * Various hardware bugs in SI, CIK, and GFX9 need this.
945 */
946 unsigned max_offchip_buffers_per_se;
947
948 /* Only certain chips can use the maximum value. */
949 if (sscreen->info.family == CHIP_VEGA12 ||
950 sscreen->info.family == CHIP_VEGA20)
951 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
952 else
953 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
954
955 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
956 sscreen->info.max_se;
957 unsigned offchip_granularity;
958
959 /* Hawaii has a bug with offchip buffers > 256 that can be worked
960 * around by setting 4K granularity.
961 */
962 if (sscreen->info.family == CHIP_HAWAII) {
963 sscreen->tess_offchip_block_dw_size = 4096;
964 offchip_granularity = V_03093C_X_4K_DWORDS;
965 } else {
966 sscreen->tess_offchip_block_dw_size = 8192;
967 offchip_granularity = V_03093C_X_8K_DWORDS;
968 }
969
970 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
971 assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
972 sscreen->tess_offchip_ring_size = max_offchip_buffers *
973 sscreen->tess_offchip_block_dw_size * 4;
974
975 if (sscreen->info.chip_class >= CIK) {
976 if (sscreen->info.chip_class >= VI)
977 --max_offchip_buffers;
978 sscreen->vgt_hs_offchip_param =
979 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
980 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
981 } else {
982 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
983 sscreen->vgt_hs_offchip_param =
984 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
985 }
986
987 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
988 * on SI. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
989 * SPI_VS_OUT_CONFIG. So only enable CI CLEAR_STATE on amdgpu kernel.*/
990 sscreen->has_clear_state = sscreen->info.chip_class >= CIK &&
991 sscreen->info.drm_major == 3;
992
993 sscreen->has_distributed_tess =
994 sscreen->info.chip_class >= VI &&
995 sscreen->info.max_se >= 2;
996
997 sscreen->has_draw_indirect_multi =
998 (sscreen->info.family >= CHIP_POLARIS10) ||
999 (sscreen->info.chip_class == VI &&
1000 sscreen->info.pfp_fw_version >= 121 &&
1001 sscreen->info.me_fw_version >= 87) ||
1002 (sscreen->info.chip_class == CIK &&
1003 sscreen->info.pfp_fw_version >= 211 &&
1004 sscreen->info.me_fw_version >= 173) ||
1005 (sscreen->info.chip_class == SI &&
1006 sscreen->info.pfp_fw_version >= 79 &&
1007 sscreen->info.me_fw_version >= 142);
1008
1009 sscreen->has_out_of_order_rast = sscreen->info.chip_class >= VI &&
1010 sscreen->info.max_se >= 2 &&
1011 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1012 sscreen->assume_no_z_fights =
1013 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1014 sscreen->commutative_blend_add =
1015 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1016 sscreen->clear_db_cache_before_clear =
1017 driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
1018 sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
1019 sscreen->info.family <= CHIP_POLARIS12) ||
1020 sscreen->info.family == CHIP_VEGA10 ||
1021 sscreen->info.family == CHIP_RAVEN;
1022 sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
1023 sscreen->info.family == CHIP_RAVEN;
1024 sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2;
1025
1026 /* Only enable primitive binning on APUs by default. */
1027 sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN ||
1028 sscreen->info.family == CHIP_RAVEN2;
1029
1030 sscreen->dfsm_allowed = sscreen->info.family == CHIP_RAVEN ||
1031 sscreen->info.family == CHIP_RAVEN2;
1032
1033 /* Process DPBB enable flags. */
1034 if (sscreen->debug_flags & DBG(DPBB)) {
1035 sscreen->dpbb_allowed = true;
1036 if (sscreen->debug_flags & DBG(DFSM))
1037 sscreen->dfsm_allowed = true;
1038 }
1039
1040 /* Process DPBB disable flags. */
1041 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1042 sscreen->dpbb_allowed = false;
1043 sscreen->dfsm_allowed = false;
1044 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1045 sscreen->dfsm_allowed = false;
1046 }
1047
1048 /* While it would be nice not to have this flag, we are constrained
1049 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1050 * on GFX9.
1051 */
1052 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= VI;
1053
1054 /* Some chips have RB+ registers, but don't support RB+. Those must
1055 * always disable it.
1056 */
1057 if (sscreen->info.family == CHIP_STONEY ||
1058 sscreen->info.chip_class >= GFX9) {
1059 sscreen->has_rbplus = true;
1060
1061 sscreen->rbplus_allowed =
1062 !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
1063 (sscreen->info.family == CHIP_STONEY ||
1064 sscreen->info.family == CHIP_VEGA12 ||
1065 sscreen->info.family == CHIP_RAVEN ||
1066 sscreen->info.family == CHIP_RAVEN2);
1067 }
1068
1069 sscreen->dcc_msaa_allowed =
1070 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1071
1072 sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= VI;
1073
1074 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1075 sscreen->use_monolithic_shaders =
1076 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1077
1078 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1079 SI_CONTEXT_INV_VMEM_L1;
1080 if (sscreen->info.chip_class <= VI) {
1081 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1082 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1083 }
1084
1085 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1086 sscreen->debug_flags |= DBG_ALL_SHADERS;
1087
1088 /* Syntax:
1089 * EQAA=s,z,c
1090 * Example:
1091 * EQAA=8,4,2
1092
1093 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1094 * Constraints:
1095 * s >= z >= c (ignoring this only wastes memory)
1096 * s = [2..16]
1097 * z = [2..8]
1098 * c = [2..8]
1099 *
1100 * Only MSAA color and depth buffers are overriden.
1101 */
1102 if (sscreen->info.has_eqaa_surface_allocator) {
1103 const char *eqaa = debug_get_option("EQAA", NULL);
1104 unsigned s,z,f;
1105
1106 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1107 sscreen->eqaa_force_coverage_samples = s;
1108 sscreen->eqaa_force_z_samples = z;
1109 sscreen->eqaa_force_color_samples = f;
1110 }
1111 }
1112
1113 for (i = 0; i < num_comp_hi_threads; i++)
1114 si_init_compiler(sscreen, &sscreen->compiler[i]);
1115 for (i = 0; i < num_comp_lo_threads; i++)
1116 si_init_compiler(sscreen, &sscreen->compiler_lowp[i]);
1117
1118 /* Create the auxiliary context. This must be done last. */
1119 sscreen->aux_context = si_create_context(&sscreen->b, 0);
1120
1121 if (sscreen->debug_flags & DBG(TEST_DMA))
1122 si_test_dma(sscreen);
1123
1124 if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) {
1125 si_test_dma_perf(sscreen);
1126 }
1127
1128 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1129 DBG(TEST_VMFAULT_SDMA) |
1130 DBG(TEST_VMFAULT_SHADER)))
1131 si_test_vmfault(sscreen);
1132
1133 if (sscreen->debug_flags & DBG(TEST_GDS))
1134 si_test_gds((struct si_context*)sscreen->aux_context);
1135
1136 if (sscreen->debug_flags & DBG(TEST_GDS_MM)) {
1137 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1138 32 * 1024, 4, RADEON_DOMAIN_GDS);
1139 }
1140 if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) {
1141 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1142 4, 1, RADEON_DOMAIN_OA);
1143 }
1144
1145 return &sscreen->b;
1146 }