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radeonsi: always use compute rings for clover on CI and newer (v2)
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "sid.h"
30
31 #include "ac_llvm_util.h"
32 #include "radeon/radeon_uvd.h"
33 #include "gallivm/lp_bld_misc.h"
34 #include "util/disk_cache.h"
35 #include "util/u_log.h"
36 #include "util/u_memory.h"
37 #include "util/u_suballoc.h"
38 #include "util/u_tests.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/xmlconfig.h"
41 #include "vl/vl_decoder.h"
42 #include "driver_ddebug/dd_util.h"
43
44 static const struct debug_named_value debug_options[] = {
45 /* Shader logging options: */
46 { "vs", DBG(VS), "Print vertex shaders" },
47 { "ps", DBG(PS), "Print pixel shaders" },
48 { "gs", DBG(GS), "Print geometry shaders" },
49 { "tcs", DBG(TCS), "Print tessellation control shaders" },
50 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
51 { "cs", DBG(CS), "Print compute shaders" },
52 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
53 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
54 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
55 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
56
57 /* Shader compiler options the shader cache should be aware of: */
58 { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" },
59 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
60 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
61
62 /* Shader compiler options (with no effect on the shader cache): */
63 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
64 { "nir", DBG(NIR), "Enable experimental NIR shaders" },
65 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
66 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
67
68 /* Information logging options: */
69 { "info", DBG(INFO), "Print driver information" },
70 { "tex", DBG(TEX), "Print texture info" },
71 { "compute", DBG(COMPUTE), "Print compute info" },
72 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
73
74 /* Driver options: */
75 { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." },
76 { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
77 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
78 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
79 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
80 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
81
82 /* 3D engine options: */
83 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
84 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
85 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
86 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
87 { "dpbb", DBG(DPBB), "Enable DPBB." },
88 { "dfsm", DBG(DFSM), "Enable DFSM." },
89 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
90 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
91 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
92 { "notiling", DBG(NO_TILING), "Disable tiling" },
93 { "nodcc", DBG(NO_DCC), "Disable DCC." },
94 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
95 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
96 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
97 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
98
99 /* Tests: */
100 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
101 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
102 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
103 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
104 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
105 { "testgds", DBG(TEST_GDS), "Test GDS." },
106 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
107 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
108
109 DEBUG_NAMED_VALUE_END /* must be last */
110 };
111
112 static void si_init_compiler(struct si_screen *sscreen,
113 struct ac_llvm_compiler *compiler)
114 {
115 /* Only create the less-optimizing version of the compiler on APUs
116 * predating Ryzen (Raven). */
117 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
118 sscreen->info.chip_class <= VI;
119
120 enum ac_target_machine_options tm_options =
121 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
122 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
123 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
124 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
125 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
126 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
127 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
128
129 ac_init_llvm_once();
130 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
131 compiler->passes = ac_create_llvm_passes(compiler->tm);
132
133 if (compiler->low_opt_tm)
134 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
135 }
136
137 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
138 {
139 ac_destroy_llvm_passes(compiler->passes);
140 ac_destroy_llvm_passes(compiler->low_opt_passes);
141 ac_destroy_llvm_compiler(compiler);
142 }
143
144 /*
145 * pipe_context
146 */
147 static void si_destroy_context(struct pipe_context *context)
148 {
149 struct si_context *sctx = (struct si_context *)context;
150 int i;
151
152 /* Unreference the framebuffer normally to disable related logic
153 * properly.
154 */
155 struct pipe_framebuffer_state fb = {};
156 if (context->set_framebuffer_state)
157 context->set_framebuffer_state(context, &fb);
158
159 si_release_all_descriptors(sctx);
160
161 pipe_resource_reference(&sctx->esgs_ring, NULL);
162 pipe_resource_reference(&sctx->gsvs_ring, NULL);
163 pipe_resource_reference(&sctx->tess_rings, NULL);
164 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
165 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
166 si_resource_reference(&sctx->border_color_buffer, NULL);
167 free(sctx->border_color_table);
168 si_resource_reference(&sctx->scratch_buffer, NULL);
169 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
170 si_resource_reference(&sctx->wait_mem_scratch, NULL);
171
172 si_pm4_free_state(sctx, sctx->init_config, ~0);
173 if (sctx->init_config_gs_rings)
174 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
175 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
176 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
177
178 if (sctx->fixed_func_tcs_shader.cso)
179 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
180 if (sctx->custom_dsa_flush)
181 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
182 if (sctx->custom_blend_resolve)
183 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
184 if (sctx->custom_blend_fmask_decompress)
185 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
186 if (sctx->custom_blend_eliminate_fastclear)
187 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
188 if (sctx->custom_blend_dcc_decompress)
189 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
190 if (sctx->vs_blit_pos)
191 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
192 if (sctx->vs_blit_pos_layered)
193 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
194 if (sctx->vs_blit_color)
195 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
196 if (sctx->vs_blit_color_layered)
197 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
198 if (sctx->vs_blit_texcoord)
199 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
200 if (sctx->cs_clear_buffer)
201 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
202 if (sctx->cs_copy_buffer)
203 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
204 if (sctx->cs_copy_image)
205 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
206 if (sctx->cs_copy_image_1d_array)
207 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
208 if (sctx->cs_clear_render_target)
209 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
210 if (sctx->cs_clear_render_target_1d_array)
211 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
212
213 if (sctx->blitter)
214 util_blitter_destroy(sctx->blitter);
215
216 /* Release DCC stats. */
217 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
218 assert(!sctx->dcc_stats[i].query_active);
219
220 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
221 if (sctx->dcc_stats[i].ps_stats[j])
222 sctx->b.destroy_query(&sctx->b,
223 sctx->dcc_stats[i].ps_stats[j]);
224
225 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
226 }
227
228 if (sctx->query_result_shader)
229 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
230
231 if (sctx->gfx_cs)
232 sctx->ws->cs_destroy(sctx->gfx_cs);
233 if (sctx->dma_cs)
234 sctx->ws->cs_destroy(sctx->dma_cs);
235 if (sctx->ctx)
236 sctx->ws->ctx_destroy(sctx->ctx);
237
238 if (sctx->b.stream_uploader)
239 u_upload_destroy(sctx->b.stream_uploader);
240 if (sctx->b.const_uploader)
241 u_upload_destroy(sctx->b.const_uploader);
242 if (sctx->cached_gtt_allocator)
243 u_upload_destroy(sctx->cached_gtt_allocator);
244
245 slab_destroy_child(&sctx->pool_transfers);
246 slab_destroy_child(&sctx->pool_transfers_unsync);
247
248 if (sctx->allocator_zeroed_memory)
249 u_suballocator_destroy(sctx->allocator_zeroed_memory);
250
251 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
252 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
253 si_resource_reference(&sctx->eop_bug_scratch, NULL);
254
255 si_destroy_compiler(&sctx->compiler);
256
257 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
258
259 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
260 _mesa_hash_table_destroy(sctx->img_handles, NULL);
261
262 util_dynarray_fini(&sctx->resident_tex_handles);
263 util_dynarray_fini(&sctx->resident_img_handles);
264 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
265 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
266 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
267 si_unref_sdma_uploads(sctx);
268 FREE(sctx);
269 }
270
271 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
272 {
273 struct si_context *sctx = (struct si_context *)ctx;
274
275 if (sctx->screen->info.has_gpu_reset_status_query)
276 return sctx->ws->ctx_query_reset_status(sctx->ctx);
277
278 if (sctx->screen->info.has_gpu_reset_counter_query) {
279 unsigned latest = sctx->ws->query_value(sctx->ws,
280 RADEON_GPU_RESET_COUNTER);
281
282 if (sctx->gpu_reset_counter == latest)
283 return PIPE_NO_RESET;
284
285 sctx->gpu_reset_counter = latest;
286 return PIPE_UNKNOWN_CONTEXT_RESET;
287 }
288
289 return PIPE_NO_RESET;
290 }
291
292 static void si_set_device_reset_callback(struct pipe_context *ctx,
293 const struct pipe_device_reset_callback *cb)
294 {
295 struct si_context *sctx = (struct si_context *)ctx;
296
297 if (cb)
298 sctx->device_reset_callback = *cb;
299 else
300 memset(&sctx->device_reset_callback, 0,
301 sizeof(sctx->device_reset_callback));
302 }
303
304 bool si_check_device_reset(struct si_context *sctx)
305 {
306 enum pipe_reset_status status;
307
308 if (!sctx->device_reset_callback.reset)
309 return false;
310
311 if (!sctx->b.get_device_reset_status)
312 return false;
313
314 status = sctx->b.get_device_reset_status(&sctx->b);
315 if (status == PIPE_NO_RESET)
316 return false;
317
318 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
319 return true;
320 }
321
322 /* Apitrace profiling:
323 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
324 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
325 * and remember its number.
326 * 3) In Mesa, enable queries and performance counters around that draw
327 * call and print the results.
328 * 4) glretrace --benchmark --markers ..
329 */
330 static void si_emit_string_marker(struct pipe_context *ctx,
331 const char *string, int len)
332 {
333 struct si_context *sctx = (struct si_context *)ctx;
334
335 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
336
337 if (sctx->log)
338 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
339 }
340
341 static void si_set_debug_callback(struct pipe_context *ctx,
342 const struct pipe_debug_callback *cb)
343 {
344 struct si_context *sctx = (struct si_context *)ctx;
345 struct si_screen *screen = sctx->screen;
346
347 util_queue_finish(&screen->shader_compiler_queue);
348 util_queue_finish(&screen->shader_compiler_queue_low_priority);
349
350 if (cb)
351 sctx->debug = *cb;
352 else
353 memset(&sctx->debug, 0, sizeof(sctx->debug));
354 }
355
356 static void si_set_log_context(struct pipe_context *ctx,
357 struct u_log_context *log)
358 {
359 struct si_context *sctx = (struct si_context *)ctx;
360 sctx->log = log;
361
362 if (log)
363 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
364 }
365
366 static void si_set_context_param(struct pipe_context *ctx,
367 enum pipe_context_param param,
368 unsigned value)
369 {
370 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
371
372 switch (param) {
373 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
374 ws->pin_threads_to_L3_cache(ws, value);
375 break;
376 default:;
377 }
378 }
379
380 static struct pipe_context *si_create_context(struct pipe_screen *screen,
381 unsigned flags)
382 {
383 struct si_context *sctx = CALLOC_STRUCT(si_context);
384 struct si_screen* sscreen = (struct si_screen *)screen;
385 struct radeon_winsys *ws = sscreen->ws;
386 int shader, i;
387 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
388
389 if (!sctx)
390 return NULL;
391
392 sctx->has_graphics = sscreen->info.chip_class == SI ||
393 !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
394
395 if (flags & PIPE_CONTEXT_DEBUG)
396 sscreen->record_llvm_ir = true; /* racy but not critical */
397
398 sctx->b.screen = screen; /* this must be set first */
399 sctx->b.priv = NULL;
400 sctx->b.destroy = si_destroy_context;
401 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
402 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
403
404 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
405 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
406
407 sctx->ws = sscreen->ws;
408 sctx->family = sscreen->info.family;
409 sctx->chip_class = sscreen->info.chip_class;
410
411 if (sscreen->info.has_gpu_reset_counter_query) {
412 sctx->gpu_reset_counter =
413 sctx->ws->query_value(sctx->ws, RADEON_GPU_RESET_COUNTER);
414 }
415
416
417 if (sctx->chip_class == CIK ||
418 sctx->chip_class == VI ||
419 sctx->chip_class == GFX9) {
420 sctx->eop_bug_scratch = si_resource(
421 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
422 16 * sscreen->info.num_render_backends));
423 if (!sctx->eop_bug_scratch)
424 goto fail;
425 }
426
427 /* Initialize context allocators. */
428 sctx->allocator_zeroed_memory =
429 u_suballocator_create(&sctx->b, 128 * 1024,
430 0, PIPE_USAGE_DEFAULT,
431 SI_RESOURCE_FLAG_UNMAPPABLE |
432 SI_RESOURCE_FLAG_CLEAR, false);
433 if (!sctx->allocator_zeroed_memory)
434 goto fail;
435
436 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
437 0, PIPE_USAGE_STREAM,
438 SI_RESOURCE_FLAG_READ_ONLY);
439 if (!sctx->b.stream_uploader)
440 goto fail;
441
442 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
443 0, PIPE_USAGE_STAGING, 0);
444 if (!sctx->cached_gtt_allocator)
445 goto fail;
446
447 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
448 if (!sctx->ctx)
449 goto fail;
450
451 if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
452 sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
453 (void*)si_flush_dma_cs,
454 sctx, stop_exec_on_failure);
455 }
456
457 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->dma_cs;
458 sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
459 0, PIPE_USAGE_DEFAULT,
460 SI_RESOURCE_FLAG_32BIT |
461 (use_sdma_upload ?
462 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA :
463 (sscreen->cpdma_prefetch_writes_memory ?
464 0 : SI_RESOURCE_FLAG_READ_ONLY)));
465 if (!sctx->b.const_uploader)
466 goto fail;
467
468 if (use_sdma_upload)
469 u_upload_enable_flush_explicit(sctx->b.const_uploader);
470
471 sctx->gfx_cs = ws->cs_create(sctx->ctx,
472 sctx->has_graphics ? RING_GFX : RING_COMPUTE,
473 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
474
475 /* Border colors. */
476 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
477 sizeof(*sctx->border_color_table));
478 if (!sctx->border_color_table)
479 goto fail;
480
481 sctx->border_color_buffer = si_resource(
482 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
483 SI_MAX_BORDER_COLORS *
484 sizeof(*sctx->border_color_table)));
485 if (!sctx->border_color_buffer)
486 goto fail;
487
488 sctx->border_color_map =
489 ws->buffer_map(sctx->border_color_buffer->buf,
490 NULL, PIPE_TRANSFER_WRITE);
491 if (!sctx->border_color_map)
492 goto fail;
493
494 /* Initialize context functions used by graphics and compute. */
495 sctx->b.emit_string_marker = si_emit_string_marker;
496 sctx->b.set_debug_callback = si_set_debug_callback;
497 sctx->b.set_log_context = si_set_log_context;
498 sctx->b.set_context_param = si_set_context_param;
499 sctx->b.get_device_reset_status = si_get_reset_status;
500 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
501 sctx->b.memory_barrier = si_memory_barrier;
502
503 si_init_all_descriptors(sctx);
504 si_init_buffer_functions(sctx);
505 si_init_clear_functions(sctx);
506 si_init_blit_functions(sctx);
507 si_init_compute_functions(sctx);
508 si_init_compute_blit_functions(sctx);
509 si_init_debug_functions(sctx);
510 si_init_fence_functions(sctx);
511
512 if (sscreen->debug_flags & DBG(FORCE_DMA))
513 sctx->b.resource_copy_region = sctx->dma_copy;
514
515 /* Initialize graphics-only context functions. */
516 if (sctx->has_graphics) {
517 si_init_context_texture_functions(sctx);
518 si_init_query_functions(sctx);
519 si_init_msaa_functions(sctx);
520 si_init_shader_functions(sctx);
521 si_init_state_functions(sctx);
522 si_init_streamout_functions(sctx);
523 si_init_viewport_functions(sctx);
524
525 sctx->blitter = util_blitter_create(&sctx->b);
526 if (sctx->blitter == NULL)
527 goto fail;
528 sctx->blitter->skip_viewport_restore = true;
529
530 si_init_draw_functions(sctx);
531 }
532
533 /* Initialize SDMA functions. */
534 if (sctx->chip_class >= CIK)
535 cik_init_sdma_functions(sctx);
536 else
537 si_init_dma_functions(sctx);
538
539 sctx->sample_mask = 0xffff;
540
541 /* Initialize multimedia functions. */
542 if (sscreen->info.has_hw_decode) {
543 sctx->b.create_video_codec = si_uvd_create_decoder;
544 sctx->b.create_video_buffer = si_video_buffer_create;
545 } else {
546 sctx->b.create_video_codec = vl_create_decoder;
547 sctx->b.create_video_buffer = vl_video_buffer_create;
548 }
549
550 if (sctx->chip_class >= GFX9) {
551 sctx->wait_mem_scratch = si_resource(
552 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4));
553 if (!sctx->wait_mem_scratch)
554 goto fail;
555
556 /* Initialize the memory. */
557 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
558 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
559 }
560
561 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
562 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
563 if (sctx->chip_class == CIK) {
564 sctx->null_const_buf.buffer =
565 pipe_aligned_buffer_create(screen,
566 SI_RESOURCE_FLAG_32BIT,
567 PIPE_USAGE_DEFAULT, 16,
568 sctx->screen->info.tcc_cache_line_size);
569 if (!sctx->null_const_buf.buffer)
570 goto fail;
571 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
572
573 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
574 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
575 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
576 sctx->b.set_constant_buffer(&sctx->b, shader, i,
577 &sctx->null_const_buf);
578 }
579 }
580
581 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
582 &sctx->null_const_buf);
583 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
584 &sctx->null_const_buf);
585 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
586 &sctx->null_const_buf);
587 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
588 &sctx->null_const_buf);
589 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
590 &sctx->null_const_buf);
591 }
592
593 uint64_t max_threads_per_block;
594 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
595 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
596 &max_threads_per_block);
597
598 /* The maximum number of scratch waves. Scratch space isn't divided
599 * evenly between CUs. The number is only a function of the number of CUs.
600 * We can decrease the constant to decrease the scratch buffer size.
601 *
602 * sctx->scratch_waves must be >= the maximum posible size of
603 * 1 threadgroup, so that the hw doesn't hang from being unable
604 * to start any.
605 *
606 * The recommended value is 4 per CU at most. Higher numbers don't
607 * bring much benefit, but they still occupy chip resources (think
608 * async compute). I've seen ~2% performance difference between 4 and 32.
609 */
610 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
611 max_threads_per_block / 64);
612
613 si_init_compiler(sscreen, &sctx->compiler);
614
615 /* Bindless handles. */
616 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
617 _mesa_key_pointer_equal);
618 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
619 _mesa_key_pointer_equal);
620
621 util_dynarray_init(&sctx->resident_tex_handles, NULL);
622 util_dynarray_init(&sctx->resident_img_handles, NULL);
623 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
624 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
625 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
626
627 sctx->sample_pos_buffer =
628 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
629 sizeof(sctx->sample_positions));
630 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
631 sizeof(sctx->sample_positions), &sctx->sample_positions);
632
633 /* this must be last */
634 si_begin_new_gfx_cs(sctx);
635
636 if (sctx->chip_class == CIK) {
637 /* Clear the NULL constant buffer, because loads should return zeros. */
638 uint32_t clear_value = 0;
639 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
640 sctx->null_const_buf.buffer->width0,
641 &clear_value, 4, SI_COHERENCY_SHADER);
642 }
643 return &sctx->b;
644 fail:
645 fprintf(stderr, "radeonsi: Failed to create a context.\n");
646 si_destroy_context(&sctx->b);
647 return NULL;
648 }
649
650 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
651 void *priv, unsigned flags)
652 {
653 struct si_screen *sscreen = (struct si_screen *)screen;
654 struct pipe_context *ctx;
655
656 if (sscreen->debug_flags & DBG(CHECK_VM))
657 flags |= PIPE_CONTEXT_DEBUG;
658
659 ctx = si_create_context(screen, flags);
660
661 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
662 return ctx;
663
664 /* Clover (compute-only) is unsupported. */
665 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
666 return ctx;
667
668 /* When shaders are logged to stderr, asynchronous compilation is
669 * disabled too. */
670 if (sscreen->debug_flags & DBG_ALL_SHADERS)
671 return ctx;
672
673 /* Use asynchronous flushes only on amdgpu, since the radeon
674 * implementation for fence_server_sync is incomplete. */
675 return threaded_context_create(ctx, &sscreen->pool_transfers,
676 si_replace_buffer_storage,
677 sscreen->info.drm_major >= 3 ? si_create_fence : NULL,
678 &((struct si_context*)ctx)->tc);
679 }
680
681 /*
682 * pipe_screen
683 */
684 static void si_destroy_screen(struct pipe_screen* pscreen)
685 {
686 struct si_screen *sscreen = (struct si_screen *)pscreen;
687 struct si_shader_part *parts[] = {
688 sscreen->vs_prologs,
689 sscreen->tcs_epilogs,
690 sscreen->gs_prologs,
691 sscreen->ps_prologs,
692 sscreen->ps_epilogs
693 };
694 unsigned i;
695
696 if (!sscreen->ws->unref(sscreen->ws))
697 return;
698
699 util_queue_destroy(&sscreen->shader_compiler_queue);
700 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
701
702 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
703 si_destroy_compiler(&sscreen->compiler[i]);
704
705 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
706 si_destroy_compiler(&sscreen->compiler_lowp[i]);
707
708 /* Free shader parts. */
709 for (i = 0; i < ARRAY_SIZE(parts); i++) {
710 while (parts[i]) {
711 struct si_shader_part *part = parts[i];
712
713 parts[i] = part->next;
714 ac_shader_binary_clean(&part->binary);
715 FREE(part);
716 }
717 }
718 mtx_destroy(&sscreen->shader_parts_mutex);
719 si_destroy_shader_cache(sscreen);
720
721 si_destroy_perfcounters(sscreen);
722 si_gpu_load_kill_thread(sscreen);
723
724 mtx_destroy(&sscreen->gpu_load_mutex);
725 mtx_destroy(&sscreen->aux_context_lock);
726 sscreen->aux_context->destroy(sscreen->aux_context);
727
728 slab_destroy_parent(&sscreen->pool_transfers);
729
730 disk_cache_destroy(sscreen->disk_shader_cache);
731 sscreen->ws->destroy(sscreen->ws);
732 FREE(sscreen);
733 }
734
735 static void si_init_gs_info(struct si_screen *sscreen)
736 {
737 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
738 sscreen->info.family);
739 }
740
741 static void si_test_vmfault(struct si_screen *sscreen)
742 {
743 struct pipe_context *ctx = sscreen->aux_context;
744 struct si_context *sctx = (struct si_context *)ctx;
745 struct pipe_resource *buf =
746 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
747
748 if (!buf) {
749 puts("Buffer allocation failed.");
750 exit(1);
751 }
752
753 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
754
755 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
756 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
757 SI_COHERENCY_NONE, L2_BYPASS);
758 ctx->flush(ctx, NULL, 0);
759 puts("VM fault test: CP - done.");
760 }
761 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
762 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
763 ctx->flush(ctx, NULL, 0);
764 puts("VM fault test: SDMA - done.");
765 }
766 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
767 util_test_constant_buffer(ctx, buf);
768 puts("VM fault test: Shader - done.");
769 }
770 exit(0);
771 }
772
773 static void si_test_gds_memory_management(struct si_context *sctx,
774 unsigned alloc_size, unsigned alignment,
775 enum radeon_bo_domain domain)
776 {
777 struct radeon_winsys *ws = sctx->ws;
778 struct radeon_cmdbuf *cs[8];
779 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
780
781 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
782 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
783 NULL, NULL, false);
784 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
785 assert(gds_bo[i]);
786 }
787
788 for (unsigned iterations = 0; iterations < 20000; iterations++) {
789 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
790 /* This clears GDS with CP DMA.
791 *
792 * We don't care if GDS is present. Just add some packet
793 * to make the GPU busy for a moment.
794 */
795 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
796 SI_CPDMA_SKIP_BO_LIST_UPDATE |
797 SI_CPDMA_SKIP_CHECK_CS_SPACE |
798 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
799
800 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
801 RADEON_USAGE_READWRITE, 0);
802 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
803 }
804 }
805 exit(0);
806 }
807
808 static void si_disk_cache_create(struct si_screen *sscreen)
809 {
810 /* Don't use the cache if shader dumping is enabled. */
811 if (sscreen->debug_flags & DBG_ALL_SHADERS)
812 return;
813
814 struct mesa_sha1 ctx;
815 unsigned char sha1[20];
816 char cache_id[20 * 2 + 1];
817
818 _mesa_sha1_init(&ctx);
819
820 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
821 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
822 &ctx))
823 return;
824
825 _mesa_sha1_final(&ctx, sha1);
826 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
827
828 /* These flags affect shader compilation. */
829 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
830 DBG(SI_SCHED) | \
831 DBG(GISEL) | \
832 DBG(UNSAFE_MATH) | \
833 DBG(NIR))
834 uint64_t shader_debug_flags = sscreen->debug_flags &
835 ALL_FLAGS;
836
837 /* Add the high bits of 32-bit addresses, which affects
838 * how 32-bit addresses are expanded to 64 bits.
839 */
840 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
841 shader_debug_flags |= (uint64_t)sscreen->info.address32_hi << 32;
842
843 sscreen->disk_shader_cache =
844 disk_cache_create(sscreen->info.name,
845 cache_id,
846 shader_debug_flags);
847 }
848
849 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
850 const struct pipe_screen_config *config)
851 {
852 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
853 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i;
854
855 if (!sscreen) {
856 return NULL;
857 }
858
859 sscreen->ws = ws;
860 ws->query_info(ws, &sscreen->info);
861
862 if (sscreen->info.chip_class >= GFX9) {
863 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
864 } else {
865 ac_get_raster_config(&sscreen->info,
866 &sscreen->pa_sc_raster_config,
867 &sscreen->pa_sc_raster_config_1,
868 &sscreen->se_tile_repeat);
869 }
870
871 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
872 debug_options, 0);
873 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
874 debug_options, 0);
875
876 /* Set functions first. */
877 sscreen->b.context_create = si_pipe_create_context;
878 sscreen->b.destroy = si_destroy_screen;
879
880 si_init_screen_get_functions(sscreen);
881 si_init_screen_buffer_functions(sscreen);
882 si_init_screen_fence_functions(sscreen);
883 si_init_screen_state_functions(sscreen);
884 si_init_screen_texture_functions(sscreen);
885 si_init_screen_query_functions(sscreen);
886
887 /* Set these flags in debug_flags early, so that the shader cache takes
888 * them into account.
889 */
890 if (driQueryOptionb(config->options,
891 "glsl_correct_derivatives_after_discard"))
892 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
893 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
894 sscreen->debug_flags |= DBG(SI_SCHED);
895 if (driQueryOptionb(config->options, "radeonsi_enable_nir"))
896 sscreen->debug_flags |= DBG(NIR);
897
898 if (sscreen->debug_flags & DBG(INFO))
899 ac_print_gpu_info(&sscreen->info);
900
901 slab_create_parent(&sscreen->pool_transfers,
902 sizeof(struct si_transfer), 64);
903
904 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
905 if (sscreen->force_aniso >= 0) {
906 printf("radeonsi: Forcing anisotropy filter to %ix\n",
907 /* round down to a power of two */
908 1 << util_logbase2(sscreen->force_aniso));
909 }
910
911 (void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
912 (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
913
914 si_init_gs_info(sscreen);
915 if (!si_init_shader_cache(sscreen)) {
916 FREE(sscreen);
917 return NULL;
918 }
919
920 si_disk_cache_create(sscreen);
921
922 /* Determine the number of shader compiler threads. */
923 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
924
925 if (hw_threads >= 12) {
926 num_comp_hi_threads = hw_threads * 3 / 4;
927 num_comp_lo_threads = hw_threads / 3;
928 } else if (hw_threads >= 6) {
929 num_comp_hi_threads = hw_threads - 2;
930 num_comp_lo_threads = hw_threads / 2;
931 } else if (hw_threads >= 2) {
932 num_comp_hi_threads = hw_threads - 1;
933 num_comp_lo_threads = hw_threads / 2;
934 } else {
935 num_comp_hi_threads = 1;
936 num_comp_lo_threads = 1;
937 }
938
939 num_comp_hi_threads = MIN2(num_comp_hi_threads,
940 ARRAY_SIZE(sscreen->compiler));
941 num_comp_lo_threads = MIN2(num_comp_lo_threads,
942 ARRAY_SIZE(sscreen->compiler_lowp));
943
944 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
945 64, num_comp_hi_threads,
946 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
947 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
948 si_destroy_shader_cache(sscreen);
949 FREE(sscreen);
950 return NULL;
951 }
952
953 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
954 "shlo",
955 64, num_comp_lo_threads,
956 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
957 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
958 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
959 si_destroy_shader_cache(sscreen);
960 FREE(sscreen);
961 return NULL;
962 }
963
964 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
965 si_init_perfcounters(sscreen);
966
967 /* Determine tessellation ring info. */
968 bool double_offchip_buffers = sscreen->info.chip_class >= CIK &&
969 sscreen->info.family != CHIP_CARRIZO &&
970 sscreen->info.family != CHIP_STONEY;
971 /* This must be one less than the maximum number due to a hw limitation.
972 * Various hardware bugs in SI, CIK, and GFX9 need this.
973 */
974 unsigned max_offchip_buffers_per_se;
975
976 /* Only certain chips can use the maximum value. */
977 if (sscreen->info.family == CHIP_VEGA12 ||
978 sscreen->info.family == CHIP_VEGA20)
979 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
980 else
981 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
982
983 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
984 sscreen->info.max_se;
985 unsigned offchip_granularity;
986
987 /* Hawaii has a bug with offchip buffers > 256 that can be worked
988 * around by setting 4K granularity.
989 */
990 if (sscreen->info.family == CHIP_HAWAII) {
991 sscreen->tess_offchip_block_dw_size = 4096;
992 offchip_granularity = V_03093C_X_4K_DWORDS;
993 } else {
994 sscreen->tess_offchip_block_dw_size = 8192;
995 offchip_granularity = V_03093C_X_8K_DWORDS;
996 }
997
998 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
999 assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
1000 sscreen->tess_offchip_ring_size = max_offchip_buffers *
1001 sscreen->tess_offchip_block_dw_size * 4;
1002
1003 if (sscreen->info.chip_class >= CIK) {
1004 if (sscreen->info.chip_class >= VI)
1005 --max_offchip_buffers;
1006 sscreen->vgt_hs_offchip_param =
1007 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1008 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1009 } else {
1010 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1011 sscreen->vgt_hs_offchip_param =
1012 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1013 }
1014
1015 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1016 * on SI. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
1017 * SPI_VS_OUT_CONFIG. So only enable CI CLEAR_STATE on amdgpu kernel.*/
1018 sscreen->has_clear_state = sscreen->info.chip_class >= CIK &&
1019 sscreen->info.drm_major == 3;
1020
1021 sscreen->has_distributed_tess =
1022 sscreen->info.chip_class >= VI &&
1023 sscreen->info.max_se >= 2;
1024
1025 sscreen->has_draw_indirect_multi =
1026 (sscreen->info.family >= CHIP_POLARIS10) ||
1027 (sscreen->info.chip_class == VI &&
1028 sscreen->info.pfp_fw_version >= 121 &&
1029 sscreen->info.me_fw_version >= 87) ||
1030 (sscreen->info.chip_class == CIK &&
1031 sscreen->info.pfp_fw_version >= 211 &&
1032 sscreen->info.me_fw_version >= 173) ||
1033 (sscreen->info.chip_class == SI &&
1034 sscreen->info.pfp_fw_version >= 79 &&
1035 sscreen->info.me_fw_version >= 142);
1036
1037 sscreen->has_out_of_order_rast = sscreen->info.chip_class >= VI &&
1038 sscreen->info.max_se >= 2 &&
1039 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1040 sscreen->assume_no_z_fights =
1041 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1042 sscreen->commutative_blend_add =
1043 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1044 sscreen->clear_db_cache_before_clear =
1045 driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
1046 sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
1047 sscreen->info.family <= CHIP_POLARIS12) ||
1048 sscreen->info.family == CHIP_VEGA10 ||
1049 sscreen->info.family == CHIP_RAVEN;
1050 sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
1051 sscreen->info.family == CHIP_RAVEN;
1052 sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2;
1053
1054 /* Only enable primitive binning on APUs by default. */
1055 sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN ||
1056 sscreen->info.family == CHIP_RAVEN2;
1057
1058 sscreen->dfsm_allowed = sscreen->info.family == CHIP_RAVEN ||
1059 sscreen->info.family == CHIP_RAVEN2;
1060
1061 /* Process DPBB enable flags. */
1062 if (sscreen->debug_flags & DBG(DPBB)) {
1063 sscreen->dpbb_allowed = true;
1064 if (sscreen->debug_flags & DBG(DFSM))
1065 sscreen->dfsm_allowed = true;
1066 }
1067
1068 /* Process DPBB disable flags. */
1069 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1070 sscreen->dpbb_allowed = false;
1071 sscreen->dfsm_allowed = false;
1072 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1073 sscreen->dfsm_allowed = false;
1074 }
1075
1076 /* While it would be nice not to have this flag, we are constrained
1077 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1078 * on GFX9.
1079 */
1080 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= VI;
1081
1082 /* Some chips have RB+ registers, but don't support RB+. Those must
1083 * always disable it.
1084 */
1085 if (sscreen->info.family == CHIP_STONEY ||
1086 sscreen->info.chip_class >= GFX9) {
1087 sscreen->has_rbplus = true;
1088
1089 sscreen->rbplus_allowed =
1090 !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
1091 (sscreen->info.family == CHIP_STONEY ||
1092 sscreen->info.family == CHIP_VEGA12 ||
1093 sscreen->info.family == CHIP_RAVEN ||
1094 sscreen->info.family == CHIP_RAVEN2);
1095 }
1096
1097 sscreen->dcc_msaa_allowed =
1098 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1099
1100 sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= VI;
1101
1102 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1103 sscreen->use_monolithic_shaders =
1104 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1105
1106 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1107 SI_CONTEXT_INV_VMEM_L1;
1108 if (sscreen->info.chip_class <= VI) {
1109 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1110 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1111 }
1112
1113 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1114 sscreen->debug_flags |= DBG_ALL_SHADERS;
1115
1116 /* Syntax:
1117 * EQAA=s,z,c
1118 * Example:
1119 * EQAA=8,4,2
1120
1121 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1122 * Constraints:
1123 * s >= z >= c (ignoring this only wastes memory)
1124 * s = [2..16]
1125 * z = [2..8]
1126 * c = [2..8]
1127 *
1128 * Only MSAA color and depth buffers are overriden.
1129 */
1130 if (sscreen->info.has_eqaa_surface_allocator) {
1131 const char *eqaa = debug_get_option("EQAA", NULL);
1132 unsigned s,z,f;
1133
1134 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1135 sscreen->eqaa_force_coverage_samples = s;
1136 sscreen->eqaa_force_z_samples = z;
1137 sscreen->eqaa_force_color_samples = f;
1138 }
1139 }
1140
1141 for (i = 0; i < num_comp_hi_threads; i++)
1142 si_init_compiler(sscreen, &sscreen->compiler[i]);
1143 for (i = 0; i < num_comp_lo_threads; i++)
1144 si_init_compiler(sscreen, &sscreen->compiler_lowp[i]);
1145
1146 /* Create the auxiliary context. This must be done last. */
1147 sscreen->aux_context = si_create_context(&sscreen->b, 0);
1148
1149 if (sscreen->debug_flags & DBG(TEST_DMA))
1150 si_test_dma(sscreen);
1151
1152 if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) {
1153 si_test_dma_perf(sscreen);
1154 }
1155
1156 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1157 DBG(TEST_VMFAULT_SDMA) |
1158 DBG(TEST_VMFAULT_SHADER)))
1159 si_test_vmfault(sscreen);
1160
1161 if (sscreen->debug_flags & DBG(TEST_GDS))
1162 si_test_gds((struct si_context*)sscreen->aux_context);
1163
1164 if (sscreen->debug_flags & DBG(TEST_GDS_MM)) {
1165 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1166 32 * 1024, 4, RADEON_DOMAIN_GDS);
1167 }
1168 if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) {
1169 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1170 4, 1, RADEON_DOMAIN_OA);
1171 }
1172
1173 return &sscreen->b;
1174 }