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radeonsi: move some global shader cache flags to per-binary flags
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
30 #include "sid.h"
31
32 #include "ac_llvm_util.h"
33 #include "radeon/radeon_uvd.h"
34 #include "util/disk_cache.h"
35 #include "util/u_log.h"
36 #include "util/u_memory.h"
37 #include "util/u_suballoc.h"
38 #include "util/u_tests.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/xmlconfig.h"
41 #include "vl/vl_decoder.h"
42 #include "driver_ddebug/dd_util.h"
43
44 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
45 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
46 #include <xf86drm.h>
47
48 static const struct debug_named_value debug_options[] = {
49 /* Shader logging options: */
50 { "vs", DBG(VS), "Print vertex shaders" },
51 { "ps", DBG(PS), "Print pixel shaders" },
52 { "gs", DBG(GS), "Print geometry shaders" },
53 { "tcs", DBG(TCS), "Print tessellation control shaders" },
54 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
55 { "cs", DBG(CS), "Print compute shaders" },
56 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
57 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
58 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
59 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
60
61 /* Shader compiler options the shader cache should be aware of: */
62 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
63 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
64 { "w32ge", DBG(W32_GE), "Use Wave32 for vertex, tessellation, and geometry shaders." },
65 { "w32ps", DBG(W32_PS), "Use Wave32 for pixel shaders." },
66 { "w32cs", DBG(W32_CS), "Use Wave32 for computes shaders." },
67 { "w64ge", DBG(W64_GE), "Use Wave64 for vertex, tessellation, and geometry shaders." },
68 { "w64ps", DBG(W64_PS), "Use Wave64 for pixel shaders." },
69 { "w64cs", DBG(W64_CS), "Use Wave64 for computes shaders." },
70
71 /* Shader compiler options (with no effect on the shader cache): */
72 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
73 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
74 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
75
76 /* Information logging options: */
77 { "info", DBG(INFO), "Print driver information" },
78 { "tex", DBG(TEX), "Print texture info" },
79 { "compute", DBG(COMPUTE), "Print compute info" },
80 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
81
82 /* Driver options: */
83 { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." },
84 { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
85 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
86 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
87 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
88 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
89
90 /* 3D engine options: */
91 { "nogfx", DBG(NO_GFX), "Disable graphics. Only multimedia compute paths can be used." },
92 { "alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader." },
93 { "pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls." },
94 { "nopd", DBG(NO_PD), "Disable the primitive discard compute shader." },
95 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
96 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
97 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
98 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
99 { "dpbb", DBG(DPBB), "Enable DPBB." },
100 { "dfsm", DBG(DFSM), "Enable DFSM." },
101 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
102 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
103 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
104 { "notiling", DBG(NO_TILING), "Disable tiling" },
105 { "nodcc", DBG(NO_DCC), "Disable DCC." },
106 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
107 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
108 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
109 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
110
111 /* Tests: */
112 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
113 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
114 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
115 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
116 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
117 { "testgds", DBG(TEST_GDS), "Test GDS." },
118 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
119 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
120
121 DEBUG_NAMED_VALUE_END /* must be last */
122 };
123
124 static void si_init_compiler(struct si_screen *sscreen,
125 struct ac_llvm_compiler *compiler)
126 {
127 /* Only create the less-optimizing version of the compiler on APUs
128 * predating Ryzen (Raven). */
129 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
130 sscreen->info.chip_class <= GFX8;
131
132 enum ac_target_machine_options tm_options =
133 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
134 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
135 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
136 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
137 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
138 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
139 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
140
141 ac_init_llvm_once();
142 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
143 compiler->passes = ac_create_llvm_passes(compiler->tm);
144
145 if (compiler->tm_wave32)
146 compiler->passes_wave32 = ac_create_llvm_passes(compiler->tm_wave32);
147 if (compiler->low_opt_tm)
148 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
149 }
150
151 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
152 {
153 ac_destroy_llvm_compiler(compiler);
154 }
155
156 /*
157 * pipe_context
158 */
159 static void si_destroy_context(struct pipe_context *context)
160 {
161 struct si_context *sctx = (struct si_context *)context;
162 int i;
163
164 util_queue_finish(&sctx->screen->shader_compiler_queue);
165 util_queue_finish(&sctx->screen->shader_compiler_queue_low_priority);
166
167 /* Unreference the framebuffer normally to disable related logic
168 * properly.
169 */
170 struct pipe_framebuffer_state fb = {};
171 if (context->set_framebuffer_state)
172 context->set_framebuffer_state(context, &fb);
173
174 si_release_all_descriptors(sctx);
175
176 if (sctx->chip_class >= GFX10)
177 gfx10_destroy_query(sctx);
178
179 pipe_resource_reference(&sctx->esgs_ring, NULL);
180 pipe_resource_reference(&sctx->gsvs_ring, NULL);
181 pipe_resource_reference(&sctx->tess_rings, NULL);
182 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
183 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
184 si_resource_reference(&sctx->border_color_buffer, NULL);
185 free(sctx->border_color_table);
186 si_resource_reference(&sctx->scratch_buffer, NULL);
187 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
188 si_resource_reference(&sctx->wait_mem_scratch, NULL);
189
190 si_pm4_free_state(sctx, sctx->init_config, ~0);
191 if (sctx->init_config_gs_rings)
192 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
193 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
194 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
195
196 if (sctx->fixed_func_tcs_shader.cso)
197 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
198 if (sctx->custom_dsa_flush)
199 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
200 if (sctx->custom_blend_resolve)
201 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
202 if (sctx->custom_blend_fmask_decompress)
203 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
204 if (sctx->custom_blend_eliminate_fastclear)
205 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
206 if (sctx->custom_blend_dcc_decompress)
207 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
208 if (sctx->vs_blit_pos)
209 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
210 if (sctx->vs_blit_pos_layered)
211 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
212 if (sctx->vs_blit_color)
213 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
214 if (sctx->vs_blit_color_layered)
215 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
216 if (sctx->vs_blit_texcoord)
217 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
218 if (sctx->cs_clear_buffer)
219 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
220 if (sctx->cs_copy_buffer)
221 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
222 if (sctx->cs_copy_image)
223 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
224 if (sctx->cs_copy_image_1d_array)
225 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
226 if (sctx->cs_clear_render_target)
227 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
228 if (sctx->cs_clear_render_target_1d_array)
229 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
230 if (sctx->cs_dcc_retile)
231 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile);
232
233 if (sctx->blitter)
234 util_blitter_destroy(sctx->blitter);
235
236 /* Release DCC stats. */
237 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
238 assert(!sctx->dcc_stats[i].query_active);
239
240 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
241 if (sctx->dcc_stats[i].ps_stats[j])
242 sctx->b.destroy_query(&sctx->b,
243 sctx->dcc_stats[i].ps_stats[j]);
244
245 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
246 }
247
248 if (sctx->query_result_shader)
249 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
250 if (sctx->sh_query_result_shader)
251 sctx->b.delete_compute_state(&sctx->b, sctx->sh_query_result_shader);
252
253 if (sctx->gfx_cs)
254 sctx->ws->cs_destroy(sctx->gfx_cs);
255 if (sctx->dma_cs)
256 sctx->ws->cs_destroy(sctx->dma_cs);
257 if (sctx->ctx)
258 sctx->ws->ctx_destroy(sctx->ctx);
259
260 if (sctx->b.stream_uploader)
261 u_upload_destroy(sctx->b.stream_uploader);
262 if (sctx->b.const_uploader)
263 u_upload_destroy(sctx->b.const_uploader);
264 if (sctx->cached_gtt_allocator)
265 u_upload_destroy(sctx->cached_gtt_allocator);
266
267 slab_destroy_child(&sctx->pool_transfers);
268 slab_destroy_child(&sctx->pool_transfers_unsync);
269
270 if (sctx->allocator_zeroed_memory)
271 u_suballocator_destroy(sctx->allocator_zeroed_memory);
272
273 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
274 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
275 sctx->ws->fence_reference(&sctx->last_ib_barrier_fence, NULL);
276 si_resource_reference(&sctx->eop_bug_scratch, NULL);
277 si_resource_reference(&sctx->index_ring, NULL);
278 si_resource_reference(&sctx->barrier_buf, NULL);
279 si_resource_reference(&sctx->last_ib_barrier_buf, NULL);
280 pb_reference(&sctx->gds, NULL);
281 pb_reference(&sctx->gds_oa, NULL);
282
283 si_destroy_compiler(&sctx->compiler);
284
285 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
286
287 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
288 _mesa_hash_table_destroy(sctx->img_handles, NULL);
289
290 util_dynarray_fini(&sctx->resident_tex_handles);
291 util_dynarray_fini(&sctx->resident_img_handles);
292 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
293 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
294 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
295 si_unref_sdma_uploads(sctx);
296 FREE(sctx);
297 }
298
299 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
300 {
301 struct si_context *sctx = (struct si_context *)ctx;
302
303 return sctx->ws->ctx_query_reset_status(sctx->ctx);
304 }
305
306 static void si_set_device_reset_callback(struct pipe_context *ctx,
307 const struct pipe_device_reset_callback *cb)
308 {
309 struct si_context *sctx = (struct si_context *)ctx;
310
311 if (cb)
312 sctx->device_reset_callback = *cb;
313 else
314 memset(&sctx->device_reset_callback, 0,
315 sizeof(sctx->device_reset_callback));
316 }
317
318 bool si_check_device_reset(struct si_context *sctx)
319 {
320 enum pipe_reset_status status;
321
322 if (!sctx->device_reset_callback.reset)
323 return false;
324
325 status = sctx->ws->ctx_query_reset_status(sctx->ctx);
326 if (status == PIPE_NO_RESET)
327 return false;
328
329 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
330 return true;
331 }
332
333 /* Apitrace profiling:
334 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
335 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
336 * and remember its number.
337 * 3) In Mesa, enable queries and performance counters around that draw
338 * call and print the results.
339 * 4) glretrace --benchmark --markers ..
340 */
341 static void si_emit_string_marker(struct pipe_context *ctx,
342 const char *string, int len)
343 {
344 struct si_context *sctx = (struct si_context *)ctx;
345
346 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
347
348 if (sctx->log)
349 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
350 }
351
352 static void si_set_debug_callback(struct pipe_context *ctx,
353 const struct pipe_debug_callback *cb)
354 {
355 struct si_context *sctx = (struct si_context *)ctx;
356 struct si_screen *screen = sctx->screen;
357
358 util_queue_finish(&screen->shader_compiler_queue);
359 util_queue_finish(&screen->shader_compiler_queue_low_priority);
360
361 if (cb)
362 sctx->debug = *cb;
363 else
364 memset(&sctx->debug, 0, sizeof(sctx->debug));
365 }
366
367 static void si_set_log_context(struct pipe_context *ctx,
368 struct u_log_context *log)
369 {
370 struct si_context *sctx = (struct si_context *)ctx;
371 sctx->log = log;
372
373 if (log)
374 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
375 }
376
377 static void si_set_context_param(struct pipe_context *ctx,
378 enum pipe_context_param param,
379 unsigned value)
380 {
381 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
382
383 switch (param) {
384 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
385 ws->pin_threads_to_L3_cache(ws, value);
386 break;
387 default:;
388 }
389 }
390
391 static struct pipe_context *si_create_context(struct pipe_screen *screen,
392 unsigned flags)
393 {
394 struct si_screen* sscreen = (struct si_screen *)screen;
395
396 /* Don't create a context if it's not compute-only and hw is compute-only. */
397 if (!sscreen->info.has_graphics &&
398 !(flags & PIPE_CONTEXT_COMPUTE_ONLY))
399 return NULL;
400
401 struct si_context *sctx = CALLOC_STRUCT(si_context);
402 struct radeon_winsys *ws = sscreen->ws;
403 int shader, i;
404 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
405
406 if (!sctx)
407 return NULL;
408
409 sctx->has_graphics = sscreen->info.chip_class == GFX6 ||
410 !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
411
412 if (flags & PIPE_CONTEXT_DEBUG)
413 sscreen->record_llvm_ir = true; /* racy but not critical */
414
415 sctx->b.screen = screen; /* this must be set first */
416 sctx->b.priv = NULL;
417 sctx->b.destroy = si_destroy_context;
418 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
419 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
420
421 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
422 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
423
424 sctx->ws = sscreen->ws;
425 sctx->family = sscreen->info.family;
426 sctx->chip_class = sscreen->info.chip_class;
427
428 if (sctx->chip_class == GFX7 ||
429 sctx->chip_class == GFX8 ||
430 sctx->chip_class == GFX9) {
431 sctx->eop_bug_scratch = si_resource(
432 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
433 16 * sscreen->info.num_render_backends));
434 if (!sctx->eop_bug_scratch)
435 goto fail;
436 }
437
438 /* Initialize context allocators. */
439 sctx->allocator_zeroed_memory =
440 u_suballocator_create(&sctx->b, 128 * 1024,
441 0, PIPE_USAGE_DEFAULT,
442 SI_RESOURCE_FLAG_UNMAPPABLE |
443 SI_RESOURCE_FLAG_CLEAR, false);
444 if (!sctx->allocator_zeroed_memory)
445 goto fail;
446
447 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
448 0, PIPE_USAGE_STREAM,
449 SI_RESOURCE_FLAG_READ_ONLY);
450 if (!sctx->b.stream_uploader)
451 goto fail;
452
453 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
454 0, PIPE_USAGE_STAGING, 0);
455 if (!sctx->cached_gtt_allocator)
456 goto fail;
457
458 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
459 if (!sctx->ctx)
460 goto fail;
461
462 if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
463 sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
464 (void*)si_flush_dma_cs,
465 sctx, stop_exec_on_failure);
466 }
467
468 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->dma_cs;
469 sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
470 0, PIPE_USAGE_DEFAULT,
471 SI_RESOURCE_FLAG_32BIT |
472 (use_sdma_upload ?
473 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA : 0));
474 if (!sctx->b.const_uploader)
475 goto fail;
476
477 if (use_sdma_upload)
478 u_upload_enable_flush_explicit(sctx->b.const_uploader);
479
480 sctx->gfx_cs = ws->cs_create(sctx->ctx,
481 sctx->has_graphics ? RING_GFX : RING_COMPUTE,
482 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
483
484 /* Border colors. */
485 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
486 sizeof(*sctx->border_color_table));
487 if (!sctx->border_color_table)
488 goto fail;
489
490 sctx->border_color_buffer = si_resource(
491 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
492 SI_MAX_BORDER_COLORS *
493 sizeof(*sctx->border_color_table)));
494 if (!sctx->border_color_buffer)
495 goto fail;
496
497 sctx->border_color_map =
498 ws->buffer_map(sctx->border_color_buffer->buf,
499 NULL, PIPE_TRANSFER_WRITE);
500 if (!sctx->border_color_map)
501 goto fail;
502
503 sctx->ngg = sscreen->use_ngg;
504
505 /* Initialize context functions used by graphics and compute. */
506 if (sctx->chip_class >= GFX10)
507 sctx->emit_cache_flush = gfx10_emit_cache_flush;
508 else
509 sctx->emit_cache_flush = si_emit_cache_flush;
510
511 sctx->b.emit_string_marker = si_emit_string_marker;
512 sctx->b.set_debug_callback = si_set_debug_callback;
513 sctx->b.set_log_context = si_set_log_context;
514 sctx->b.set_context_param = si_set_context_param;
515 sctx->b.get_device_reset_status = si_get_reset_status;
516 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
517
518 si_init_all_descriptors(sctx);
519 si_init_buffer_functions(sctx);
520 si_init_clear_functions(sctx);
521 si_init_blit_functions(sctx);
522 si_init_compute_functions(sctx);
523 si_init_compute_blit_functions(sctx);
524 si_init_debug_functions(sctx);
525 si_init_fence_functions(sctx);
526 si_init_query_functions(sctx);
527 si_init_state_compute_functions(sctx);
528 si_init_context_texture_functions(sctx);
529
530 /* Initialize graphics-only context functions. */
531 if (sctx->has_graphics) {
532 if (sctx->chip_class >= GFX10)
533 gfx10_init_query(sctx);
534 si_init_msaa_functions(sctx);
535 si_init_shader_functions(sctx);
536 si_init_state_functions(sctx);
537 si_init_streamout_functions(sctx);
538 si_init_viewport_functions(sctx);
539
540 sctx->blitter = util_blitter_create(&sctx->b);
541 if (sctx->blitter == NULL)
542 goto fail;
543 sctx->blitter->skip_viewport_restore = true;
544
545 /* Some states are expected to be always non-NULL. */
546 sctx->noop_blend = util_blitter_get_noop_blend_state(sctx->blitter);
547 sctx->queued.named.blend = sctx->noop_blend;
548
549 sctx->noop_dsa = util_blitter_get_noop_dsa_state(sctx->blitter);
550 sctx->queued.named.dsa = sctx->noop_dsa;
551
552 sctx->discard_rasterizer_state =
553 util_blitter_get_discard_rasterizer_state(sctx->blitter);
554 sctx->queued.named.rasterizer = sctx->discard_rasterizer_state;
555
556 si_init_draw_functions(sctx);
557 si_initialize_prim_discard_tunables(sctx);
558 }
559
560 /* Initialize SDMA functions. */
561 if (sctx->chip_class >= GFX7)
562 cik_init_sdma_functions(sctx);
563 else
564 si_init_dma_functions(sctx);
565
566 if (sscreen->debug_flags & DBG(FORCE_DMA))
567 sctx->b.resource_copy_region = sctx->dma_copy;
568
569 sctx->sample_mask = 0xffff;
570
571 /* Initialize multimedia functions. */
572 if (sscreen->info.has_hw_decode) {
573 sctx->b.create_video_codec = si_uvd_create_decoder;
574 sctx->b.create_video_buffer = si_video_buffer_create;
575 } else {
576 sctx->b.create_video_codec = vl_create_decoder;
577 sctx->b.create_video_buffer = vl_video_buffer_create;
578 }
579
580 if (sctx->chip_class >= GFX9) {
581 sctx->wait_mem_scratch = si_resource(
582 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 8));
583 if (!sctx->wait_mem_scratch)
584 goto fail;
585
586 /* Initialize the memory. */
587 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
588 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
589 }
590
591 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
592 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
593 if (sctx->chip_class == GFX7) {
594 sctx->null_const_buf.buffer =
595 pipe_aligned_buffer_create(screen,
596 SI_RESOURCE_FLAG_32BIT,
597 PIPE_USAGE_DEFAULT, 16,
598 sctx->screen->info.tcc_cache_line_size);
599 if (!sctx->null_const_buf.buffer)
600 goto fail;
601 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
602
603 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
604 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
605 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
606 sctx->b.set_constant_buffer(&sctx->b, shader, i,
607 &sctx->null_const_buf);
608 }
609 }
610
611 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
612 &sctx->null_const_buf);
613 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
614 &sctx->null_const_buf);
615 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
616 &sctx->null_const_buf);
617 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
618 &sctx->null_const_buf);
619 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
620 &sctx->null_const_buf);
621 }
622
623 uint64_t max_threads_per_block;
624 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
625 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
626 &max_threads_per_block);
627
628 /* The maximum number of scratch waves. Scratch space isn't divided
629 * evenly between CUs. The number is only a function of the number of CUs.
630 * We can decrease the constant to decrease the scratch buffer size.
631 *
632 * sctx->scratch_waves must be >= the maximum posible size of
633 * 1 threadgroup, so that the hw doesn't hang from being unable
634 * to start any.
635 *
636 * The recommended value is 4 per CU at most. Higher numbers don't
637 * bring much benefit, but they still occupy chip resources (think
638 * async compute). I've seen ~2% performance difference between 4 and 32.
639 */
640 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
641 max_threads_per_block / 64);
642
643 si_init_compiler(sscreen, &sctx->compiler);
644
645 /* Bindless handles. */
646 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
647 _mesa_key_pointer_equal);
648 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
649 _mesa_key_pointer_equal);
650
651 util_dynarray_init(&sctx->resident_tex_handles, NULL);
652 util_dynarray_init(&sctx->resident_img_handles, NULL);
653 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
654 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
655 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
656
657 sctx->sample_pos_buffer =
658 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
659 sizeof(sctx->sample_positions));
660 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
661 sizeof(sctx->sample_positions), &sctx->sample_positions);
662
663 /* this must be last */
664 si_begin_new_gfx_cs(sctx);
665
666 if (sctx->chip_class == GFX7) {
667 /* Clear the NULL constant buffer, because loads should return zeros.
668 * Note that this forces CP DMA to be used, because clover deadlocks
669 * for some reason when the compute codepath is used.
670 */
671 uint32_t clear_value = 0;
672 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
673 sctx->null_const_buf.buffer->width0,
674 &clear_value, 4, SI_COHERENCY_SHADER, true);
675 }
676 return &sctx->b;
677 fail:
678 fprintf(stderr, "radeonsi: Failed to create a context.\n");
679 si_destroy_context(&sctx->b);
680 return NULL;
681 }
682
683 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
684 void *priv, unsigned flags)
685 {
686 struct si_screen *sscreen = (struct si_screen *)screen;
687 struct pipe_context *ctx;
688
689 if (sscreen->debug_flags & DBG(CHECK_VM))
690 flags |= PIPE_CONTEXT_DEBUG;
691
692 ctx = si_create_context(screen, flags);
693
694 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
695 return ctx;
696
697 /* Clover (compute-only) is unsupported. */
698 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
699 return ctx;
700
701 /* When shaders are logged to stderr, asynchronous compilation is
702 * disabled too. */
703 if (sscreen->debug_flags & DBG_ALL_SHADERS)
704 return ctx;
705
706 /* Use asynchronous flushes only on amdgpu, since the radeon
707 * implementation for fence_server_sync is incomplete. */
708 return threaded_context_create(ctx, &sscreen->pool_transfers,
709 si_replace_buffer_storage,
710 sscreen->info.is_amdgpu ? si_create_fence : NULL,
711 &((struct si_context*)ctx)->tc);
712 }
713
714 /*
715 * pipe_screen
716 */
717 static void si_destroy_screen(struct pipe_screen* pscreen)
718 {
719 struct si_screen *sscreen = (struct si_screen *)pscreen;
720 struct si_shader_part *parts[] = {
721 sscreen->vs_prologs,
722 sscreen->tcs_epilogs,
723 sscreen->gs_prologs,
724 sscreen->ps_prologs,
725 sscreen->ps_epilogs
726 };
727 unsigned i;
728
729 if (!sscreen->ws->unref(sscreen->ws))
730 return;
731
732 mtx_destroy(&sscreen->aux_context_lock);
733
734 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
735 if (aux_log) {
736 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
737 u_log_context_destroy(aux_log);
738 FREE(aux_log);
739 }
740
741 sscreen->aux_context->destroy(sscreen->aux_context);
742
743 util_queue_destroy(&sscreen->shader_compiler_queue);
744 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
745
746 /* Release the reference on glsl types of the compiler threads. */
747 glsl_type_singleton_decref();
748
749 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
750 si_destroy_compiler(&sscreen->compiler[i]);
751
752 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
753 si_destroy_compiler(&sscreen->compiler_lowp[i]);
754
755 /* Free shader parts. */
756 for (i = 0; i < ARRAY_SIZE(parts); i++) {
757 while (parts[i]) {
758 struct si_shader_part *part = parts[i];
759
760 parts[i] = part->next;
761 si_shader_binary_clean(&part->binary);
762 FREE(part);
763 }
764 }
765 mtx_destroy(&sscreen->shader_parts_mutex);
766 si_destroy_shader_cache(sscreen);
767
768 si_destroy_perfcounters(sscreen);
769 si_gpu_load_kill_thread(sscreen);
770
771 mtx_destroy(&sscreen->gpu_load_mutex);
772
773 slab_destroy_parent(&sscreen->pool_transfers);
774
775 disk_cache_destroy(sscreen->disk_shader_cache);
776 sscreen->ws->destroy(sscreen->ws);
777 FREE(sscreen);
778 }
779
780 static void si_init_gs_info(struct si_screen *sscreen)
781 {
782 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
783 sscreen->info.family);
784 }
785
786 static void si_test_vmfault(struct si_screen *sscreen)
787 {
788 struct pipe_context *ctx = sscreen->aux_context;
789 struct si_context *sctx = (struct si_context *)ctx;
790 struct pipe_resource *buf =
791 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
792
793 if (!buf) {
794 puts("Buffer allocation failed.");
795 exit(1);
796 }
797
798 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
799
800 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
801 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
802 SI_COHERENCY_NONE, L2_BYPASS);
803 ctx->flush(ctx, NULL, 0);
804 puts("VM fault test: CP - done.");
805 }
806 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
807 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
808 ctx->flush(ctx, NULL, 0);
809 puts("VM fault test: SDMA - done.");
810 }
811 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
812 util_test_constant_buffer(ctx, buf);
813 puts("VM fault test: Shader - done.");
814 }
815 exit(0);
816 }
817
818 static void si_test_gds_memory_management(struct si_context *sctx,
819 unsigned alloc_size, unsigned alignment,
820 enum radeon_bo_domain domain)
821 {
822 struct radeon_winsys *ws = sctx->ws;
823 struct radeon_cmdbuf *cs[8];
824 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
825
826 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
827 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
828 NULL, NULL, false);
829 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
830 assert(gds_bo[i]);
831 }
832
833 for (unsigned iterations = 0; iterations < 20000; iterations++) {
834 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
835 /* This clears GDS with CP DMA.
836 *
837 * We don't care if GDS is present. Just add some packet
838 * to make the GPU busy for a moment.
839 */
840 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
841 SI_CPDMA_SKIP_BO_LIST_UPDATE |
842 SI_CPDMA_SKIP_CHECK_CS_SPACE |
843 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
844
845 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
846 RADEON_USAGE_READWRITE, 0);
847 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
848 }
849 }
850 exit(0);
851 }
852
853 static void si_disk_cache_create(struct si_screen *sscreen)
854 {
855 /* Don't use the cache if shader dumping is enabled. */
856 if (sscreen->debug_flags & DBG_ALL_SHADERS)
857 return;
858
859 struct mesa_sha1 ctx;
860 unsigned char sha1[20];
861 char cache_id[20 * 2 + 1];
862
863 _mesa_sha1_init(&ctx);
864
865 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
866 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
867 &ctx))
868 return;
869
870 _mesa_sha1_final(&ctx, sha1);
871 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
872
873 /* These flags affect shader compilation. */
874 #define ALL_FLAGS (DBG(SI_SCHED) | DBG(GISEL))
875 uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS;
876
877 /* Add the high bits of 32-bit addresses, which affects
878 * how 32-bit addresses are expanded to 64 bits.
879 */
880 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
881 assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
882 shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
883
884 sscreen->disk_shader_cache =
885 disk_cache_create(sscreen->info.name,
886 cache_id,
887 shader_debug_flags);
888 }
889
890 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen,
891 unsigned max_threads)
892 {
893 struct si_screen *sscreen = (struct si_screen *)screen;
894
895 /* This function doesn't allow a greater number of threads than
896 * the queue had at its creation. */
897 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue,
898 max_threads);
899 /* Don't change the number of threads on the low priority queue. */
900 }
901
902 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen,
903 void *shader,
904 enum pipe_shader_type shader_type)
905 {
906 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
907
908 return util_queue_fence_is_signalled(&sel->ready);
909 }
910
911 static struct pipe_screen *
912 radeonsi_screen_create_impl(struct radeon_winsys *ws,
913 const struct pipe_screen_config *config)
914 {
915 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
916 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i;
917
918 if (!sscreen) {
919 return NULL;
920 }
921
922 sscreen->ws = ws;
923 ws->query_info(ws, &sscreen->info);
924
925 if (sscreen->info.chip_class == GFX10 && HAVE_LLVM < 0x0900) {
926 fprintf(stderr, "radeonsi: Navi family support requires LLVM 9 or higher\n");
927 FREE(sscreen);
928 return NULL;
929 }
930
931 if (sscreen->info.chip_class >= GFX9) {
932 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
933 } else {
934 ac_get_raster_config(&sscreen->info,
935 &sscreen->pa_sc_raster_config,
936 &sscreen->pa_sc_raster_config_1,
937 &sscreen->se_tile_repeat);
938 }
939
940 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
941 debug_options, 0);
942 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
943 debug_options, 0);
944
945 if (sscreen->debug_flags & DBG(NO_GFX))
946 sscreen->info.has_graphics = false;
947
948 /* Set functions first. */
949 sscreen->b.context_create = si_pipe_create_context;
950 sscreen->b.destroy = si_destroy_screen;
951 sscreen->b.set_max_shader_compiler_threads =
952 si_set_max_shader_compiler_threads;
953 sscreen->b.is_parallel_shader_compilation_finished =
954 si_is_parallel_shader_compilation_finished;
955
956 si_init_screen_get_functions(sscreen);
957 si_init_screen_buffer_functions(sscreen);
958 si_init_screen_fence_functions(sscreen);
959 si_init_screen_state_functions(sscreen);
960 si_init_screen_texture_functions(sscreen);
961 si_init_screen_query_functions(sscreen);
962
963 /* Set these flags in debug_flags early, so that the shader cache takes
964 * them into account.
965 */
966 if (driQueryOptionb(config->options,
967 "glsl_correct_derivatives_after_discard"))
968 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
969 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
970 sscreen->debug_flags |= DBG(SI_SCHED);
971
972 if (sscreen->debug_flags & DBG(INFO))
973 ac_print_gpu_info(&sscreen->info);
974
975 slab_create_parent(&sscreen->pool_transfers,
976 sizeof(struct si_transfer), 64);
977
978 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
979 if (sscreen->force_aniso == -1) {
980 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
981 }
982
983 if (sscreen->force_aniso >= 0) {
984 printf("radeonsi: Forcing anisotropy filter to %ix\n",
985 /* round down to a power of two */
986 1 << util_logbase2(sscreen->force_aniso));
987 }
988
989 (void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
990 (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
991
992 si_init_gs_info(sscreen);
993 if (!si_init_shader_cache(sscreen)) {
994 FREE(sscreen);
995 return NULL;
996 }
997
998 si_disk_cache_create(sscreen);
999
1000 /* Determine the number of shader compiler threads. */
1001 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
1002
1003 if (hw_threads >= 12) {
1004 num_comp_hi_threads = hw_threads * 3 / 4;
1005 num_comp_lo_threads = hw_threads / 3;
1006 } else if (hw_threads >= 6) {
1007 num_comp_hi_threads = hw_threads - 2;
1008 num_comp_lo_threads = hw_threads / 2;
1009 } else if (hw_threads >= 2) {
1010 num_comp_hi_threads = hw_threads - 1;
1011 num_comp_lo_threads = hw_threads / 2;
1012 } else {
1013 num_comp_hi_threads = 1;
1014 num_comp_lo_threads = 1;
1015 }
1016
1017 num_comp_hi_threads = MIN2(num_comp_hi_threads,
1018 ARRAY_SIZE(sscreen->compiler));
1019 num_comp_lo_threads = MIN2(num_comp_lo_threads,
1020 ARRAY_SIZE(sscreen->compiler_lowp));
1021
1022 /* Take a reference on the glsl types for the compiler threads. */
1023 glsl_type_singleton_init_or_ref();
1024
1025 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
1026 64, num_comp_hi_threads,
1027 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1028 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
1029 si_destroy_shader_cache(sscreen);
1030 FREE(sscreen);
1031 glsl_type_singleton_decref();
1032 return NULL;
1033 }
1034
1035 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
1036 "shlo",
1037 64, num_comp_lo_threads,
1038 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1039 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
1040 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1041 si_destroy_shader_cache(sscreen);
1042 FREE(sscreen);
1043 glsl_type_singleton_decref();
1044 return NULL;
1045 }
1046
1047 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1048 si_init_perfcounters(sscreen);
1049
1050 /* Determine tessellation ring info. */
1051 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
1052 sscreen->info.family != CHIP_CARRIZO &&
1053 sscreen->info.family != CHIP_STONEY;
1054 /* This must be one less than the maximum number due to a hw limitation.
1055 * Various hardware bugs need this.
1056 */
1057 unsigned max_offchip_buffers_per_se;
1058
1059 if (sscreen->info.chip_class >= GFX10)
1060 max_offchip_buffers_per_se = 256;
1061 /* Only certain chips can use the maximum value. */
1062 else if (sscreen->info.family == CHIP_VEGA12 ||
1063 sscreen->info.family == CHIP_VEGA20)
1064 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1065 else
1066 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1067
1068 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1069 sscreen->info.max_se;
1070 unsigned offchip_granularity;
1071
1072 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1073 * around by setting 4K granularity.
1074 */
1075 if (sscreen->info.family == CHIP_HAWAII) {
1076 sscreen->tess_offchip_block_dw_size = 4096;
1077 offchip_granularity = V_03093C_X_4K_DWORDS;
1078 } else {
1079 sscreen->tess_offchip_block_dw_size = 8192;
1080 offchip_granularity = V_03093C_X_8K_DWORDS;
1081 }
1082
1083 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
1084 sscreen->tess_offchip_ring_size = max_offchip_buffers *
1085 sscreen->tess_offchip_block_dw_size * 4;
1086
1087 if (sscreen->info.chip_class >= GFX7) {
1088 if (sscreen->info.chip_class >= GFX8)
1089 --max_offchip_buffers;
1090 sscreen->vgt_hs_offchip_param =
1091 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1092 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1093 } else {
1094 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1095 sscreen->vgt_hs_offchip_param =
1096 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1097 }
1098
1099 sscreen->has_draw_indirect_multi =
1100 (sscreen->info.family >= CHIP_POLARIS10) ||
1101 (sscreen->info.chip_class == GFX8 &&
1102 sscreen->info.pfp_fw_version >= 121 &&
1103 sscreen->info.me_fw_version >= 87) ||
1104 (sscreen->info.chip_class == GFX7 &&
1105 sscreen->info.pfp_fw_version >= 211 &&
1106 sscreen->info.me_fw_version >= 173) ||
1107 (sscreen->info.chip_class == GFX6 &&
1108 sscreen->info.pfp_fw_version >= 79 &&
1109 sscreen->info.me_fw_version >= 142);
1110
1111 sscreen->has_out_of_order_rast = sscreen->info.has_out_of_order_rast &&
1112 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1113 sscreen->assume_no_z_fights =
1114 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1115 sscreen->commutative_blend_add =
1116 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1117
1118 {
1119 #define OPT_BOOL(name, dflt, description) \
1120 sscreen->options.name = \
1121 driQueryOptionb(config->options, "radeonsi_"#name);
1122 #include "si_debug_options.h"
1123 }
1124
1125 sscreen->use_ngg = sscreen->info.chip_class >= GFX10;
1126 sscreen->use_ngg_streamout = sscreen->info.chip_class >= GFX10;
1127
1128 /* Only enable primitive binning on APUs by default. */
1129 if (sscreen->info.chip_class >= GFX10) {
1130 sscreen->dpbb_allowed = true;
1131 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1132 } else if (sscreen->info.chip_class == GFX9) {
1133 sscreen->dpbb_allowed = !sscreen->info.has_dedicated_vram;
1134 sscreen->dfsm_allowed = !sscreen->info.has_dedicated_vram;
1135 }
1136
1137 /* Process DPBB enable flags. */
1138 if (sscreen->debug_flags & DBG(DPBB)) {
1139 sscreen->dpbb_allowed = true;
1140 if (sscreen->debug_flags & DBG(DFSM))
1141 sscreen->dfsm_allowed = true;
1142 }
1143
1144 /* Process DPBB disable flags. */
1145 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1146 sscreen->dpbb_allowed = false;
1147 sscreen->dfsm_allowed = false;
1148 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1149 sscreen->dfsm_allowed = false;
1150 }
1151
1152 /* While it would be nice not to have this flag, we are constrained
1153 * by the reality that LLVM 9.0 has buggy VGPR indexing on GFX9.
1154 */
1155 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class != GFX9;
1156
1157 sscreen->dcc_msaa_allowed =
1158 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1159
1160 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1161 sscreen->use_monolithic_shaders =
1162 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1163
1164 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SCACHE |
1165 SI_CONTEXT_INV_VCACHE;
1166 if (sscreen->info.chip_class <= GFX8) {
1167 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_L2;
1168 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WB_L2;
1169 }
1170
1171 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1172 sscreen->debug_flags |= DBG_ALL_SHADERS;
1173
1174 /* Syntax:
1175 * EQAA=s,z,c
1176 * Example:
1177 * EQAA=8,4,2
1178
1179 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1180 * Constraints:
1181 * s >= z >= c (ignoring this only wastes memory)
1182 * s = [2..16]
1183 * z = [2..8]
1184 * c = [2..8]
1185 *
1186 * Only MSAA color and depth buffers are overriden.
1187 */
1188 if (sscreen->info.has_eqaa_surface_allocator) {
1189 const char *eqaa = debug_get_option("EQAA", NULL);
1190 unsigned s,z,f;
1191
1192 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1193 sscreen->eqaa_force_coverage_samples = s;
1194 sscreen->eqaa_force_z_samples = z;
1195 sscreen->eqaa_force_color_samples = f;
1196 }
1197 }
1198
1199 for (i = 0; i < num_comp_hi_threads; i++)
1200 si_init_compiler(sscreen, &sscreen->compiler[i]);
1201 for (i = 0; i < num_comp_lo_threads; i++)
1202 si_init_compiler(sscreen, &sscreen->compiler_lowp[i]);
1203
1204 sscreen->ge_wave_size = 64;
1205 sscreen->ps_wave_size = 64;
1206 sscreen->compute_wave_size = 64;
1207
1208 if (sscreen->info.chip_class >= GFX10) {
1209 /* Pixels shaders: Wave64 is recommended.
1210 * Compute shaders: There are piglit failures with Wave32.
1211 */
1212 sscreen->ge_wave_size = 32;
1213
1214 if (sscreen->debug_flags & DBG(W32_GE))
1215 sscreen->ge_wave_size = 32;
1216 if (sscreen->debug_flags & DBG(W32_PS))
1217 sscreen->ps_wave_size = 32;
1218 if (sscreen->debug_flags & DBG(W32_CS))
1219 sscreen->compute_wave_size = 32;
1220
1221 if (sscreen->debug_flags & DBG(W64_GE))
1222 sscreen->ge_wave_size = 64;
1223 if (sscreen->debug_flags & DBG(W64_PS))
1224 sscreen->ps_wave_size = 64;
1225 if (sscreen->debug_flags & DBG(W64_CS))
1226 sscreen->compute_wave_size = 64;
1227 }
1228
1229 /* Create the auxiliary context. This must be done last. */
1230 sscreen->aux_context = si_create_context(&sscreen->b,
1231 (sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0) |
1232 (sscreen->info.has_graphics ? 0 : PIPE_CONTEXT_COMPUTE_ONLY));
1233 if (sscreen->options.aux_debug) {
1234 struct u_log_context *log = CALLOC_STRUCT(u_log_context);
1235 u_log_context_init(log);
1236 sscreen->aux_context->set_log_context(sscreen->aux_context, log);
1237 }
1238
1239 if (sscreen->debug_flags & DBG(TEST_DMA))
1240 si_test_dma(sscreen);
1241
1242 if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) {
1243 si_test_dma_perf(sscreen);
1244 }
1245
1246 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1247 DBG(TEST_VMFAULT_SDMA) |
1248 DBG(TEST_VMFAULT_SHADER)))
1249 si_test_vmfault(sscreen);
1250
1251 if (sscreen->debug_flags & DBG(TEST_GDS))
1252 si_test_gds((struct si_context*)sscreen->aux_context);
1253
1254 if (sscreen->debug_flags & DBG(TEST_GDS_MM)) {
1255 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1256 32 * 1024, 4, RADEON_DOMAIN_GDS);
1257 }
1258 if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) {
1259 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1260 4, 1, RADEON_DOMAIN_OA);
1261 }
1262
1263 return &sscreen->b;
1264 }
1265
1266 struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config)
1267 {
1268 drmVersionPtr version = drmGetVersion(fd);
1269 struct radeon_winsys *rw = NULL;
1270
1271 switch (version->version_major) {
1272 case 2:
1273 rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl);
1274 break;
1275 case 3:
1276 rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl);
1277 break;
1278 }
1279
1280 drmFreeVersion(version);
1281 return rw ? rw->screen : NULL;
1282 }