src/gallium/drivers/radeonsi/si_pipe.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_pipe.h"
  25 #include "si_shader.h"
  26 #include "si_public.h"
  27 #include "sid.h"
  28
  29 #include "radeon/radeon_llvm_emit.h"
  30 #include "radeon/radeon_uvd.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_suballoc.h"
  33 #include "vl/vl_decoder.h"
  34 #include "../ddebug/dd_util.h"
  35
  36 #define SI_LLVM_DEFAULT_FEATURES \
  37         "+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals"
  38
  39 /*
  40  * pipe_context
  41  */
  42 static void si_destroy_context(struct pipe_context *context)
  43 {
  44         struct si_context *sctx = (struct si_context *)context;
  45         int i;
  46
  47         /* Unreference the framebuffer normally to disable related logic
  48          * properly.
  49          */
  50         struct pipe_framebuffer_state fb = {};
  51         context->set_framebuffer_state(context, &fb);
  52
  53         si_release_all_descriptors(sctx);
  54
  55         if (sctx->ce_suballocator)
  56                 u_suballocator_destroy(sctx->ce_suballocator);
  57
  58         pipe_resource_reference(&sctx->esgs_ring, NULL);
  59         pipe_resource_reference(&sctx->gsvs_ring, NULL);
  60         pipe_resource_reference(&sctx->tf_ring, NULL);
  61         pipe_resource_reference(&sctx->tess_offchip_ring, NULL);
  62         pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
  63         r600_resource_reference(&sctx->border_color_buffer, NULL);
  64         free(sctx->border_color_table);
  65         r600_resource_reference(&sctx->scratch_buffer, NULL);
  66         r600_resource_reference(&sctx->compute_scratch_buffer, NULL);
  67
  68         si_pm4_free_state(sctx, sctx->init_config, ~0);
  69         if (sctx->init_config_gs_rings)
  70                 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
  71         for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
  72                 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
  73
  74         if (sctx->fixed_func_tcs_shader.cso)
  75                 sctx->b.b.delete_tcs_state(&sctx->b.b, sctx->fixed_func_tcs_shader.cso);
  76         if (sctx->custom_dsa_flush)
  77                 sctx->b.b.delete_depth_stencil_alpha_state(&sctx->b.b, sctx->custom_dsa_flush);
  78         if (sctx->custom_blend_resolve)
  79                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_resolve);
  80         if (sctx->custom_blend_decompress)
  81                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_decompress);
  82         if (sctx->custom_blend_fastclear)
  83                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_fastclear);
  84         if (sctx->custom_blend_dcc_decompress)
  85                 sctx->b.b.delete_blend_state(&sctx->b.b, sctx->custom_blend_dcc_decompress);
  86
  87         if (sctx->blitter)
  88                 util_blitter_destroy(sctx->blitter);
  89
  90         r600_common_context_cleanup(&sctx->b);
  91
  92         LLVMDisposeTargetMachine(sctx->tm);
  93
  94         r600_resource_reference(&sctx->trace_buf, NULL);
  95         r600_resource_reference(&sctx->last_trace_buf, NULL);
  96         radeon_clear_saved_cs(&sctx->last_gfx);
  97
  98         FREE(sctx);
  99 }
 100
 101 static enum pipe_reset_status
 102 si_amdgpu_get_reset_status(struct pipe_context *ctx)
 103 {
 104         struct si_context *sctx = (struct si_context *)ctx;
 105
 106         return sctx->b.ws->ctx_query_reset_status(sctx->b.ctx);
 107 }
 108
 109 /* Apitrace profiling:
 110  *   1) qapitrace : Tools -> Profile: Measure CPU & GPU times
 111  *   2) In the middle panel, zoom in (mouse wheel) on some bad draw call
 112  *      and remember its number.
 113  *   3) In Mesa, enable queries and performance counters around that draw
 114  *      call and print the results.
 115  *   4) glretrace --benchmark --markers ..
 116  */
 117 static void si_emit_string_marker(struct pipe_context *ctx,
 118                                   const char *string, int len)
 119 {
 120         struct si_context *sctx = (struct si_context *)ctx;
 121
 122         dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
 123 }
 124
 125 static LLVMTargetMachineRef
 126 si_create_llvm_target_machine(struct si_screen *sscreen)
 127 {
 128         const char *triple = "amdgcn--";
 129
 130         return LLVMCreateTargetMachine(radeon_llvm_get_r600_target(triple), triple,
 131                                        r600_get_llvm_processor_name(sscreen->b.family),
 132 #if HAVE_LLVM >= 0x0308
 133                                        sscreen->b.debug_flags & DBG_SI_SCHED ?
 134                                                SI_LLVM_DEFAULT_FEATURES ",+si-scheduler" :
 135 #endif
 136                                                SI_LLVM_DEFAULT_FEATURES,
 137                                        LLVMCodeGenLevelDefault,
 138                                        LLVMRelocDefault,
 139                                        LLVMCodeModelDefault);
 140 }
 141
 142 static struct pipe_context *si_create_context(struct pipe_screen *screen,
 143                                               void *priv, unsigned flags)
 144 {
 145         struct si_context *sctx = CALLOC_STRUCT(si_context);
 146         struct si_screen* sscreen = (struct si_screen *)screen;
 147         struct radeon_winsys *ws = sscreen->b.ws;
 148         int shader, i;
 149
 150         if (!sctx)
 151                 return NULL;
 152
 153         if (sscreen->b.debug_flags & DBG_CHECK_VM)
 154                 flags |= PIPE_CONTEXT_DEBUG;
 155
 156         if (flags & PIPE_CONTEXT_DEBUG)
 157                 sscreen->record_llvm_ir = true; /* racy but not critical */
 158
 159         sctx->b.b.screen = screen; /* this must be set first */
 160         sctx->b.b.priv = priv;
 161         sctx->b.b.destroy = si_destroy_context;
 162         sctx->b.b.emit_string_marker = si_emit_string_marker;
 163         sctx->b.set_atom_dirty = (void *)si_set_atom_dirty;
 164         sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
 165         sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
 166
 167         if (!r600_common_context_init(&sctx->b, &sscreen->b, flags))
 168                 goto fail;
 169
 170         if (sscreen->b.info.drm_major == 3)
 171                 sctx->b.b.get_device_reset_status = si_amdgpu_get_reset_status;
 172
 173         si_init_blit_functions(sctx);
 174         si_init_compute_functions(sctx);
 175         si_init_cp_dma_functions(sctx);
 176         si_init_debug_functions(sctx);
 177
 178         if (sscreen->b.info.has_uvd) {
 179                 sctx->b.b.create_video_codec = si_uvd_create_decoder;
 180                 sctx->b.b.create_video_buffer = si_video_buffer_create;
 181         } else {
 182                 sctx->b.b.create_video_codec = vl_create_decoder;
 183                 sctx->b.b.create_video_buffer = vl_video_buffer_create;
 184         }
 185
 186         sctx->b.gfx.cs = ws->cs_create(sctx->b.ctx, RING_GFX,
 187                                        si_context_gfx_flush, sctx);
 188
 189         if (!(sscreen->b.debug_flags & DBG_NO_CE) && ws->cs_add_const_ib) {
 190                 sctx->ce_ib = ws->cs_add_const_ib(sctx->b.gfx.cs);
 191                 if (!sctx->ce_ib)
 192                         goto fail;
 193
 194                 if (ws->cs_add_const_preamble_ib) {
 195                         sctx->ce_preamble_ib =
 196                                    ws->cs_add_const_preamble_ib(sctx->b.gfx.cs);
 197
 198                         if (!sctx->ce_preamble_ib)
 199                                 goto fail;
 200                 }
 201
 202                 sctx->ce_suballocator =
 203                                 u_suballocator_create(&sctx->b.b, 1024 * 1024,
 204                                                       PIPE_BIND_CUSTOM,
 205                                                       PIPE_USAGE_DEFAULT, false);
 206                 if (!sctx->ce_suballocator)
 207                         goto fail;
 208         }
 209
 210         sctx->b.gfx.flush = si_context_gfx_flush;
 211
 212         /* Border colors. */
 213         sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
 214                                           sizeof(*sctx->border_color_table));
 215         if (!sctx->border_color_table)
 216                 goto fail;
 217
 218         sctx->border_color_buffer = (struct r600_resource*)
 219                 pipe_buffer_create(screen, PIPE_BIND_CUSTOM, PIPE_USAGE_DEFAULT,
 220                                    SI_MAX_BORDER_COLORS *
 221                                    sizeof(*sctx->border_color_table));
 222         if (!sctx->border_color_buffer)
 223                 goto fail;
 224
 225         sctx->border_color_map =
 226                 ws->buffer_map(sctx->border_color_buffer->buf,
 227                                NULL, PIPE_TRANSFER_WRITE);
 228         if (!sctx->border_color_map)
 229                 goto fail;
 230
 231         si_init_all_descriptors(sctx);
 232         si_init_state_functions(sctx);
 233         si_init_shader_functions(sctx);
 234
 235         if (sctx->b.chip_class >= CIK)
 236                 cik_init_sdma_functions(sctx);
 237         else
 238                 si_init_dma_functions(sctx);
 239
 240         if (sscreen->b.debug_flags & DBG_FORCE_DMA)
 241                 sctx->b.b.resource_copy_region = sctx->b.dma_copy;
 242
 243         sctx->blitter = util_blitter_create(&sctx->b.b);
 244         if (sctx->blitter == NULL)
 245                 goto fail;
 246         sctx->blitter->draw_rectangle = r600_draw_rectangle;
 247
 248         sctx->sample_mask.sample_mask = 0xffff;
 249
 250         /* these must be last */
 251         si_begin_new_cs(sctx);
 252         r600_query_init_backend_mask(&sctx->b); /* this emits commands and must be last */
 253
 254         /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD is buggy
 255          * with a NULL buffer). We need to use a dummy buffer instead. */
 256         if (sctx->b.chip_class == CIK) {
 257                 sctx->null_const_buf.buffer = pipe_buffer_create(screen, PIPE_BIND_CONSTANT_BUFFER,
 258                                                                  PIPE_USAGE_DEFAULT, 16);
 259                 if (!sctx->null_const_buf.buffer)
 260                         goto fail;
 261                 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
 262
 263                 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
 264                         for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
 265                                 sctx->b.b.set_constant_buffer(&sctx->b.b, shader, i,
 266                                                               &sctx->null_const_buf);
 267                         }
 268                 }
 269
 270                 /* Clear the NULL constant buffer, because loads should return zeros. */
 271                 sctx->b.clear_buffer(&sctx->b.b, sctx->null_const_buf.buffer, 0,
 272                                      sctx->null_const_buf.buffer->width0, 0,
 273                                      R600_COHERENCY_SHADER);
 274         }
 275
 276         uint64_t max_threads_per_block;
 277         screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
 278                                   PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
 279                                   &max_threads_per_block);
 280
 281         /* The maximum number of scratch waves. Scratch space isn't divided
 282          * evenly between CUs. The number is only a function of the number of CUs.
 283          * We can decrease the constant to decrease the scratch buffer size.
 284          *
 285          * sctx->scratch_waves must be >= the maximum posible size of
 286          * 1 threadgroup, so that the hw doesn't hang from being unable
 287          * to start any.
 288          *
 289          * The recommended value is 4 per CU at most. Higher numbers don't
 290          * bring much benefit, but they still occupy chip resources (think
 291          * async compute). I've seen ~2% performance difference between 4 and 32.
 292          */
 293         sctx->scratch_waves = MAX2(32 * sscreen->b.info.num_good_compute_units,
 294                                    max_threads_per_block / 64);
 295
 296         sctx->tm = si_create_llvm_target_machine(sscreen);
 297
 298         return &sctx->b.b;
 299 fail:
 300         fprintf(stderr, "radeonsi: Failed to create a context.\n");
 301         si_destroy_context(&sctx->b.b);
 302         return NULL;
 303 }
 304
 305 /*
 306  * pipe_screen
 307  */
 308
 309 static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param)
 310 {
 311         struct si_screen *sscreen = (struct si_screen *)pscreen;
 312
 313         switch (param) {
 314         /* Supported features (boolean caps). */
 315         case PIPE_CAP_TWO_SIDED_STENCIL:
 316         case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
 317         case PIPE_CAP_ANISOTROPIC_FILTER:
 318         case PIPE_CAP_POINT_SPRITE:
 319         case PIPE_CAP_OCCLUSION_QUERY:
 320         case PIPE_CAP_TEXTURE_SHADOW_MAP:
 321         case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
 322         case PIPE_CAP_BLEND_EQUATION_SEPARATE:
 323         case PIPE_CAP_TEXTURE_SWIZZLE:
 324         case PIPE_CAP_DEPTH_CLIP_DISABLE:
 325         case PIPE_CAP_SHADER_STENCIL_EXPORT:
 326         case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
 327         case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
 328         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
 329         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
 330         case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
 331         case PIPE_CAP_SM3:
 332         case PIPE_CAP_SEAMLESS_CUBE_MAP:
 333         case PIPE_CAP_PRIMITIVE_RESTART:
 334         case PIPE_CAP_CONDITIONAL_RENDER:
 335         case PIPE_CAP_TEXTURE_BARRIER:
 336         case PIPE_CAP_INDEP_BLEND_ENABLE:
 337         case PIPE_CAP_INDEP_BLEND_FUNC:
 338         case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
 339         case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
 340         case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
 341         case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
 342         case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
 343         case PIPE_CAP_USER_INDEX_BUFFERS:
 344         case PIPE_CAP_USER_CONSTANT_BUFFERS:
 345         case PIPE_CAP_START_INSTANCE:
 346         case PIPE_CAP_NPOT_TEXTURES:
 347         case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
 348         case PIPE_CAP_VERTEX_COLOR_CLAMPED:
 349         case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
 350         case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
 351         case PIPE_CAP_TGSI_INSTANCEID:
 352         case PIPE_CAP_COMPUTE:
 353         case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
 354         case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
 355         case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
 356         case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
 357         case PIPE_CAP_CUBE_MAP_ARRAY:
 358         case PIPE_CAP_SAMPLE_SHADING:
 359         case PIPE_CAP_DRAW_INDIRECT:
 360         case PIPE_CAP_CLIP_HALFZ:
 361         case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
 362         case PIPE_CAP_POLYGON_OFFSET_CLAMP:
 363         case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
 364         case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
 365         case PIPE_CAP_TGSI_TEXCOORD:
 366         case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
 367         case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
 368         case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
 369         case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
 370         case PIPE_CAP_SHAREABLE_SHADERS:
 371         case PIPE_CAP_DEPTH_BOUNDS_TEST:
 372         case PIPE_CAP_SAMPLER_VIEW_TARGET:
 373         case PIPE_CAP_TEXTURE_QUERY_LOD:
 374         case PIPE_CAP_TEXTURE_GATHER_SM5:
 375         case PIPE_CAP_TGSI_TXQS:
 376         case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
 377         case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
 378         case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
 379         case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
 380         case PIPE_CAP_INVALIDATE_BUFFER:
 381         case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
 382         case PIPE_CAP_QUERY_MEMORY_INFO:
 383         case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
 384         case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
 385         case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
 386         case PIPE_CAP_GENERATE_MIPMAP:
 387         case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
 388         case PIPE_CAP_STRING_MARKER:
 389                 return 1;
 390
 391         case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
 392                 return !SI_BIG_ENDIAN && sscreen->b.info.has_userptr;
 393
 394         case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
 395                 return (sscreen->b.info.drm_major == 2 &&
 396                         sscreen->b.info.drm_minor >= 43) ||
 397                        sscreen->b.info.drm_major == 3;
 398
 399         case PIPE_CAP_TEXTURE_MULTISAMPLE:
 400                 /* 2D tiling on CIK is supported since DRM 2.35.0 */
 401                 return sscreen->b.chip_class < CIK ||
 402                        (sscreen->b.info.drm_major == 2 &&
 403                         sscreen->b.info.drm_minor >= 35) ||
 404                        sscreen->b.info.drm_major == 3;
 405
 406         case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
 407                 return R600_MAP_BUFFER_ALIGNMENT;
 408
 409         case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
 410         case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
 411         case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
 412                 return 4;
 413         case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
 414                 return HAVE_LLVM >= 0x0309 ? 4 : 0;
 415
 416         case PIPE_CAP_GLSL_FEATURE_LEVEL:
 417                 if (pscreen->get_shader_param(pscreen, PIPE_SHADER_COMPUTE,
 418                                               PIPE_SHADER_CAP_SUPPORTED_IRS) &
 419                     (1 << PIPE_SHADER_IR_TGSI))
 420                         return 430;
 421                 return HAVE_LLVM >= 0x0309 ? 420 :
 422                        HAVE_LLVM >= 0x0307 ? 410 : 330;
 423
 424         case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
 425                 return MIN2(sscreen->b.info.max_alloc_size, INT_MAX);
 426
 427         case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
 428                 return 0;
 429
 430         /* Unsupported features. */
 431         case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
 432         case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
 433         case PIPE_CAP_USER_VERTEX_BUFFERS:
 434         case PIPE_CAP_FAKE_SW_MSAA:
 435         case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
 436         case PIPE_CAP_VERTEXID_NOBASE:
 437         case PIPE_CAP_CLEAR_TEXTURE:
 438         case PIPE_CAP_DRAW_PARAMETERS:
 439         case PIPE_CAP_MULTI_DRAW_INDIRECT:
 440         case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
 441         case PIPE_CAP_QUERY_BUFFER_OBJECT:
 442         case PIPE_CAP_CULL_DISTANCE:
 443         case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
 444         case PIPE_CAP_TGSI_VOTE:
 445         case PIPE_CAP_MAX_WINDOW_RECTANGLES:
 446                 return 0;
 447
 448         case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
 449                 return 30;
 450
 451         case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
 452                 return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600;
 453
 454         /* Stream output. */
 455         case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
 456                 return sscreen->b.has_streamout ? 4 : 0;
 457         case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
 458                 return sscreen->b.has_streamout ? 1 : 0;
 459         case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
 460         case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
 461                 return sscreen->b.has_streamout ? 32*4 : 0;
 462
 463         /* Geometry shader output. */
 464         case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
 465                 return 1024;
 466         case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
 467                 return 4095;
 468         case PIPE_CAP_MAX_VERTEX_STREAMS:
 469                 return 4;
 470
 471         case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
 472                 return 2048;
 473
 474         /* Texturing. */
 475         case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
 476         case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
 477                 return 15; /* 16384 */
 478         case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
 479                 /* textures support 8192, but layered rendering supports 2048 */
 480                 return 12;
 481         case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
 482                 /* textures support 8192, but layered rendering supports 2048 */
 483                 return 2048;
 484
 485         /* Render targets. */
 486         case PIPE_CAP_MAX_RENDER_TARGETS:
 487                 return 8;
 488
 489         case PIPE_CAP_MAX_VIEWPORTS:
 490                 return R600_MAX_VIEWPORTS;
 491         case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
 492                 return 8;
 493
 494         /* Timer queries, present when the clock frequency is non zero. */
 495         case PIPE_CAP_QUERY_TIMESTAMP:
 496         case PIPE_CAP_QUERY_TIME_ELAPSED:
 497                 return sscreen->b.info.clock_crystal_freq != 0;
 498
 499         case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
 500         case PIPE_CAP_MIN_TEXEL_OFFSET:
 501                 return -32;
 502
 503         case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
 504         case PIPE_CAP_MAX_TEXEL_OFFSET:
 505                 return 31;
 506
 507         case PIPE_CAP_ENDIANNESS:
 508                 return PIPE_ENDIAN_LITTLE;
 509
 510         case PIPE_CAP_VENDOR_ID:
 511                 return ATI_VENDOR_ID;
 512         case PIPE_CAP_DEVICE_ID:
 513                 return sscreen->b.info.pci_id;
 514         case PIPE_CAP_ACCELERATED:
 515                 return 1;
 516         case PIPE_CAP_VIDEO_MEMORY:
 517                 return sscreen->b.info.vram_size >> 20;
 518         case PIPE_CAP_UMA:
 519                 return 0;
 520         case PIPE_CAP_PCI_GROUP:
 521                 return sscreen->b.info.pci_domain;
 522         case PIPE_CAP_PCI_BUS:
 523                 return sscreen->b.info.pci_bus;
 524         case PIPE_CAP_PCI_DEVICE:
 525                 return sscreen->b.info.pci_dev;
 526         case PIPE_CAP_PCI_FUNCTION:
 527                 return sscreen->b.info.pci_func;
 528         }
 529         return 0;
 530 }
 531
 532 static int si_get_shader_param(struct pipe_screen* pscreen, unsigned shader, enum pipe_shader_cap param)
 533 {
 534         struct si_screen *sscreen = (struct si_screen *)pscreen;
 535
 536         switch(shader)
 537         {
 538         case PIPE_SHADER_FRAGMENT:
 539         case PIPE_SHADER_VERTEX:
 540         case PIPE_SHADER_GEOMETRY:
 541                 break;
 542         case PIPE_SHADER_TESS_CTRL:
 543         case PIPE_SHADER_TESS_EVAL:
 544                 /* LLVM 3.6.2 is required for tessellation because of bug fixes there */
 545                 if (HAVE_LLVM == 0x0306 && MESA_LLVM_VERSION_PATCH < 2)
 546                         return 0;
 547                 break;
 548         case PIPE_SHADER_COMPUTE:
 549                 switch (param) {
 550                 case PIPE_SHADER_CAP_PREFERRED_IR:
 551                         return PIPE_SHADER_IR_NATIVE;
 552
 553                 case PIPE_SHADER_CAP_SUPPORTED_IRS: {
 554                         int ir = 1 << PIPE_SHADER_IR_NATIVE;
 555
 556                         /* Old kernels disallowed some register writes for SI
 557                          * that are used for indirect dispatches. */
 558                         if (HAVE_LLVM >= 0x309 && (sscreen->b.chip_class >= CIK ||
 559                                                    sscreen->b.info.drm_major == 3 ||
 560                                                    (sscreen->b.info.drm_major == 2 &&
 561                                                     sscreen->b.info.drm_minor >= 45)))
 562                                 ir |= 1 << PIPE_SHADER_IR_TGSI;
 563
 564                         return ir;
 565                 }
 566                 case PIPE_SHADER_CAP_DOUBLES:
 567                         return HAVE_LLVM >= 0x0307;
 568
 569                 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: {
 570                         uint64_t max_const_buffer_size;
 571                         pscreen->get_compute_param(pscreen, PIPE_SHADER_IR_TGSI,
 572                                 PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
 573                                 &max_const_buffer_size);
 574                         return MIN2(max_const_buffer_size, INT_MAX);
 575                 }
 576                 default:
 577                         /* If compute shaders don't require a special value
 578                          * for this cap, we can return the same value we
 579                          * do for other shader types. */
 580                         break;
 581                 }
 582                 break;
 583         default:
 584                 return 0;
 585         }
 586
 587         switch (param) {
 588         case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
 589         case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
 590         case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
 591         case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
 592                 return 16384;
 593         case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
 594                 return 32;
 595         case PIPE_SHADER_CAP_MAX_INPUTS:
 596                 return shader == PIPE_SHADER_VERTEX ? SI_NUM_VERTEX_BUFFERS : 32;
 597         case PIPE_SHADER_CAP_MAX_OUTPUTS:
 598                 return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
 599         case PIPE_SHADER_CAP_MAX_TEMPS:
 600                 return 256; /* Max native temporaries. */
 601         case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
 602                 return 4096 * sizeof(float[4]); /* actually only memory limits this */
 603         case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
 604                 return SI_NUM_CONST_BUFFERS;
 605         case PIPE_SHADER_CAP_MAX_PREDS:
 606                 return 0; /* FIXME */
 607         case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
 608                 return 1;
 609         case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
 610                 return 1;
 611         case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
 612                 /* Indirection of geometry shader input dimension is not
 613                  * handled yet
 614                  */
 615                 return shader != PIPE_SHADER_GEOMETRY;
 616         case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
 617         case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
 618         case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
 619                 return 1;
 620         case PIPE_SHADER_CAP_INTEGERS:
 621                 return 1;
 622         case PIPE_SHADER_CAP_SUBROUTINES:
 623                 return 0;
 624         case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
 625         case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
 626                 return SI_NUM_SAMPLERS;
 627         case PIPE_SHADER_CAP_PREFERRED_IR:
 628                 return PIPE_SHADER_IR_TGSI;
 629         case PIPE_SHADER_CAP_SUPPORTED_IRS:
 630                 return 0;
 631         case PIPE_SHADER_CAP_DOUBLES:
 632                 return HAVE_LLVM >= 0x0307;
 633         case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
 634         case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
 635                 return 0;
 636         case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
 637         case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
 638                 return 1;
 639         case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
 640                 return 32;
 641         case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
 642                 return HAVE_LLVM >= 0x0309 ? SI_NUM_SHADER_BUFFERS : 0;
 643         case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
 644                 return HAVE_LLVM >= 0x0309 ? SI_NUM_IMAGES : 0;
 645         }
 646         return 0;
 647 }
 648
 649 static void si_destroy_screen(struct pipe_screen* pscreen)
 650 {
 651         struct si_screen *sscreen = (struct si_screen *)pscreen;
 652         struct si_shader_part *parts[] = {
 653                 sscreen->vs_prologs,
 654                 sscreen->vs_epilogs,
 655                 sscreen->tcs_epilogs,
 656                 sscreen->ps_prologs,
 657                 sscreen->ps_epilogs
 658         };
 659         unsigned i;
 660
 661         if (!sscreen)
 662                 return;
 663
 664         if (!sscreen->b.ws->unref(sscreen->b.ws))
 665                 return;
 666
 667         if (util_queue_is_initialized(&sscreen->shader_compiler_queue))
 668                 util_queue_destroy(&sscreen->shader_compiler_queue);
 669
 670         for (i = 0; i < ARRAY_SIZE(sscreen->tm); i++)
 671                 if (sscreen->tm[i])
 672                         LLVMDisposeTargetMachine(sscreen->tm[i]);
 673
 674         /* Free shader parts. */
 675         for (i = 0; i < ARRAY_SIZE(parts); i++) {
 676                 while (parts[i]) {
 677                         struct si_shader_part *part = parts[i];
 678
 679                         parts[i] = part->next;
 680                         radeon_shader_binary_clean(&part->binary);
 681                         FREE(part);
 682                 }
 683         }
 684         pipe_mutex_destroy(sscreen->shader_parts_mutex);
 685         si_destroy_shader_cache(sscreen);
 686         r600_destroy_common_screen(&sscreen->b);
 687 }
 688
 689 static bool si_init_gs_info(struct si_screen *sscreen)
 690 {
 691         switch (sscreen->b.family) {
 692         case CHIP_OLAND:
 693         case CHIP_HAINAN:
 694         case CHIP_KAVERI:
 695         case CHIP_KABINI:
 696         case CHIP_MULLINS:
 697         case CHIP_ICELAND:
 698         case CHIP_CARRIZO:
 699         case CHIP_STONEY:
 700                 sscreen->gs_table_depth = 16;
 701                 return true;
 702         case CHIP_TAHITI:
 703         case CHIP_PITCAIRN:
 704         case CHIP_VERDE:
 705         case CHIP_BONAIRE:
 706         case CHIP_HAWAII:
 707         case CHIP_TONGA:
 708         case CHIP_FIJI:
 709         case CHIP_POLARIS10:
 710         case CHIP_POLARIS11:
 711                 sscreen->gs_table_depth = 32;
 712                 return true;
 713         default:
 714                 return false;
 715         }
 716 }
 717
 718 static void si_handle_env_var_force_family(struct si_screen *sscreen)
 719 {
 720         const char *family = debug_get_option("SI_FORCE_FAMILY", NULL);
 721         unsigned i;
 722
 723         if (!family)
 724                 return;
 725
 726         for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
 727                 if (!strcmp(family, r600_get_llvm_processor_name(i))) {
 728                         /* Override family and chip_class. */
 729                         sscreen->b.family = sscreen->b.info.family = i;
 730
 731                         if (i >= CHIP_TONGA)
 732                                 sscreen->b.chip_class = sscreen->b.info.chip_class = VI;
 733                         else if (i >= CHIP_BONAIRE)
 734                                 sscreen->b.chip_class = sscreen->b.info.chip_class = CIK;
 735                         else
 736                                 sscreen->b.chip_class = sscreen->b.info.chip_class = SI;
 737
 738                         /* Don't submit any IBs. */
 739                         setenv("RADEON_NOOP", "1", 1);
 740                         return;
 741                 }
 742         }
 743
 744         fprintf(stderr, "radeonsi: Unknown family: %s\n", family);
 745         exit(1);
 746 }
 747
 748 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws)
 749 {
 750         struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
 751         unsigned num_cpus, num_compiler_threads, i;
 752
 753         if (!sscreen) {
 754                 return NULL;
 755         }
 756
 757         /* Set functions first. */
 758         sscreen->b.b.context_create = si_create_context;
 759         sscreen->b.b.destroy = si_destroy_screen;
 760         sscreen->b.b.get_param = si_get_param;
 761         sscreen->b.b.get_shader_param = si_get_shader_param;
 762         sscreen->b.b.resource_create = r600_resource_create_common;
 763
 764         si_init_screen_state_functions(sscreen);
 765
 766         if (!r600_common_screen_init(&sscreen->b, ws) ||
 767             !si_init_gs_info(sscreen) ||
 768             !si_init_shader_cache(sscreen)) {
 769                 FREE(sscreen);
 770                 return NULL;
 771         }
 772
 773         si_handle_env_var_force_family(sscreen);
 774
 775         if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
 776                 si_init_perfcounters(sscreen);
 777
 778         /* Hawaii has a bug with offchip buffers > 256 that can be worked
 779          * around by setting 4K granularity.
 780          */
 781         sscreen->tess_offchip_block_dw_size =
 782                 sscreen->b.family == CHIP_HAWAII ? 4096 : 8192;
 783
 784         sscreen->has_distributed_tess =
 785                 sscreen->b.chip_class >= VI &&
 786                 sscreen->b.info.max_se >= 2;
 787
 788         sscreen->b.has_cp_dma = true;
 789         sscreen->b.has_streamout = true;
 790         pipe_mutex_init(sscreen->shader_parts_mutex);
 791         sscreen->use_monolithic_shaders =
 792                 HAVE_LLVM < 0x0308 ||
 793                 (sscreen->b.debug_flags & DBG_MONOLITHIC_SHADERS) != 0;
 794
 795         if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
 796                 sscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS | DBG_CS;
 797
 798         /* Only enable as many threads as we have target machines and CPUs. */
 799         num_cpus = sysconf(_SC_NPROCESSORS_ONLN);
 800         num_compiler_threads = MIN2(num_cpus, ARRAY_SIZE(sscreen->tm));
 801
 802         for (i = 0; i < num_compiler_threads; i++)
 803                 sscreen->tm[i] = si_create_llvm_target_machine(sscreen);
 804
 805         util_queue_init(&sscreen->shader_compiler_queue, "si_shader",
 806                         32, num_compiler_threads);
 807
 808         /* Create the auxiliary context. This must be done last. */
 809         sscreen->b.aux_context = sscreen->b.b.context_create(&sscreen->b.b, NULL, 0);
 810
 811         if (sscreen->b.debug_flags & DBG_TEST_DMA)
 812                 r600_test_dma(&sscreen->b);
 813
 814         return &sscreen->b.b;
 815 }