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radeonsi: implement ARB/KHR_parallel_shader_compile callbacks
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
30 #include "sid.h"
31
32 #include "ac_llvm_util.h"
33 #include "radeon/radeon_uvd.h"
34 #include "gallivm/lp_bld_misc.h"
35 #include "util/disk_cache.h"
36 #include "util/u_log.h"
37 #include "util/u_memory.h"
38 #include "util/u_suballoc.h"
39 #include "util/u_tests.h"
40 #include "util/u_upload_mgr.h"
41 #include "util/xmlconfig.h"
42 #include "vl/vl_decoder.h"
43 #include "driver_ddebug/dd_util.h"
44
45 static const struct debug_named_value debug_options[] = {
46 /* Shader logging options: */
47 { "vs", DBG(VS), "Print vertex shaders" },
48 { "ps", DBG(PS), "Print pixel shaders" },
49 { "gs", DBG(GS), "Print geometry shaders" },
50 { "tcs", DBG(TCS), "Print tessellation control shaders" },
51 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
52 { "cs", DBG(CS), "Print compute shaders" },
53 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
54 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
55 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
56 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
57
58 /* Shader compiler options the shader cache should be aware of: */
59 { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" },
60 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
61 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
62
63 /* Shader compiler options (with no effect on the shader cache): */
64 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
65 { "nir", DBG(NIR), "Enable experimental NIR shaders" },
66 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
67 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
68
69 /* Information logging options: */
70 { "info", DBG(INFO), "Print driver information" },
71 { "tex", DBG(TEX), "Print texture info" },
72 { "compute", DBG(COMPUTE), "Print compute info" },
73 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
74
75 /* Driver options: */
76 { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." },
77 { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
78 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
79 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
80 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
81 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
82
83 /* 3D engine options: */
84 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
85 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
86 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
87 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
88 { "dpbb", DBG(DPBB), "Enable DPBB." },
89 { "dfsm", DBG(DFSM), "Enable DFSM." },
90 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
91 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
92 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
93 { "notiling", DBG(NO_TILING), "Disable tiling" },
94 { "nodcc", DBG(NO_DCC), "Disable DCC." },
95 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
96 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
97 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
98 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
99
100 /* Tests: */
101 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
102 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
103 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
104 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
105 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
106 { "testgds", DBG(TEST_GDS), "Test GDS." },
107 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
108 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
109
110 DEBUG_NAMED_VALUE_END /* must be last */
111 };
112
113 static void si_init_compiler(struct si_screen *sscreen,
114 struct ac_llvm_compiler *compiler)
115 {
116 /* Only create the less-optimizing version of the compiler on APUs
117 * predating Ryzen (Raven). */
118 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
119 sscreen->info.chip_class <= VI;
120
121 enum ac_target_machine_options tm_options =
122 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
123 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
124 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
125 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
126 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
127 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
128 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
129
130 ac_init_llvm_once();
131 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
132 compiler->passes = ac_create_llvm_passes(compiler->tm);
133
134 if (compiler->low_opt_tm)
135 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
136 }
137
138 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
139 {
140 ac_destroy_llvm_passes(compiler->passes);
141 ac_destroy_llvm_passes(compiler->low_opt_passes);
142 ac_destroy_llvm_compiler(compiler);
143 }
144
145 /*
146 * pipe_context
147 */
148 static void si_destroy_context(struct pipe_context *context)
149 {
150 struct si_context *sctx = (struct si_context *)context;
151 int i;
152
153 /* Unreference the framebuffer normally to disable related logic
154 * properly.
155 */
156 struct pipe_framebuffer_state fb = {};
157 if (context->set_framebuffer_state)
158 context->set_framebuffer_state(context, &fb);
159
160 si_release_all_descriptors(sctx);
161
162 pipe_resource_reference(&sctx->esgs_ring, NULL);
163 pipe_resource_reference(&sctx->gsvs_ring, NULL);
164 pipe_resource_reference(&sctx->tess_rings, NULL);
165 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
166 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
167 si_resource_reference(&sctx->border_color_buffer, NULL);
168 free(sctx->border_color_table);
169 si_resource_reference(&sctx->scratch_buffer, NULL);
170 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
171 si_resource_reference(&sctx->wait_mem_scratch, NULL);
172
173 si_pm4_free_state(sctx, sctx->init_config, ~0);
174 if (sctx->init_config_gs_rings)
175 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
176 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
177 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
178
179 if (sctx->fixed_func_tcs_shader.cso)
180 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
181 if (sctx->custom_dsa_flush)
182 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
183 if (sctx->custom_blend_resolve)
184 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
185 if (sctx->custom_blend_fmask_decompress)
186 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
187 if (sctx->custom_blend_eliminate_fastclear)
188 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
189 if (sctx->custom_blend_dcc_decompress)
190 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
191 if (sctx->vs_blit_pos)
192 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
193 if (sctx->vs_blit_pos_layered)
194 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
195 if (sctx->vs_blit_color)
196 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
197 if (sctx->vs_blit_color_layered)
198 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
199 if (sctx->vs_blit_texcoord)
200 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
201 if (sctx->cs_clear_buffer)
202 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
203 if (sctx->cs_copy_buffer)
204 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
205 if (sctx->cs_copy_image)
206 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
207 if (sctx->cs_copy_image_1d_array)
208 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
209 if (sctx->cs_clear_render_target)
210 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
211 if (sctx->cs_clear_render_target_1d_array)
212 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
213
214 if (sctx->blitter)
215 util_blitter_destroy(sctx->blitter);
216
217 /* Release DCC stats. */
218 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
219 assert(!sctx->dcc_stats[i].query_active);
220
221 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
222 if (sctx->dcc_stats[i].ps_stats[j])
223 sctx->b.destroy_query(&sctx->b,
224 sctx->dcc_stats[i].ps_stats[j]);
225
226 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
227 }
228
229 if (sctx->query_result_shader)
230 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
231
232 if (sctx->gfx_cs)
233 sctx->ws->cs_destroy(sctx->gfx_cs);
234 if (sctx->dma_cs)
235 sctx->ws->cs_destroy(sctx->dma_cs);
236 if (sctx->ctx)
237 sctx->ws->ctx_destroy(sctx->ctx);
238
239 if (sctx->b.stream_uploader)
240 u_upload_destroy(sctx->b.stream_uploader);
241 if (sctx->b.const_uploader)
242 u_upload_destroy(sctx->b.const_uploader);
243 if (sctx->cached_gtt_allocator)
244 u_upload_destroy(sctx->cached_gtt_allocator);
245
246 slab_destroy_child(&sctx->pool_transfers);
247 slab_destroy_child(&sctx->pool_transfers_unsync);
248
249 if (sctx->allocator_zeroed_memory)
250 u_suballocator_destroy(sctx->allocator_zeroed_memory);
251
252 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
253 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
254 si_resource_reference(&sctx->eop_bug_scratch, NULL);
255
256 si_destroy_compiler(&sctx->compiler);
257
258 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
259
260 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
261 _mesa_hash_table_destroy(sctx->img_handles, NULL);
262
263 util_dynarray_fini(&sctx->resident_tex_handles);
264 util_dynarray_fini(&sctx->resident_img_handles);
265 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
266 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
267 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
268 si_unref_sdma_uploads(sctx);
269 FREE(sctx);
270 }
271
272 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
273 {
274 struct si_context *sctx = (struct si_context *)ctx;
275
276 if (sctx->screen->info.has_gpu_reset_status_query)
277 return sctx->ws->ctx_query_reset_status(sctx->ctx);
278
279 if (sctx->screen->info.has_gpu_reset_counter_query) {
280 unsigned latest = sctx->ws->query_value(sctx->ws,
281 RADEON_GPU_RESET_COUNTER);
282
283 if (sctx->gpu_reset_counter == latest)
284 return PIPE_NO_RESET;
285
286 sctx->gpu_reset_counter = latest;
287 return PIPE_UNKNOWN_CONTEXT_RESET;
288 }
289
290 return PIPE_NO_RESET;
291 }
292
293 static void si_set_device_reset_callback(struct pipe_context *ctx,
294 const struct pipe_device_reset_callback *cb)
295 {
296 struct si_context *sctx = (struct si_context *)ctx;
297
298 if (cb)
299 sctx->device_reset_callback = *cb;
300 else
301 memset(&sctx->device_reset_callback, 0,
302 sizeof(sctx->device_reset_callback));
303 }
304
305 bool si_check_device_reset(struct si_context *sctx)
306 {
307 enum pipe_reset_status status;
308
309 if (!sctx->device_reset_callback.reset)
310 return false;
311
312 if (!sctx->b.get_device_reset_status)
313 return false;
314
315 status = sctx->b.get_device_reset_status(&sctx->b);
316 if (status == PIPE_NO_RESET)
317 return false;
318
319 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
320 return true;
321 }
322
323 /* Apitrace profiling:
324 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
325 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
326 * and remember its number.
327 * 3) In Mesa, enable queries and performance counters around that draw
328 * call and print the results.
329 * 4) glretrace --benchmark --markers ..
330 */
331 static void si_emit_string_marker(struct pipe_context *ctx,
332 const char *string, int len)
333 {
334 struct si_context *sctx = (struct si_context *)ctx;
335
336 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
337
338 if (sctx->log)
339 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
340 }
341
342 static void si_set_debug_callback(struct pipe_context *ctx,
343 const struct pipe_debug_callback *cb)
344 {
345 struct si_context *sctx = (struct si_context *)ctx;
346 struct si_screen *screen = sctx->screen;
347
348 util_queue_finish(&screen->shader_compiler_queue);
349 util_queue_finish(&screen->shader_compiler_queue_low_priority);
350
351 if (cb)
352 sctx->debug = *cb;
353 else
354 memset(&sctx->debug, 0, sizeof(sctx->debug));
355 }
356
357 static void si_set_log_context(struct pipe_context *ctx,
358 struct u_log_context *log)
359 {
360 struct si_context *sctx = (struct si_context *)ctx;
361 sctx->log = log;
362
363 if (log)
364 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
365 }
366
367 static void si_set_context_param(struct pipe_context *ctx,
368 enum pipe_context_param param,
369 unsigned value)
370 {
371 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
372
373 switch (param) {
374 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
375 ws->pin_threads_to_L3_cache(ws, value);
376 break;
377 default:;
378 }
379 }
380
381 static struct pipe_context *si_create_context(struct pipe_screen *screen,
382 unsigned flags)
383 {
384 struct si_context *sctx = CALLOC_STRUCT(si_context);
385 struct si_screen* sscreen = (struct si_screen *)screen;
386 struct radeon_winsys *ws = sscreen->ws;
387 int shader, i;
388 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
389
390 if (!sctx)
391 return NULL;
392
393 sctx->has_graphics = sscreen->info.chip_class == SI ||
394 !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
395
396 if (flags & PIPE_CONTEXT_DEBUG)
397 sscreen->record_llvm_ir = true; /* racy but not critical */
398
399 sctx->b.screen = screen; /* this must be set first */
400 sctx->b.priv = NULL;
401 sctx->b.destroy = si_destroy_context;
402 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
403 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
404
405 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
406 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
407
408 sctx->ws = sscreen->ws;
409 sctx->family = sscreen->info.family;
410 sctx->chip_class = sscreen->info.chip_class;
411
412 if (sscreen->info.has_gpu_reset_counter_query) {
413 sctx->gpu_reset_counter =
414 sctx->ws->query_value(sctx->ws, RADEON_GPU_RESET_COUNTER);
415 }
416
417
418 if (sctx->chip_class == CIK ||
419 sctx->chip_class == VI ||
420 sctx->chip_class == GFX9) {
421 sctx->eop_bug_scratch = si_resource(
422 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
423 16 * sscreen->info.num_render_backends));
424 if (!sctx->eop_bug_scratch)
425 goto fail;
426 }
427
428 /* Initialize context allocators. */
429 sctx->allocator_zeroed_memory =
430 u_suballocator_create(&sctx->b, 128 * 1024,
431 0, PIPE_USAGE_DEFAULT,
432 SI_RESOURCE_FLAG_UNMAPPABLE |
433 SI_RESOURCE_FLAG_CLEAR, false);
434 if (!sctx->allocator_zeroed_memory)
435 goto fail;
436
437 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
438 0, PIPE_USAGE_STREAM,
439 SI_RESOURCE_FLAG_READ_ONLY);
440 if (!sctx->b.stream_uploader)
441 goto fail;
442
443 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
444 0, PIPE_USAGE_STAGING, 0);
445 if (!sctx->cached_gtt_allocator)
446 goto fail;
447
448 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
449 if (!sctx->ctx)
450 goto fail;
451
452 if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
453 sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
454 (void*)si_flush_dma_cs,
455 sctx, stop_exec_on_failure);
456 }
457
458 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->dma_cs;
459 sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
460 0, PIPE_USAGE_DEFAULT,
461 SI_RESOURCE_FLAG_32BIT |
462 (use_sdma_upload ?
463 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA :
464 (sscreen->cpdma_prefetch_writes_memory ?
465 0 : SI_RESOURCE_FLAG_READ_ONLY)));
466 if (!sctx->b.const_uploader)
467 goto fail;
468
469 if (use_sdma_upload)
470 u_upload_enable_flush_explicit(sctx->b.const_uploader);
471
472 sctx->gfx_cs = ws->cs_create(sctx->ctx,
473 sctx->has_graphics ? RING_GFX : RING_COMPUTE,
474 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
475
476 /* Border colors. */
477 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
478 sizeof(*sctx->border_color_table));
479 if (!sctx->border_color_table)
480 goto fail;
481
482 sctx->border_color_buffer = si_resource(
483 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
484 SI_MAX_BORDER_COLORS *
485 sizeof(*sctx->border_color_table)));
486 if (!sctx->border_color_buffer)
487 goto fail;
488
489 sctx->border_color_map =
490 ws->buffer_map(sctx->border_color_buffer->buf,
491 NULL, PIPE_TRANSFER_WRITE);
492 if (!sctx->border_color_map)
493 goto fail;
494
495 /* Initialize context functions used by graphics and compute. */
496 sctx->b.emit_string_marker = si_emit_string_marker;
497 sctx->b.set_debug_callback = si_set_debug_callback;
498 sctx->b.set_log_context = si_set_log_context;
499 sctx->b.set_context_param = si_set_context_param;
500 sctx->b.get_device_reset_status = si_get_reset_status;
501 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
502 sctx->b.memory_barrier = si_memory_barrier;
503
504 si_init_all_descriptors(sctx);
505 si_init_buffer_functions(sctx);
506 si_init_clear_functions(sctx);
507 si_init_blit_functions(sctx);
508 si_init_compute_functions(sctx);
509 si_init_compute_blit_functions(sctx);
510 si_init_debug_functions(sctx);
511 si_init_fence_functions(sctx);
512
513 if (sscreen->debug_flags & DBG(FORCE_DMA))
514 sctx->b.resource_copy_region = sctx->dma_copy;
515
516 /* Initialize graphics-only context functions. */
517 if (sctx->has_graphics) {
518 si_init_context_texture_functions(sctx);
519 si_init_query_functions(sctx);
520 si_init_msaa_functions(sctx);
521 si_init_shader_functions(sctx);
522 si_init_state_functions(sctx);
523 si_init_streamout_functions(sctx);
524 si_init_viewport_functions(sctx);
525
526 sctx->blitter = util_blitter_create(&sctx->b);
527 if (sctx->blitter == NULL)
528 goto fail;
529 sctx->blitter->skip_viewport_restore = true;
530
531 si_init_draw_functions(sctx);
532 }
533
534 /* Initialize SDMA functions. */
535 if (sctx->chip_class >= CIK)
536 cik_init_sdma_functions(sctx);
537 else
538 si_init_dma_functions(sctx);
539
540 sctx->sample_mask = 0xffff;
541
542 /* Initialize multimedia functions. */
543 if (sscreen->info.has_hw_decode) {
544 sctx->b.create_video_codec = si_uvd_create_decoder;
545 sctx->b.create_video_buffer = si_video_buffer_create;
546 } else {
547 sctx->b.create_video_codec = vl_create_decoder;
548 sctx->b.create_video_buffer = vl_video_buffer_create;
549 }
550
551 if (sctx->chip_class >= GFX9) {
552 sctx->wait_mem_scratch = si_resource(
553 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4));
554 if (!sctx->wait_mem_scratch)
555 goto fail;
556
557 /* Initialize the memory. */
558 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
559 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
560 }
561
562 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
563 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
564 if (sctx->chip_class == CIK) {
565 sctx->null_const_buf.buffer =
566 pipe_aligned_buffer_create(screen,
567 SI_RESOURCE_FLAG_32BIT,
568 PIPE_USAGE_DEFAULT, 16,
569 sctx->screen->info.tcc_cache_line_size);
570 if (!sctx->null_const_buf.buffer)
571 goto fail;
572 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
573
574 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
575 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
576 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
577 sctx->b.set_constant_buffer(&sctx->b, shader, i,
578 &sctx->null_const_buf);
579 }
580 }
581
582 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
583 &sctx->null_const_buf);
584 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
585 &sctx->null_const_buf);
586 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
587 &sctx->null_const_buf);
588 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
589 &sctx->null_const_buf);
590 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
591 &sctx->null_const_buf);
592 }
593
594 uint64_t max_threads_per_block;
595 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
596 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
597 &max_threads_per_block);
598
599 /* The maximum number of scratch waves. Scratch space isn't divided
600 * evenly between CUs. The number is only a function of the number of CUs.
601 * We can decrease the constant to decrease the scratch buffer size.
602 *
603 * sctx->scratch_waves must be >= the maximum posible size of
604 * 1 threadgroup, so that the hw doesn't hang from being unable
605 * to start any.
606 *
607 * The recommended value is 4 per CU at most. Higher numbers don't
608 * bring much benefit, but they still occupy chip resources (think
609 * async compute). I've seen ~2% performance difference between 4 and 32.
610 */
611 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
612 max_threads_per_block / 64);
613
614 si_init_compiler(sscreen, &sctx->compiler);
615
616 /* Bindless handles. */
617 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
618 _mesa_key_pointer_equal);
619 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
620 _mesa_key_pointer_equal);
621
622 util_dynarray_init(&sctx->resident_tex_handles, NULL);
623 util_dynarray_init(&sctx->resident_img_handles, NULL);
624 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
625 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
626 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
627
628 sctx->sample_pos_buffer =
629 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
630 sizeof(sctx->sample_positions));
631 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
632 sizeof(sctx->sample_positions), &sctx->sample_positions);
633
634 /* this must be last */
635 si_begin_new_gfx_cs(sctx);
636
637 if (sctx->chip_class == CIK) {
638 /* Clear the NULL constant buffer, because loads should return zeros. */
639 uint32_t clear_value = 0;
640 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
641 sctx->null_const_buf.buffer->width0,
642 &clear_value, 4, SI_COHERENCY_SHADER);
643 }
644 return &sctx->b;
645 fail:
646 fprintf(stderr, "radeonsi: Failed to create a context.\n");
647 si_destroy_context(&sctx->b);
648 return NULL;
649 }
650
651 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
652 void *priv, unsigned flags)
653 {
654 struct si_screen *sscreen = (struct si_screen *)screen;
655 struct pipe_context *ctx;
656
657 if (sscreen->debug_flags & DBG(CHECK_VM))
658 flags |= PIPE_CONTEXT_DEBUG;
659
660 ctx = si_create_context(screen, flags);
661
662 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
663 return ctx;
664
665 /* Clover (compute-only) is unsupported. */
666 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
667 return ctx;
668
669 /* When shaders are logged to stderr, asynchronous compilation is
670 * disabled too. */
671 if (sscreen->debug_flags & DBG_ALL_SHADERS)
672 return ctx;
673
674 /* Use asynchronous flushes only on amdgpu, since the radeon
675 * implementation for fence_server_sync is incomplete. */
676 return threaded_context_create(ctx, &sscreen->pool_transfers,
677 si_replace_buffer_storage,
678 sscreen->info.drm_major >= 3 ? si_create_fence : NULL,
679 &((struct si_context*)ctx)->tc);
680 }
681
682 /*
683 * pipe_screen
684 */
685 static void si_destroy_screen(struct pipe_screen* pscreen)
686 {
687 struct si_screen *sscreen = (struct si_screen *)pscreen;
688 struct si_shader_part *parts[] = {
689 sscreen->vs_prologs,
690 sscreen->tcs_epilogs,
691 sscreen->gs_prologs,
692 sscreen->ps_prologs,
693 sscreen->ps_epilogs
694 };
695 unsigned i;
696
697 if (!sscreen->ws->unref(sscreen->ws))
698 return;
699
700 util_queue_destroy(&sscreen->shader_compiler_queue);
701 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
702
703 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
704 si_destroy_compiler(&sscreen->compiler[i]);
705
706 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
707 si_destroy_compiler(&sscreen->compiler_lowp[i]);
708
709 /* Free shader parts. */
710 for (i = 0; i < ARRAY_SIZE(parts); i++) {
711 while (parts[i]) {
712 struct si_shader_part *part = parts[i];
713
714 parts[i] = part->next;
715 ac_shader_binary_clean(&part->binary);
716 FREE(part);
717 }
718 }
719 mtx_destroy(&sscreen->shader_parts_mutex);
720 si_destroy_shader_cache(sscreen);
721
722 si_destroy_perfcounters(sscreen);
723 si_gpu_load_kill_thread(sscreen);
724
725 mtx_destroy(&sscreen->gpu_load_mutex);
726 mtx_destroy(&sscreen->aux_context_lock);
727 sscreen->aux_context->destroy(sscreen->aux_context);
728
729 slab_destroy_parent(&sscreen->pool_transfers);
730
731 disk_cache_destroy(sscreen->disk_shader_cache);
732 sscreen->ws->destroy(sscreen->ws);
733 FREE(sscreen);
734 }
735
736 static void si_init_gs_info(struct si_screen *sscreen)
737 {
738 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
739 sscreen->info.family);
740 }
741
742 static void si_test_vmfault(struct si_screen *sscreen)
743 {
744 struct pipe_context *ctx = sscreen->aux_context;
745 struct si_context *sctx = (struct si_context *)ctx;
746 struct pipe_resource *buf =
747 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
748
749 if (!buf) {
750 puts("Buffer allocation failed.");
751 exit(1);
752 }
753
754 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
755
756 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
757 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
758 SI_COHERENCY_NONE, L2_BYPASS);
759 ctx->flush(ctx, NULL, 0);
760 puts("VM fault test: CP - done.");
761 }
762 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
763 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
764 ctx->flush(ctx, NULL, 0);
765 puts("VM fault test: SDMA - done.");
766 }
767 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
768 util_test_constant_buffer(ctx, buf);
769 puts("VM fault test: Shader - done.");
770 }
771 exit(0);
772 }
773
774 static void si_test_gds_memory_management(struct si_context *sctx,
775 unsigned alloc_size, unsigned alignment,
776 enum radeon_bo_domain domain)
777 {
778 struct radeon_winsys *ws = sctx->ws;
779 struct radeon_cmdbuf *cs[8];
780 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
781
782 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
783 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
784 NULL, NULL, false);
785 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
786 assert(gds_bo[i]);
787 }
788
789 for (unsigned iterations = 0; iterations < 20000; iterations++) {
790 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
791 /* This clears GDS with CP DMA.
792 *
793 * We don't care if GDS is present. Just add some packet
794 * to make the GPU busy for a moment.
795 */
796 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
797 SI_CPDMA_SKIP_BO_LIST_UPDATE |
798 SI_CPDMA_SKIP_CHECK_CS_SPACE |
799 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
800
801 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
802 RADEON_USAGE_READWRITE, 0);
803 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
804 }
805 }
806 exit(0);
807 }
808
809 static void si_disk_cache_create(struct si_screen *sscreen)
810 {
811 /* Don't use the cache if shader dumping is enabled. */
812 if (sscreen->debug_flags & DBG_ALL_SHADERS)
813 return;
814
815 struct mesa_sha1 ctx;
816 unsigned char sha1[20];
817 char cache_id[20 * 2 + 1];
818
819 _mesa_sha1_init(&ctx);
820
821 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
822 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
823 &ctx))
824 return;
825
826 _mesa_sha1_final(&ctx, sha1);
827 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
828
829 /* These flags affect shader compilation. */
830 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
831 DBG(SI_SCHED) | \
832 DBG(GISEL) | \
833 DBG(UNSAFE_MATH) | \
834 DBG(NIR))
835 uint64_t shader_debug_flags = sscreen->debug_flags &
836 ALL_FLAGS;
837
838 /* Add the high bits of 32-bit addresses, which affects
839 * how 32-bit addresses are expanded to 64 bits.
840 */
841 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
842 shader_debug_flags |= (uint64_t)sscreen->info.address32_hi << 32;
843
844 sscreen->disk_shader_cache =
845 disk_cache_create(sscreen->info.name,
846 cache_id,
847 shader_debug_flags);
848 }
849
850 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen,
851 unsigned max_threads)
852 {
853 struct si_screen *sscreen = (struct si_screen *)screen;
854
855 /* This function doesn't allow a greater number of threads than
856 * the queue had at its creation. */
857 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue,
858 max_threads);
859 /* Don't change the number of threads on the low priority queue. */
860 }
861
862 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen,
863 void *shader,
864 unsigned shader_type)
865 {
866 if (shader_type == PIPE_SHADER_COMPUTE) {
867 struct si_compute *cs = (struct si_compute*)shader;
868
869 return util_queue_fence_is_signalled(&cs->ready);
870 }
871 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
872
873 return util_queue_fence_is_signalled(&sel->ready);
874 }
875
876 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
877 const struct pipe_screen_config *config)
878 {
879 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
880 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i;
881
882 if (!sscreen) {
883 return NULL;
884 }
885
886 sscreen->ws = ws;
887 ws->query_info(ws, &sscreen->info);
888
889 if (sscreen->info.chip_class >= GFX9) {
890 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
891 } else {
892 ac_get_raster_config(&sscreen->info,
893 &sscreen->pa_sc_raster_config,
894 &sscreen->pa_sc_raster_config_1,
895 &sscreen->se_tile_repeat);
896 }
897
898 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
899 debug_options, 0);
900 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
901 debug_options, 0);
902
903 /* Set functions first. */
904 sscreen->b.context_create = si_pipe_create_context;
905 sscreen->b.destroy = si_destroy_screen;
906 sscreen->b.set_max_shader_compiler_threads =
907 si_set_max_shader_compiler_threads;
908 sscreen->b.is_parallel_shader_compilation_finished =
909 si_is_parallel_shader_compilation_finished;
910
911 si_init_screen_get_functions(sscreen);
912 si_init_screen_buffer_functions(sscreen);
913 si_init_screen_fence_functions(sscreen);
914 si_init_screen_state_functions(sscreen);
915 si_init_screen_texture_functions(sscreen);
916 si_init_screen_query_functions(sscreen);
917
918 /* Set these flags in debug_flags early, so that the shader cache takes
919 * them into account.
920 */
921 if (driQueryOptionb(config->options,
922 "glsl_correct_derivatives_after_discard"))
923 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
924 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
925 sscreen->debug_flags |= DBG(SI_SCHED);
926 if (driQueryOptionb(config->options, "radeonsi_enable_nir"))
927 sscreen->debug_flags |= DBG(NIR);
928
929 if (sscreen->debug_flags & DBG(INFO))
930 ac_print_gpu_info(&sscreen->info);
931
932 slab_create_parent(&sscreen->pool_transfers,
933 sizeof(struct si_transfer), 64);
934
935 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
936 if (sscreen->force_aniso >= 0) {
937 printf("radeonsi: Forcing anisotropy filter to %ix\n",
938 /* round down to a power of two */
939 1 << util_logbase2(sscreen->force_aniso));
940 }
941
942 (void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
943 (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
944
945 si_init_gs_info(sscreen);
946 if (!si_init_shader_cache(sscreen)) {
947 FREE(sscreen);
948 return NULL;
949 }
950
951 si_disk_cache_create(sscreen);
952
953 /* Determine the number of shader compiler threads. */
954 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
955
956 if (hw_threads >= 12) {
957 num_comp_hi_threads = hw_threads * 3 / 4;
958 num_comp_lo_threads = hw_threads / 3;
959 } else if (hw_threads >= 6) {
960 num_comp_hi_threads = hw_threads - 2;
961 num_comp_lo_threads = hw_threads / 2;
962 } else if (hw_threads >= 2) {
963 num_comp_hi_threads = hw_threads - 1;
964 num_comp_lo_threads = hw_threads / 2;
965 } else {
966 num_comp_hi_threads = 1;
967 num_comp_lo_threads = 1;
968 }
969
970 num_comp_hi_threads = MIN2(num_comp_hi_threads,
971 ARRAY_SIZE(sscreen->compiler));
972 num_comp_lo_threads = MIN2(num_comp_lo_threads,
973 ARRAY_SIZE(sscreen->compiler_lowp));
974
975 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
976 64, num_comp_hi_threads,
977 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
978 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
979 si_destroy_shader_cache(sscreen);
980 FREE(sscreen);
981 return NULL;
982 }
983
984 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
985 "shlo",
986 64, num_comp_lo_threads,
987 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
988 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
989 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
990 si_destroy_shader_cache(sscreen);
991 FREE(sscreen);
992 return NULL;
993 }
994
995 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
996 si_init_perfcounters(sscreen);
997
998 /* Determine tessellation ring info. */
999 bool double_offchip_buffers = sscreen->info.chip_class >= CIK &&
1000 sscreen->info.family != CHIP_CARRIZO &&
1001 sscreen->info.family != CHIP_STONEY;
1002 /* This must be one less than the maximum number due to a hw limitation.
1003 * Various hardware bugs in SI, CIK, and GFX9 need this.
1004 */
1005 unsigned max_offchip_buffers_per_se;
1006
1007 /* Only certain chips can use the maximum value. */
1008 if (sscreen->info.family == CHIP_VEGA12 ||
1009 sscreen->info.family == CHIP_VEGA20)
1010 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1011 else
1012 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1013
1014 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1015 sscreen->info.max_se;
1016 unsigned offchip_granularity;
1017
1018 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1019 * around by setting 4K granularity.
1020 */
1021 if (sscreen->info.family == CHIP_HAWAII) {
1022 sscreen->tess_offchip_block_dw_size = 4096;
1023 offchip_granularity = V_03093C_X_4K_DWORDS;
1024 } else {
1025 sscreen->tess_offchip_block_dw_size = 8192;
1026 offchip_granularity = V_03093C_X_8K_DWORDS;
1027 }
1028
1029 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
1030 assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
1031 sscreen->tess_offchip_ring_size = max_offchip_buffers *
1032 sscreen->tess_offchip_block_dw_size * 4;
1033
1034 if (sscreen->info.chip_class >= CIK) {
1035 if (sscreen->info.chip_class >= VI)
1036 --max_offchip_buffers;
1037 sscreen->vgt_hs_offchip_param =
1038 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1039 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1040 } else {
1041 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1042 sscreen->vgt_hs_offchip_param =
1043 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1044 }
1045
1046 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1047 * on SI. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
1048 * SPI_VS_OUT_CONFIG. So only enable CI CLEAR_STATE on amdgpu kernel.*/
1049 sscreen->has_clear_state = sscreen->info.chip_class >= CIK &&
1050 sscreen->info.drm_major == 3;
1051
1052 sscreen->has_distributed_tess =
1053 sscreen->info.chip_class >= VI &&
1054 sscreen->info.max_se >= 2;
1055
1056 sscreen->has_draw_indirect_multi =
1057 (sscreen->info.family >= CHIP_POLARIS10) ||
1058 (sscreen->info.chip_class == VI &&
1059 sscreen->info.pfp_fw_version >= 121 &&
1060 sscreen->info.me_fw_version >= 87) ||
1061 (sscreen->info.chip_class == CIK &&
1062 sscreen->info.pfp_fw_version >= 211 &&
1063 sscreen->info.me_fw_version >= 173) ||
1064 (sscreen->info.chip_class == SI &&
1065 sscreen->info.pfp_fw_version >= 79 &&
1066 sscreen->info.me_fw_version >= 142);
1067
1068 sscreen->has_out_of_order_rast = sscreen->info.chip_class >= VI &&
1069 sscreen->info.max_se >= 2 &&
1070 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1071 sscreen->assume_no_z_fights =
1072 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1073 sscreen->commutative_blend_add =
1074 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1075 sscreen->clear_db_cache_before_clear =
1076 driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
1077 sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
1078 sscreen->info.family <= CHIP_POLARIS12) ||
1079 sscreen->info.family == CHIP_VEGA10 ||
1080 sscreen->info.family == CHIP_RAVEN;
1081 sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
1082 sscreen->info.family == CHIP_RAVEN;
1083 sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2;
1084
1085 /* Only enable primitive binning on APUs by default. */
1086 sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN ||
1087 sscreen->info.family == CHIP_RAVEN2;
1088
1089 sscreen->dfsm_allowed = sscreen->info.family == CHIP_RAVEN ||
1090 sscreen->info.family == CHIP_RAVEN2;
1091
1092 /* Process DPBB enable flags. */
1093 if (sscreen->debug_flags & DBG(DPBB)) {
1094 sscreen->dpbb_allowed = true;
1095 if (sscreen->debug_flags & DBG(DFSM))
1096 sscreen->dfsm_allowed = true;
1097 }
1098
1099 /* Process DPBB disable flags. */
1100 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1101 sscreen->dpbb_allowed = false;
1102 sscreen->dfsm_allowed = false;
1103 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1104 sscreen->dfsm_allowed = false;
1105 }
1106
1107 /* While it would be nice not to have this flag, we are constrained
1108 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1109 * on GFX9.
1110 */
1111 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= VI;
1112
1113 /* Some chips have RB+ registers, but don't support RB+. Those must
1114 * always disable it.
1115 */
1116 if (sscreen->info.family == CHIP_STONEY ||
1117 sscreen->info.chip_class >= GFX9) {
1118 sscreen->has_rbplus = true;
1119
1120 sscreen->rbplus_allowed =
1121 !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
1122 (sscreen->info.family == CHIP_STONEY ||
1123 sscreen->info.family == CHIP_VEGA12 ||
1124 sscreen->info.family == CHIP_RAVEN ||
1125 sscreen->info.family == CHIP_RAVEN2);
1126 }
1127
1128 sscreen->dcc_msaa_allowed =
1129 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1130
1131 sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= VI;
1132
1133 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1134 sscreen->use_monolithic_shaders =
1135 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1136
1137 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1138 SI_CONTEXT_INV_VMEM_L1;
1139 if (sscreen->info.chip_class <= VI) {
1140 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1141 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1142 }
1143
1144 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1145 sscreen->debug_flags |= DBG_ALL_SHADERS;
1146
1147 /* Syntax:
1148 * EQAA=s,z,c
1149 * Example:
1150 * EQAA=8,4,2
1151
1152 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1153 * Constraints:
1154 * s >= z >= c (ignoring this only wastes memory)
1155 * s = [2..16]
1156 * z = [2..8]
1157 * c = [2..8]
1158 *
1159 * Only MSAA color and depth buffers are overriden.
1160 */
1161 if (sscreen->info.has_eqaa_surface_allocator) {
1162 const char *eqaa = debug_get_option("EQAA", NULL);
1163 unsigned s,z,f;
1164
1165 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1166 sscreen->eqaa_force_coverage_samples = s;
1167 sscreen->eqaa_force_z_samples = z;
1168 sscreen->eqaa_force_color_samples = f;
1169 }
1170 }
1171
1172 for (i = 0; i < num_comp_hi_threads; i++)
1173 si_init_compiler(sscreen, &sscreen->compiler[i]);
1174 for (i = 0; i < num_comp_lo_threads; i++)
1175 si_init_compiler(sscreen, &sscreen->compiler_lowp[i]);
1176
1177 /* Create the auxiliary context. This must be done last. */
1178 sscreen->aux_context = si_create_context(&sscreen->b, 0);
1179
1180 if (sscreen->debug_flags & DBG(TEST_DMA))
1181 si_test_dma(sscreen);
1182
1183 if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) {
1184 si_test_dma_perf(sscreen);
1185 }
1186
1187 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1188 DBG(TEST_VMFAULT_SDMA) |
1189 DBG(TEST_VMFAULT_SHADER)))
1190 si_test_vmfault(sscreen);
1191
1192 if (sscreen->debug_flags & DBG(TEST_GDS))
1193 si_test_gds((struct si_context*)sscreen->aux_context);
1194
1195 if (sscreen->debug_flags & DBG(TEST_GDS_MM)) {
1196 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1197 32 * 1024, 4, RADEON_DOMAIN_GDS);
1198 }
1199 if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) {
1200 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1201 4, 1, RADEON_DOMAIN_OA);
1202 }
1203
1204 return &sscreen->b;
1205 }