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radeonsi: add driconf option radeonsi_enable_nir
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "sid.h"
30
31 #include "ac_llvm_util.h"
32 #include "radeon/radeon_uvd.h"
33 #include "gallivm/lp_bld_misc.h"
34 #include "util/disk_cache.h"
35 #include "util/u_log.h"
36 #include "util/u_memory.h"
37 #include "util/u_suballoc.h"
38 #include "util/u_tests.h"
39 #include "util/u_upload_mgr.h"
40 #include "util/xmlconfig.h"
41 #include "vl/vl_decoder.h"
42 #include "driver_ddebug/dd_util.h"
43
44 static const struct debug_named_value debug_options[] = {
45 /* Shader logging options: */
46 { "vs", DBG(VS), "Print vertex shaders" },
47 { "ps", DBG(PS), "Print pixel shaders" },
48 { "gs", DBG(GS), "Print geometry shaders" },
49 { "tcs", DBG(TCS), "Print tessellation control shaders" },
50 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
51 { "cs", DBG(CS), "Print compute shaders" },
52 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
53 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
54 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
55 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
56
57 /* Shader compiler options the shader cache should be aware of: */
58 { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" },
59 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
60 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
61
62 /* Shader compiler options (with no effect on the shader cache): */
63 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
64 { "nir", DBG(NIR), "Enable experimental NIR shaders" },
65 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
66 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
67
68 /* Information logging options: */
69 { "info", DBG(INFO), "Print driver information" },
70 { "tex", DBG(TEX), "Print texture info" },
71 { "compute", DBG(COMPUTE), "Print compute info" },
72 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
73
74 /* Driver options: */
75 { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." },
76 { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
77 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
78 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
79 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
80 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
81
82 /* 3D engine options: */
83 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
84 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
85 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
86 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
87 { "dpbb", DBG(DPBB), "Enable DPBB." },
88 { "dfsm", DBG(DFSM), "Enable DFSM." },
89 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
90 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
91 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
92 { "notiling", DBG(NO_TILING), "Disable tiling" },
93 { "nodcc", DBG(NO_DCC), "Disable DCC." },
94 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
95 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
96 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
97 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
98
99 /* Tests: */
100 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
101 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
102 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
103 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
104 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
105 { "testgds", DBG(TEST_GDS), "Test GDS." },
106 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
107 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
108
109 DEBUG_NAMED_VALUE_END /* must be last */
110 };
111
112 static void si_init_compiler(struct si_screen *sscreen,
113 struct ac_llvm_compiler *compiler)
114 {
115 /* Only create the less-optimizing version of the compiler on APUs
116 * predating Ryzen (Raven). */
117 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
118 sscreen->info.chip_class <= VI;
119
120 enum ac_target_machine_options tm_options =
121 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
122 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
123 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
124 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
125 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
126 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
127 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
128
129 ac_init_llvm_once();
130 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
131 compiler->passes = ac_create_llvm_passes(compiler->tm);
132
133 if (compiler->low_opt_tm)
134 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
135 }
136
137 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
138 {
139 ac_destroy_llvm_passes(compiler->passes);
140 ac_destroy_llvm_passes(compiler->low_opt_passes);
141 ac_destroy_llvm_compiler(compiler);
142 }
143
144 /*
145 * pipe_context
146 */
147 static void si_destroy_context(struct pipe_context *context)
148 {
149 struct si_context *sctx = (struct si_context *)context;
150 int i;
151
152 /* Unreference the framebuffer normally to disable related logic
153 * properly.
154 */
155 struct pipe_framebuffer_state fb = {};
156 if (context->set_framebuffer_state)
157 context->set_framebuffer_state(context, &fb);
158
159 si_release_all_descriptors(sctx);
160
161 pipe_resource_reference(&sctx->esgs_ring, NULL);
162 pipe_resource_reference(&sctx->gsvs_ring, NULL);
163 pipe_resource_reference(&sctx->tess_rings, NULL);
164 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
165 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
166 si_resource_reference(&sctx->border_color_buffer, NULL);
167 free(sctx->border_color_table);
168 si_resource_reference(&sctx->scratch_buffer, NULL);
169 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
170 si_resource_reference(&sctx->wait_mem_scratch, NULL);
171
172 si_pm4_free_state(sctx, sctx->init_config, ~0);
173 if (sctx->init_config_gs_rings)
174 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
175 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
176 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
177
178 if (sctx->fixed_func_tcs_shader.cso)
179 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
180 if (sctx->custom_dsa_flush)
181 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
182 if (sctx->custom_blend_resolve)
183 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
184 if (sctx->custom_blend_fmask_decompress)
185 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
186 if (sctx->custom_blend_eliminate_fastclear)
187 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
188 if (sctx->custom_blend_dcc_decompress)
189 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
190 if (sctx->vs_blit_pos)
191 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
192 if (sctx->vs_blit_pos_layered)
193 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
194 if (sctx->vs_blit_color)
195 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
196 if (sctx->vs_blit_color_layered)
197 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
198 if (sctx->vs_blit_texcoord)
199 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
200 if (sctx->cs_clear_buffer)
201 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
202 if (sctx->cs_copy_buffer)
203 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
204 if (sctx->cs_copy_image)
205 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
206 if (sctx->cs_copy_image_1d_array)
207 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
208 if (sctx->cs_clear_render_target)
209 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
210 if (sctx->cs_clear_render_target_1d_array)
211 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
212
213 if (sctx->blitter)
214 util_blitter_destroy(sctx->blitter);
215
216 /* Release DCC stats. */
217 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
218 assert(!sctx->dcc_stats[i].query_active);
219
220 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
221 if (sctx->dcc_stats[i].ps_stats[j])
222 sctx->b.destroy_query(&sctx->b,
223 sctx->dcc_stats[i].ps_stats[j]);
224
225 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
226 }
227
228 if (sctx->query_result_shader)
229 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
230
231 if (sctx->gfx_cs)
232 sctx->ws->cs_destroy(sctx->gfx_cs);
233 if (sctx->dma_cs)
234 sctx->ws->cs_destroy(sctx->dma_cs);
235 if (sctx->ctx)
236 sctx->ws->ctx_destroy(sctx->ctx);
237
238 if (sctx->b.stream_uploader)
239 u_upload_destroy(sctx->b.stream_uploader);
240 if (sctx->b.const_uploader)
241 u_upload_destroy(sctx->b.const_uploader);
242 if (sctx->cached_gtt_allocator)
243 u_upload_destroy(sctx->cached_gtt_allocator);
244
245 slab_destroy_child(&sctx->pool_transfers);
246 slab_destroy_child(&sctx->pool_transfers_unsync);
247
248 if (sctx->allocator_zeroed_memory)
249 u_suballocator_destroy(sctx->allocator_zeroed_memory);
250
251 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
252 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
253 si_resource_reference(&sctx->eop_bug_scratch, NULL);
254
255 si_destroy_compiler(&sctx->compiler);
256
257 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
258
259 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
260 _mesa_hash_table_destroy(sctx->img_handles, NULL);
261
262 util_dynarray_fini(&sctx->resident_tex_handles);
263 util_dynarray_fini(&sctx->resident_img_handles);
264 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
265 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
266 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
267 FREE(sctx);
268 }
269
270 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
271 {
272 struct si_context *sctx = (struct si_context *)ctx;
273
274 if (sctx->screen->info.has_gpu_reset_status_query)
275 return sctx->ws->ctx_query_reset_status(sctx->ctx);
276
277 if (sctx->screen->info.has_gpu_reset_counter_query) {
278 unsigned latest = sctx->ws->query_value(sctx->ws,
279 RADEON_GPU_RESET_COUNTER);
280
281 if (sctx->gpu_reset_counter == latest)
282 return PIPE_NO_RESET;
283
284 sctx->gpu_reset_counter = latest;
285 return PIPE_UNKNOWN_CONTEXT_RESET;
286 }
287
288 return PIPE_NO_RESET;
289 }
290
291 static void si_set_device_reset_callback(struct pipe_context *ctx,
292 const struct pipe_device_reset_callback *cb)
293 {
294 struct si_context *sctx = (struct si_context *)ctx;
295
296 if (cb)
297 sctx->device_reset_callback = *cb;
298 else
299 memset(&sctx->device_reset_callback, 0,
300 sizeof(sctx->device_reset_callback));
301 }
302
303 bool si_check_device_reset(struct si_context *sctx)
304 {
305 enum pipe_reset_status status;
306
307 if (!sctx->device_reset_callback.reset)
308 return false;
309
310 if (!sctx->b.get_device_reset_status)
311 return false;
312
313 status = sctx->b.get_device_reset_status(&sctx->b);
314 if (status == PIPE_NO_RESET)
315 return false;
316
317 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
318 return true;
319 }
320
321 /* Apitrace profiling:
322 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
323 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
324 * and remember its number.
325 * 3) In Mesa, enable queries and performance counters around that draw
326 * call and print the results.
327 * 4) glretrace --benchmark --markers ..
328 */
329 static void si_emit_string_marker(struct pipe_context *ctx,
330 const char *string, int len)
331 {
332 struct si_context *sctx = (struct si_context *)ctx;
333
334 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
335
336 if (sctx->log)
337 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
338 }
339
340 static void si_set_debug_callback(struct pipe_context *ctx,
341 const struct pipe_debug_callback *cb)
342 {
343 struct si_context *sctx = (struct si_context *)ctx;
344 struct si_screen *screen = sctx->screen;
345
346 util_queue_finish(&screen->shader_compiler_queue);
347 util_queue_finish(&screen->shader_compiler_queue_low_priority);
348
349 if (cb)
350 sctx->debug = *cb;
351 else
352 memset(&sctx->debug, 0, sizeof(sctx->debug));
353 }
354
355 static void si_set_log_context(struct pipe_context *ctx,
356 struct u_log_context *log)
357 {
358 struct si_context *sctx = (struct si_context *)ctx;
359 sctx->log = log;
360
361 if (log)
362 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
363 }
364
365 static void si_set_context_param(struct pipe_context *ctx,
366 enum pipe_context_param param,
367 unsigned value)
368 {
369 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
370
371 switch (param) {
372 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
373 ws->pin_threads_to_L3_cache(ws, value);
374 break;
375 default:;
376 }
377 }
378
379 static struct pipe_context *si_create_context(struct pipe_screen *screen,
380 unsigned flags)
381 {
382 struct si_context *sctx = CALLOC_STRUCT(si_context);
383 struct si_screen* sscreen = (struct si_screen *)screen;
384 struct radeon_winsys *ws = sscreen->ws;
385 int shader, i;
386 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
387
388 if (!sctx)
389 return NULL;
390
391 if (flags & PIPE_CONTEXT_DEBUG)
392 sscreen->record_llvm_ir = true; /* racy but not critical */
393
394 sctx->b.screen = screen; /* this must be set first */
395 sctx->b.priv = NULL;
396 sctx->b.destroy = si_destroy_context;
397 sctx->b.emit_string_marker = si_emit_string_marker;
398 sctx->b.set_debug_callback = si_set_debug_callback;
399 sctx->b.set_log_context = si_set_log_context;
400 sctx->b.set_context_param = si_set_context_param;
401 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
402 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
403
404 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
405 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
406
407 sctx->ws = sscreen->ws;
408 sctx->family = sscreen->info.family;
409 sctx->chip_class = sscreen->info.chip_class;
410
411 if (sscreen->info.has_gpu_reset_counter_query) {
412 sctx->gpu_reset_counter =
413 sctx->ws->query_value(sctx->ws, RADEON_GPU_RESET_COUNTER);
414 }
415
416 sctx->b.get_device_reset_status = si_get_reset_status;
417 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
418
419 si_init_context_texture_functions(sctx);
420 si_init_query_functions(sctx);
421
422 if (sctx->chip_class == CIK ||
423 sctx->chip_class == VI ||
424 sctx->chip_class == GFX9) {
425 sctx->eop_bug_scratch = si_resource(
426 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
427 16 * sscreen->info.num_render_backends));
428 if (!sctx->eop_bug_scratch)
429 goto fail;
430 }
431
432 sctx->allocator_zeroed_memory =
433 u_suballocator_create(&sctx->b, 128 * 1024,
434 0, PIPE_USAGE_DEFAULT,
435 SI_RESOURCE_FLAG_UNMAPPABLE |
436 SI_RESOURCE_FLAG_CLEAR, false);
437 if (!sctx->allocator_zeroed_memory)
438 goto fail;
439
440 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
441 0, PIPE_USAGE_STREAM,
442 SI_RESOURCE_FLAG_READ_ONLY);
443 if (!sctx->b.stream_uploader)
444 goto fail;
445
446 sctx->b.const_uploader = u_upload_create(&sctx->b, 128 * 1024,
447 0, PIPE_USAGE_DEFAULT,
448 SI_RESOURCE_FLAG_32BIT |
449 (sscreen->cpdma_prefetch_writes_memory ?
450 0 : SI_RESOURCE_FLAG_READ_ONLY));
451 if (!sctx->b.const_uploader)
452 goto fail;
453
454 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
455 0, PIPE_USAGE_STAGING, 0);
456 if (!sctx->cached_gtt_allocator)
457 goto fail;
458
459 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
460 if (!sctx->ctx)
461 goto fail;
462
463 if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
464 sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
465 (void*)si_flush_dma_cs,
466 sctx, stop_exec_on_failure);
467 }
468
469 si_init_buffer_functions(sctx);
470 si_init_clear_functions(sctx);
471 si_init_blit_functions(sctx);
472 si_init_compute_functions(sctx);
473 si_init_compute_blit_functions(sctx);
474 si_init_debug_functions(sctx);
475 si_init_msaa_functions(sctx);
476 si_init_streamout_functions(sctx);
477
478 if (sscreen->info.has_hw_decode) {
479 sctx->b.create_video_codec = si_uvd_create_decoder;
480 sctx->b.create_video_buffer = si_video_buffer_create;
481 } else {
482 sctx->b.create_video_codec = vl_create_decoder;
483 sctx->b.create_video_buffer = vl_video_buffer_create;
484 }
485
486 sctx->gfx_cs = ws->cs_create(sctx->ctx, RING_GFX,
487 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
488
489 /* Border colors. */
490 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
491 sizeof(*sctx->border_color_table));
492 if (!sctx->border_color_table)
493 goto fail;
494
495 sctx->border_color_buffer = si_resource(
496 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
497 SI_MAX_BORDER_COLORS *
498 sizeof(*sctx->border_color_table)));
499 if (!sctx->border_color_buffer)
500 goto fail;
501
502 sctx->border_color_map =
503 ws->buffer_map(sctx->border_color_buffer->buf,
504 NULL, PIPE_TRANSFER_WRITE);
505 if (!sctx->border_color_map)
506 goto fail;
507
508 si_init_all_descriptors(sctx);
509 si_init_fence_functions(sctx);
510 si_init_state_functions(sctx);
511 si_init_shader_functions(sctx);
512 si_init_viewport_functions(sctx);
513
514 if (sctx->chip_class >= CIK)
515 cik_init_sdma_functions(sctx);
516 else
517 si_init_dma_functions(sctx);
518
519 if (sscreen->debug_flags & DBG(FORCE_DMA))
520 sctx->b.resource_copy_region = sctx->dma_copy;
521
522 sctx->blitter = util_blitter_create(&sctx->b);
523 if (sctx->blitter == NULL)
524 goto fail;
525 sctx->blitter->skip_viewport_restore = true;
526
527 si_init_draw_functions(sctx);
528
529 sctx->sample_mask = 0xffff;
530
531 if (sctx->chip_class >= GFX9) {
532 sctx->wait_mem_scratch = si_resource(
533 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 4));
534 if (!sctx->wait_mem_scratch)
535 goto fail;
536
537 /* Initialize the memory. */
538 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
539 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
540 }
541
542 /* CIK cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
543 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
544 if (sctx->chip_class == CIK) {
545 sctx->null_const_buf.buffer =
546 pipe_aligned_buffer_create(screen,
547 SI_RESOURCE_FLAG_32BIT,
548 PIPE_USAGE_DEFAULT, 16,
549 sctx->screen->info.tcc_cache_line_size);
550 if (!sctx->null_const_buf.buffer)
551 goto fail;
552 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
553
554 for (shader = 0; shader < SI_NUM_SHADERS; shader++) {
555 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
556 sctx->b.set_constant_buffer(&sctx->b, shader, i,
557 &sctx->null_const_buf);
558 }
559 }
560
561 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
562 &sctx->null_const_buf);
563 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
564 &sctx->null_const_buf);
565 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
566 &sctx->null_const_buf);
567 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
568 &sctx->null_const_buf);
569 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
570 &sctx->null_const_buf);
571 }
572
573 uint64_t max_threads_per_block;
574 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
575 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
576 &max_threads_per_block);
577
578 /* The maximum number of scratch waves. Scratch space isn't divided
579 * evenly between CUs. The number is only a function of the number of CUs.
580 * We can decrease the constant to decrease the scratch buffer size.
581 *
582 * sctx->scratch_waves must be >= the maximum posible size of
583 * 1 threadgroup, so that the hw doesn't hang from being unable
584 * to start any.
585 *
586 * The recommended value is 4 per CU at most. Higher numbers don't
587 * bring much benefit, but they still occupy chip resources (think
588 * async compute). I've seen ~2% performance difference between 4 and 32.
589 */
590 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
591 max_threads_per_block / 64);
592
593 si_init_compiler(sscreen, &sctx->compiler);
594
595 /* Bindless handles. */
596 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
597 _mesa_key_pointer_equal);
598 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
599 _mesa_key_pointer_equal);
600
601 util_dynarray_init(&sctx->resident_tex_handles, NULL);
602 util_dynarray_init(&sctx->resident_img_handles, NULL);
603 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
604 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
605 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
606
607 sctx->sample_pos_buffer =
608 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
609 sizeof(sctx->sample_positions));
610 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
611 sizeof(sctx->sample_positions), &sctx->sample_positions);
612
613 /* this must be last */
614 si_begin_new_gfx_cs(sctx);
615
616 if (sctx->chip_class == CIK) {
617 /* Clear the NULL constant buffer, because loads should return zeros. */
618 uint32_t clear_value = 0;
619 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
620 sctx->null_const_buf.buffer->width0,
621 &clear_value, 4, SI_COHERENCY_SHADER);
622 }
623 return &sctx->b;
624 fail:
625 fprintf(stderr, "radeonsi: Failed to create a context.\n");
626 si_destroy_context(&sctx->b);
627 return NULL;
628 }
629
630 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
631 void *priv, unsigned flags)
632 {
633 struct si_screen *sscreen = (struct si_screen *)screen;
634 struct pipe_context *ctx;
635
636 if (sscreen->debug_flags & DBG(CHECK_VM))
637 flags |= PIPE_CONTEXT_DEBUG;
638
639 ctx = si_create_context(screen, flags);
640
641 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
642 return ctx;
643
644 /* Clover (compute-only) is unsupported. */
645 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
646 return ctx;
647
648 /* When shaders are logged to stderr, asynchronous compilation is
649 * disabled too. */
650 if (sscreen->debug_flags & DBG_ALL_SHADERS)
651 return ctx;
652
653 /* Use asynchronous flushes only on amdgpu, since the radeon
654 * implementation for fence_server_sync is incomplete. */
655 return threaded_context_create(ctx, &sscreen->pool_transfers,
656 si_replace_buffer_storage,
657 sscreen->info.drm_major >= 3 ? si_create_fence : NULL,
658 &((struct si_context*)ctx)->tc);
659 }
660
661 /*
662 * pipe_screen
663 */
664 static void si_destroy_screen(struct pipe_screen* pscreen)
665 {
666 struct si_screen *sscreen = (struct si_screen *)pscreen;
667 struct si_shader_part *parts[] = {
668 sscreen->vs_prologs,
669 sscreen->tcs_epilogs,
670 sscreen->gs_prologs,
671 sscreen->ps_prologs,
672 sscreen->ps_epilogs
673 };
674 unsigned i;
675
676 if (!sscreen->ws->unref(sscreen->ws))
677 return;
678
679 util_queue_destroy(&sscreen->shader_compiler_queue);
680 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
681
682 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
683 si_destroy_compiler(&sscreen->compiler[i]);
684
685 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
686 si_destroy_compiler(&sscreen->compiler_lowp[i]);
687
688 /* Free shader parts. */
689 for (i = 0; i < ARRAY_SIZE(parts); i++) {
690 while (parts[i]) {
691 struct si_shader_part *part = parts[i];
692
693 parts[i] = part->next;
694 ac_shader_binary_clean(&part->binary);
695 FREE(part);
696 }
697 }
698 mtx_destroy(&sscreen->shader_parts_mutex);
699 si_destroy_shader_cache(sscreen);
700
701 si_destroy_perfcounters(sscreen);
702 si_gpu_load_kill_thread(sscreen);
703
704 mtx_destroy(&sscreen->gpu_load_mutex);
705 mtx_destroy(&sscreen->aux_context_lock);
706 sscreen->aux_context->destroy(sscreen->aux_context);
707
708 slab_destroy_parent(&sscreen->pool_transfers);
709
710 disk_cache_destroy(sscreen->disk_shader_cache);
711 sscreen->ws->destroy(sscreen->ws);
712 FREE(sscreen);
713 }
714
715 static void si_init_gs_info(struct si_screen *sscreen)
716 {
717 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
718 sscreen->info.family);
719 }
720
721 static void si_test_vmfault(struct si_screen *sscreen)
722 {
723 struct pipe_context *ctx = sscreen->aux_context;
724 struct si_context *sctx = (struct si_context *)ctx;
725 struct pipe_resource *buf =
726 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
727
728 if (!buf) {
729 puts("Buffer allocation failed.");
730 exit(1);
731 }
732
733 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
734
735 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
736 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
737 SI_COHERENCY_NONE, L2_BYPASS);
738 ctx->flush(ctx, NULL, 0);
739 puts("VM fault test: CP - done.");
740 }
741 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
742 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
743 ctx->flush(ctx, NULL, 0);
744 puts("VM fault test: SDMA - done.");
745 }
746 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
747 util_test_constant_buffer(ctx, buf);
748 puts("VM fault test: Shader - done.");
749 }
750 exit(0);
751 }
752
753 static void si_test_gds_memory_management(struct si_context *sctx,
754 unsigned alloc_size, unsigned alignment,
755 enum radeon_bo_domain domain)
756 {
757 struct radeon_winsys *ws = sctx->ws;
758 struct radeon_cmdbuf *cs[8];
759 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
760
761 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
762 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
763 NULL, NULL, false);
764 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
765 assert(gds_bo[i]);
766 }
767
768 for (unsigned iterations = 0; iterations < 20000; iterations++) {
769 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
770 /* This clears GDS with CP DMA.
771 *
772 * We don't care if GDS is present. Just add some packet
773 * to make the GPU busy for a moment.
774 */
775 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
776 SI_CPDMA_SKIP_BO_LIST_UPDATE |
777 SI_CPDMA_SKIP_CHECK_CS_SPACE |
778 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
779
780 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
781 RADEON_USAGE_READWRITE, 0);
782 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
783 }
784 }
785 exit(0);
786 }
787
788 static void si_disk_cache_create(struct si_screen *sscreen)
789 {
790 /* Don't use the cache if shader dumping is enabled. */
791 if (sscreen->debug_flags & DBG_ALL_SHADERS)
792 return;
793
794 struct mesa_sha1 ctx;
795 unsigned char sha1[20];
796 char cache_id[20 * 2 + 1];
797
798 _mesa_sha1_init(&ctx);
799
800 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
801 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
802 &ctx))
803 return;
804
805 _mesa_sha1_final(&ctx, sha1);
806 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
807
808 /* These flags affect shader compilation. */
809 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
810 DBG(SI_SCHED) | \
811 DBG(GISEL) | \
812 DBG(UNSAFE_MATH) | \
813 DBG(NIR))
814 uint64_t shader_debug_flags = sscreen->debug_flags &
815 ALL_FLAGS;
816
817 /* Add the high bits of 32-bit addresses, which affects
818 * how 32-bit addresses are expanded to 64 bits.
819 */
820 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
821 shader_debug_flags |= (uint64_t)sscreen->info.address32_hi << 32;
822
823 sscreen->disk_shader_cache =
824 disk_cache_create(sscreen->info.name,
825 cache_id,
826 shader_debug_flags);
827 }
828
829 struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
830 const struct pipe_screen_config *config)
831 {
832 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
833 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i;
834
835 if (!sscreen) {
836 return NULL;
837 }
838
839 sscreen->ws = ws;
840 ws->query_info(ws, &sscreen->info);
841
842 if (sscreen->info.chip_class >= GFX9) {
843 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
844 } else {
845 ac_get_raster_config(&sscreen->info,
846 &sscreen->pa_sc_raster_config,
847 &sscreen->pa_sc_raster_config_1,
848 &sscreen->se_tile_repeat);
849 }
850
851 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
852 debug_options, 0);
853 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
854 debug_options, 0);
855
856 /* Set functions first. */
857 sscreen->b.context_create = si_pipe_create_context;
858 sscreen->b.destroy = si_destroy_screen;
859
860 si_init_screen_get_functions(sscreen);
861 si_init_screen_buffer_functions(sscreen);
862 si_init_screen_fence_functions(sscreen);
863 si_init_screen_state_functions(sscreen);
864 si_init_screen_texture_functions(sscreen);
865 si_init_screen_query_functions(sscreen);
866
867 /* Set these flags in debug_flags early, so that the shader cache takes
868 * them into account.
869 */
870 if (driQueryOptionb(config->options,
871 "glsl_correct_derivatives_after_discard"))
872 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
873 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
874 sscreen->debug_flags |= DBG(SI_SCHED);
875 if (driQueryOptionb(config->options, "radeonsi_enable_nir"))
876 sscreen->debug_flags |= DBG(NIR);
877
878 if (sscreen->debug_flags & DBG(INFO))
879 ac_print_gpu_info(&sscreen->info);
880
881 slab_create_parent(&sscreen->pool_transfers,
882 sizeof(struct si_transfer), 64);
883
884 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
885 if (sscreen->force_aniso >= 0) {
886 printf("radeonsi: Forcing anisotropy filter to %ix\n",
887 /* round down to a power of two */
888 1 << util_logbase2(sscreen->force_aniso));
889 }
890
891 (void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
892 (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
893
894 si_init_gs_info(sscreen);
895 if (!si_init_shader_cache(sscreen)) {
896 FREE(sscreen);
897 return NULL;
898 }
899
900 si_disk_cache_create(sscreen);
901
902 /* Determine the number of shader compiler threads. */
903 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
904
905 if (hw_threads >= 12) {
906 num_comp_hi_threads = hw_threads * 3 / 4;
907 num_comp_lo_threads = hw_threads / 3;
908 } else if (hw_threads >= 6) {
909 num_comp_hi_threads = hw_threads - 2;
910 num_comp_lo_threads = hw_threads / 2;
911 } else if (hw_threads >= 2) {
912 num_comp_hi_threads = hw_threads - 1;
913 num_comp_lo_threads = hw_threads / 2;
914 } else {
915 num_comp_hi_threads = 1;
916 num_comp_lo_threads = 1;
917 }
918
919 num_comp_hi_threads = MIN2(num_comp_hi_threads,
920 ARRAY_SIZE(sscreen->compiler));
921 num_comp_lo_threads = MIN2(num_comp_lo_threads,
922 ARRAY_SIZE(sscreen->compiler_lowp));
923
924 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
925 64, num_comp_hi_threads,
926 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
927 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
928 si_destroy_shader_cache(sscreen);
929 FREE(sscreen);
930 return NULL;
931 }
932
933 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
934 "shlo",
935 64, num_comp_lo_threads,
936 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
937 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
938 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
939 si_destroy_shader_cache(sscreen);
940 FREE(sscreen);
941 return NULL;
942 }
943
944 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
945 si_init_perfcounters(sscreen);
946
947 /* Determine tessellation ring info. */
948 bool double_offchip_buffers = sscreen->info.chip_class >= CIK &&
949 sscreen->info.family != CHIP_CARRIZO &&
950 sscreen->info.family != CHIP_STONEY;
951 /* This must be one less than the maximum number due to a hw limitation.
952 * Various hardware bugs in SI, CIK, and GFX9 need this.
953 */
954 unsigned max_offchip_buffers_per_se;
955
956 /* Only certain chips can use the maximum value. */
957 if (sscreen->info.family == CHIP_VEGA12 ||
958 sscreen->info.family == CHIP_VEGA20)
959 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
960 else
961 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
962
963 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
964 sscreen->info.max_se;
965 unsigned offchip_granularity;
966
967 /* Hawaii has a bug with offchip buffers > 256 that can be worked
968 * around by setting 4K granularity.
969 */
970 if (sscreen->info.family == CHIP_HAWAII) {
971 sscreen->tess_offchip_block_dw_size = 4096;
972 offchip_granularity = V_03093C_X_4K_DWORDS;
973 } else {
974 sscreen->tess_offchip_block_dw_size = 8192;
975 offchip_granularity = V_03093C_X_8K_DWORDS;
976 }
977
978 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
979 assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
980 sscreen->tess_offchip_ring_size = max_offchip_buffers *
981 sscreen->tess_offchip_block_dw_size * 4;
982
983 if (sscreen->info.chip_class >= CIK) {
984 if (sscreen->info.chip_class >= VI)
985 --max_offchip_buffers;
986 sscreen->vgt_hs_offchip_param =
987 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
988 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
989 } else {
990 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
991 sscreen->vgt_hs_offchip_param =
992 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
993 }
994
995 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
996 * on SI. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
997 * SPI_VS_OUT_CONFIG. So only enable CI CLEAR_STATE on amdgpu kernel.*/
998 sscreen->has_clear_state = sscreen->info.chip_class >= CIK &&
999 sscreen->info.drm_major == 3;
1000
1001 sscreen->has_distributed_tess =
1002 sscreen->info.chip_class >= VI &&
1003 sscreen->info.max_se >= 2;
1004
1005 sscreen->has_draw_indirect_multi =
1006 (sscreen->info.family >= CHIP_POLARIS10) ||
1007 (sscreen->info.chip_class == VI &&
1008 sscreen->info.pfp_fw_version >= 121 &&
1009 sscreen->info.me_fw_version >= 87) ||
1010 (sscreen->info.chip_class == CIK &&
1011 sscreen->info.pfp_fw_version >= 211 &&
1012 sscreen->info.me_fw_version >= 173) ||
1013 (sscreen->info.chip_class == SI &&
1014 sscreen->info.pfp_fw_version >= 79 &&
1015 sscreen->info.me_fw_version >= 142);
1016
1017 sscreen->has_out_of_order_rast = sscreen->info.chip_class >= VI &&
1018 sscreen->info.max_se >= 2 &&
1019 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1020 sscreen->assume_no_z_fights =
1021 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1022 sscreen->commutative_blend_add =
1023 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1024 sscreen->clear_db_cache_before_clear =
1025 driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
1026 sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
1027 sscreen->info.family <= CHIP_POLARIS12) ||
1028 sscreen->info.family == CHIP_VEGA10 ||
1029 sscreen->info.family == CHIP_RAVEN;
1030 sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
1031 sscreen->info.family == CHIP_RAVEN;
1032 sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2;
1033
1034 /* Only enable primitive binning on APUs by default. */
1035 sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN ||
1036 sscreen->info.family == CHIP_RAVEN2;
1037
1038 sscreen->dfsm_allowed = sscreen->info.family == CHIP_RAVEN ||
1039 sscreen->info.family == CHIP_RAVEN2;
1040
1041 /* Process DPBB enable flags. */
1042 if (sscreen->debug_flags & DBG(DPBB)) {
1043 sscreen->dpbb_allowed = true;
1044 if (sscreen->debug_flags & DBG(DFSM))
1045 sscreen->dfsm_allowed = true;
1046 }
1047
1048 /* Process DPBB disable flags. */
1049 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1050 sscreen->dpbb_allowed = false;
1051 sscreen->dfsm_allowed = false;
1052 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1053 sscreen->dfsm_allowed = false;
1054 }
1055
1056 /* While it would be nice not to have this flag, we are constrained
1057 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1058 * on GFX9.
1059 */
1060 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= VI;
1061
1062 /* Some chips have RB+ registers, but don't support RB+. Those must
1063 * always disable it.
1064 */
1065 if (sscreen->info.family == CHIP_STONEY ||
1066 sscreen->info.chip_class >= GFX9) {
1067 sscreen->has_rbplus = true;
1068
1069 sscreen->rbplus_allowed =
1070 !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
1071 (sscreen->info.family == CHIP_STONEY ||
1072 sscreen->info.family == CHIP_VEGA12 ||
1073 sscreen->info.family == CHIP_RAVEN ||
1074 sscreen->info.family == CHIP_RAVEN2);
1075 }
1076
1077 sscreen->dcc_msaa_allowed =
1078 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1079
1080 sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= VI;
1081
1082 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1083 sscreen->use_monolithic_shaders =
1084 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1085
1086 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1087 SI_CONTEXT_INV_VMEM_L1;
1088 if (sscreen->info.chip_class <= VI) {
1089 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1090 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1091 }
1092
1093 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1094 sscreen->debug_flags |= DBG_ALL_SHADERS;
1095
1096 /* Syntax:
1097 * EQAA=s,z,c
1098 * Example:
1099 * EQAA=8,4,2
1100
1101 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1102 * Constraints:
1103 * s >= z >= c (ignoring this only wastes memory)
1104 * s = [2..16]
1105 * z = [2..8]
1106 * c = [2..8]
1107 *
1108 * Only MSAA color and depth buffers are overriden.
1109 */
1110 if (sscreen->info.has_eqaa_surface_allocator) {
1111 const char *eqaa = debug_get_option("EQAA", NULL);
1112 unsigned s,z,f;
1113
1114 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1115 sscreen->eqaa_force_coverage_samples = s;
1116 sscreen->eqaa_force_z_samples = z;
1117 sscreen->eqaa_force_color_samples = f;
1118 }
1119 }
1120
1121 for (i = 0; i < num_comp_hi_threads; i++)
1122 si_init_compiler(sscreen, &sscreen->compiler[i]);
1123 for (i = 0; i < num_comp_lo_threads; i++)
1124 si_init_compiler(sscreen, &sscreen->compiler_lowp[i]);
1125
1126 /* Create the auxiliary context. This must be done last. */
1127 sscreen->aux_context = si_create_context(&sscreen->b, 0);
1128
1129 if (sscreen->debug_flags & DBG(TEST_DMA))
1130 si_test_dma(sscreen);
1131
1132 if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) {
1133 si_test_dma_perf(sscreen);
1134 }
1135
1136 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1137 DBG(TEST_VMFAULT_SDMA) |
1138 DBG(TEST_VMFAULT_SHADER)))
1139 si_test_vmfault(sscreen);
1140
1141 if (sscreen->debug_flags & DBG(TEST_GDS))
1142 si_test_gds((struct si_context*)sscreen->aux_context);
1143
1144 if (sscreen->debug_flags & DBG(TEST_GDS_MM)) {
1145 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1146 32 * 1024, 4, RADEON_DOMAIN_GDS);
1147 }
1148 if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) {
1149 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1150 4, 1, RADEON_DOMAIN_OA);
1151 }
1152
1153 return &sscreen->b;
1154 }