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radeonsi: clean up winsys creation
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25
26 #include "si_pipe.h"
27 #include "si_public.h"
28 #include "si_shader_internal.h"
29 #include "si_compute.h"
30 #include "sid.h"
31
32 #include "ac_llvm_util.h"
33 #include "radeon/radeon_uvd.h"
34 #include "gallivm/lp_bld_misc.h"
35 #include "util/disk_cache.h"
36 #include "util/u_log.h"
37 #include "util/u_memory.h"
38 #include "util/u_suballoc.h"
39 #include "util/u_tests.h"
40 #include "util/u_upload_mgr.h"
41 #include "util/xmlconfig.h"
42 #include "vl/vl_decoder.h"
43 #include "driver_ddebug/dd_util.h"
44
45 #include "gallium/winsys/radeon/drm/radeon_drm_public.h"
46 #include "gallium/winsys/amdgpu/drm/amdgpu_public.h"
47 #include <xf86drm.h>
48
49 static const struct debug_named_value debug_options[] = {
50 /* Shader logging options: */
51 { "vs", DBG(VS), "Print vertex shaders" },
52 { "ps", DBG(PS), "Print pixel shaders" },
53 { "gs", DBG(GS), "Print geometry shaders" },
54 { "tcs", DBG(TCS), "Print tessellation control shaders" },
55 { "tes", DBG(TES), "Print tessellation evaluation shaders" },
56 { "cs", DBG(CS), "Print compute shaders" },
57 { "noir", DBG(NO_IR), "Don't print the LLVM IR"},
58 { "notgsi", DBG(NO_TGSI), "Don't print the TGSI"},
59 { "noasm", DBG(NO_ASM), "Don't print disassembled shaders"},
60 { "preoptir", DBG(PREOPT_IR), "Print the LLVM IR before initial optimizations" },
61
62 /* Shader compiler options the shader cache should be aware of: */
63 { "unsafemath", DBG(UNSAFE_MATH), "Enable unsafe math shader optimizations" },
64 { "sisched", DBG(SI_SCHED), "Enable LLVM SI Machine Instruction Scheduler." },
65 { "gisel", DBG(GISEL), "Enable LLVM global instruction selector." },
66
67 /* Shader compiler options (with no effect on the shader cache): */
68 { "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
69 { "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
70 { "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
71
72 /* Information logging options: */
73 { "info", DBG(INFO), "Print driver information" },
74 { "tex", DBG(TEX), "Print texture info" },
75 { "compute", DBG(COMPUTE), "Print compute info" },
76 { "vm", DBG(VM), "Print virtual addresses when creating resources" },
77
78 /* Driver options: */
79 { "forcedma", DBG(FORCE_DMA), "Use asynchronous DMA for all operations when possible." },
80 { "nodma", DBG(NO_ASYNC_DMA), "Disable asynchronous DMA" },
81 { "nowc", DBG(NO_WC), "Disable GTT write combining" },
82 { "check_vm", DBG(CHECK_VM), "Check VM faults and dump debug info." },
83 { "reserve_vmid", DBG(RESERVE_VMID), "Force VMID reservation per context." },
84 { "zerovram", DBG(ZERO_VRAM), "Clear VRAM allocations." },
85
86 /* 3D engine options: */
87 { "alwayspd", DBG(ALWAYS_PD), "Always enable the primitive discard compute shader." },
88 { "pd", DBG(PD), "Enable the primitive discard compute shader for large draw calls." },
89 { "nopd", DBG(NO_PD), "Disable the primitive discard compute shader." },
90 { "switch_on_eop", DBG(SWITCH_ON_EOP), "Program WD/IA to switch on end-of-packet." },
91 { "nooutoforder", DBG(NO_OUT_OF_ORDER), "Disable out-of-order rasterization" },
92 { "nodpbb", DBG(NO_DPBB), "Disable DPBB." },
93 { "nodfsm", DBG(NO_DFSM), "Disable DFSM." },
94 { "dpbb", DBG(DPBB), "Enable DPBB." },
95 { "dfsm", DBG(DFSM), "Enable DFSM." },
96 { "nohyperz", DBG(NO_HYPERZ), "Disable Hyper-Z" },
97 { "norbplus", DBG(NO_RB_PLUS), "Disable RB+." },
98 { "no2d", DBG(NO_2D_TILING), "Disable 2D tiling" },
99 { "notiling", DBG(NO_TILING), "Disable tiling" },
100 { "nodcc", DBG(NO_DCC), "Disable DCC." },
101 { "nodccclear", DBG(NO_DCC_CLEAR), "Disable DCC fast clear." },
102 { "nodccfb", DBG(NO_DCC_FB), "Disable separate DCC on the main framebuffer" },
103 { "nodccmsaa", DBG(NO_DCC_MSAA), "Disable DCC for MSAA" },
104 { "nofmask", DBG(NO_FMASK), "Disable MSAA compression" },
105
106 /* Tests: */
107 { "testdma", DBG(TEST_DMA), "Invoke SDMA tests and exit." },
108 { "testvmfaultcp", DBG(TEST_VMFAULT_CP), "Invoke a CP VM fault test and exit." },
109 { "testvmfaultsdma", DBG(TEST_VMFAULT_SDMA), "Invoke a SDMA VM fault test and exit." },
110 { "testvmfaultshader", DBG(TEST_VMFAULT_SHADER), "Invoke a shader VM fault test and exit." },
111 { "testdmaperf", DBG(TEST_DMA_PERF), "Test DMA performance" },
112 { "testgds", DBG(TEST_GDS), "Test GDS." },
113 { "testgdsmm", DBG(TEST_GDS_MM), "Test GDS memory management." },
114 { "testgdsoamm", DBG(TEST_GDS_OA_MM), "Test GDS OA memory management." },
115
116 DEBUG_NAMED_VALUE_END /* must be last */
117 };
118
119 static void si_init_compiler(struct si_screen *sscreen,
120 struct ac_llvm_compiler *compiler)
121 {
122 /* Only create the less-optimizing version of the compiler on APUs
123 * predating Ryzen (Raven). */
124 bool create_low_opt_compiler = !sscreen->info.has_dedicated_vram &&
125 sscreen->info.chip_class <= GFX8;
126
127 enum ac_target_machine_options tm_options =
128 (sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
129 (sscreen->debug_flags & DBG(GISEL) ? AC_TM_ENABLE_GLOBAL_ISEL : 0) |
130 (sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
131 (sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
132 (!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
133 (sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0) |
134 (create_low_opt_compiler ? AC_TM_CREATE_LOW_OPT : 0);
135
136 ac_init_llvm_once();
137 ac_init_llvm_compiler(compiler, sscreen->info.family, tm_options);
138 compiler->passes = ac_create_llvm_passes(compiler->tm);
139
140 if (compiler->low_opt_tm)
141 compiler->low_opt_passes = ac_create_llvm_passes(compiler->low_opt_tm);
142 }
143
144 static void si_destroy_compiler(struct ac_llvm_compiler *compiler)
145 {
146 ac_destroy_llvm_passes(compiler->passes);
147 ac_destroy_llvm_passes(compiler->low_opt_passes);
148 ac_destroy_llvm_compiler(compiler);
149 }
150
151 /*
152 * pipe_context
153 */
154 static void si_destroy_context(struct pipe_context *context)
155 {
156 struct si_context *sctx = (struct si_context *)context;
157 int i;
158
159 util_queue_finish(&sctx->screen->shader_compiler_queue);
160 util_queue_finish(&sctx->screen->shader_compiler_queue_low_priority);
161
162 /* Unreference the framebuffer normally to disable related logic
163 * properly.
164 */
165 struct pipe_framebuffer_state fb = {};
166 if (context->set_framebuffer_state)
167 context->set_framebuffer_state(context, &fb);
168
169 si_release_all_descriptors(sctx);
170
171 pipe_resource_reference(&sctx->esgs_ring, NULL);
172 pipe_resource_reference(&sctx->gsvs_ring, NULL);
173 pipe_resource_reference(&sctx->tess_rings, NULL);
174 pipe_resource_reference(&sctx->null_const_buf.buffer, NULL);
175 pipe_resource_reference(&sctx->sample_pos_buffer, NULL);
176 si_resource_reference(&sctx->border_color_buffer, NULL);
177 free(sctx->border_color_table);
178 si_resource_reference(&sctx->scratch_buffer, NULL);
179 si_resource_reference(&sctx->compute_scratch_buffer, NULL);
180 si_resource_reference(&sctx->wait_mem_scratch, NULL);
181
182 si_pm4_free_state(sctx, sctx->init_config, ~0);
183 if (sctx->init_config_gs_rings)
184 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
185 for (i = 0; i < ARRAY_SIZE(sctx->vgt_shader_config); i++)
186 si_pm4_delete_state(sctx, vgt_shader_config, sctx->vgt_shader_config[i]);
187
188 if (sctx->fixed_func_tcs_shader.cso)
189 sctx->b.delete_tcs_state(&sctx->b, sctx->fixed_func_tcs_shader.cso);
190 if (sctx->custom_dsa_flush)
191 sctx->b.delete_depth_stencil_alpha_state(&sctx->b, sctx->custom_dsa_flush);
192 if (sctx->custom_blend_resolve)
193 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_resolve);
194 if (sctx->custom_blend_fmask_decompress)
195 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_fmask_decompress);
196 if (sctx->custom_blend_eliminate_fastclear)
197 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_eliminate_fastclear);
198 if (sctx->custom_blend_dcc_decompress)
199 sctx->b.delete_blend_state(&sctx->b, sctx->custom_blend_dcc_decompress);
200 if (sctx->vs_blit_pos)
201 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos);
202 if (sctx->vs_blit_pos_layered)
203 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_pos_layered);
204 if (sctx->vs_blit_color)
205 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color);
206 if (sctx->vs_blit_color_layered)
207 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_color_layered);
208 if (sctx->vs_blit_texcoord)
209 sctx->b.delete_vs_state(&sctx->b, sctx->vs_blit_texcoord);
210 if (sctx->cs_clear_buffer)
211 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_buffer);
212 if (sctx->cs_copy_buffer)
213 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_buffer);
214 if (sctx->cs_copy_image)
215 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image);
216 if (sctx->cs_copy_image_1d_array)
217 sctx->b.delete_compute_state(&sctx->b, sctx->cs_copy_image_1d_array);
218 if (sctx->cs_clear_render_target)
219 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target);
220 if (sctx->cs_clear_render_target_1d_array)
221 sctx->b.delete_compute_state(&sctx->b, sctx->cs_clear_render_target_1d_array);
222 if (sctx->cs_dcc_retile)
223 sctx->b.delete_compute_state(&sctx->b, sctx->cs_dcc_retile);
224
225 if (sctx->blitter)
226 util_blitter_destroy(sctx->blitter);
227
228 /* Release DCC stats. */
229 for (int i = 0; i < ARRAY_SIZE(sctx->dcc_stats); i++) {
230 assert(!sctx->dcc_stats[i].query_active);
231
232 for (int j = 0; j < ARRAY_SIZE(sctx->dcc_stats[i].ps_stats); j++)
233 if (sctx->dcc_stats[i].ps_stats[j])
234 sctx->b.destroy_query(&sctx->b,
235 sctx->dcc_stats[i].ps_stats[j]);
236
237 si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
238 }
239
240 if (sctx->query_result_shader)
241 sctx->b.delete_compute_state(&sctx->b, sctx->query_result_shader);
242
243 if (sctx->gfx_cs)
244 sctx->ws->cs_destroy(sctx->gfx_cs);
245 if (sctx->dma_cs)
246 sctx->ws->cs_destroy(sctx->dma_cs);
247 if (sctx->ctx)
248 sctx->ws->ctx_destroy(sctx->ctx);
249
250 if (sctx->b.stream_uploader)
251 u_upload_destroy(sctx->b.stream_uploader);
252 if (sctx->b.const_uploader)
253 u_upload_destroy(sctx->b.const_uploader);
254 if (sctx->cached_gtt_allocator)
255 u_upload_destroy(sctx->cached_gtt_allocator);
256
257 slab_destroy_child(&sctx->pool_transfers);
258 slab_destroy_child(&sctx->pool_transfers_unsync);
259
260 if (sctx->allocator_zeroed_memory)
261 u_suballocator_destroy(sctx->allocator_zeroed_memory);
262
263 sctx->ws->fence_reference(&sctx->last_gfx_fence, NULL);
264 sctx->ws->fence_reference(&sctx->last_sdma_fence, NULL);
265 sctx->ws->fence_reference(&sctx->last_ib_barrier_fence, NULL);
266 si_resource_reference(&sctx->eop_bug_scratch, NULL);
267 si_resource_reference(&sctx->index_ring, NULL);
268 si_resource_reference(&sctx->barrier_buf, NULL);
269 si_resource_reference(&sctx->last_ib_barrier_buf, NULL);
270 pb_reference(&sctx->gds, NULL);
271 pb_reference(&sctx->gds_oa, NULL);
272
273 si_destroy_compiler(&sctx->compiler);
274
275 si_saved_cs_reference(&sctx->current_saved_cs, NULL);
276
277 _mesa_hash_table_destroy(sctx->tex_handles, NULL);
278 _mesa_hash_table_destroy(sctx->img_handles, NULL);
279
280 util_dynarray_fini(&sctx->resident_tex_handles);
281 util_dynarray_fini(&sctx->resident_img_handles);
282 util_dynarray_fini(&sctx->resident_tex_needs_color_decompress);
283 util_dynarray_fini(&sctx->resident_img_needs_color_decompress);
284 util_dynarray_fini(&sctx->resident_tex_needs_depth_decompress);
285 si_unref_sdma_uploads(sctx);
286 FREE(sctx);
287 }
288
289 static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
290 {
291 struct si_context *sctx = (struct si_context *)ctx;
292
293 return sctx->ws->ctx_query_reset_status(sctx->ctx);
294 }
295
296 static void si_set_device_reset_callback(struct pipe_context *ctx,
297 const struct pipe_device_reset_callback *cb)
298 {
299 struct si_context *sctx = (struct si_context *)ctx;
300
301 if (cb)
302 sctx->device_reset_callback = *cb;
303 else
304 memset(&sctx->device_reset_callback, 0,
305 sizeof(sctx->device_reset_callback));
306 }
307
308 bool si_check_device_reset(struct si_context *sctx)
309 {
310 enum pipe_reset_status status;
311
312 if (!sctx->device_reset_callback.reset)
313 return false;
314
315 status = sctx->ws->ctx_query_reset_status(sctx->ctx);
316 if (status == PIPE_NO_RESET)
317 return false;
318
319 sctx->device_reset_callback.reset(sctx->device_reset_callback.data, status);
320 return true;
321 }
322
323 /* Apitrace profiling:
324 * 1) qapitrace : Tools -> Profile: Measure CPU & GPU times
325 * 2) In the middle panel, zoom in (mouse wheel) on some bad draw call
326 * and remember its number.
327 * 3) In Mesa, enable queries and performance counters around that draw
328 * call and print the results.
329 * 4) glretrace --benchmark --markers ..
330 */
331 static void si_emit_string_marker(struct pipe_context *ctx,
332 const char *string, int len)
333 {
334 struct si_context *sctx = (struct si_context *)ctx;
335
336 dd_parse_apitrace_marker(string, len, &sctx->apitrace_call_number);
337
338 if (sctx->log)
339 u_log_printf(sctx->log, "\nString marker: %*s\n", len, string);
340 }
341
342 static void si_set_debug_callback(struct pipe_context *ctx,
343 const struct pipe_debug_callback *cb)
344 {
345 struct si_context *sctx = (struct si_context *)ctx;
346 struct si_screen *screen = sctx->screen;
347
348 util_queue_finish(&screen->shader_compiler_queue);
349 util_queue_finish(&screen->shader_compiler_queue_low_priority);
350
351 if (cb)
352 sctx->debug = *cb;
353 else
354 memset(&sctx->debug, 0, sizeof(sctx->debug));
355 }
356
357 static void si_set_log_context(struct pipe_context *ctx,
358 struct u_log_context *log)
359 {
360 struct si_context *sctx = (struct si_context *)ctx;
361 sctx->log = log;
362
363 if (log)
364 u_log_add_auto_logger(log, si_auto_log_cs, sctx);
365 }
366
367 static void si_set_context_param(struct pipe_context *ctx,
368 enum pipe_context_param param,
369 unsigned value)
370 {
371 struct radeon_winsys *ws = ((struct si_context *)ctx)->ws;
372
373 switch (param) {
374 case PIPE_CONTEXT_PARAM_PIN_THREADS_TO_L3_CACHE:
375 ws->pin_threads_to_L3_cache(ws, value);
376 break;
377 default:;
378 }
379 }
380
381 static struct pipe_context *si_create_context(struct pipe_screen *screen,
382 unsigned flags)
383 {
384 struct si_context *sctx = CALLOC_STRUCT(si_context);
385 struct si_screen* sscreen = (struct si_screen *)screen;
386 struct radeon_winsys *ws = sscreen->ws;
387 int shader, i;
388 bool stop_exec_on_failure = (flags & PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET) != 0;
389
390 if (!sctx)
391 return NULL;
392
393 sctx->has_graphics = sscreen->info.chip_class == GFX6 ||
394 !(flags & PIPE_CONTEXT_COMPUTE_ONLY);
395
396 if (flags & PIPE_CONTEXT_DEBUG)
397 sscreen->record_llvm_ir = true; /* racy but not critical */
398
399 sctx->b.screen = screen; /* this must be set first */
400 sctx->b.priv = NULL;
401 sctx->b.destroy = si_destroy_context;
402 sctx->screen = sscreen; /* Easy accessing of screen/winsys. */
403 sctx->is_debug = (flags & PIPE_CONTEXT_DEBUG) != 0;
404
405 slab_create_child(&sctx->pool_transfers, &sscreen->pool_transfers);
406 slab_create_child(&sctx->pool_transfers_unsync, &sscreen->pool_transfers);
407
408 sctx->ws = sscreen->ws;
409 sctx->family = sscreen->info.family;
410 sctx->chip_class = sscreen->info.chip_class;
411
412 if (sctx->chip_class == GFX7 ||
413 sctx->chip_class == GFX8 ||
414 sctx->chip_class == GFX9) {
415 sctx->eop_bug_scratch = si_resource(
416 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
417 16 * sscreen->info.num_render_backends));
418 if (!sctx->eop_bug_scratch)
419 goto fail;
420 }
421
422 /* Initialize context allocators. */
423 sctx->allocator_zeroed_memory =
424 u_suballocator_create(&sctx->b, 128 * 1024,
425 0, PIPE_USAGE_DEFAULT,
426 SI_RESOURCE_FLAG_UNMAPPABLE |
427 SI_RESOURCE_FLAG_CLEAR, false);
428 if (!sctx->allocator_zeroed_memory)
429 goto fail;
430
431 sctx->b.stream_uploader = u_upload_create(&sctx->b, 1024 * 1024,
432 0, PIPE_USAGE_STREAM,
433 SI_RESOURCE_FLAG_READ_ONLY);
434 if (!sctx->b.stream_uploader)
435 goto fail;
436
437 sctx->cached_gtt_allocator = u_upload_create(&sctx->b, 16 * 1024,
438 0, PIPE_USAGE_STAGING, 0);
439 if (!sctx->cached_gtt_allocator)
440 goto fail;
441
442 sctx->ctx = sctx->ws->ctx_create(sctx->ws);
443 if (!sctx->ctx)
444 goto fail;
445
446 if (sscreen->info.num_sdma_rings && !(sscreen->debug_flags & DBG(NO_ASYNC_DMA))) {
447 sctx->dma_cs = sctx->ws->cs_create(sctx->ctx, RING_DMA,
448 (void*)si_flush_dma_cs,
449 sctx, stop_exec_on_failure);
450 }
451
452 bool use_sdma_upload = sscreen->info.has_dedicated_vram && sctx->dma_cs;
453 sctx->b.const_uploader = u_upload_create(&sctx->b, 256 * 1024,
454 0, PIPE_USAGE_DEFAULT,
455 SI_RESOURCE_FLAG_32BIT |
456 (use_sdma_upload ?
457 SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA :
458 (sscreen->cpdma_prefetch_writes_memory ?
459 0 : SI_RESOURCE_FLAG_READ_ONLY)));
460 if (!sctx->b.const_uploader)
461 goto fail;
462
463 if (use_sdma_upload)
464 u_upload_enable_flush_explicit(sctx->b.const_uploader);
465
466 sctx->gfx_cs = ws->cs_create(sctx->ctx,
467 sctx->has_graphics ? RING_GFX : RING_COMPUTE,
468 (void*)si_flush_gfx_cs, sctx, stop_exec_on_failure);
469
470 /* Border colors. */
471 sctx->border_color_table = malloc(SI_MAX_BORDER_COLORS *
472 sizeof(*sctx->border_color_table));
473 if (!sctx->border_color_table)
474 goto fail;
475
476 sctx->border_color_buffer = si_resource(
477 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT,
478 SI_MAX_BORDER_COLORS *
479 sizeof(*sctx->border_color_table)));
480 if (!sctx->border_color_buffer)
481 goto fail;
482
483 sctx->border_color_map =
484 ws->buffer_map(sctx->border_color_buffer->buf,
485 NULL, PIPE_TRANSFER_WRITE);
486 if (!sctx->border_color_map)
487 goto fail;
488
489 /* Initialize context functions used by graphics and compute. */
490 sctx->b.emit_string_marker = si_emit_string_marker;
491 sctx->b.set_debug_callback = si_set_debug_callback;
492 sctx->b.set_log_context = si_set_log_context;
493 sctx->b.set_context_param = si_set_context_param;
494 sctx->b.get_device_reset_status = si_get_reset_status;
495 sctx->b.set_device_reset_callback = si_set_device_reset_callback;
496
497 si_init_all_descriptors(sctx);
498 si_init_buffer_functions(sctx);
499 si_init_clear_functions(sctx);
500 si_init_blit_functions(sctx);
501 si_init_compute_functions(sctx);
502 si_init_compute_blit_functions(sctx);
503 si_init_debug_functions(sctx);
504 si_init_fence_functions(sctx);
505 si_init_query_functions(sctx);
506 si_init_state_compute_functions(sctx);
507
508 if (sscreen->debug_flags & DBG(FORCE_DMA))
509 sctx->b.resource_copy_region = sctx->dma_copy;
510
511 /* Initialize graphics-only context functions. */
512 if (sctx->has_graphics) {
513 si_init_context_texture_functions(sctx);
514 si_init_msaa_functions(sctx);
515 si_init_shader_functions(sctx);
516 si_init_state_functions(sctx);
517 si_init_streamout_functions(sctx);
518 si_init_viewport_functions(sctx);
519
520 sctx->blitter = util_blitter_create(&sctx->b);
521 if (sctx->blitter == NULL)
522 goto fail;
523 sctx->blitter->skip_viewport_restore = true;
524
525 si_init_draw_functions(sctx);
526 si_initialize_prim_discard_tunables(sctx);
527 }
528
529 /* Initialize SDMA functions. */
530 if (sctx->chip_class >= GFX7)
531 cik_init_sdma_functions(sctx);
532 else
533 si_init_dma_functions(sctx);
534
535 sctx->sample_mask = 0xffff;
536
537 /* Initialize multimedia functions. */
538 if (sscreen->info.has_hw_decode) {
539 sctx->b.create_video_codec = si_uvd_create_decoder;
540 sctx->b.create_video_buffer = si_video_buffer_create;
541 } else {
542 sctx->b.create_video_codec = vl_create_decoder;
543 sctx->b.create_video_buffer = vl_video_buffer_create;
544 }
545
546 if (sctx->chip_class >= GFX9) {
547 sctx->wait_mem_scratch = si_resource(
548 pipe_buffer_create(screen, 0, PIPE_USAGE_DEFAULT, 8));
549 if (!sctx->wait_mem_scratch)
550 goto fail;
551
552 /* Initialize the memory. */
553 si_cp_write_data(sctx, sctx->wait_mem_scratch, 0, 4,
554 V_370_MEM, V_370_ME, &sctx->wait_mem_number);
555 }
556
557 /* GFX7 cannot unbind a constant buffer (S_BUFFER_LOAD doesn't skip loads
558 * if NUM_RECORDS == 0). We need to use a dummy buffer instead. */
559 if (sctx->chip_class == GFX7) {
560 sctx->null_const_buf.buffer =
561 pipe_aligned_buffer_create(screen,
562 SI_RESOURCE_FLAG_32BIT,
563 PIPE_USAGE_DEFAULT, 16,
564 sctx->screen->info.tcc_cache_line_size);
565 if (!sctx->null_const_buf.buffer)
566 goto fail;
567 sctx->null_const_buf.buffer_size = sctx->null_const_buf.buffer->width0;
568
569 unsigned start_shader = sctx->has_graphics ? 0 : PIPE_SHADER_COMPUTE;
570 for (shader = start_shader; shader < SI_NUM_SHADERS; shader++) {
571 for (i = 0; i < SI_NUM_CONST_BUFFERS; i++) {
572 sctx->b.set_constant_buffer(&sctx->b, shader, i,
573 &sctx->null_const_buf);
574 }
575 }
576
577 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS,
578 &sctx->null_const_buf);
579 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS,
580 &sctx->null_const_buf);
581 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES,
582 &sctx->null_const_buf);
583 si_set_rw_buffer(sctx, SI_PS_CONST_POLY_STIPPLE,
584 &sctx->null_const_buf);
585 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS,
586 &sctx->null_const_buf);
587 }
588
589 uint64_t max_threads_per_block;
590 screen->get_compute_param(screen, PIPE_SHADER_IR_TGSI,
591 PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK,
592 &max_threads_per_block);
593
594 /* The maximum number of scratch waves. Scratch space isn't divided
595 * evenly between CUs. The number is only a function of the number of CUs.
596 * We can decrease the constant to decrease the scratch buffer size.
597 *
598 * sctx->scratch_waves must be >= the maximum posible size of
599 * 1 threadgroup, so that the hw doesn't hang from being unable
600 * to start any.
601 *
602 * The recommended value is 4 per CU at most. Higher numbers don't
603 * bring much benefit, but they still occupy chip resources (think
604 * async compute). I've seen ~2% performance difference between 4 and 32.
605 */
606 sctx->scratch_waves = MAX2(32 * sscreen->info.num_good_compute_units,
607 max_threads_per_block / 64);
608
609 si_init_compiler(sscreen, &sctx->compiler);
610
611 /* Bindless handles. */
612 sctx->tex_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
613 _mesa_key_pointer_equal);
614 sctx->img_handles = _mesa_hash_table_create(NULL, _mesa_hash_pointer,
615 _mesa_key_pointer_equal);
616
617 util_dynarray_init(&sctx->resident_tex_handles, NULL);
618 util_dynarray_init(&sctx->resident_img_handles, NULL);
619 util_dynarray_init(&sctx->resident_tex_needs_color_decompress, NULL);
620 util_dynarray_init(&sctx->resident_img_needs_color_decompress, NULL);
621 util_dynarray_init(&sctx->resident_tex_needs_depth_decompress, NULL);
622
623 sctx->sample_pos_buffer =
624 pipe_buffer_create(sctx->b.screen, 0, PIPE_USAGE_DEFAULT,
625 sizeof(sctx->sample_positions));
626 pipe_buffer_write(&sctx->b, sctx->sample_pos_buffer, 0,
627 sizeof(sctx->sample_positions), &sctx->sample_positions);
628
629 /* this must be last */
630 si_begin_new_gfx_cs(sctx);
631
632 if (sctx->chip_class == GFX7) {
633 /* Clear the NULL constant buffer, because loads should return zeros.
634 * Note that this forces CP DMA to be used, because clover deadlocks
635 * for some reason when the compute codepath is used.
636 */
637 uint32_t clear_value = 0;
638 si_clear_buffer(sctx, sctx->null_const_buf.buffer, 0,
639 sctx->null_const_buf.buffer->width0,
640 &clear_value, 4, SI_COHERENCY_SHADER, true);
641 }
642 return &sctx->b;
643 fail:
644 fprintf(stderr, "radeonsi: Failed to create a context.\n");
645 si_destroy_context(&sctx->b);
646 return NULL;
647 }
648
649 static struct pipe_context *si_pipe_create_context(struct pipe_screen *screen,
650 void *priv, unsigned flags)
651 {
652 struct si_screen *sscreen = (struct si_screen *)screen;
653 struct pipe_context *ctx;
654
655 if (sscreen->debug_flags & DBG(CHECK_VM))
656 flags |= PIPE_CONTEXT_DEBUG;
657
658 ctx = si_create_context(screen, flags);
659
660 if (!(flags & PIPE_CONTEXT_PREFER_THREADED))
661 return ctx;
662
663 /* Clover (compute-only) is unsupported. */
664 if (flags & PIPE_CONTEXT_COMPUTE_ONLY)
665 return ctx;
666
667 /* When shaders are logged to stderr, asynchronous compilation is
668 * disabled too. */
669 if (sscreen->debug_flags & DBG_ALL_SHADERS)
670 return ctx;
671
672 /* Use asynchronous flushes only on amdgpu, since the radeon
673 * implementation for fence_server_sync is incomplete. */
674 return threaded_context_create(ctx, &sscreen->pool_transfers,
675 si_replace_buffer_storage,
676 sscreen->info.drm_major >= 3 ? si_create_fence : NULL,
677 &((struct si_context*)ctx)->tc);
678 }
679
680 /*
681 * pipe_screen
682 */
683 static void si_destroy_screen(struct pipe_screen* pscreen)
684 {
685 struct si_screen *sscreen = (struct si_screen *)pscreen;
686 struct si_shader_part *parts[] = {
687 sscreen->vs_prologs,
688 sscreen->tcs_epilogs,
689 sscreen->gs_prologs,
690 sscreen->ps_prologs,
691 sscreen->ps_epilogs
692 };
693 unsigned i;
694
695 if (!sscreen->ws->unref(sscreen->ws))
696 return;
697
698 mtx_destroy(&sscreen->aux_context_lock);
699
700 struct u_log_context *aux_log = ((struct si_context *)sscreen->aux_context)->log;
701 if (aux_log) {
702 sscreen->aux_context->set_log_context(sscreen->aux_context, NULL);
703 u_log_context_destroy(aux_log);
704 FREE(aux_log);
705 }
706
707 sscreen->aux_context->destroy(sscreen->aux_context);
708
709 util_queue_destroy(&sscreen->shader_compiler_queue);
710 util_queue_destroy(&sscreen->shader_compiler_queue_low_priority);
711
712 for (i = 0; i < ARRAY_SIZE(sscreen->compiler); i++)
713 si_destroy_compiler(&sscreen->compiler[i]);
714
715 for (i = 0; i < ARRAY_SIZE(sscreen->compiler_lowp); i++)
716 si_destroy_compiler(&sscreen->compiler_lowp[i]);
717
718 /* Free shader parts. */
719 for (i = 0; i < ARRAY_SIZE(parts); i++) {
720 while (parts[i]) {
721 struct si_shader_part *part = parts[i];
722
723 parts[i] = part->next;
724 ac_shader_binary_clean(&part->binary);
725 FREE(part);
726 }
727 }
728 mtx_destroy(&sscreen->shader_parts_mutex);
729 si_destroy_shader_cache(sscreen);
730
731 si_destroy_perfcounters(sscreen);
732 si_gpu_load_kill_thread(sscreen);
733
734 mtx_destroy(&sscreen->gpu_load_mutex);
735
736 slab_destroy_parent(&sscreen->pool_transfers);
737
738 disk_cache_destroy(sscreen->disk_shader_cache);
739 sscreen->ws->destroy(sscreen->ws);
740 FREE(sscreen);
741 }
742
743 static void si_init_gs_info(struct si_screen *sscreen)
744 {
745 sscreen->gs_table_depth = ac_get_gs_table_depth(sscreen->info.chip_class,
746 sscreen->info.family);
747 }
748
749 static void si_test_vmfault(struct si_screen *sscreen)
750 {
751 struct pipe_context *ctx = sscreen->aux_context;
752 struct si_context *sctx = (struct si_context *)ctx;
753 struct pipe_resource *buf =
754 pipe_buffer_create_const0(&sscreen->b, 0, PIPE_USAGE_DEFAULT, 64);
755
756 if (!buf) {
757 puts("Buffer allocation failed.");
758 exit(1);
759 }
760
761 si_resource(buf)->gpu_address = 0; /* cause a VM fault */
762
763 if (sscreen->debug_flags & DBG(TEST_VMFAULT_CP)) {
764 si_cp_dma_copy_buffer(sctx, buf, buf, 0, 4, 4, 0,
765 SI_COHERENCY_NONE, L2_BYPASS);
766 ctx->flush(ctx, NULL, 0);
767 puts("VM fault test: CP - done.");
768 }
769 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SDMA)) {
770 si_sdma_clear_buffer(sctx, buf, 0, 4, 0);
771 ctx->flush(ctx, NULL, 0);
772 puts("VM fault test: SDMA - done.");
773 }
774 if (sscreen->debug_flags & DBG(TEST_VMFAULT_SHADER)) {
775 util_test_constant_buffer(ctx, buf);
776 puts("VM fault test: Shader - done.");
777 }
778 exit(0);
779 }
780
781 static void si_test_gds_memory_management(struct si_context *sctx,
782 unsigned alloc_size, unsigned alignment,
783 enum radeon_bo_domain domain)
784 {
785 struct radeon_winsys *ws = sctx->ws;
786 struct radeon_cmdbuf *cs[8];
787 struct pb_buffer *gds_bo[ARRAY_SIZE(cs)];
788
789 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
790 cs[i] = ws->cs_create(sctx->ctx, RING_COMPUTE,
791 NULL, NULL, false);
792 gds_bo[i] = ws->buffer_create(ws, alloc_size, alignment, domain, 0);
793 assert(gds_bo[i]);
794 }
795
796 for (unsigned iterations = 0; iterations < 20000; iterations++) {
797 for (unsigned i = 0; i < ARRAY_SIZE(cs); i++) {
798 /* This clears GDS with CP DMA.
799 *
800 * We don't care if GDS is present. Just add some packet
801 * to make the GPU busy for a moment.
802 */
803 si_cp_dma_clear_buffer(sctx, cs[i], NULL, 0, alloc_size, 0,
804 SI_CPDMA_SKIP_BO_LIST_UPDATE |
805 SI_CPDMA_SKIP_CHECK_CS_SPACE |
806 SI_CPDMA_SKIP_GFX_SYNC, 0, 0);
807
808 ws->cs_add_buffer(cs[i], gds_bo[i], domain,
809 RADEON_USAGE_READWRITE, 0);
810 ws->cs_flush(cs[i], PIPE_FLUSH_ASYNC, NULL);
811 }
812 }
813 exit(0);
814 }
815
816 static void si_disk_cache_create(struct si_screen *sscreen)
817 {
818 /* Don't use the cache if shader dumping is enabled. */
819 if (sscreen->debug_flags & DBG_ALL_SHADERS)
820 return;
821
822 struct mesa_sha1 ctx;
823 unsigned char sha1[20];
824 char cache_id[20 * 2 + 1];
825
826 _mesa_sha1_init(&ctx);
827
828 if (!disk_cache_get_function_identifier(si_disk_cache_create, &ctx) ||
829 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo,
830 &ctx))
831 return;
832
833 _mesa_sha1_final(&ctx, sha1);
834 disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
835
836 /* These flags affect shader compilation. */
837 #define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
838 DBG(SI_SCHED) | \
839 DBG(GISEL) | \
840 DBG(UNSAFE_MATH))
841 uint64_t shader_debug_flags = sscreen->debug_flags &
842 ALL_FLAGS;
843
844 /* Add the high bits of 32-bit addresses, which affects
845 * how 32-bit addresses are expanded to 64 bits.
846 */
847 STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
848 assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
849 shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
850
851 if (sscreen->options.enable_nir)
852 shader_debug_flags |= 1ull << 48;
853
854 sscreen->disk_shader_cache =
855 disk_cache_create(sscreen->info.name,
856 cache_id,
857 shader_debug_flags);
858 }
859
860 static void si_set_max_shader_compiler_threads(struct pipe_screen *screen,
861 unsigned max_threads)
862 {
863 struct si_screen *sscreen = (struct si_screen *)screen;
864
865 /* This function doesn't allow a greater number of threads than
866 * the queue had at its creation. */
867 util_queue_adjust_num_threads(&sscreen->shader_compiler_queue,
868 max_threads);
869 /* Don't change the number of threads on the low priority queue. */
870 }
871
872 static bool si_is_parallel_shader_compilation_finished(struct pipe_screen *screen,
873 void *shader,
874 unsigned shader_type)
875 {
876 if (shader_type == PIPE_SHADER_COMPUTE) {
877 struct si_compute *cs = (struct si_compute*)shader;
878
879 return util_queue_fence_is_signalled(&cs->ready);
880 }
881 struct si_shader_selector *sel = (struct si_shader_selector *)shader;
882
883 return util_queue_fence_is_signalled(&sel->ready);
884 }
885
886 static struct pipe_screen *
887 radeonsi_screen_create_impl(struct radeon_winsys *ws,
888 const struct pipe_screen_config *config)
889 {
890 struct si_screen *sscreen = CALLOC_STRUCT(si_screen);
891 unsigned hw_threads, num_comp_hi_threads, num_comp_lo_threads, i;
892
893 if (!sscreen) {
894 return NULL;
895 }
896
897 sscreen->ws = ws;
898 ws->query_info(ws, &sscreen->info);
899
900 if (sscreen->info.chip_class >= GFX9) {
901 sscreen->se_tile_repeat = 32 * sscreen->info.max_se;
902 } else {
903 ac_get_raster_config(&sscreen->info,
904 &sscreen->pa_sc_raster_config,
905 &sscreen->pa_sc_raster_config_1,
906 &sscreen->se_tile_repeat);
907 }
908
909 sscreen->debug_flags = debug_get_flags_option("R600_DEBUG",
910 debug_options, 0);
911 sscreen->debug_flags |= debug_get_flags_option("AMD_DEBUG",
912 debug_options, 0);
913
914 /* Set functions first. */
915 sscreen->b.context_create = si_pipe_create_context;
916 sscreen->b.destroy = si_destroy_screen;
917 sscreen->b.set_max_shader_compiler_threads =
918 si_set_max_shader_compiler_threads;
919 sscreen->b.is_parallel_shader_compilation_finished =
920 si_is_parallel_shader_compilation_finished;
921
922 si_init_screen_get_functions(sscreen);
923 si_init_screen_buffer_functions(sscreen);
924 si_init_screen_fence_functions(sscreen);
925 si_init_screen_state_functions(sscreen);
926 si_init_screen_texture_functions(sscreen);
927 si_init_screen_query_functions(sscreen);
928
929 /* Set these flags in debug_flags early, so that the shader cache takes
930 * them into account.
931 */
932 if (driQueryOptionb(config->options,
933 "glsl_correct_derivatives_after_discard"))
934 sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
935 if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
936 sscreen->debug_flags |= DBG(SI_SCHED);
937
938 if (sscreen->debug_flags & DBG(INFO))
939 ac_print_gpu_info(&sscreen->info);
940
941 slab_create_parent(&sscreen->pool_transfers,
942 sizeof(struct si_transfer), 64);
943
944 sscreen->force_aniso = MIN2(16, debug_get_num_option("R600_TEX_ANISO", -1));
945 if (sscreen->force_aniso == -1) {
946 sscreen->force_aniso = MIN2(16, debug_get_num_option("AMD_TEX_ANISO", -1));
947 }
948
949 if (sscreen->force_aniso >= 0) {
950 printf("radeonsi: Forcing anisotropy filter to %ix\n",
951 /* round down to a power of two */
952 1 << util_logbase2(sscreen->force_aniso));
953 }
954
955 (void) mtx_init(&sscreen->aux_context_lock, mtx_plain);
956 (void) mtx_init(&sscreen->gpu_load_mutex, mtx_plain);
957
958 si_init_gs_info(sscreen);
959 if (!si_init_shader_cache(sscreen)) {
960 FREE(sscreen);
961 return NULL;
962 }
963
964 si_disk_cache_create(sscreen);
965
966 /* Determine the number of shader compiler threads. */
967 hw_threads = sysconf(_SC_NPROCESSORS_ONLN);
968
969 if (hw_threads >= 12) {
970 num_comp_hi_threads = hw_threads * 3 / 4;
971 num_comp_lo_threads = hw_threads / 3;
972 } else if (hw_threads >= 6) {
973 num_comp_hi_threads = hw_threads - 2;
974 num_comp_lo_threads = hw_threads / 2;
975 } else if (hw_threads >= 2) {
976 num_comp_hi_threads = hw_threads - 1;
977 num_comp_lo_threads = hw_threads / 2;
978 } else {
979 num_comp_hi_threads = 1;
980 num_comp_lo_threads = 1;
981 }
982
983 num_comp_hi_threads = MIN2(num_comp_hi_threads,
984 ARRAY_SIZE(sscreen->compiler));
985 num_comp_lo_threads = MIN2(num_comp_lo_threads,
986 ARRAY_SIZE(sscreen->compiler_lowp));
987
988 if (!util_queue_init(&sscreen->shader_compiler_queue, "sh",
989 64, num_comp_hi_threads,
990 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
991 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY)) {
992 si_destroy_shader_cache(sscreen);
993 FREE(sscreen);
994 return NULL;
995 }
996
997 if (!util_queue_init(&sscreen->shader_compiler_queue_low_priority,
998 "shlo",
999 64, num_comp_lo_threads,
1000 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
1001 UTIL_QUEUE_INIT_SET_FULL_THREAD_AFFINITY |
1002 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
1003 si_destroy_shader_cache(sscreen);
1004 FREE(sscreen);
1005 return NULL;
1006 }
1007
1008 if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
1009 si_init_perfcounters(sscreen);
1010
1011 /* Determine tessellation ring info. */
1012 bool double_offchip_buffers = sscreen->info.chip_class >= GFX7 &&
1013 sscreen->info.family != CHIP_CARRIZO &&
1014 sscreen->info.family != CHIP_STONEY;
1015 /* This must be one less than the maximum number due to a hw limitation.
1016 * Various hardware bugs need this.
1017 */
1018 unsigned max_offchip_buffers_per_se;
1019
1020 /* Only certain chips can use the maximum value. */
1021 if (sscreen->info.family == CHIP_VEGA12 ||
1022 sscreen->info.family == CHIP_VEGA20)
1023 max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1024 else
1025 max_offchip_buffers_per_se = double_offchip_buffers ? 127 : 63;
1026
1027 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1028 sscreen->info.max_se;
1029 unsigned offchip_granularity;
1030
1031 /* Hawaii has a bug with offchip buffers > 256 that can be worked
1032 * around by setting 4K granularity.
1033 */
1034 if (sscreen->info.family == CHIP_HAWAII) {
1035 sscreen->tess_offchip_block_dw_size = 4096;
1036 offchip_granularity = V_03093C_X_4K_DWORDS;
1037 } else {
1038 sscreen->tess_offchip_block_dw_size = 8192;
1039 offchip_granularity = V_03093C_X_8K_DWORDS;
1040 }
1041
1042 sscreen->tess_factor_ring_size = 32768 * sscreen->info.max_se;
1043 assert(((sscreen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
1044 sscreen->tess_offchip_ring_size = max_offchip_buffers *
1045 sscreen->tess_offchip_block_dw_size * 4;
1046
1047 if (sscreen->info.chip_class >= GFX7) {
1048 if (sscreen->info.chip_class >= GFX8)
1049 --max_offchip_buffers;
1050 sscreen->vgt_hs_offchip_param =
1051 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1052 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1053 } else {
1054 assert(offchip_granularity == V_03093C_X_8K_DWORDS);
1055 sscreen->vgt_hs_offchip_param =
1056 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1057 }
1058
1059 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
1060 * on GFX6. Some CLEAR_STATE cause asic hang on radeon kernel, etc.
1061 * SPI_VS_OUT_CONFIG. So only enable GFX7 CLEAR_STATE on amdgpu kernel.*/
1062 sscreen->has_clear_state = sscreen->info.chip_class >= GFX7 &&
1063 sscreen->info.drm_major == 3;
1064
1065 sscreen->has_distributed_tess =
1066 sscreen->info.chip_class >= GFX8 &&
1067 sscreen->info.max_se >= 2;
1068
1069 sscreen->has_draw_indirect_multi =
1070 (sscreen->info.family >= CHIP_POLARIS10) ||
1071 (sscreen->info.chip_class == GFX8 &&
1072 sscreen->info.pfp_fw_version >= 121 &&
1073 sscreen->info.me_fw_version >= 87) ||
1074 (sscreen->info.chip_class == GFX7 &&
1075 sscreen->info.pfp_fw_version >= 211 &&
1076 sscreen->info.me_fw_version >= 173) ||
1077 (sscreen->info.chip_class == GFX6 &&
1078 sscreen->info.pfp_fw_version >= 79 &&
1079 sscreen->info.me_fw_version >= 142);
1080
1081 sscreen->has_out_of_order_rast = sscreen->info.chip_class >= GFX8 &&
1082 sscreen->info.max_se >= 2 &&
1083 !(sscreen->debug_flags & DBG(NO_OUT_OF_ORDER));
1084 sscreen->assume_no_z_fights =
1085 driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
1086 sscreen->commutative_blend_add =
1087 driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
1088
1089 {
1090 #define OPT_BOOL(name, dflt, description) \
1091 sscreen->options.name = \
1092 driQueryOptionb(config->options, "radeonsi_"#name);
1093 #include "si_debug_options.h"
1094 }
1095
1096 sscreen->has_gfx9_scissor_bug = sscreen->info.family == CHIP_VEGA10 ||
1097 sscreen->info.family == CHIP_RAVEN;
1098 sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
1099 sscreen->info.family <= CHIP_POLARIS12) ||
1100 sscreen->info.family == CHIP_VEGA10 ||
1101 sscreen->info.family == CHIP_RAVEN;
1102 sscreen->has_ls_vgpr_init_bug = sscreen->info.family == CHIP_VEGA10 ||
1103 sscreen->info.family == CHIP_RAVEN;
1104 sscreen->has_dcc_constant_encode = sscreen->info.family == CHIP_RAVEN2;
1105
1106 /* Only enable primitive binning on APUs by default. */
1107 sscreen->dpbb_allowed = sscreen->info.family == CHIP_RAVEN ||
1108 sscreen->info.family == CHIP_RAVEN2;
1109
1110 sscreen->dfsm_allowed = sscreen->info.family == CHIP_RAVEN ||
1111 sscreen->info.family == CHIP_RAVEN2;
1112
1113 /* Process DPBB enable flags. */
1114 if (sscreen->debug_flags & DBG(DPBB)) {
1115 sscreen->dpbb_allowed = true;
1116 if (sscreen->debug_flags & DBG(DFSM))
1117 sscreen->dfsm_allowed = true;
1118 }
1119
1120 /* Process DPBB disable flags. */
1121 if (sscreen->debug_flags & DBG(NO_DPBB)) {
1122 sscreen->dpbb_allowed = false;
1123 sscreen->dfsm_allowed = false;
1124 } else if (sscreen->debug_flags & DBG(NO_DFSM)) {
1125 sscreen->dfsm_allowed = false;
1126 }
1127
1128 /* While it would be nice not to have this flag, we are constrained
1129 * by the reality that LLVM 5.0 doesn't have working VGPR indexing
1130 * on GFX9.
1131 */
1132 sscreen->llvm_has_working_vgpr_indexing = sscreen->info.chip_class <= GFX8;
1133
1134 /* Some chips have RB+ registers, but don't support RB+. Those must
1135 * always disable it.
1136 */
1137 if (sscreen->info.family == CHIP_STONEY ||
1138 sscreen->info.chip_class >= GFX9) {
1139 sscreen->has_rbplus = true;
1140
1141 sscreen->rbplus_allowed =
1142 !(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
1143 (sscreen->info.family == CHIP_STONEY ||
1144 sscreen->info.family == CHIP_VEGA12 ||
1145 sscreen->info.family == CHIP_RAVEN ||
1146 sscreen->info.family == CHIP_RAVEN2);
1147 }
1148
1149 sscreen->dcc_msaa_allowed =
1150 !(sscreen->debug_flags & DBG(NO_DCC_MSAA));
1151
1152 sscreen->cpdma_prefetch_writes_memory = sscreen->info.chip_class <= GFX8;
1153
1154 (void) mtx_init(&sscreen->shader_parts_mutex, mtx_plain);
1155 sscreen->use_monolithic_shaders =
1156 (sscreen->debug_flags & DBG(MONOLITHIC_SHADERS)) != 0;
1157
1158 sscreen->barrier_flags.cp_to_L2 = SI_CONTEXT_INV_SMEM_L1 |
1159 SI_CONTEXT_INV_VMEM_L1;
1160 if (sscreen->info.chip_class <= GFX8) {
1161 sscreen->barrier_flags.cp_to_L2 |= SI_CONTEXT_INV_GLOBAL_L2;
1162 sscreen->barrier_flags.L2_to_cp |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1163 }
1164
1165 if (debug_get_bool_option("RADEON_DUMP_SHADERS", false))
1166 sscreen->debug_flags |= DBG_ALL_SHADERS;
1167
1168 /* Syntax:
1169 * EQAA=s,z,c
1170 * Example:
1171 * EQAA=8,4,2
1172
1173 * That means 8 coverage samples, 4 Z/S samples, and 2 color samples.
1174 * Constraints:
1175 * s >= z >= c (ignoring this only wastes memory)
1176 * s = [2..16]
1177 * z = [2..8]
1178 * c = [2..8]
1179 *
1180 * Only MSAA color and depth buffers are overriden.
1181 */
1182 if (sscreen->info.has_eqaa_surface_allocator) {
1183 const char *eqaa = debug_get_option("EQAA", NULL);
1184 unsigned s,z,f;
1185
1186 if (eqaa && sscanf(eqaa, "%u,%u,%u", &s, &z, &f) == 3 && s && z && f) {
1187 sscreen->eqaa_force_coverage_samples = s;
1188 sscreen->eqaa_force_z_samples = z;
1189 sscreen->eqaa_force_color_samples = f;
1190 }
1191 }
1192
1193 for (i = 0; i < num_comp_hi_threads; i++)
1194 si_init_compiler(sscreen, &sscreen->compiler[i]);
1195 for (i = 0; i < num_comp_lo_threads; i++)
1196 si_init_compiler(sscreen, &sscreen->compiler_lowp[i]);
1197
1198 /* Create the auxiliary context. This must be done last. */
1199 sscreen->aux_context = si_create_context(
1200 &sscreen->b, sscreen->options.aux_debug ? PIPE_CONTEXT_DEBUG : 0);
1201 if (sscreen->options.aux_debug) {
1202 struct u_log_context *log = CALLOC_STRUCT(u_log_context);
1203 u_log_context_init(log);
1204 sscreen->aux_context->set_log_context(sscreen->aux_context, log);
1205 }
1206
1207 if (sscreen->debug_flags & DBG(TEST_DMA))
1208 si_test_dma(sscreen);
1209
1210 if (sscreen->debug_flags & DBG(TEST_DMA_PERF)) {
1211 si_test_dma_perf(sscreen);
1212 }
1213
1214 if (sscreen->debug_flags & (DBG(TEST_VMFAULT_CP) |
1215 DBG(TEST_VMFAULT_SDMA) |
1216 DBG(TEST_VMFAULT_SHADER)))
1217 si_test_vmfault(sscreen);
1218
1219 if (sscreen->debug_flags & DBG(TEST_GDS))
1220 si_test_gds((struct si_context*)sscreen->aux_context);
1221
1222 if (sscreen->debug_flags & DBG(TEST_GDS_MM)) {
1223 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1224 32 * 1024, 4, RADEON_DOMAIN_GDS);
1225 }
1226 if (sscreen->debug_flags & DBG(TEST_GDS_OA_MM)) {
1227 si_test_gds_memory_management((struct si_context*)sscreen->aux_context,
1228 4, 1, RADEON_DOMAIN_OA);
1229 }
1230
1231 return &sscreen->b;
1232 }
1233
1234 struct pipe_screen *radeonsi_screen_create(int fd, const struct pipe_screen_config *config)
1235 {
1236 drmVersionPtr version = drmGetVersion(fd);
1237 struct radeon_winsys *rw = NULL;
1238
1239 switch (version->version_major) {
1240 case 2:
1241 rw = radeon_drm_winsys_create(fd, config, radeonsi_screen_create_impl);
1242 break;
1243 case 3:
1244 rw = amdgpu_winsys_create(fd, config, radeonsi_screen_create_impl);
1245 break;
1246 }
1247
1248 drmFreeVersion(version);
1249 return rw ? rw->screen : NULL;
1250 }