src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef SI_PIPE_H
  27 #define SI_PIPE_H
  28
  29 #include "si_shader.h"
  30
  31 #ifdef PIPE_ARCH_BIG_ENDIAN
  32 #define SI_BIG_ENDIAN 1
  33 #else
  34 #define SI_BIG_ENDIAN 0
  35 #endif
  36
  37 /* The base vertex and primitive restart can be any number, but we must pick
  38  * one which will mean "unknown" for the purpose of state tracking and
  39  * the number shouldn't be a commonly-used one. */
  40 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  41 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  42 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  43 #define SI_GS_PER_ES 128
  44
  45 /* Instruction cache. */
  46 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  47 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  48 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  49 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  50 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  51 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  52 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  53 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  54  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  55 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (R600_CONTEXT_PRIVATE_FLAG << 4)
  56 /* Framebuffer caches. */
  57 #define SI_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
  58 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 6)
  59 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 7)
  60 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 8)
  61 /* Engine synchronization. */
  62 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  63 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  64 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 11)
  65 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 12)
  66 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 13)
  67
  68 #define SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER (SI_CONTEXT_FLUSH_AND_INV_CB | \
  69                                               SI_CONTEXT_FLUSH_AND_INV_CB_META | \
  70                                               SI_CONTEXT_FLUSH_AND_INV_DB | \
  71                                               SI_CONTEXT_FLUSH_AND_INV_DB_META)
  72
  73 #define SI_ENCODE_TRACE_POINT(id)       (0xcafe0000 | ((id) & 0xffff))
  74 #define SI_IS_TRACE_POINT(x)            (((x) & 0xcafe0000) == 0xcafe0000)
  75 #define SI_GET_TRACE_POINT_ID(x)        ((x) & 0xffff)
  76
  77 #define SI_MAX_BORDER_COLORS    4096
  78
  79 struct si_compute;
  80 struct hash_table;
  81 struct u_suballocator;
  82
  83 struct si_screen {
  84         struct r600_common_screen       b;
  85         unsigned                        gs_table_depth;
  86         unsigned                        tess_offchip_block_dw_size;
  87         bool                            has_distributed_tess;
  88         bool                            has_draw_indirect_multi;
  89         bool                            has_ds_bpermute;
  90
  91         /* Whether shaders are monolithic (1-part) or separate (3-part). */
  92         bool                            use_monolithic_shaders;
  93         bool                            record_llvm_ir;
  94
  95         pipe_mutex                      shader_parts_mutex;
  96         struct si_shader_part           *vs_prologs;
  97         struct si_shader_part           *vs_epilogs;
  98         struct si_shader_part           *tcs_epilogs;
  99         struct si_shader_part           *ps_prologs;
 100         struct si_shader_part           *ps_epilogs;
 101
 102         /* Shader cache in memory.
 103          *
 104          * Design & limitations:
 105          * - The shader cache is per screen (= per process), never saved to
 106          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 107          * - It can only be used with one-variant-per-shader support, in which
 108          *   case only the main (typically middle) part of shaders is cached.
 109          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 110          *   variants of VS and TES are cached, so LS and ES aren't.
 111          * - GS and CS aren't cached, but it's certainly possible to cache
 112          *   those as well.
 113          */
 114         pipe_mutex                      shader_cache_mutex;
 115         struct hash_table               *shader_cache;
 116
 117         /* Shader compiler queue for multithreaded compilation. */
 118         struct util_queue               shader_compiler_queue;
 119         LLVMTargetMachineRef            tm[4]; /* used by the queue only */
 120 };
 121
 122 struct si_blend_color {
 123         struct r600_atom                atom;
 124         struct pipe_blend_color         state;
 125 };
 126
 127 struct si_sampler_view {
 128         struct pipe_sampler_view        base;
 129         /* [0..7] = image descriptor
 130          * [4..7] = buffer descriptor */
 131         uint32_t                        state[8];
 132         uint32_t                        fmask_state[8];
 133         const struct radeon_surf_level  *base_level_info;
 134         unsigned                        base_level;
 135         unsigned                        block_width;
 136         bool is_stencil_sampler;
 137 };
 138
 139 struct si_sampler_state {
 140         uint32_t                        val[4];
 141 };
 142
 143 struct si_cs_shader_state {
 144         struct si_compute               *program;
 145         struct si_compute               *emitted_program;
 146         unsigned                        offset;
 147         bool                            initialized;
 148         bool                            uses_scratch;
 149 };
 150
 151 struct si_textures_info {
 152         struct si_sampler_views         views;
 153         uint32_t                        depth_texture_mask; /* which textures are depth */
 154         uint32_t                        compressed_colortex_mask;
 155 };
 156
 157 struct si_images_info {
 158         struct pipe_image_view          views[SI_NUM_IMAGES];
 159         uint32_t                        compressed_colortex_mask;
 160         unsigned                        enabled_mask;
 161 };
 162
 163 struct si_framebuffer {
 164         struct r600_atom                atom;
 165         struct pipe_framebuffer_state   state;
 166         unsigned                        nr_samples;
 167         unsigned                        log_samples;
 168         unsigned                        compressed_cb_mask;
 169         unsigned                        spi_shader_col_format;
 170         unsigned                        spi_shader_col_format_alpha;
 171         unsigned                        spi_shader_col_format_blend;
 172         unsigned                        spi_shader_col_format_blend_alpha;
 173         unsigned                        color_is_int8; /* bitmask */
 174         unsigned                        dirty_cbufs;
 175         bool                            dirty_zsbuf;
 176         bool                            any_dst_linear;
 177 };
 178
 179 struct si_clip_state {
 180         struct r600_atom                atom;
 181         struct pipe_clip_state          state;
 182 };
 183
 184 struct si_sample_locs {
 185         struct r600_atom        atom;
 186         unsigned                nr_samples;
 187 };
 188
 189 struct si_sample_mask {
 190         struct r600_atom        atom;
 191         uint16_t                sample_mask;
 192 };
 193
 194 /* A shader state consists of the shader selector, which is a constant state
 195  * object shared by multiple contexts and shouldn't be modified, and
 196  * the current shader variant selected for this context.
 197  */
 198 struct si_shader_ctx_state {
 199         struct si_shader_selector       *cso;
 200         struct si_shader                *current;
 201 };
 202
 203 struct si_context {
 204         struct r600_common_context      b;
 205         struct blitter_context          *blitter;
 206         void                            *custom_dsa_flush;
 207         void                            *custom_blend_resolve;
 208         void                            *custom_blend_decompress;
 209         void                            *custom_blend_fastclear;
 210         void                            *custom_blend_dcc_decompress;
 211         struct si_screen                *screen;
 212
 213         struct radeon_winsys_cs         *ce_ib;
 214         struct radeon_winsys_cs         *ce_preamble_ib;
 215         bool                            ce_need_synchronization;
 216         struct u_suballocator           *ce_suballocator;
 217
 218         struct si_shader_ctx_state      fixed_func_tcs_shader;
 219         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 220         bool                            gfx_flush_in_progress;
 221         bool                            compute_is_busy;
 222
 223         /* Atoms (direct states). */
 224         union si_state_atoms            atoms;
 225         unsigned                        dirty_atoms; /* mask */
 226         /* PM4 states (precomputed immutable states) */
 227         union si_state                  queued;
 228         union si_state                  emitted;
 229
 230         /* Atom declarations. */
 231         struct si_framebuffer           framebuffer;
 232         struct si_sample_locs           msaa_sample_locs;
 233         struct r600_atom                db_render_state;
 234         struct r600_atom                msaa_config;
 235         struct si_sample_mask           sample_mask;
 236         struct r600_atom                cb_render_state;
 237         struct si_blend_color           blend_color;
 238         struct r600_atom                clip_regs;
 239         struct si_clip_state            clip_state;
 240         struct si_shader_data           shader_userdata;
 241         struct si_stencil_ref           stencil_ref;
 242         struct r600_atom                spi_map;
 243
 244         /* Precomputed states. */
 245         struct si_pm4_state             *init_config;
 246         struct si_pm4_state             *init_config_gs_rings;
 247         bool                            init_config_has_vgt_flush;
 248         struct si_pm4_state             *vgt_shader_config[4];
 249
 250         /* shaders */
 251         struct si_shader_ctx_state      ps_shader;
 252         struct si_shader_ctx_state      gs_shader;
 253         struct si_shader_ctx_state      vs_shader;
 254         struct si_shader_ctx_state      tcs_shader;
 255         struct si_shader_ctx_state      tes_shader;
 256         struct si_cs_shader_state       cs_shader_state;
 257
 258         /* shader information */
 259         struct si_vertex_element        *vertex_elements;
 260         unsigned                        sprite_coord_enable;
 261         bool                            flatshade;
 262         bool                            do_update_shaders;
 263
 264         /* shader descriptors */
 265         struct si_descriptors           vertex_buffers;
 266         struct si_descriptors           descriptors[SI_NUM_DESCS];
 267         unsigned                        descriptors_dirty;
 268         struct si_buffer_resources      rw_buffers;
 269         struct si_buffer_resources      const_buffers[SI_NUM_SHADERS];
 270         struct si_buffer_resources      shader_buffers[SI_NUM_SHADERS];
 271         struct si_textures_info         samplers[SI_NUM_SHADERS];
 272         struct si_images_info           images[SI_NUM_SHADERS];
 273
 274         /* other shader resources */
 275         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 276         struct pipe_resource            *esgs_ring;
 277         struct pipe_resource            *gsvs_ring;
 278         struct pipe_resource            *tf_ring;
 279         struct pipe_resource            *tess_offchip_ring;
 280         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 281         struct r600_resource            *border_color_buffer;
 282         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 283         unsigned                        border_color_count;
 284
 285         /* Vertex and index buffers. */
 286         bool                            vertex_buffers_dirty;
 287         struct pipe_index_buffer        index_buffer;
 288         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 289
 290         /* MSAA config state. */
 291         int                             ps_iter_samples;
 292         bool                            smoothing_enabled;
 293
 294         /* DB render state. */
 295         bool                    dbcb_depth_copy_enabled;
 296         bool                    dbcb_stencil_copy_enabled;
 297         unsigned                dbcb_copy_sample;
 298         bool                    db_flush_depth_inplace;
 299         bool                    db_flush_stencil_inplace;
 300         bool                    db_depth_clear;
 301         bool                    db_depth_disable_expclear;
 302         bool                    db_stencil_clear;
 303         bool                    db_stencil_disable_expclear;
 304         unsigned                ps_db_shader_control;
 305         bool                    occlusion_queries_disabled;
 306
 307         /* Emitted draw state. */
 308         int                     last_index_size;
 309         int                     last_base_vertex;
 310         int                     last_start_instance;
 311         int                     last_drawid;
 312         int                     last_sh_base_reg;
 313         int                     last_primitive_restart_en;
 314         int                     last_restart_index;
 315         int                     last_gs_out_prim;
 316         int                     last_prim;
 317         int                     last_multi_vgt_param;
 318         int                     last_rast_prim;
 319         unsigned                last_sc_line_stipple;
 320         int                     last_vtx_reuse_depth;
 321         int                     current_rast_prim; /* primitive type after TES, GS */
 322         unsigned                last_gsvs_itemsize;
 323
 324         /* Scratch buffer */
 325         struct r600_resource    *scratch_buffer;
 326         bool                    emit_scratch_reloc;
 327         unsigned                scratch_waves;
 328         unsigned                spi_tmpring_size;
 329
 330         struct r600_resource    *compute_scratch_buffer;
 331
 332         /* Emitted derived tessellation state. */
 333         struct si_shader        *last_ls; /* local shader (VS) */
 334         struct si_shader_selector *last_tcs;
 335         int                     last_num_tcs_input_cp;
 336         int                     last_tes_sh_base;
 337
 338         /* Debug state. */
 339         bool                    is_debug;
 340         struct radeon_saved_cs  last_gfx;
 341         struct r600_resource    *last_trace_buf;
 342         struct r600_resource    *trace_buf;
 343         unsigned                trace_id;
 344         uint64_t                dmesg_timestamp;
 345         unsigned                apitrace_call_number;
 346
 347         /* Other state */
 348         bool need_check_render_feedback;
 349 };
 350
 351 /* cik_sdma.c */
 352 void cik_init_sdma_functions(struct si_context *sctx);
 353
 354 /* si_blit.c */
 355 void si_init_blit_functions(struct si_context *sctx);
 356 void si_decompress_graphics_textures(struct si_context *sctx);
 357 void si_decompress_compute_textures(struct si_context *sctx);
 358 void si_resource_copy_region(struct pipe_context *ctx,
 359                              struct pipe_resource *dst,
 360                              unsigned dst_level,
 361                              unsigned dstx, unsigned dsty, unsigned dstz,
 362                              struct pipe_resource *src,
 363                              unsigned src_level,
 364                              const struct pipe_box *src_box);
 365
 366 /* si_cp_dma.c */
 367 void si_copy_buffer(struct si_context *sctx,
 368                     struct pipe_resource *dst, struct pipe_resource *src,
 369                     uint64_t dst_offset, uint64_t src_offset, unsigned size);
 370 void si_init_cp_dma_functions(struct si_context *sctx);
 371
 372 /* si_debug.c */
 373 void si_init_debug_functions(struct si_context *sctx);
 374 void si_check_vm_faults(struct r600_common_context *ctx,
 375                         struct radeon_saved_cs *saved, enum ring_type ring);
 376 bool si_replace_shader(unsigned num, struct radeon_shader_binary *binary);
 377
 378 /* si_dma.c */
 379 void si_init_dma_functions(struct si_context *sctx);
 380
 381 /* si_hw_context.c */
 382 void si_context_gfx_flush(void *context, unsigned flags,
 383                           struct pipe_fence_handle **fence);
 384 void si_begin_new_cs(struct si_context *ctx);
 385 void si_need_cs_space(struct si_context *ctx);
 386
 387 /* si_compute.c */
 388 void si_init_compute_functions(struct si_context *sctx);
 389
 390 /* si_perfcounters.c */
 391 void si_init_perfcounters(struct si_screen *screen);
 392
 393 /* si_uvd.c */
 394 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 395                                                const struct pipe_video_codec *templ);
 396
 397 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 398                                                  const struct pipe_video_buffer *tmpl);
 399
 400 /*
 401  * common helpers
 402  */
 403
 404 static inline struct r600_resource *
 405 si_resource_create_custom(struct pipe_screen *screen,
 406                           unsigned usage, unsigned size)
 407 {
 408         assert(size);
 409         return r600_resource(pipe_buffer_create(screen, 0, usage, size));
 410 }
 411
 412 static inline void
 413 si_invalidate_draw_sh_constants(struct si_context *sctx)
 414 {
 415         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 416 }
 417
 418 static inline void
 419 si_set_atom_dirty(struct si_context *sctx,
 420                   struct r600_atom *atom, bool dirty)
 421 {
 422         unsigned bit = 1 << (atom->id - 1);
 423
 424         if (dirty)
 425                 sctx->dirty_atoms |= bit;
 426         else
 427                 sctx->dirty_atoms &= ~bit;
 428 }
 429
 430 static inline bool
 431 si_is_atom_dirty(struct si_context *sctx,
 432                   struct r600_atom *atom)
 433 {
 434         unsigned bit = 1 << (atom->id - 1);
 435
 436         return sctx->dirty_atoms & bit;
 437 }
 438
 439 static inline void
 440 si_mark_atom_dirty(struct si_context *sctx,
 441                    struct r600_atom *atom)
 442 {
 443         si_set_atom_dirty(sctx, atom, true);
 444 }
 445
 446 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 447 {
 448         if (sctx->gs_shader.cso)
 449                 return &sctx->gs_shader.cso->info;
 450         else if (sctx->tes_shader.cso)
 451                 return &sctx->tes_shader.cso->info;
 452         else if (sctx->vs_shader.cso)
 453                 return &sctx->vs_shader.cso->info;
 454         else
 455                 return NULL;
 456 }
 457
 458 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 459 {
 460         if (sctx->gs_shader.current)
 461                 return sctx->gs_shader.current->gs_copy_shader;
 462         else if (sctx->tes_shader.current)
 463                 return sctx->tes_shader.current;
 464         else
 465                 return sctx->vs_shader.current;
 466 }
 467
 468 static inline bool si_vs_exports_prim_id(struct si_shader *shader)
 469 {
 470         if (shader->selector->type == PIPE_SHADER_VERTEX)
 471                 return shader->key.vs.epilog.export_prim_id;
 472         else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
 473                 return shader->key.tes.epilog.export_prim_id;
 474         else
 475                 return false;
 476 }
 477
 478 #endif