projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: fix scratch buffer WAVESIZE setting leading to corruption
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42 #define SI_PRIM_DISCARD_DEBUG 0
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
56
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
69 * GFX10: This also invalidates the L1 shader array cache. */
70 #define SI_CONTEXT_INV_SCACHE (1 << 4)
71 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
72 * GFX10: This also invalidates the L1 shader array cache. */
73 #define SI_CONTEXT_INV_VCACHE (1 << 5)
74 /* L2 cache + L2 metadata cache writeback & invalidate.
75 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
76 #define SI_CONTEXT_INV_L2 (1 << 6)
77 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
78 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
79 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
80 #define SI_CONTEXT_WB_L2 (1 << 7)
81 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
82 * a CB or DB flush. */
83 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
84 /* Framebuffer caches. */
85 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
86 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
87 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
88 /* Engine synchronization. */
89 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
90 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
91 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
92 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
93 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
94
95 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
96 #define SI_PREFETCH_LS (1 << 1)
97 #define SI_PREFETCH_HS (1 << 2)
98 #define SI_PREFETCH_ES (1 << 3)
99 #define SI_PREFETCH_GS (1 << 4)
100 #define SI_PREFETCH_VS (1 << 5)
101 #define SI_PREFETCH_PS (1 << 6)
102
103 #define SI_MAX_BORDER_COLORS 4096
104 #define SI_MAX_VIEWPORTS 16
105 #define SIX_BITS 0x3F
106 #define SI_MAP_BUFFER_ALIGNMENT 64
107 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
108
109 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
110 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
111 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
112 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
113 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
114 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
115 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
116 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
117 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
118 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
119
120 enum si_clear_code
121 {
122 DCC_CLEAR_COLOR_0000 = 0x00000000,
123 DCC_CLEAR_COLOR_0001 = 0x40404040,
124 DCC_CLEAR_COLOR_1110 = 0x80808080,
125 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
126 DCC_CLEAR_COLOR_REG = 0x20202020,
127 DCC_UNCOMPRESSED = 0xFFFFFFFF,
128 };
129
130 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
131
132 /* Debug flags. */
133 enum {
134 /* Shader logging options: */
135 DBG_VS = PIPE_SHADER_VERTEX,
136 DBG_PS = PIPE_SHADER_FRAGMENT,
137 DBG_GS = PIPE_SHADER_GEOMETRY,
138 DBG_TCS = PIPE_SHADER_TESS_CTRL,
139 DBG_TES = PIPE_SHADER_TESS_EVAL,
140 DBG_CS = PIPE_SHADER_COMPUTE,
141 DBG_NO_IR,
142 DBG_NO_TGSI,
143 DBG_NO_ASM,
144 DBG_PREOPT_IR,
145
146 /* Shader compiler options the shader cache should be aware of: */
147 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
148 DBG_SI_SCHED,
149 DBG_GISEL,
150 DBG_W32_GE,
151 DBG_W32_PS,
152 DBG_W32_CS,
153 DBG_W64_GE,
154 DBG_W64_PS,
155 DBG_W64_CS,
156
157 /* Shader compiler options (with no effect on the shader cache): */
158 DBG_CHECK_IR,
159 DBG_MONOLITHIC_SHADERS,
160 DBG_NO_OPT_VARIANT,
161
162 /* Information logging options: */
163 DBG_INFO,
164 DBG_TEX,
165 DBG_COMPUTE,
166 DBG_VM,
167
168 /* Driver options: */
169 DBG_FORCE_DMA,
170 DBG_NO_ASYNC_DMA,
171 DBG_NO_WC,
172 DBG_CHECK_VM,
173 DBG_RESERVE_VMID,
174 DBG_ZERO_VRAM,
175
176 /* 3D engine options: */
177 DBG_NO_GFX,
178 DBG_NO_NGG,
179 DBG_ALWAYS_PD,
180 DBG_PD,
181 DBG_NO_PD,
182 DBG_SWITCH_ON_EOP,
183 DBG_NO_OUT_OF_ORDER,
184 DBG_NO_DPBB,
185 DBG_NO_DFSM,
186 DBG_DPBB,
187 DBG_DFSM,
188 DBG_NO_HYPERZ,
189 DBG_NO_RB_PLUS,
190 DBG_NO_2D_TILING,
191 DBG_NO_TILING,
192 DBG_NO_DCC,
193 DBG_NO_DCC_CLEAR,
194 DBG_NO_DCC_FB,
195 DBG_NO_DCC_MSAA,
196 DBG_NO_FMASK,
197
198 /* Tests: */
199 DBG_TEST_DMA,
200 DBG_TEST_VMFAULT_CP,
201 DBG_TEST_VMFAULT_SDMA,
202 DBG_TEST_VMFAULT_SHADER,
203 DBG_TEST_DMA_PERF,
204 DBG_TEST_GDS,
205 DBG_TEST_GDS_MM,
206 DBG_TEST_GDS_OA_MM,
207 };
208
209 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
210 #define DBG(name) (1ull << DBG_##name)
211
212 enum si_cache_policy {
213 L2_BYPASS,
214 L2_STREAM, /* same as SLC=1 */
215 L2_LRU, /* same as SLC=0 */
216 };
217
218 enum si_coherency {
219 SI_COHERENCY_NONE, /* no cache flushes needed */
220 SI_COHERENCY_SHADER,
221 SI_COHERENCY_CB_META,
222 SI_COHERENCY_CP,
223 };
224
225 struct si_compute;
226 struct si_shader_context;
227 struct hash_table;
228 struct u_suballocator;
229
230 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
231 * at the moment.
232 */
233 struct si_resource {
234 struct threaded_resource b;
235
236 /* Winsys objects. */
237 struct pb_buffer *buf;
238 uint64_t gpu_address;
239 /* Memory usage if the buffer placement is optimal. */
240 uint64_t vram_usage;
241 uint64_t gart_usage;
242
243 /* Resource properties. */
244 uint64_t bo_size;
245 unsigned bo_alignment;
246 enum radeon_bo_domain domains;
247 enum radeon_bo_flag flags;
248 unsigned bind_history;
249 int max_forced_staging_uploads;
250
251 /* The buffer range which is initialized (with a write transfer,
252 * streamout, DMA, or as a random access target). The rest of
253 * the buffer is considered invalid and can be mapped unsynchronized.
254 *
255 * This allows unsychronized mapping of a buffer range which hasn't
256 * been used yet. It's for applications which forget to use
257 * the unsynchronized map flag and expect the driver to figure it out.
258 */
259 struct util_range valid_buffer_range;
260
261 /* For buffers only. This indicates that a write operation has been
262 * performed by TC L2, but the cache hasn't been flushed.
263 * Any hw block which doesn't use or bypasses TC L2 should check this
264 * flag and flush the cache before using the buffer.
265 *
266 * For example, TC L2 must be flushed if a buffer which has been
267 * modified by a shader store instruction is about to be used as
268 * an index buffer. The reason is that VGT DMA index fetching doesn't
269 * use TC L2.
270 */
271 bool TC_L2_dirty;
272
273 /* Whether this resource is referenced by bindless handles. */
274 bool texture_handle_allocated;
275 bool image_handle_allocated;
276
277 /* Whether the resource has been exported via resource_get_handle. */
278 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
279 };
280
281 struct si_transfer {
282 struct threaded_transfer b;
283 struct si_resource *staging;
284 unsigned offset;
285 };
286
287 struct si_texture {
288 struct si_resource buffer;
289
290 struct radeon_surf surface;
291 uint64_t size;
292 struct si_texture *flushed_depth_texture;
293
294 /* One texture allocation can contain these buffers:
295 * - image (pixel data)
296 * - FMASK buffer (MSAA compression)
297 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
298 * - HTILE buffer (Z/S compression and fast Z/S clear)
299 * - DCC buffer (color compression and new fast color clear)
300 * - displayable DCC buffer (if the DCC buffer is not displayable)
301 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
302 */
303 uint64_t fmask_offset;
304 uint64_t cmask_offset;
305 uint64_t cmask_base_address_reg;
306 struct si_resource *cmask_buffer;
307 uint64_t dcc_offset; /* 0 = disabled */
308 uint64_t display_dcc_offset;
309 uint64_t dcc_retile_map_offset;
310 unsigned cb_color_info; /* fast clear enable bit */
311 unsigned color_clear_value[2];
312 unsigned last_msaa_resolve_target_micro_mode;
313 unsigned num_level0_transfers;
314
315 /* Depth buffer compression and fast clear. */
316 uint64_t htile_offset;
317 float depth_clear_value;
318 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
319 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
320 enum pipe_format db_render_format:16;
321 uint8_t stencil_clear_value;
322 bool tc_compatible_htile:1;
323 bool htile_stencil_disabled:1;
324 bool depth_cleared:1; /* if it was cleared at least once */
325 bool stencil_cleared:1; /* if it was cleared at least once */
326 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
327 bool is_depth:1;
328 bool db_compatible:1;
329 bool can_sample_z:1;
330 bool can_sample_s:1;
331
332 /* We need to track DCC dirtiness, because st/dri usually calls
333 * flush_resource twice per frame (not a bug) and we don't wanna
334 * decompress DCC twice. Also, the dirty tracking must be done even
335 * if DCC isn't used, because it's required by the DCC usage analysis
336 * for a possible future enablement.
337 */
338 bool separate_dcc_dirty:1;
339 /* Statistics gathering for the DCC enablement heuristic. */
340 bool dcc_gather_statistics:1;
341 /* Counter that should be non-zero if the texture is bound to a
342 * framebuffer.
343 */
344 unsigned framebuffers_bound;
345 /* Whether the texture is a displayable back buffer and needs DCC
346 * decompression, which is expensive. Therefore, it's enabled only
347 * if statistics suggest that it will pay off and it's allocated
348 * separately. It can't be bound as a sampler by apps. Limited to
349 * target == 2D and last_level == 0. If enabled, dcc_offset contains
350 * the absolute GPUVM address, not the relative one.
351 */
352 struct si_resource *dcc_separate_buffer;
353 /* When DCC is temporarily disabled, the separate buffer is here. */
354 struct si_resource *last_dcc_separate_buffer;
355 /* Estimate of how much this color buffer is written to in units of
356 * full-screen draws: ps_invocations / (width * height)
357 * Shader kills, late Z, and blending with trivial discards make it
358 * inaccurate (we need to count CB updates, not PS invocations).
359 */
360 unsigned ps_draw_ratio;
361 /* The number of clears since the last DCC usage analysis. */
362 unsigned num_slow_clears;
363 };
364
365 struct si_surface {
366 struct pipe_surface base;
367
368 /* These can vary with block-compressed textures. */
369 uint16_t width0;
370 uint16_t height0;
371
372 bool color_initialized:1;
373 bool depth_initialized:1;
374
375 /* Misc. color flags. */
376 bool color_is_int8:1;
377 bool color_is_int10:1;
378 bool dcc_incompatible:1;
379
380 /* Color registers. */
381 unsigned cb_color_info;
382 unsigned cb_color_view;
383 unsigned cb_color_attrib;
384 unsigned cb_color_attrib2; /* GFX9 and later */
385 unsigned cb_color_attrib3; /* GFX10 and later */
386 unsigned cb_dcc_control; /* GFX8 and later */
387 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
388 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
389 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
390 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
391
392 /* DB registers. */
393 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
394 uint64_t db_stencil_base;
395 uint64_t db_htile_data_base;
396 unsigned db_depth_info;
397 unsigned db_z_info;
398 unsigned db_z_info2; /* GFX9 only */
399 unsigned db_depth_view;
400 unsigned db_depth_size;
401 unsigned db_depth_slice;
402 unsigned db_stencil_info;
403 unsigned db_stencil_info2; /* GFX9 only */
404 unsigned db_htile_surface;
405 };
406
407 struct si_mmio_counter {
408 unsigned busy;
409 unsigned idle;
410 };
411
412 union si_mmio_counters {
413 struct {
414 /* For global GPU load including SDMA. */
415 struct si_mmio_counter gpu;
416
417 /* GRBM_STATUS */
418 struct si_mmio_counter spi;
419 struct si_mmio_counter gui;
420 struct si_mmio_counter ta;
421 struct si_mmio_counter gds;
422 struct si_mmio_counter vgt;
423 struct si_mmio_counter ia;
424 struct si_mmio_counter sx;
425 struct si_mmio_counter wd;
426 struct si_mmio_counter bci;
427 struct si_mmio_counter sc;
428 struct si_mmio_counter pa;
429 struct si_mmio_counter db;
430 struct si_mmio_counter cp;
431 struct si_mmio_counter cb;
432
433 /* SRBM_STATUS2 */
434 struct si_mmio_counter sdma;
435
436 /* CP_STAT */
437 struct si_mmio_counter pfp;
438 struct si_mmio_counter meq;
439 struct si_mmio_counter me;
440 struct si_mmio_counter surf_sync;
441 struct si_mmio_counter cp_dma;
442 struct si_mmio_counter scratch_ram;
443 } named;
444 unsigned array[0];
445 };
446
447 struct si_memory_object {
448 struct pipe_memory_object b;
449 struct pb_buffer *buf;
450 uint32_t stride;
451 };
452
453 /* Saved CS data for debugging features. */
454 struct radeon_saved_cs {
455 uint32_t *ib;
456 unsigned num_dw;
457
458 struct radeon_bo_list_item *bo_list;
459 unsigned bo_count;
460 };
461
462 struct si_screen {
463 struct pipe_screen b;
464 struct radeon_winsys *ws;
465 struct disk_cache *disk_shader_cache;
466
467 struct radeon_info info;
468 uint64_t debug_flags;
469 char renderer_string[183];
470
471 void (*make_texture_descriptor)(
472 struct si_screen *screen,
473 struct si_texture *tex,
474 bool sampler,
475 enum pipe_texture_target target,
476 enum pipe_format pipe_format,
477 const unsigned char state_swizzle[4],
478 unsigned first_level, unsigned last_level,
479 unsigned first_layer, unsigned last_layer,
480 unsigned width, unsigned height, unsigned depth,
481 uint32_t *state,
482 uint32_t *fmask_state);
483
484 unsigned pa_sc_raster_config;
485 unsigned pa_sc_raster_config_1;
486 unsigned se_tile_repeat;
487 unsigned gs_table_depth;
488 unsigned tess_offchip_block_dw_size;
489 unsigned tess_offchip_ring_size;
490 unsigned tess_factor_ring_size;
491 unsigned vgt_hs_offchip_param;
492 unsigned eqaa_force_coverage_samples;
493 unsigned eqaa_force_z_samples;
494 unsigned eqaa_force_color_samples;
495 bool has_draw_indirect_multi;
496 bool has_out_of_order_rast;
497 bool assume_no_z_fights;
498 bool commutative_blend_add;
499 bool dpbb_allowed;
500 bool dfsm_allowed;
501 bool llvm_has_working_vgpr_indexing;
502 bool use_ngg;
503 bool use_ngg_streamout;
504
505 struct {
506 #define OPT_BOOL(name, dflt, description) bool name:1;
507 #include "si_debug_options.h"
508 } options;
509
510 /* Whether shaders are monolithic (1-part) or separate (3-part). */
511 bool use_monolithic_shaders;
512 bool record_llvm_ir;
513 bool dcc_msaa_allowed;
514
515 struct slab_parent_pool pool_transfers;
516
517 /* Texture filter settings. */
518 int force_aniso; /* -1 = disabled */
519
520 /* Auxiliary context. Mainly used to initialize resources.
521 * It must be locked prior to using and flushed before unlocking. */
522 struct pipe_context *aux_context;
523 mtx_t aux_context_lock;
524
525 /* This must be in the screen, because UE4 uses one context for
526 * compilation and another one for rendering.
527 */
528 unsigned num_compilations;
529 /* Along with ST_DEBUG=precompile, this should show if applications
530 * are loading shaders on demand. This is a monotonic counter.
531 */
532 unsigned num_shaders_created;
533 unsigned num_shader_cache_hits;
534
535 /* GPU load thread. */
536 mtx_t gpu_load_mutex;
537 thrd_t gpu_load_thread;
538 union si_mmio_counters mmio_counters;
539 volatile unsigned gpu_load_stop_thread; /* bool */
540
541 /* Performance counters. */
542 struct si_perfcounters *perfcounters;
543
544 /* If pipe_screen wants to recompute and re-emit the framebuffer,
545 * sampler, and image states of all contexts, it should atomically
546 * increment this.
547 *
548 * Each context will compare this with its own last known value of
549 * the counter before drawing and re-emit the states accordingly.
550 */
551 unsigned dirty_tex_counter;
552 unsigned dirty_buf_counter;
553
554 /* Atomically increment this counter when an existing texture's
555 * metadata is enabled or disabled in a way that requires changing
556 * contexts' compressed texture binding masks.
557 */
558 unsigned compressed_colortex_counter;
559
560 struct {
561 /* Context flags to set so that all writes from earlier jobs
562 * in the CP are seen by L2 clients.
563 */
564 unsigned cp_to_L2;
565
566 /* Context flags to set so that all writes from earlier jobs
567 * that end in L2 are seen by CP.
568 */
569 unsigned L2_to_cp;
570 } barrier_flags;
571
572 mtx_t shader_parts_mutex;
573 struct si_shader_part *vs_prologs;
574 struct si_shader_part *tcs_epilogs;
575 struct si_shader_part *gs_prologs;
576 struct si_shader_part *ps_prologs;
577 struct si_shader_part *ps_epilogs;
578
579 /* Shader cache in memory.
580 *
581 * Design & limitations:
582 * - The shader cache is per screen (= per process), never saved to
583 * disk, and skips redundant shader compilations from TGSI to bytecode.
584 * - It can only be used with one-variant-per-shader support, in which
585 * case only the main (typically middle) part of shaders is cached.
586 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
587 * variants of VS and TES are cached, so LS and ES aren't.
588 * - GS and CS aren't cached, but it's certainly possible to cache
589 * those as well.
590 */
591 mtx_t shader_cache_mutex;
592 struct hash_table *shader_cache;
593
594 /* Shader compiler queue for multithreaded compilation. */
595 struct util_queue shader_compiler_queue;
596 /* Use at most 3 normal compiler threads on quadcore and better.
597 * Hyperthreaded CPUs report the number of threads, but we want
598 * the number of cores. We only need this many threads for shader-db. */
599 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
600
601 struct util_queue shader_compiler_queue_low_priority;
602 /* Use at most 2 low priority threads on quadcore and better.
603 * We want to minimize the impact on multithreaded Mesa. */
604 struct ac_llvm_compiler compiler_lowp[10];
605
606 unsigned compute_wave_size;
607 unsigned ps_wave_size;
608 unsigned ge_wave_size;
609 };
610
611 struct si_blend_color {
612 struct pipe_blend_color state;
613 bool any_nonzeros;
614 };
615
616 struct si_sampler_view {
617 struct pipe_sampler_view base;
618 /* [0..7] = image descriptor
619 * [4..7] = buffer descriptor */
620 uint32_t state[8];
621 uint32_t fmask_state[8];
622 const struct legacy_surf_level *base_level_info;
623 ubyte base_level;
624 ubyte block_width;
625 bool is_stencil_sampler;
626 bool is_integer;
627 bool dcc_incompatible;
628 };
629
630 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
631
632 struct si_sampler_state {
633 #ifndef NDEBUG
634 unsigned magic;
635 #endif
636 uint32_t val[4];
637 uint32_t integer_val[4];
638 uint32_t upgraded_depth_val[4];
639 };
640
641 struct si_cs_shader_state {
642 struct si_compute *program;
643 struct si_compute *emitted_program;
644 unsigned offset;
645 bool initialized;
646 bool uses_scratch;
647 };
648
649 struct si_samplers {
650 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
651 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
652
653 /* The i-th bit is set if that element is enabled (non-NULL resource). */
654 unsigned enabled_mask;
655 uint32_t needs_depth_decompress_mask;
656 uint32_t needs_color_decompress_mask;
657 };
658
659 struct si_images {
660 struct pipe_image_view views[SI_NUM_IMAGES];
661 uint32_t needs_color_decompress_mask;
662 unsigned enabled_mask;
663 };
664
665 struct si_framebuffer {
666 struct pipe_framebuffer_state state;
667 unsigned colorbuf_enabled_4bit;
668 unsigned spi_shader_col_format;
669 unsigned spi_shader_col_format_alpha;
670 unsigned spi_shader_col_format_blend;
671 unsigned spi_shader_col_format_blend_alpha;
672 ubyte nr_samples:5; /* at most 16xAA */
673 ubyte log_samples:3; /* at most 4 = 16xAA */
674 ubyte nr_color_samples; /* at most 8xAA */
675 ubyte compressed_cb_mask;
676 ubyte uncompressed_cb_mask;
677 ubyte color_is_int8;
678 ubyte color_is_int10;
679 ubyte dirty_cbufs;
680 ubyte dcc_overwrite_combiner_watermark;
681 ubyte min_bytes_per_pixel;
682 bool dirty_zsbuf;
683 bool any_dst_linear;
684 bool CB_has_shader_readable_metadata;
685 bool DB_has_shader_readable_metadata;
686 bool all_DCC_pipe_aligned;
687 };
688
689 enum si_quant_mode {
690 /* This is the list we want to support. */
691 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
692 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
693 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
694 };
695
696 struct si_signed_scissor {
697 int minx;
698 int miny;
699 int maxx;
700 int maxy;
701 enum si_quant_mode quant_mode;
702 };
703
704 struct si_viewports {
705 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
706 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
707 bool y_inverted;
708 };
709
710 struct si_clip_state {
711 struct pipe_clip_state state;
712 bool any_nonzeros;
713 };
714
715 struct si_streamout_target {
716 struct pipe_stream_output_target b;
717
718 /* The buffer where BUFFER_FILLED_SIZE is stored. */
719 struct si_resource *buf_filled_size;
720 unsigned buf_filled_size_offset;
721 bool buf_filled_size_valid;
722
723 unsigned stride_in_dw;
724 };
725
726 struct si_streamout {
727 bool begin_emitted;
728
729 unsigned enabled_mask;
730 unsigned num_targets;
731 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
732
733 unsigned append_bitmask;
734 bool suspended;
735
736 /* External state which comes from the vertex shader,
737 * it must be set explicitly when binding a shader. */
738 uint16_t *stride_in_dw;
739 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
740
741 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
742 unsigned hw_enabled_mask;
743
744 /* The state of VGT_STRMOUT_(CONFIG|EN). */
745 bool streamout_enabled;
746 bool prims_gen_query_enabled;
747 int num_prims_gen_queries;
748 };
749
750 /* A shader state consists of the shader selector, which is a constant state
751 * object shared by multiple contexts and shouldn't be modified, and
752 * the current shader variant selected for this context.
753 */
754 struct si_shader_ctx_state {
755 struct si_shader_selector *cso;
756 struct si_shader *current;
757 };
758
759 #define SI_NUM_VGT_PARAM_KEY_BITS 12
760 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
761
762 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
763 * Some fields are set by state-change calls, most are set by draw_vbo.
764 */
765 union si_vgt_param_key {
766 struct {
767 #ifdef PIPE_ARCH_LITTLE_ENDIAN
768 unsigned prim:4;
769 unsigned uses_instancing:1;
770 unsigned multi_instances_smaller_than_primgroup:1;
771 unsigned primitive_restart:1;
772 unsigned count_from_stream_output:1;
773 unsigned line_stipple_enabled:1;
774 unsigned uses_tess:1;
775 unsigned tess_uses_prim_id:1;
776 unsigned uses_gs:1;
777 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
778 #else /* PIPE_ARCH_BIG_ENDIAN */
779 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
780 unsigned uses_gs:1;
781 unsigned tess_uses_prim_id:1;
782 unsigned uses_tess:1;
783 unsigned line_stipple_enabled:1;
784 unsigned count_from_stream_output:1;
785 unsigned primitive_restart:1;
786 unsigned multi_instances_smaller_than_primgroup:1;
787 unsigned uses_instancing:1;
788 unsigned prim:4;
789 #endif
790 } u;
791 uint32_t index;
792 };
793
794 #define SI_NUM_VGT_STAGES_KEY_BITS 4
795 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
796
797 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
798 * Some fields are set by state-change calls, most are set by draw_vbo.
799 */
800 union si_vgt_stages_key {
801 struct {
802 #ifdef PIPE_ARCH_LITTLE_ENDIAN
803 unsigned tess:1;
804 unsigned gs:1;
805 unsigned ngg:1; /* gfx10+ */
806 unsigned streamout:1; /* only used with NGG */
807 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
808 #else /* PIPE_ARCH_BIG_ENDIAN */
809 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
810 unsigned streamout:1;
811 unsigned ngg:1;
812 unsigned gs:1;
813 unsigned tess:1;
814 #endif
815 } u;
816 uint32_t index;
817 };
818
819 struct si_texture_handle
820 {
821 unsigned desc_slot;
822 bool desc_dirty;
823 struct pipe_sampler_view *view;
824 struct si_sampler_state sstate;
825 };
826
827 struct si_image_handle
828 {
829 unsigned desc_slot;
830 bool desc_dirty;
831 struct pipe_image_view view;
832 };
833
834 struct si_saved_cs {
835 struct pipe_reference reference;
836 struct si_context *ctx;
837 struct radeon_saved_cs gfx;
838 struct radeon_saved_cs compute;
839 struct si_resource *trace_buf;
840 unsigned trace_id;
841
842 unsigned gfx_last_dw;
843 unsigned compute_last_dw;
844 bool flushed;
845 int64_t time_flush;
846 };
847
848 struct si_sdma_upload {
849 struct si_resource *dst;
850 struct si_resource *src;
851 unsigned src_offset;
852 unsigned dst_offset;
853 unsigned size;
854 };
855
856 struct si_context {
857 struct pipe_context b; /* base class */
858
859 enum radeon_family family;
860 enum chip_class chip_class;
861
862 struct radeon_winsys *ws;
863 struct radeon_winsys_ctx *ctx;
864 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
865 struct radeon_cmdbuf *dma_cs;
866 struct pipe_fence_handle *last_gfx_fence;
867 struct pipe_fence_handle *last_sdma_fence;
868 struct si_resource *eop_bug_scratch;
869 struct u_upload_mgr *cached_gtt_allocator;
870 struct threaded_context *tc;
871 struct u_suballocator *allocator_zeroed_memory;
872 struct slab_child_pool pool_transfers;
873 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
874 struct pipe_device_reset_callback device_reset_callback;
875 struct u_log_context *log;
876 void *query_result_shader;
877 void *sh_query_result_shader;
878
879 void (*emit_cache_flush)(struct si_context *ctx);
880
881 struct blitter_context *blitter;
882 void *noop_blend;
883 void *noop_dsa;
884 void *discard_rasterizer_state;
885 void *custom_dsa_flush;
886 void *custom_blend_resolve;
887 void *custom_blend_fmask_decompress;
888 void *custom_blend_eliminate_fastclear;
889 void *custom_blend_dcc_decompress;
890 void *vs_blit_pos;
891 void *vs_blit_pos_layered;
892 void *vs_blit_color;
893 void *vs_blit_color_layered;
894 void *vs_blit_texcoord;
895 void *cs_clear_buffer;
896 void *cs_copy_buffer;
897 void *cs_copy_image;
898 void *cs_copy_image_1d_array;
899 void *cs_clear_render_target;
900 void *cs_clear_render_target_1d_array;
901 void *cs_dcc_retile;
902 struct si_screen *screen;
903 struct pipe_debug_callback debug;
904 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
905 struct si_shader_ctx_state fixed_func_tcs_shader;
906 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
907 struct si_resource *wait_mem_scratch;
908 unsigned wait_mem_number;
909 uint16_t prefetch_L2_mask;
910
911 bool has_graphics;
912 bool gfx_flush_in_progress:1;
913 bool gfx_last_ib_is_busy:1;
914 bool compute_is_busy:1;
915
916 unsigned num_gfx_cs_flushes;
917 unsigned initial_gfx_cs_size;
918 unsigned last_dirty_tex_counter;
919 unsigned last_dirty_buf_counter;
920 unsigned last_compressed_colortex_counter;
921 unsigned last_num_draw_calls;
922 unsigned flags; /* flush flags */
923 /* Current unaccounted memory usage. */
924 uint64_t vram;
925 uint64_t gtt;
926
927 /* Compute-based primitive discard. */
928 unsigned prim_discard_vertex_count_threshold;
929 struct pb_buffer *gds;
930 struct pb_buffer *gds_oa;
931 struct radeon_cmdbuf *prim_discard_compute_cs;
932 unsigned compute_gds_offset;
933 struct si_shader *compute_ib_last_shader;
934 uint32_t compute_rewind_va;
935 unsigned compute_num_prims_in_batch;
936 bool preserve_prim_restart_gds_at_flush;
937 /* index_ring is divided into 2 halves for doublebuffering. */
938 struct si_resource *index_ring;
939 unsigned index_ring_base; /* offset of a per-IB portion */
940 unsigned index_ring_offset; /* offset within a per-IB portion */
941 unsigned index_ring_size_per_ib; /* max available size per IB */
942 bool prim_discard_compute_ib_initialized;
943 /* For tracking the last execution barrier - it can be either
944 * a WRITE_DATA packet or a fence. */
945 uint32_t *last_pkt3_write_data;
946 struct si_resource *barrier_buf;
947 unsigned barrier_buf_offset;
948 struct pipe_fence_handle *last_ib_barrier_fence;
949 struct si_resource *last_ib_barrier_buf;
950 unsigned last_ib_barrier_buf_offset;
951
952 /* Atoms (direct states). */
953 union si_state_atoms atoms;
954 unsigned dirty_atoms; /* mask */
955 /* PM4 states (precomputed immutable states) */
956 unsigned dirty_states;
957 union si_state queued;
958 union si_state emitted;
959
960 /* Atom declarations. */
961 struct si_framebuffer framebuffer;
962 unsigned sample_locs_num_samples;
963 uint16_t sample_mask;
964 unsigned last_cb_target_mask;
965 struct si_blend_color blend_color;
966 struct si_clip_state clip_state;
967 struct si_shader_data shader_pointers;
968 struct si_stencil_ref stencil_ref;
969 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
970 struct si_streamout streamout;
971 struct si_viewports viewports;
972 unsigned num_window_rectangles;
973 bool window_rectangles_include;
974 struct pipe_scissor_state window_rectangles[4];
975
976 /* Precomputed states. */
977 struct si_pm4_state *init_config;
978 struct si_pm4_state *init_config_gs_rings;
979 bool init_config_has_vgt_flush;
980 struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
981
982 /* shaders */
983 struct si_shader_ctx_state ps_shader;
984 struct si_shader_ctx_state gs_shader;
985 struct si_shader_ctx_state vs_shader;
986 struct si_shader_ctx_state tcs_shader;
987 struct si_shader_ctx_state tes_shader;
988 struct si_shader_ctx_state cs_prim_discard_state;
989 struct si_cs_shader_state cs_shader_state;
990
991 /* shader information */
992 struct si_vertex_elements *vertex_elements;
993 unsigned sprite_coord_enable;
994 unsigned cs_max_waves_per_sh;
995 bool flatshade;
996 bool do_update_shaders;
997
998 /* vertex buffer descriptors */
999 uint32_t *vb_descriptors_gpu_list;
1000 struct si_resource *vb_descriptors_buffer;
1001 unsigned vb_descriptors_offset;
1002
1003 /* shader descriptors */
1004 struct si_descriptors descriptors[SI_NUM_DESCS];
1005 unsigned descriptors_dirty;
1006 unsigned shader_pointers_dirty;
1007 unsigned shader_needs_decompress_mask;
1008 struct si_buffer_resources rw_buffers;
1009 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
1010 struct si_samplers samplers[SI_NUM_SHADERS];
1011 struct si_images images[SI_NUM_SHADERS];
1012 bool bo_list_add_all_resident_resources;
1013 bool bo_list_add_all_gfx_resources;
1014 bool bo_list_add_all_compute_resources;
1015
1016 /* other shader resources */
1017 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
1018 struct pipe_resource *esgs_ring;
1019 struct pipe_resource *gsvs_ring;
1020 struct pipe_resource *tess_rings;
1021 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
1022 struct si_resource *border_color_buffer;
1023 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
1024 unsigned border_color_count;
1025 unsigned num_vs_blit_sgprs;
1026 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
1027 uint32_t cs_user_data[4];
1028
1029 /* Vertex and index buffers. */
1030 bool vertex_buffers_dirty;
1031 bool vertex_buffer_pointer_dirty;
1032 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
1033 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
1034
1035 /* MSAA config state. */
1036 int ps_iter_samples;
1037 bool ps_uses_fbfetch;
1038 bool smoothing_enabled;
1039
1040 /* DB render state. */
1041 unsigned ps_db_shader_control;
1042 unsigned dbcb_copy_sample;
1043 bool dbcb_depth_copy_enabled:1;
1044 bool dbcb_stencil_copy_enabled:1;
1045 bool db_flush_depth_inplace:1;
1046 bool db_flush_stencil_inplace:1;
1047 bool db_depth_clear:1;
1048 bool db_depth_disable_expclear:1;
1049 bool db_stencil_clear:1;
1050 bool db_stencil_disable_expclear:1;
1051 bool occlusion_queries_disabled:1;
1052 bool generate_mipmap_for_depth:1;
1053
1054 /* Emitted draw state. */
1055 bool gs_tri_strip_adj_fix:1;
1056 bool ls_vgpr_fix:1;
1057 bool prim_discard_cs_instancing:1;
1058 bool ngg:1;
1059 int last_index_size;
1060 int last_base_vertex;
1061 int last_start_instance;
1062 int last_instance_count;
1063 int last_drawid;
1064 int last_sh_base_reg;
1065 int last_primitive_restart_en;
1066 int last_restart_index;
1067 int last_prim;
1068 int last_multi_vgt_param;
1069 int last_rast_prim;
1070 int last_flatshade_first;
1071 int last_binning_enabled;
1072 unsigned last_sc_line_stipple;
1073 unsigned current_vs_state;
1074 unsigned last_vs_state;
1075 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
1076
1077 /* Scratch buffer */
1078 struct si_resource *scratch_buffer;
1079 unsigned scratch_waves;
1080 unsigned spi_tmpring_size;
1081 unsigned max_seen_scratch_bytes_per_wave;
1082 unsigned max_seen_compute_scratch_bytes_per_wave;
1083
1084 struct si_resource *compute_scratch_buffer;
1085
1086 /* Emitted derived tessellation state. */
1087 /* Local shader (VS), or HS if LS-HS are merged. */
1088 struct si_shader *last_ls;
1089 struct si_shader_selector *last_tcs;
1090 int last_num_tcs_input_cp;
1091 int last_tes_sh_base;
1092 bool last_tess_uses_primid;
1093 unsigned last_num_patches;
1094 int last_ls_hs_config;
1095
1096 /* Debug state. */
1097 bool is_debug;
1098 struct si_saved_cs *current_saved_cs;
1099 uint64_t dmesg_timestamp;
1100 unsigned apitrace_call_number;
1101
1102 /* Other state */
1103 bool need_check_render_feedback;
1104 bool decompression_enabled;
1105 bool dpbb_force_off;
1106 bool vs_writes_viewport_index;
1107 bool vs_disables_clipping_viewport;
1108
1109 /* Precomputed IA_MULTI_VGT_PARAM */
1110 union si_vgt_param_key ia_multi_vgt_param_key;
1111 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1112
1113 /* Bindless descriptors. */
1114 struct si_descriptors bindless_descriptors;
1115 struct util_idalloc bindless_used_slots;
1116 unsigned num_bindless_descriptors;
1117 bool bindless_descriptors_dirty;
1118 bool graphics_bindless_pointer_dirty;
1119 bool compute_bindless_pointer_dirty;
1120
1121 /* Allocated bindless handles */
1122 struct hash_table *tex_handles;
1123 struct hash_table *img_handles;
1124
1125 /* Resident bindless handles */
1126 struct util_dynarray resident_tex_handles;
1127 struct util_dynarray resident_img_handles;
1128
1129 /* Resident bindless handles which need decompression */
1130 struct util_dynarray resident_tex_needs_color_decompress;
1131 struct util_dynarray resident_img_needs_color_decompress;
1132 struct util_dynarray resident_tex_needs_depth_decompress;
1133
1134 /* Bindless state */
1135 bool uses_bindless_samplers;
1136 bool uses_bindless_images;
1137
1138 /* MSAA sample locations.
1139 * The first index is the sample index.
1140 * The second index is the coordinate: X, Y. */
1141 struct {
1142 float x1[1][2];
1143 float x2[2][2];
1144 float x4[4][2];
1145 float x8[8][2];
1146 float x16[16][2];
1147 } sample_positions;
1148 struct pipe_resource *sample_pos_buffer;
1149
1150 /* Misc stats. */
1151 unsigned num_draw_calls;
1152 unsigned num_decompress_calls;
1153 unsigned num_mrt_draw_calls;
1154 unsigned num_prim_restart_calls;
1155 unsigned num_spill_draw_calls;
1156 unsigned num_compute_calls;
1157 unsigned num_spill_compute_calls;
1158 unsigned num_dma_calls;
1159 unsigned num_cp_dma_calls;
1160 unsigned num_vs_flushes;
1161 unsigned num_ps_flushes;
1162 unsigned num_cs_flushes;
1163 unsigned num_cb_cache_flushes;
1164 unsigned num_db_cache_flushes;
1165 unsigned num_L2_invalidates;
1166 unsigned num_L2_writebacks;
1167 unsigned num_resident_handles;
1168 uint64_t num_alloc_tex_transfer_bytes;
1169 unsigned last_tex_ps_draw_ratio; /* for query */
1170 unsigned compute_num_verts_accepted;
1171 unsigned compute_num_verts_rejected;
1172 unsigned compute_num_verts_ineligible; /* due to low vertex count */
1173 unsigned context_roll;
1174
1175 /* Queries. */
1176 /* Maintain the list of active queries for pausing between IBs. */
1177 int num_occlusion_queries;
1178 int num_perfect_occlusion_queries;
1179 int num_pipeline_stat_queries;
1180 struct list_head active_queries;
1181 unsigned num_cs_dw_queries_suspend;
1182
1183 /* Render condition. */
1184 struct pipe_query *render_cond;
1185 unsigned render_cond_mode;
1186 bool render_cond_invert;
1187 bool render_cond_force_off; /* for u_blitter */
1188
1189 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1190 bool sdma_uploads_in_progress;
1191 struct si_sdma_upload *sdma_uploads;
1192 unsigned num_sdma_uploads;
1193 unsigned max_sdma_uploads;
1194
1195 /* Shader-based queries. */
1196 struct list_head shader_query_buffers;
1197 unsigned num_active_shader_queries;
1198
1199 /* Statistics gathering for the DCC enablement heuristic. It can't be
1200 * in si_texture because si_texture can be shared by multiple
1201 * contexts. This is for back buffers only. We shouldn't get too many
1202 * of those.
1203 *
1204 * X11 DRI3 rotates among a finite set of back buffers. They should
1205 * all fit in this array. If they don't, separate DCC might never be
1206 * enabled by DCC stat gathering.
1207 */
1208 struct {
1209 struct si_texture *tex;
1210 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1211 struct pipe_query *ps_stats[3];
1212 /* If all slots are used and another slot is needed,
1213 * the least recently used slot is evicted based on this. */
1214 int64_t last_use_timestamp;
1215 bool query_active;
1216 } dcc_stats[5];
1217
1218 /* Copy one resource to another using async DMA. */
1219 void (*dma_copy)(struct pipe_context *ctx,
1220 struct pipe_resource *dst,
1221 unsigned dst_level,
1222 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1223 struct pipe_resource *src,
1224 unsigned src_level,
1225 const struct pipe_box *src_box);
1226
1227 struct si_tracked_regs tracked_regs;
1228 };
1229
1230 /* cik_sdma.c */
1231 void cik_init_sdma_functions(struct si_context *sctx);
1232
1233 /* si_blit.c */
1234 enum si_blitter_op /* bitmask */
1235 {
1236 SI_SAVE_TEXTURES = 1,
1237 SI_SAVE_FRAMEBUFFER = 2,
1238 SI_SAVE_FRAGMENT_STATE = 4,
1239 SI_DISABLE_RENDER_COND = 8,
1240 };
1241
1242 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1243 void si_blitter_end(struct si_context *sctx);
1244 void si_init_blit_functions(struct si_context *sctx);
1245 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1246 void si_resource_copy_region(struct pipe_context *ctx,
1247 struct pipe_resource *dst,
1248 unsigned dst_level,
1249 unsigned dstx, unsigned dsty, unsigned dstz,
1250 struct pipe_resource *src,
1251 unsigned src_level,
1252 const struct pipe_box *src_box);
1253 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1254
1255 /* si_buffer.c */
1256 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1257 struct pb_buffer *buf,
1258 enum radeon_bo_usage usage);
1259 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1260 struct si_resource *resource,
1261 unsigned usage);
1262 void si_init_resource_fields(struct si_screen *sscreen,
1263 struct si_resource *res,
1264 uint64_t size, unsigned alignment);
1265 bool si_alloc_resource(struct si_screen *sscreen,
1266 struct si_resource *res);
1267 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1268 unsigned flags, unsigned usage,
1269 unsigned size, unsigned alignment);
1270 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1271 unsigned flags, unsigned usage,
1272 unsigned size, unsigned alignment);
1273 void si_replace_buffer_storage(struct pipe_context *ctx,
1274 struct pipe_resource *dst,
1275 struct pipe_resource *src);
1276 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1277 void si_init_buffer_functions(struct si_context *sctx);
1278
1279 /* si_clear.c */
1280 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1281 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
1282 bool vi_dcc_clear_level(struct si_context *sctx,
1283 struct si_texture *tex,
1284 unsigned level, unsigned clear_value);
1285 void si_init_clear_functions(struct si_context *sctx);
1286
1287 /* si_compute_blit.c */
1288 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1289 enum si_cache_policy cache_policy);
1290 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1291 uint64_t offset, uint64_t size, uint32_t *clear_value,
1292 uint32_t clear_value_size, enum si_coherency coher,
1293 bool force_cpdma);
1294 void si_copy_buffer(struct si_context *sctx,
1295 struct pipe_resource *dst, struct pipe_resource *src,
1296 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1297 void si_compute_copy_image(struct si_context *sctx,
1298 struct pipe_resource *dst,
1299 unsigned dst_level,
1300 struct pipe_resource *src,
1301 unsigned src_level,
1302 unsigned dstx, unsigned dsty, unsigned dstz,
1303 const struct pipe_box *src_box);
1304 void si_compute_clear_render_target(struct pipe_context *ctx,
1305 struct pipe_surface *dstsurf,
1306 const union pipe_color_union *color,
1307 unsigned dstx, unsigned dsty,
1308 unsigned width, unsigned height,
1309 bool render_condition_enabled);
1310 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1311 void si_init_compute_blit_functions(struct si_context *sctx);
1312
1313 /* si_cp_dma.c */
1314 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1315 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1316 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1317 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1318 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1319 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1320 SI_CPDMA_SKIP_SYNC_AFTER | \
1321 SI_CPDMA_SKIP_SYNC_BEFORE | \
1322 SI_CPDMA_SKIP_GFX_SYNC | \
1323 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1324
1325 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1326 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1327 struct pipe_resource *dst, uint64_t offset,
1328 uint64_t size, unsigned value, unsigned user_flags,
1329 enum si_coherency coher, enum si_cache_policy cache_policy);
1330 void si_cp_dma_copy_buffer(struct si_context *sctx,
1331 struct pipe_resource *dst, struct pipe_resource *src,
1332 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1333 unsigned user_flags, enum si_coherency coher,
1334 enum si_cache_policy cache_policy);
1335 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1336 uint64_t offset, unsigned size);
1337 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1338 void si_test_gds(struct si_context *sctx);
1339 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
1340 unsigned offset, unsigned size, unsigned dst_sel,
1341 unsigned engine, const void *data);
1342 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs,
1343 unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
1344 unsigned src_sel, struct si_resource *src, unsigned src_offset);
1345
1346 /* si_debug.c */
1347 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1348 struct radeon_saved_cs *saved, bool get_buffer_list);
1349 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1350 void si_destroy_saved_cs(struct si_saved_cs *scs);
1351 void si_auto_log_cs(void *data, struct u_log_context *log);
1352 void si_log_hw_flush(struct si_context *sctx);
1353 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1354 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1355 void si_init_debug_functions(struct si_context *sctx);
1356 void si_check_vm_faults(struct si_context *sctx,
1357 struct radeon_saved_cs *saved, enum ring_type ring);
1358 bool si_replace_shader(unsigned num, struct si_shader_binary *binary);
1359
1360 /* si_dma.c */
1361 void si_init_dma_functions(struct si_context *sctx);
1362
1363 /* si_dma_cs.c */
1364 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
1365 uint64_t offset);
1366 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1367 uint64_t offset, uint64_t size, unsigned clear_value);
1368 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1369 struct si_resource *dst, struct si_resource *src);
1370 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1371 struct pipe_fence_handle **fence);
1372 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1373 uint64_t offset, uint64_t size, unsigned value);
1374
1375 /* si_fence.c */
1376 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1377 unsigned event, unsigned event_flags,
1378 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1379 struct si_resource *buf, uint64_t va,
1380 uint32_t new_fence, unsigned query_type);
1381 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1382 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1383 uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
1384 void si_init_fence_functions(struct si_context *ctx);
1385 void si_init_screen_fence_functions(struct si_screen *screen);
1386 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1387 struct tc_unflushed_batch_token *tc_token);
1388
1389 /* si_get.c */
1390 void si_init_screen_get_functions(struct si_screen *sscreen);
1391
1392 /* si_gfx_cs.c */
1393 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1394 struct pipe_fence_handle **fence);
1395 void si_allocate_gds(struct si_context *ctx);
1396 void si_begin_new_gfx_cs(struct si_context *ctx);
1397 void si_need_gfx_cs_space(struct si_context *ctx);
1398 void si_unref_sdma_uploads(struct si_context *sctx);
1399
1400 /* si_gpu_load.c */
1401 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1402 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1403 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1404 uint64_t begin);
1405
1406 /* si_compute.c */
1407 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1408 void si_init_compute_functions(struct si_context *sctx);
1409
1410 /* si_compute_prim_discard.c */
1411 enum si_prim_discard_outcome {
1412 SI_PRIM_DISCARD_ENABLED,
1413 SI_PRIM_DISCARD_DISABLED,
1414 SI_PRIM_DISCARD_DRAW_SPLIT,
1415 };
1416
1417 void si_build_prim_discard_compute_shader(struct si_shader_context *ctx);
1418 enum si_prim_discard_outcome
1419 si_prepare_prim_discard_or_split_draw(struct si_context *sctx,
1420 const struct pipe_draw_info *info,
1421 bool primitive_restart);
1422 void si_compute_signal_gfx(struct si_context *sctx);
1423 void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx,
1424 const struct pipe_draw_info *info,
1425 unsigned index_size,
1426 unsigned base_vertex,
1427 uint64_t input_indexbuf_va,
1428 unsigned input_indexbuf_max_elements);
1429 void si_initialize_prim_discard_tunables(struct si_context *sctx);
1430
1431 /* si_perfcounters.c */
1432 void si_init_perfcounters(struct si_screen *screen);
1433 void si_destroy_perfcounters(struct si_screen *screen);
1434
1435 /* si_pipe.c */
1436 bool si_check_device_reset(struct si_context *sctx);
1437
1438 /* si_query.c */
1439 void si_init_screen_query_functions(struct si_screen *sscreen);
1440 void si_init_query_functions(struct si_context *sctx);
1441 void si_suspend_queries(struct si_context *sctx);
1442 void si_resume_queries(struct si_context *sctx);
1443
1444 /* si_shaderlib_tgsi.c */
1445 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1446 unsigned num_layers);
1447 void *si_create_fixed_func_tcs(struct si_context *sctx);
1448 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1449 unsigned num_dwords_per_thread,
1450 bool dst_stream_cache_policy, bool is_copy);
1451 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1452 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1453 void *si_clear_render_target_shader(struct pipe_context *ctx);
1454 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1455 void *si_create_dcc_retile_cs(struct pipe_context *ctx);
1456 void *si_create_query_result_cs(struct si_context *sctx);
1457 void *gfx10_create_sh_query_result_cs(struct si_context *sctx);
1458
1459 /* gfx10_query.c */
1460 void gfx10_init_query(struct si_context *sctx);
1461 void gfx10_destroy_query(struct si_context *sctx);
1462
1463 /* si_test_dma.c */
1464 void si_test_dma(struct si_screen *sscreen);
1465
1466 /* si_test_clearbuffer.c */
1467 void si_test_dma_perf(struct si_screen *sscreen);
1468
1469 /* si_uvd.c */
1470 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1471 const struct pipe_video_codec *templ);
1472
1473 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1474 const struct pipe_video_buffer *tmpl);
1475
1476 /* si_viewport.c */
1477 void si_update_vs_viewport_state(struct si_context *ctx);
1478 void si_init_viewport_functions(struct si_context *ctx);
1479
1480 /* si_texture.c */
1481 bool si_prepare_for_dma_blit(struct si_context *sctx,
1482 struct si_texture *dst,
1483 unsigned dst_level, unsigned dstx,
1484 unsigned dsty, unsigned dstz,
1485 struct si_texture *src,
1486 unsigned src_level,
1487 const struct pipe_box *src_box);
1488 void si_eliminate_fast_color_clear(struct si_context *sctx,
1489 struct si_texture *tex);
1490 void si_texture_discard_cmask(struct si_screen *sscreen,
1491 struct si_texture *tex);
1492 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1493 struct pipe_resource *texture);
1494 void si_print_texture_info(struct si_screen *sscreen,
1495 struct si_texture *tex, struct u_log_context *log);
1496 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1497 const struct pipe_resource *templ);
1498 bool vi_dcc_formats_compatible(struct si_screen *sscreen,
1499 enum pipe_format format1,
1500 enum pipe_format format2);
1501 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1502 unsigned level,
1503 enum pipe_format view_format);
1504 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1505 struct pipe_resource *tex,
1506 unsigned level,
1507 enum pipe_format view_format);
1508 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1509 struct pipe_resource *texture,
1510 const struct pipe_surface *templ,
1511 unsigned width0, unsigned height0,
1512 unsigned width, unsigned height);
1513 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1514 void vi_separate_dcc_try_enable(struct si_context *sctx,
1515 struct si_texture *tex);
1516 void vi_separate_dcc_start_query(struct si_context *sctx,
1517 struct si_texture *tex);
1518 void vi_separate_dcc_stop_query(struct si_context *sctx,
1519 struct si_texture *tex);
1520 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1521 struct si_texture *tex);
1522 bool si_texture_disable_dcc(struct si_context *sctx,
1523 struct si_texture *tex);
1524 void si_init_screen_texture_functions(struct si_screen *sscreen);
1525 void si_init_context_texture_functions(struct si_context *sctx);
1526
1527
1528 /*
1529 * common helpers
1530 */
1531
1532 static inline struct si_resource *si_resource(struct pipe_resource *r)
1533 {
1534 return (struct si_resource*)r;
1535 }
1536
1537 static inline void
1538 si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1539 {
1540 pipe_resource_reference((struct pipe_resource **)ptr,
1541 (struct pipe_resource *)res);
1542 }
1543
1544 static inline void
1545 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1546 {
1547 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1548 }
1549
1550 static inline bool
1551 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1552 {
1553 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
1554 }
1555
1556 static inline unsigned
1557 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1558 {
1559 if (stencil)
1560 return tex->surface.u.legacy.stencil_tiling_index[level];
1561 else
1562 return tex->surface.u.legacy.tiling_index[level];
1563 }
1564
1565 static inline unsigned
1566 si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx)
1567 {
1568 /* Don't count the needed CS space exactly and just use an upper bound.
1569 *
1570 * Also reserve space for stopping queries at the end of IB, because
1571 * the number of active queries is unlimited in theory.
1572 */
1573 return 2048 + sctx->num_cs_dw_queries_suspend;
1574 }
1575
1576 static inline void
1577 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1578 {
1579 if (r) {
1580 /* Add memory usage for need_gfx_cs_space */
1581 sctx->vram += si_resource(r)->vram_usage;
1582 sctx->gtt += si_resource(r)->gart_usage;
1583 }
1584 }
1585
1586 static inline void
1587 si_invalidate_draw_sh_constants(struct si_context *sctx)
1588 {
1589 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1590 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1591 }
1592
1593 static inline unsigned
1594 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1595 {
1596 return 1 << (atom - sctx->atoms.array);
1597 }
1598
1599 static inline void
1600 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1601 {
1602 unsigned bit = si_get_atom_bit(sctx, atom);
1603
1604 if (dirty)
1605 sctx->dirty_atoms |= bit;
1606 else
1607 sctx->dirty_atoms &= ~bit;
1608 }
1609
1610 static inline bool
1611 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1612 {
1613 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1614 }
1615
1616 static inline void
1617 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1618 {
1619 si_set_atom_dirty(sctx, atom, true);
1620 }
1621
1622 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1623 {
1624 if (sctx->gs_shader.cso)
1625 return &sctx->gs_shader;
1626 if (sctx->tes_shader.cso)
1627 return &sctx->tes_shader;
1628
1629 return &sctx->vs_shader;
1630 }
1631
1632 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1633 {
1634 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1635
1636 return vs->cso ? &vs->cso->info : NULL;
1637 }
1638
1639 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1640 {
1641 if (sctx->gs_shader.cso &&
1642 sctx->gs_shader.current &&
1643 !sctx->gs_shader.current->key.as_ngg)
1644 return sctx->gs_shader.cso->gs_copy_shader;
1645
1646 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1647 return vs->current ? vs->current : NULL;
1648 }
1649
1650 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1651 unsigned processor)
1652 {
1653 return sscreen->debug_flags & (1 << processor);
1654 }
1655
1656 static inline bool si_get_strmout_en(struct si_context *sctx)
1657 {
1658 return sctx->streamout.streamout_enabled ||
1659 sctx->streamout.prims_gen_query_enabled;
1660 }
1661
1662 static inline unsigned
1663 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1664 {
1665 unsigned alignment, tcc_cache_line_size;
1666
1667 /* If the upload size is less than the cache line size (e.g. 16, 32),
1668 * the whole thing will fit into a cache line if we align it to its size.
1669 * The idea is that multiple small uploads can share a cache line.
1670 * If the upload size is greater, align it to the cache line size.
1671 */
1672 alignment = util_next_power_of_two(upload_size);
1673 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1674 return MIN2(alignment, tcc_cache_line_size);
1675 }
1676
1677 static inline void
1678 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1679 {
1680 if (pipe_reference(&(*dst)->reference, &src->reference))
1681 si_destroy_saved_cs(*dst);
1682
1683 *dst = src;
1684 }
1685
1686 static inline void
1687 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1688 bool shaders_read_metadata, bool dcc_pipe_aligned)
1689 {
1690 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1691 SI_CONTEXT_INV_VCACHE;
1692
1693 if (sctx->chip_class >= GFX10) {
1694 if (shaders_read_metadata)
1695 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1696 } else if (sctx->chip_class == GFX9) {
1697 /* Single-sample color is coherent with shaders on GFX9, but
1698 * L2 metadata must be flushed if shaders read metadata.
1699 * (DCC, CMASK).
1700 */
1701 if (num_samples >= 2 ||
1702 (shaders_read_metadata && !dcc_pipe_aligned))
1703 sctx->flags |= SI_CONTEXT_INV_L2;
1704 else if (shaders_read_metadata)
1705 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1706 } else {
1707 /* GFX6-GFX8 */
1708 sctx->flags |= SI_CONTEXT_INV_L2;
1709 }
1710 }
1711
1712 static inline void
1713 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1714 bool include_stencil, bool shaders_read_metadata)
1715 {
1716 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1717 SI_CONTEXT_INV_VCACHE;
1718
1719 if (sctx->chip_class >= GFX10) {
1720 if (shaders_read_metadata)
1721 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1722 } else if (sctx->chip_class == GFX9) {
1723 /* Single-sample depth (not stencil) is coherent with shaders
1724 * on GFX9, but L2 metadata must be flushed if shaders read
1725 * metadata.
1726 */
1727 if (num_samples >= 2 || include_stencil)
1728 sctx->flags |= SI_CONTEXT_INV_L2;
1729 else if (shaders_read_metadata)
1730 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1731 } else {
1732 /* GFX6-GFX8 */
1733 sctx->flags |= SI_CONTEXT_INV_L2;
1734 }
1735 }
1736
1737 static inline bool
1738 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1739 {
1740 return (stencil_sampler && tex->can_sample_s) ||
1741 (!stencil_sampler && tex->can_sample_z);
1742 }
1743
1744 static inline bool
1745 si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1746 {
1747 if (zs_mask == PIPE_MASK_S && tex->htile_stencil_disabled)
1748 return false;
1749
1750 return tex->htile_offset && level == 0;
1751 }
1752
1753 static inline bool
1754 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1755 {
1756 assert(!tex->tc_compatible_htile || tex->htile_offset);
1757 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
1758 }
1759
1760 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1761 {
1762 if (sctx->ps_uses_fbfetch)
1763 return sctx->framebuffer.nr_color_samples;
1764
1765 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1766 }
1767
1768 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1769 {
1770 if (sctx->queued.named.rasterizer->rasterizer_discard)
1771 return 0;
1772
1773 struct si_shader_selector *ps = sctx->ps_shader.cso;
1774 if (!ps)
1775 return 0;
1776
1777 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1778 sctx->queued.named.blend->cb_target_mask;
1779
1780 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1781 colormask &= ps->colors_written_4bit;
1782 else if (!ps->colors_written_4bit)
1783 colormask = 0; /* color0 writes all cbufs, but it's not written */
1784
1785 return colormask;
1786 }
1787
1788 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1789 (1 << PIPE_PRIM_LINE_LOOP) | \
1790 (1 << PIPE_PRIM_LINE_STRIP) | \
1791 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1792 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1793
1794 static inline bool util_prim_is_lines(unsigned prim)
1795 {
1796 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1797 }
1798
1799 static inline bool util_prim_is_points_or_lines(unsigned prim)
1800 {
1801 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1802 (1 << PIPE_PRIM_POINTS))) != 0;
1803 }
1804
1805 static inline bool util_rast_prim_is_triangles(unsigned prim)
1806 {
1807 return ((1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1808 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1809 (1 << PIPE_PRIM_TRIANGLE_FAN) |
1810 (1 << PIPE_PRIM_QUADS) |
1811 (1 << PIPE_PRIM_QUAD_STRIP) |
1812 (1 << PIPE_PRIM_POLYGON) |
1813 (1 << PIPE_PRIM_TRIANGLES_ADJACENCY) |
1814 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY)));
1815 }
1816
1817 /**
1818 * Return true if there is enough memory in VRAM and GTT for the buffers
1819 * added so far.
1820 *
1821 * \param vram VRAM memory size not added to the buffer list yet
1822 * \param gtt GTT memory size not added to the buffer list yet
1823 */
1824 static inline bool
1825 radeon_cs_memory_below_limit(struct si_screen *screen,
1826 struct radeon_cmdbuf *cs,
1827 uint64_t vram, uint64_t gtt)
1828 {
1829 vram += cs->used_vram;
1830 gtt += cs->used_gart;
1831
1832 /* Anything that goes above the VRAM size should go to GTT. */
1833 if (vram > screen->info.vram_size)
1834 gtt += vram - screen->info.vram_size;
1835
1836 /* Now we just need to check if we have enough GTT. */
1837 return gtt < screen->info.gart_size * 0.7;
1838 }
1839
1840 /**
1841 * Add a buffer to the buffer list for the given command stream (CS).
1842 *
1843 * All buffers used by a CS must be added to the list. This tells the kernel
1844 * driver which buffers are used by GPU commands. Other buffers can
1845 * be swapped out (not accessible) during execution.
1846 *
1847 * The buffer list becomes empty after every context flush and must be
1848 * rebuilt.
1849 */
1850 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1851 struct radeon_cmdbuf *cs,
1852 struct si_resource *bo,
1853 enum radeon_bo_usage usage,
1854 enum radeon_bo_priority priority)
1855 {
1856 assert(usage);
1857 sctx->ws->cs_add_buffer(
1858 cs, bo->buf,
1859 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1860 bo->domains, priority);
1861 }
1862
1863 /**
1864 * Same as above, but also checks memory usage and flushes the context
1865 * accordingly.
1866 *
1867 * When this SHOULD NOT be used:
1868 *
1869 * - if si_context_add_resource_size has been called for the buffer
1870 * followed by *_need_cs_space for checking the memory usage
1871 *
1872 * - if si_need_dma_space has been called for the buffer
1873 *
1874 * - when emitting state packets and draw packets (because preceding packets
1875 * can't be re-emitted at that point)
1876 *
1877 * - if shader resource "enabled_mask" is not up-to-date or there is
1878 * a different constraint disallowing a context flush
1879 */
1880 static inline void
1881 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1882 struct si_resource *bo,
1883 enum radeon_bo_usage usage,
1884 enum radeon_bo_priority priority,
1885 bool check_mem)
1886 {
1887 if (check_mem &&
1888 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1889 sctx->vram + bo->vram_usage,
1890 sctx->gtt + bo->gart_usage))
1891 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1892
1893 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1894 }
1895
1896 static inline bool si_compute_prim_discard_enabled(struct si_context *sctx)
1897 {
1898 return sctx->prim_discard_vertex_count_threshold != UINT_MAX;
1899 }
1900
1901 static inline unsigned si_get_wave_size(struct si_screen *sscreen,
1902 enum pipe_shader_type shader_type,
1903 bool ngg, bool es)
1904 {
1905 if (shader_type == PIPE_SHADER_COMPUTE)
1906 return sscreen->compute_wave_size;
1907 else if (shader_type == PIPE_SHADER_FRAGMENT)
1908 return sscreen->ps_wave_size;
1909 else if ((shader_type == PIPE_SHADER_VERTEX && es && !ngg) ||
1910 (shader_type == PIPE_SHADER_TESS_EVAL && es && !ngg) ||
1911 (shader_type == PIPE_SHADER_GEOMETRY && !ngg)) /* legacy GS only supports Wave64 */
1912 return 64;
1913 else
1914 return sscreen->ge_wave_size;
1915 }
1916
1917 static inline unsigned si_get_shader_wave_size(struct si_shader *shader)
1918 {
1919 return si_get_wave_size(shader->selector->screen, shader->selector->type,
1920 shader->key.as_ngg, shader->key.as_es);
1921 }
1922
1923 #define PRINT_ERR(fmt, args...) \
1924 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1925
1926 #endif