projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: delay adding BOs at the beginning of IBs until the first draw
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
56
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
69 #define SI_CONTEXT_INV_SMEM_L1 (1 << 4)
70 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
71 #define SI_CONTEXT_INV_VMEM_L1 (1 << 5)
72 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
73 #define SI_CONTEXT_INV_GLOBAL_L2 (1 << 6)
74 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
75 * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
76 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2 (1 << 7)
77 /* Writeback & invalidate the L2 metadata cache. It can only be coupled with
78 * a CB or DB flush. */
79 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
80 /* Framebuffer caches. */
81 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
82 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
83 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
84 /* Engine synchronization. */
85 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
86 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
87 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
88 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
89 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
90
91 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
92 #define SI_PREFETCH_LS (1 << 1)
93 #define SI_PREFETCH_HS (1 << 2)
94 #define SI_PREFETCH_ES (1 << 3)
95 #define SI_PREFETCH_GS (1 << 4)
96 #define SI_PREFETCH_VS (1 << 5)
97 #define SI_PREFETCH_PS (1 << 6)
98
99 #define SI_MAX_BORDER_COLORS 4096
100 #define SI_MAX_VIEWPORTS 16
101 #define SIX_BITS 0x3F
102 #define SI_MAP_BUFFER_ALIGNMENT 64
103 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
104
105 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
106 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
107 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
108 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
109 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
110 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
111 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
112 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
113 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
114 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
115
116 enum si_clear_code
117 {
118 DCC_CLEAR_COLOR_0000 = 0x00000000,
119 DCC_CLEAR_COLOR_0001 = 0x40404040,
120 DCC_CLEAR_COLOR_1110 = 0x80808080,
121 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
122 DCC_CLEAR_COLOR_REG = 0x20202020,
123 DCC_UNCOMPRESSED = 0xFFFFFFFF,
124 };
125
126 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
127
128 /* Debug flags. */
129 enum {
130 /* Shader logging options: */
131 DBG_VS = PIPE_SHADER_VERTEX,
132 DBG_PS = PIPE_SHADER_FRAGMENT,
133 DBG_GS = PIPE_SHADER_GEOMETRY,
134 DBG_TCS = PIPE_SHADER_TESS_CTRL,
135 DBG_TES = PIPE_SHADER_TESS_EVAL,
136 DBG_CS = PIPE_SHADER_COMPUTE,
137 DBG_NO_IR,
138 DBG_NO_TGSI,
139 DBG_NO_ASM,
140 DBG_PREOPT_IR,
141
142 /* Shader compiler options the shader cache should be aware of: */
143 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
144 DBG_UNSAFE_MATH,
145 DBG_SI_SCHED,
146 DBG_GISEL,
147
148 /* Shader compiler options (with no effect on the shader cache): */
149 DBG_CHECK_IR,
150 DBG_NIR,
151 DBG_MONOLITHIC_SHADERS,
152 DBG_NO_OPT_VARIANT,
153
154 /* Information logging options: */
155 DBG_INFO,
156 DBG_TEX,
157 DBG_COMPUTE,
158 DBG_VM,
159
160 /* Driver options: */
161 DBG_FORCE_DMA,
162 DBG_NO_ASYNC_DMA,
163 DBG_NO_WC,
164 DBG_CHECK_VM,
165 DBG_RESERVE_VMID,
166 DBG_ZERO_VRAM,
167
168 /* 3D engine options: */
169 DBG_SWITCH_ON_EOP,
170 DBG_NO_OUT_OF_ORDER,
171 DBG_NO_DPBB,
172 DBG_NO_DFSM,
173 DBG_DPBB,
174 DBG_DFSM,
175 DBG_NO_HYPERZ,
176 DBG_NO_RB_PLUS,
177 DBG_NO_2D_TILING,
178 DBG_NO_TILING,
179 DBG_NO_DCC,
180 DBG_NO_DCC_CLEAR,
181 DBG_NO_DCC_FB,
182 DBG_NO_DCC_MSAA,
183 DBG_NO_FMASK,
184
185 /* Tests: */
186 DBG_TEST_DMA,
187 DBG_TEST_VMFAULT_CP,
188 DBG_TEST_VMFAULT_SDMA,
189 DBG_TEST_VMFAULT_SHADER,
190 DBG_TEST_DMA_PERF,
191 DBG_TEST_GDS,
192 DBG_TEST_GDS_MM,
193 DBG_TEST_GDS_OA_MM,
194 };
195
196 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
197 #define DBG(name) (1ull << DBG_##name)
198
199 enum si_cache_policy {
200 L2_BYPASS,
201 L2_STREAM, /* same as SLC=1 */
202 L2_LRU, /* same as SLC=0 */
203 };
204
205 enum si_coherency {
206 SI_COHERENCY_NONE, /* no cache flushes needed */
207 SI_COHERENCY_SHADER,
208 SI_COHERENCY_CB_META,
209 SI_COHERENCY_CP,
210 };
211
212 struct si_compute;
213 struct hash_table;
214 struct u_suballocator;
215
216 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
217 * at the moment.
218 */
219 struct si_resource {
220 struct threaded_resource b;
221
222 /* Winsys objects. */
223 struct pb_buffer *buf;
224 uint64_t gpu_address;
225 /* Memory usage if the buffer placement is optimal. */
226 uint64_t vram_usage;
227 uint64_t gart_usage;
228
229 /* Resource properties. */
230 uint64_t bo_size;
231 unsigned bo_alignment;
232 enum radeon_bo_domain domains;
233 enum radeon_bo_flag flags;
234 unsigned bind_history;
235 int max_forced_staging_uploads;
236
237 /* The buffer range which is initialized (with a write transfer,
238 * streamout, DMA, or as a random access target). The rest of
239 * the buffer is considered invalid and can be mapped unsynchronized.
240 *
241 * This allows unsychronized mapping of a buffer range which hasn't
242 * been used yet. It's for applications which forget to use
243 * the unsynchronized map flag and expect the driver to figure it out.
244 */
245 struct util_range valid_buffer_range;
246
247 /* For buffers only. This indicates that a write operation has been
248 * performed by TC L2, but the cache hasn't been flushed.
249 * Any hw block which doesn't use or bypasses TC L2 should check this
250 * flag and flush the cache before using the buffer.
251 *
252 * For example, TC L2 must be flushed if a buffer which has been
253 * modified by a shader store instruction is about to be used as
254 * an index buffer. The reason is that VGT DMA index fetching doesn't
255 * use TC L2.
256 */
257 bool TC_L2_dirty;
258
259 /* Whether this resource is referenced by bindless handles. */
260 bool texture_handle_allocated;
261 bool image_handle_allocated;
262
263 /* Whether the resource has been exported via resource_get_handle. */
264 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
265 };
266
267 struct si_transfer {
268 struct threaded_transfer b;
269 struct si_resource *staging;
270 unsigned offset;
271 };
272
273 struct si_texture {
274 struct si_resource buffer;
275
276 struct radeon_surf surface;
277 uint64_t size;
278 struct si_texture *flushed_depth_texture;
279
280 /* One texture allocation can contain these buffers:
281 * - image (pixel data)
282 * - FMASK buffer (MSAA compression)
283 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
284 * - HTILE buffer (Z/S compression and fast Z/S clear)
285 * - DCC buffer (color compression and new fast color clear)
286 * - displayable DCC buffer (if the DCC buffer is not displayable)
287 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
288 */
289 uint64_t fmask_offset;
290 uint64_t cmask_offset;
291 uint64_t cmask_base_address_reg;
292 struct si_resource *cmask_buffer;
293 uint64_t dcc_offset; /* 0 = disabled */
294 uint64_t display_dcc_offset;
295 uint64_t dcc_retile_map_offset;
296 unsigned cb_color_info; /* fast clear enable bit */
297 unsigned color_clear_value[2];
298 unsigned last_msaa_resolve_target_micro_mode;
299 unsigned num_level0_transfers;
300
301 /* Depth buffer compression and fast clear. */
302 uint64_t htile_offset;
303 float depth_clear_value;
304 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
305 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
306 enum pipe_format db_render_format:16;
307 uint8_t stencil_clear_value;
308 bool tc_compatible_htile:1;
309 bool depth_cleared:1; /* if it was cleared at least once */
310 bool stencil_cleared:1; /* if it was cleared at least once */
311 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
312 bool is_depth:1;
313 bool db_compatible:1;
314 bool can_sample_z:1;
315 bool can_sample_s:1;
316
317 /* We need to track DCC dirtiness, because st/dri usually calls
318 * flush_resource twice per frame (not a bug) and we don't wanna
319 * decompress DCC twice. Also, the dirty tracking must be done even
320 * if DCC isn't used, because it's required by the DCC usage analysis
321 * for a possible future enablement.
322 */
323 bool separate_dcc_dirty:1;
324 /* Statistics gathering for the DCC enablement heuristic. */
325 bool dcc_gather_statistics:1;
326 /* Counter that should be non-zero if the texture is bound to a
327 * framebuffer.
328 */
329 unsigned framebuffers_bound;
330 /* Whether the texture is a displayable back buffer and needs DCC
331 * decompression, which is expensive. Therefore, it's enabled only
332 * if statistics suggest that it will pay off and it's allocated
333 * separately. It can't be bound as a sampler by apps. Limited to
334 * target == 2D and last_level == 0. If enabled, dcc_offset contains
335 * the absolute GPUVM address, not the relative one.
336 */
337 struct si_resource *dcc_separate_buffer;
338 /* When DCC is temporarily disabled, the separate buffer is here. */
339 struct si_resource *last_dcc_separate_buffer;
340 /* Estimate of how much this color buffer is written to in units of
341 * full-screen draws: ps_invocations / (width * height)
342 * Shader kills, late Z, and blending with trivial discards make it
343 * inaccurate (we need to count CB updates, not PS invocations).
344 */
345 unsigned ps_draw_ratio;
346 /* The number of clears since the last DCC usage analysis. */
347 unsigned num_slow_clears;
348 };
349
350 struct si_surface {
351 struct pipe_surface base;
352
353 /* These can vary with block-compressed textures. */
354 uint16_t width0;
355 uint16_t height0;
356
357 bool color_initialized:1;
358 bool depth_initialized:1;
359
360 /* Misc. color flags. */
361 bool color_is_int8:1;
362 bool color_is_int10:1;
363 bool dcc_incompatible:1;
364
365 /* Color registers. */
366 unsigned cb_color_info;
367 unsigned cb_color_view;
368 unsigned cb_color_attrib;
369 unsigned cb_color_attrib2; /* GFX9 and later */
370 unsigned cb_dcc_control; /* VI and later */
371 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
372 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
373 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
374 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
375
376 /* DB registers. */
377 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
378 uint64_t db_stencil_base;
379 uint64_t db_htile_data_base;
380 unsigned db_depth_info;
381 unsigned db_z_info;
382 unsigned db_z_info2; /* GFX9+ */
383 unsigned db_depth_view;
384 unsigned db_depth_size;
385 unsigned db_depth_slice;
386 unsigned db_stencil_info;
387 unsigned db_stencil_info2; /* GFX9+ */
388 unsigned db_htile_surface;
389 };
390
391 struct si_mmio_counter {
392 unsigned busy;
393 unsigned idle;
394 };
395
396 union si_mmio_counters {
397 struct {
398 /* For global GPU load including SDMA. */
399 struct si_mmio_counter gpu;
400
401 /* GRBM_STATUS */
402 struct si_mmio_counter spi;
403 struct si_mmio_counter gui;
404 struct si_mmio_counter ta;
405 struct si_mmio_counter gds;
406 struct si_mmio_counter vgt;
407 struct si_mmio_counter ia;
408 struct si_mmio_counter sx;
409 struct si_mmio_counter wd;
410 struct si_mmio_counter bci;
411 struct si_mmio_counter sc;
412 struct si_mmio_counter pa;
413 struct si_mmio_counter db;
414 struct si_mmio_counter cp;
415 struct si_mmio_counter cb;
416
417 /* SRBM_STATUS2 */
418 struct si_mmio_counter sdma;
419
420 /* CP_STAT */
421 struct si_mmio_counter pfp;
422 struct si_mmio_counter meq;
423 struct si_mmio_counter me;
424 struct si_mmio_counter surf_sync;
425 struct si_mmio_counter cp_dma;
426 struct si_mmio_counter scratch_ram;
427 } named;
428 unsigned array[0];
429 };
430
431 struct si_memory_object {
432 struct pipe_memory_object b;
433 struct pb_buffer *buf;
434 uint32_t stride;
435 };
436
437 /* Saved CS data for debugging features. */
438 struct radeon_saved_cs {
439 uint32_t *ib;
440 unsigned num_dw;
441
442 struct radeon_bo_list_item *bo_list;
443 unsigned bo_count;
444 };
445
446 struct si_screen {
447 struct pipe_screen b;
448 struct radeon_winsys *ws;
449 struct disk_cache *disk_shader_cache;
450
451 struct radeon_info info;
452 uint64_t debug_flags;
453 char renderer_string[183];
454
455 unsigned pa_sc_raster_config;
456 unsigned pa_sc_raster_config_1;
457 unsigned se_tile_repeat;
458 unsigned gs_table_depth;
459 unsigned tess_offchip_block_dw_size;
460 unsigned tess_offchip_ring_size;
461 unsigned tess_factor_ring_size;
462 unsigned vgt_hs_offchip_param;
463 unsigned eqaa_force_coverage_samples;
464 unsigned eqaa_force_z_samples;
465 unsigned eqaa_force_color_samples;
466 bool has_clear_state;
467 bool has_distributed_tess;
468 bool has_draw_indirect_multi;
469 bool has_out_of_order_rast;
470 bool assume_no_z_fights;
471 bool commutative_blend_add;
472 bool clear_db_cache_before_clear;
473 bool has_msaa_sample_loc_bug;
474 bool has_ls_vgpr_init_bug;
475 bool has_dcc_constant_encode;
476 bool dpbb_allowed;
477 bool dfsm_allowed;
478 bool llvm_has_working_vgpr_indexing;
479
480 /* Whether shaders are monolithic (1-part) or separate (3-part). */
481 bool use_monolithic_shaders;
482 bool record_llvm_ir;
483 bool has_rbplus; /* if RB+ registers exist */
484 bool rbplus_allowed; /* if RB+ is allowed */
485 bool dcc_msaa_allowed;
486 bool cpdma_prefetch_writes_memory;
487
488 struct slab_parent_pool pool_transfers;
489
490 /* Texture filter settings. */
491 int force_aniso; /* -1 = disabled */
492
493 /* Auxiliary context. Mainly used to initialize resources.
494 * It must be locked prior to using and flushed before unlocking. */
495 struct pipe_context *aux_context;
496 mtx_t aux_context_lock;
497
498 /* This must be in the screen, because UE4 uses one context for
499 * compilation and another one for rendering.
500 */
501 unsigned num_compilations;
502 /* Along with ST_DEBUG=precompile, this should show if applications
503 * are loading shaders on demand. This is a monotonic counter.
504 */
505 unsigned num_shaders_created;
506 unsigned num_shader_cache_hits;
507
508 /* GPU load thread. */
509 mtx_t gpu_load_mutex;
510 thrd_t gpu_load_thread;
511 union si_mmio_counters mmio_counters;
512 volatile unsigned gpu_load_stop_thread; /* bool */
513
514 /* Performance counters. */
515 struct si_perfcounters *perfcounters;
516
517 /* If pipe_screen wants to recompute and re-emit the framebuffer,
518 * sampler, and image states of all contexts, it should atomically
519 * increment this.
520 *
521 * Each context will compare this with its own last known value of
522 * the counter before drawing and re-emit the states accordingly.
523 */
524 unsigned dirty_tex_counter;
525
526 /* Atomically increment this counter when an existing texture's
527 * metadata is enabled or disabled in a way that requires changing
528 * contexts' compressed texture binding masks.
529 */
530 unsigned compressed_colortex_counter;
531
532 struct {
533 /* Context flags to set so that all writes from earlier jobs
534 * in the CP are seen by L2 clients.
535 */
536 unsigned cp_to_L2;
537
538 /* Context flags to set so that all writes from earlier jobs
539 * that end in L2 are seen by CP.
540 */
541 unsigned L2_to_cp;
542 } barrier_flags;
543
544 mtx_t shader_parts_mutex;
545 struct si_shader_part *vs_prologs;
546 struct si_shader_part *tcs_epilogs;
547 struct si_shader_part *gs_prologs;
548 struct si_shader_part *ps_prologs;
549 struct si_shader_part *ps_epilogs;
550
551 /* Shader cache in memory.
552 *
553 * Design & limitations:
554 * - The shader cache is per screen (= per process), never saved to
555 * disk, and skips redundant shader compilations from TGSI to bytecode.
556 * - It can only be used with one-variant-per-shader support, in which
557 * case only the main (typically middle) part of shaders is cached.
558 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
559 * variants of VS and TES are cached, so LS and ES aren't.
560 * - GS and CS aren't cached, but it's certainly possible to cache
561 * those as well.
562 */
563 mtx_t shader_cache_mutex;
564 struct hash_table *shader_cache;
565
566 /* Shader compiler queue for multithreaded compilation. */
567 struct util_queue shader_compiler_queue;
568 /* Use at most 3 normal compiler threads on quadcore and better.
569 * Hyperthreaded CPUs report the number of threads, but we want
570 * the number of cores. We only need this many threads for shader-db. */
571 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
572
573 struct util_queue shader_compiler_queue_low_priority;
574 /* Use at most 2 low priority threads on quadcore and better.
575 * We want to minimize the impact on multithreaded Mesa. */
576 struct ac_llvm_compiler compiler_lowp[10];
577 };
578
579 struct si_blend_color {
580 struct pipe_blend_color state;
581 bool any_nonzeros;
582 };
583
584 struct si_sampler_view {
585 struct pipe_sampler_view base;
586 /* [0..7] = image descriptor
587 * [4..7] = buffer descriptor */
588 uint32_t state[8];
589 uint32_t fmask_state[8];
590 const struct legacy_surf_level *base_level_info;
591 ubyte base_level;
592 ubyte block_width;
593 bool is_stencil_sampler;
594 bool is_integer;
595 bool dcc_incompatible;
596 };
597
598 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
599
600 struct si_sampler_state {
601 #ifdef DEBUG
602 unsigned magic;
603 #endif
604 uint32_t val[4];
605 uint32_t integer_val[4];
606 uint32_t upgraded_depth_val[4];
607 };
608
609 struct si_cs_shader_state {
610 struct si_compute *program;
611 struct si_compute *emitted_program;
612 unsigned offset;
613 bool initialized;
614 bool uses_scratch;
615 };
616
617 struct si_samplers {
618 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
619 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
620
621 /* The i-th bit is set if that element is enabled (non-NULL resource). */
622 unsigned enabled_mask;
623 uint32_t needs_depth_decompress_mask;
624 uint32_t needs_color_decompress_mask;
625 };
626
627 struct si_images {
628 struct pipe_image_view views[SI_NUM_IMAGES];
629 uint32_t needs_color_decompress_mask;
630 unsigned enabled_mask;
631 };
632
633 struct si_framebuffer {
634 struct pipe_framebuffer_state state;
635 unsigned colorbuf_enabled_4bit;
636 unsigned spi_shader_col_format;
637 unsigned spi_shader_col_format_alpha;
638 unsigned spi_shader_col_format_blend;
639 unsigned spi_shader_col_format_blend_alpha;
640 ubyte nr_samples:5; /* at most 16xAA */
641 ubyte log_samples:3; /* at most 4 = 16xAA */
642 ubyte nr_color_samples; /* at most 8xAA */
643 ubyte compressed_cb_mask;
644 ubyte uncompressed_cb_mask;
645 ubyte color_is_int8;
646 ubyte color_is_int10;
647 ubyte dirty_cbufs;
648 ubyte dcc_overwrite_combiner_watermark;
649 bool dirty_zsbuf;
650 bool any_dst_linear;
651 bool CB_has_shader_readable_metadata;
652 bool DB_has_shader_readable_metadata;
653 bool all_DCC_pipe_aligned;
654 };
655
656 enum si_quant_mode {
657 /* This is the list we want to support. */
658 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
659 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
660 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
661 };
662
663 struct si_signed_scissor {
664 int minx;
665 int miny;
666 int maxx;
667 int maxy;
668 enum si_quant_mode quant_mode;
669 };
670
671 struct si_scissors {
672 unsigned dirty_mask;
673 struct pipe_scissor_state states[SI_MAX_VIEWPORTS];
674 };
675
676 struct si_viewports {
677 unsigned dirty_mask;
678 unsigned depth_range_dirty_mask;
679 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
680 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
681 };
682
683 struct si_clip_state {
684 struct pipe_clip_state state;
685 bool any_nonzeros;
686 };
687
688 struct si_streamout_target {
689 struct pipe_stream_output_target b;
690
691 /* The buffer where BUFFER_FILLED_SIZE is stored. */
692 struct si_resource *buf_filled_size;
693 unsigned buf_filled_size_offset;
694 bool buf_filled_size_valid;
695
696 unsigned stride_in_dw;
697 };
698
699 struct si_streamout {
700 bool begin_emitted;
701
702 unsigned enabled_mask;
703 unsigned num_targets;
704 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
705
706 unsigned append_bitmask;
707 bool suspended;
708
709 /* External state which comes from the vertex shader,
710 * it must be set explicitly when binding a shader. */
711 uint16_t *stride_in_dw;
712 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
713
714 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
715 unsigned hw_enabled_mask;
716
717 /* The state of VGT_STRMOUT_(CONFIG|EN). */
718 bool streamout_enabled;
719 bool prims_gen_query_enabled;
720 int num_prims_gen_queries;
721 };
722
723 /* A shader state consists of the shader selector, which is a constant state
724 * object shared by multiple contexts and shouldn't be modified, and
725 * the current shader variant selected for this context.
726 */
727 struct si_shader_ctx_state {
728 struct si_shader_selector *cso;
729 struct si_shader *current;
730 };
731
732 #define SI_NUM_VGT_PARAM_KEY_BITS 12
733 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
734
735 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
736 * Some fields are set by state-change calls, most are set by draw_vbo.
737 */
738 union si_vgt_param_key {
739 struct {
740 #ifdef PIPE_ARCH_LITTLE_ENDIAN
741 unsigned prim:4;
742 unsigned uses_instancing:1;
743 unsigned multi_instances_smaller_than_primgroup:1;
744 unsigned primitive_restart:1;
745 unsigned count_from_stream_output:1;
746 unsigned line_stipple_enabled:1;
747 unsigned uses_tess:1;
748 unsigned tess_uses_prim_id:1;
749 unsigned uses_gs:1;
750 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
751 #else /* PIPE_ARCH_BIG_ENDIAN */
752 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
753 unsigned uses_gs:1;
754 unsigned tess_uses_prim_id:1;
755 unsigned uses_tess:1;
756 unsigned line_stipple_enabled:1;
757 unsigned count_from_stream_output:1;
758 unsigned primitive_restart:1;
759 unsigned multi_instances_smaller_than_primgroup:1;
760 unsigned uses_instancing:1;
761 unsigned prim:4;
762 #endif
763 } u;
764 uint32_t index;
765 };
766
767 struct si_texture_handle
768 {
769 unsigned desc_slot;
770 bool desc_dirty;
771 struct pipe_sampler_view *view;
772 struct si_sampler_state sstate;
773 };
774
775 struct si_image_handle
776 {
777 unsigned desc_slot;
778 bool desc_dirty;
779 struct pipe_image_view view;
780 };
781
782 struct si_saved_cs {
783 struct pipe_reference reference;
784 struct si_context *ctx;
785 struct radeon_saved_cs gfx;
786 struct si_resource *trace_buf;
787 unsigned trace_id;
788
789 unsigned gfx_last_dw;
790 bool flushed;
791 int64_t time_flush;
792 };
793
794 struct si_sdma_upload {
795 struct si_resource *dst;
796 struct si_resource *src;
797 unsigned src_offset;
798 unsigned dst_offset;
799 unsigned size;
800 };
801
802 struct si_context {
803 struct pipe_context b; /* base class */
804
805 enum radeon_family family;
806 enum chip_class chip_class;
807
808 struct radeon_winsys *ws;
809 struct radeon_winsys_ctx *ctx;
810 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
811 struct radeon_cmdbuf *dma_cs;
812 struct pipe_fence_handle *last_gfx_fence;
813 struct pipe_fence_handle *last_sdma_fence;
814 struct si_resource *eop_bug_scratch;
815 struct u_upload_mgr *cached_gtt_allocator;
816 struct threaded_context *tc;
817 struct u_suballocator *allocator_zeroed_memory;
818 struct slab_child_pool pool_transfers;
819 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
820 struct pipe_device_reset_callback device_reset_callback;
821 struct u_log_context *log;
822 void *query_result_shader;
823 struct blitter_context *blitter;
824 void *custom_dsa_flush;
825 void *custom_blend_resolve;
826 void *custom_blend_fmask_decompress;
827 void *custom_blend_eliminate_fastclear;
828 void *custom_blend_dcc_decompress;
829 void *vs_blit_pos;
830 void *vs_blit_pos_layered;
831 void *vs_blit_color;
832 void *vs_blit_color_layered;
833 void *vs_blit_texcoord;
834 void *cs_clear_buffer;
835 void *cs_copy_buffer;
836 void *cs_copy_image;
837 void *cs_copy_image_1d_array;
838 void *cs_clear_render_target;
839 void *cs_clear_render_target_1d_array;
840 void *cs_dcc_retile;
841 struct si_screen *screen;
842 struct pipe_debug_callback debug;
843 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
844 struct si_shader_ctx_state fixed_func_tcs_shader;
845 struct si_resource *wait_mem_scratch;
846 unsigned wait_mem_number;
847 uint16_t prefetch_L2_mask;
848
849 bool has_graphics;
850 bool gfx_flush_in_progress:1;
851 bool gfx_last_ib_is_busy:1;
852 bool compute_is_busy:1;
853
854 unsigned num_gfx_cs_flushes;
855 unsigned initial_gfx_cs_size;
856 unsigned gpu_reset_counter;
857 unsigned last_dirty_tex_counter;
858 unsigned last_compressed_colortex_counter;
859 unsigned last_num_draw_calls;
860 unsigned flags; /* flush flags */
861 /* Current unaccounted memory usage. */
862 uint64_t vram;
863 uint64_t gtt;
864
865 /* Atoms (direct states). */
866 union si_state_atoms atoms;
867 unsigned dirty_atoms; /* mask */
868 /* PM4 states (precomputed immutable states) */
869 unsigned dirty_states;
870 union si_state queued;
871 union si_state emitted;
872
873 /* Atom declarations. */
874 struct si_framebuffer framebuffer;
875 unsigned sample_locs_num_samples;
876 uint16_t sample_mask;
877 unsigned last_cb_target_mask;
878 struct si_blend_color blend_color;
879 struct si_clip_state clip_state;
880 struct si_shader_data shader_pointers;
881 struct si_stencil_ref stencil_ref;
882 struct si_scissors scissors;
883 struct si_streamout streamout;
884 struct si_viewports viewports;
885 unsigned num_window_rectangles;
886 bool window_rectangles_include;
887 struct pipe_scissor_state window_rectangles[4];
888
889 /* Precomputed states. */
890 struct si_pm4_state *init_config;
891 struct si_pm4_state *init_config_gs_rings;
892 bool init_config_has_vgt_flush;
893 struct si_pm4_state *vgt_shader_config[4];
894
895 /* shaders */
896 struct si_shader_ctx_state ps_shader;
897 struct si_shader_ctx_state gs_shader;
898 struct si_shader_ctx_state vs_shader;
899 struct si_shader_ctx_state tcs_shader;
900 struct si_shader_ctx_state tes_shader;
901 struct si_cs_shader_state cs_shader_state;
902
903 /* shader information */
904 struct si_vertex_elements *vertex_elements;
905 unsigned sprite_coord_enable;
906 unsigned cs_max_waves_per_sh;
907 bool flatshade;
908 bool do_update_shaders;
909
910 /* vertex buffer descriptors */
911 uint32_t *vb_descriptors_gpu_list;
912 struct si_resource *vb_descriptors_buffer;
913 unsigned vb_descriptors_offset;
914
915 /* shader descriptors */
916 struct si_descriptors descriptors[SI_NUM_DESCS];
917 unsigned descriptors_dirty;
918 unsigned shader_pointers_dirty;
919 unsigned shader_needs_decompress_mask;
920 struct si_buffer_resources rw_buffers;
921 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
922 struct si_samplers samplers[SI_NUM_SHADERS];
923 struct si_images images[SI_NUM_SHADERS];
924 bool bo_list_add_all_resident_resources;
925 bool bo_list_add_all_gfx_resources;
926 bool bo_list_add_all_compute_resources;
927
928 /* other shader resources */
929 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
930 struct pipe_resource *esgs_ring;
931 struct pipe_resource *gsvs_ring;
932 struct pipe_resource *tess_rings;
933 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
934 struct si_resource *border_color_buffer;
935 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
936 unsigned border_color_count;
937 unsigned num_vs_blit_sgprs;
938 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
939 uint32_t cs_user_data[4];
940
941 /* Vertex and index buffers. */
942 bool vertex_buffers_dirty;
943 bool vertex_buffer_pointer_dirty;
944 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
945
946 /* MSAA config state. */
947 int ps_iter_samples;
948 bool ps_uses_fbfetch;
949 bool smoothing_enabled;
950
951 /* DB render state. */
952 unsigned ps_db_shader_control;
953 unsigned dbcb_copy_sample;
954 bool dbcb_depth_copy_enabled:1;
955 bool dbcb_stencil_copy_enabled:1;
956 bool db_flush_depth_inplace:1;
957 bool db_flush_stencil_inplace:1;
958 bool db_depth_clear:1;
959 bool db_depth_disable_expclear:1;
960 bool db_stencil_clear:1;
961 bool db_stencil_disable_expclear:1;
962 bool occlusion_queries_disabled:1;
963 bool generate_mipmap_for_depth:1;
964
965 /* Emitted draw state. */
966 bool gs_tri_strip_adj_fix:1;
967 bool ls_vgpr_fix:1;
968 int last_index_size;
969 int last_base_vertex;
970 int last_start_instance;
971 int last_instance_count;
972 int last_drawid;
973 int last_sh_base_reg;
974 int last_primitive_restart_en;
975 int last_restart_index;
976 int last_prim;
977 int last_multi_vgt_param;
978 int last_rast_prim;
979 unsigned last_sc_line_stipple;
980 unsigned current_vs_state;
981 unsigned last_vs_state;
982 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
983
984 /* Scratch buffer */
985 struct si_resource *scratch_buffer;
986 unsigned scratch_waves;
987 unsigned spi_tmpring_size;
988
989 struct si_resource *compute_scratch_buffer;
990
991 /* Emitted derived tessellation state. */
992 /* Local shader (VS), or HS if LS-HS are merged. */
993 struct si_shader *last_ls;
994 struct si_shader_selector *last_tcs;
995 int last_num_tcs_input_cp;
996 int last_tes_sh_base;
997 bool last_tess_uses_primid;
998 unsigned last_num_patches;
999 int last_ls_hs_config;
1000
1001 /* Debug state. */
1002 bool is_debug;
1003 struct si_saved_cs *current_saved_cs;
1004 uint64_t dmesg_timestamp;
1005 unsigned apitrace_call_number;
1006
1007 /* Other state */
1008 bool need_check_render_feedback;
1009 bool decompression_enabled;
1010 bool dpbb_force_off;
1011 bool vs_writes_viewport_index;
1012 bool vs_disables_clipping_viewport;
1013
1014 /* Precomputed IA_MULTI_VGT_PARAM */
1015 union si_vgt_param_key ia_multi_vgt_param_key;
1016 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1017
1018 /* Bindless descriptors. */
1019 struct si_descriptors bindless_descriptors;
1020 struct util_idalloc bindless_used_slots;
1021 unsigned num_bindless_descriptors;
1022 bool bindless_descriptors_dirty;
1023 bool graphics_bindless_pointer_dirty;
1024 bool compute_bindless_pointer_dirty;
1025
1026 /* Allocated bindless handles */
1027 struct hash_table *tex_handles;
1028 struct hash_table *img_handles;
1029
1030 /* Resident bindless handles */
1031 struct util_dynarray resident_tex_handles;
1032 struct util_dynarray resident_img_handles;
1033
1034 /* Resident bindless handles which need decompression */
1035 struct util_dynarray resident_tex_needs_color_decompress;
1036 struct util_dynarray resident_img_needs_color_decompress;
1037 struct util_dynarray resident_tex_needs_depth_decompress;
1038
1039 /* Bindless state */
1040 bool uses_bindless_samplers;
1041 bool uses_bindless_images;
1042
1043 /* MSAA sample locations.
1044 * The first index is the sample index.
1045 * The second index is the coordinate: X, Y. */
1046 struct {
1047 float x1[1][2];
1048 float x2[2][2];
1049 float x4[4][2];
1050 float x8[8][2];
1051 float x16[16][2];
1052 } sample_positions;
1053 struct pipe_resource *sample_pos_buffer;
1054
1055 /* Misc stats. */
1056 unsigned num_draw_calls;
1057 unsigned num_decompress_calls;
1058 unsigned num_mrt_draw_calls;
1059 unsigned num_prim_restart_calls;
1060 unsigned num_spill_draw_calls;
1061 unsigned num_compute_calls;
1062 unsigned num_spill_compute_calls;
1063 unsigned num_dma_calls;
1064 unsigned num_cp_dma_calls;
1065 unsigned num_vs_flushes;
1066 unsigned num_ps_flushes;
1067 unsigned num_cs_flushes;
1068 unsigned num_cb_cache_flushes;
1069 unsigned num_db_cache_flushes;
1070 unsigned num_L2_invalidates;
1071 unsigned num_L2_writebacks;
1072 unsigned num_resident_handles;
1073 uint64_t num_alloc_tex_transfer_bytes;
1074 unsigned last_tex_ps_draw_ratio; /* for query */
1075 unsigned context_roll_counter;
1076
1077 /* Queries. */
1078 /* Maintain the list of active queries for pausing between IBs. */
1079 int num_occlusion_queries;
1080 int num_perfect_occlusion_queries;
1081 struct list_head active_queries;
1082 unsigned num_cs_dw_queries_suspend;
1083
1084 /* Render condition. */
1085 struct pipe_query *render_cond;
1086 unsigned render_cond_mode;
1087 bool render_cond_invert;
1088 bool render_cond_force_off; /* for u_blitter */
1089
1090 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1091 bool sdma_uploads_in_progress;
1092 struct si_sdma_upload *sdma_uploads;
1093 unsigned num_sdma_uploads;
1094 unsigned max_sdma_uploads;
1095
1096 /* Statistics gathering for the DCC enablement heuristic. It can't be
1097 * in si_texture because si_texture can be shared by multiple
1098 * contexts. This is for back buffers only. We shouldn't get too many
1099 * of those.
1100 *
1101 * X11 DRI3 rotates among a finite set of back buffers. They should
1102 * all fit in this array. If they don't, separate DCC might never be
1103 * enabled by DCC stat gathering.
1104 */
1105 struct {
1106 struct si_texture *tex;
1107 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1108 struct pipe_query *ps_stats[3];
1109 /* If all slots are used and another slot is needed,
1110 * the least recently used slot is evicted based on this. */
1111 int64_t last_use_timestamp;
1112 bool query_active;
1113 } dcc_stats[5];
1114
1115 /* Copy one resource to another using async DMA. */
1116 void (*dma_copy)(struct pipe_context *ctx,
1117 struct pipe_resource *dst,
1118 unsigned dst_level,
1119 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1120 struct pipe_resource *src,
1121 unsigned src_level,
1122 const struct pipe_box *src_box);
1123
1124 struct si_tracked_regs tracked_regs;
1125 };
1126
1127 /* cik_sdma.c */
1128 void cik_init_sdma_functions(struct si_context *sctx);
1129
1130 /* si_blit.c */
1131 enum si_blitter_op /* bitmask */
1132 {
1133 SI_SAVE_TEXTURES = 1,
1134 SI_SAVE_FRAMEBUFFER = 2,
1135 SI_SAVE_FRAGMENT_STATE = 4,
1136 SI_DISABLE_RENDER_COND = 8,
1137 };
1138
1139 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1140 void si_blitter_end(struct si_context *sctx);
1141 void si_init_blit_functions(struct si_context *sctx);
1142 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1143 void si_resource_copy_region(struct pipe_context *ctx,
1144 struct pipe_resource *dst,
1145 unsigned dst_level,
1146 unsigned dstx, unsigned dsty, unsigned dstz,
1147 struct pipe_resource *src,
1148 unsigned src_level,
1149 const struct pipe_box *src_box);
1150 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1151 void si_blit_decompress_depth(struct pipe_context *ctx,
1152 struct si_texture *texture,
1153 struct si_texture *staging,
1154 unsigned first_level, unsigned last_level,
1155 unsigned first_layer, unsigned last_layer,
1156 unsigned first_sample, unsigned last_sample);
1157
1158 /* si_buffer.c */
1159 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1160 struct pb_buffer *buf,
1161 enum radeon_bo_usage usage);
1162 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1163 struct si_resource *resource,
1164 unsigned usage);
1165 void si_init_resource_fields(struct si_screen *sscreen,
1166 struct si_resource *res,
1167 uint64_t size, unsigned alignment);
1168 bool si_alloc_resource(struct si_screen *sscreen,
1169 struct si_resource *res);
1170 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1171 unsigned flags, unsigned usage,
1172 unsigned size, unsigned alignment);
1173 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1174 unsigned flags, unsigned usage,
1175 unsigned size, unsigned alignment);
1176 void si_replace_buffer_storage(struct pipe_context *ctx,
1177 struct pipe_resource *dst,
1178 struct pipe_resource *src);
1179 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1180 void si_init_buffer_functions(struct si_context *sctx);
1181
1182 /* si_clear.c */
1183 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1184 bool vi_alpha_is_on_msb(enum pipe_format format);
1185 void vi_dcc_clear_level(struct si_context *sctx,
1186 struct si_texture *tex,
1187 unsigned level, unsigned clear_value);
1188 void si_init_clear_functions(struct si_context *sctx);
1189
1190 /* si_compute_blit.c */
1191 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1192 enum si_cache_policy cache_policy);
1193 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1194 uint64_t offset, uint64_t size, uint32_t *clear_value,
1195 uint32_t clear_value_size, enum si_coherency coher,
1196 bool force_cpdma);
1197 void si_copy_buffer(struct si_context *sctx,
1198 struct pipe_resource *dst, struct pipe_resource *src,
1199 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1200 void si_compute_copy_image(struct si_context *sctx,
1201 struct pipe_resource *dst,
1202 unsigned dst_level,
1203 struct pipe_resource *src,
1204 unsigned src_level,
1205 unsigned dstx, unsigned dsty, unsigned dstz,
1206 const struct pipe_box *src_box);
1207 void si_compute_clear_render_target(struct pipe_context *ctx,
1208 struct pipe_surface *dstsurf,
1209 const union pipe_color_union *color,
1210 unsigned dstx, unsigned dsty,
1211 unsigned width, unsigned height,
1212 bool render_condition_enabled);
1213 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1214 void si_init_compute_blit_functions(struct si_context *sctx);
1215
1216 /* si_cp_dma.c */
1217 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1218 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1219 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1220 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1221 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1222 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1223 SI_CPDMA_SKIP_SYNC_AFTER | \
1224 SI_CPDMA_SKIP_SYNC_BEFORE | \
1225 SI_CPDMA_SKIP_GFX_SYNC | \
1226 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1227
1228 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1229 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1230 struct pipe_resource *dst, uint64_t offset,
1231 uint64_t size, unsigned value, unsigned user_flags,
1232 enum si_coherency coher, enum si_cache_policy cache_policy);
1233 void si_cp_dma_copy_buffer(struct si_context *sctx,
1234 struct pipe_resource *dst, struct pipe_resource *src,
1235 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1236 unsigned user_flags, enum si_coherency coher,
1237 enum si_cache_policy cache_policy);
1238 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1239 uint64_t offset, unsigned size);
1240 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1241 void si_test_gds(struct si_context *sctx);
1242 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
1243 unsigned offset, unsigned size, unsigned dst_sel,
1244 unsigned engine, const void *data);
1245 void si_cp_copy_data(struct si_context *sctx,
1246 unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
1247 unsigned src_sel, struct si_resource *src, unsigned src_offset);
1248
1249 /* si_debug.c */
1250 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1251 struct radeon_saved_cs *saved, bool get_buffer_list);
1252 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1253 void si_destroy_saved_cs(struct si_saved_cs *scs);
1254 void si_auto_log_cs(void *data, struct u_log_context *log);
1255 void si_log_hw_flush(struct si_context *sctx);
1256 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1257 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1258 void si_init_debug_functions(struct si_context *sctx);
1259 void si_check_vm_faults(struct si_context *sctx,
1260 struct radeon_saved_cs *saved, enum ring_type ring);
1261 bool si_replace_shader(unsigned num, struct ac_shader_binary *binary);
1262
1263 /* si_dma.c */
1264 void si_init_dma_functions(struct si_context *sctx);
1265
1266 /* si_dma_cs.c */
1267 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
1268 uint64_t offset);
1269 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1270 uint64_t offset, uint64_t size, unsigned clear_value);
1271 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1272 struct si_resource *dst, struct si_resource *src);
1273 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1274 struct pipe_fence_handle **fence);
1275 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1276 uint64_t offset, uint64_t size, unsigned value);
1277
1278 /* si_fence.c */
1279 void si_cp_release_mem(struct si_context *ctx,
1280 unsigned event, unsigned event_flags,
1281 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1282 struct si_resource *buf, uint64_t va,
1283 uint32_t new_fence, unsigned query_type);
1284 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1285 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1286 uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
1287 void si_init_fence_functions(struct si_context *ctx);
1288 void si_init_screen_fence_functions(struct si_screen *screen);
1289 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1290 struct tc_unflushed_batch_token *tc_token);
1291
1292 /* si_get.c */
1293 void si_init_screen_get_functions(struct si_screen *sscreen);
1294
1295 /* si_gfx_cs.c */
1296 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1297 struct pipe_fence_handle **fence);
1298 void si_begin_new_gfx_cs(struct si_context *ctx);
1299 void si_need_gfx_cs_space(struct si_context *ctx);
1300 void si_unref_sdma_uploads(struct si_context *sctx);
1301
1302 /* si_gpu_load.c */
1303 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1304 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1305 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1306 uint64_t begin);
1307
1308 /* si_compute.c */
1309 void si_init_compute_functions(struct si_context *sctx);
1310
1311 /* si_perfcounters.c */
1312 void si_init_perfcounters(struct si_screen *screen);
1313 void si_destroy_perfcounters(struct si_screen *screen);
1314
1315 /* si_pipe.c */
1316 bool si_check_device_reset(struct si_context *sctx);
1317
1318 /* si_query.c */
1319 void si_init_screen_query_functions(struct si_screen *sscreen);
1320 void si_init_query_functions(struct si_context *sctx);
1321 void si_suspend_queries(struct si_context *sctx);
1322 void si_resume_queries(struct si_context *sctx);
1323
1324 /* si_shaderlib_tgsi.c */
1325 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1326 unsigned num_layers);
1327 void *si_create_fixed_func_tcs(struct si_context *sctx);
1328 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1329 unsigned num_dwords_per_thread,
1330 bool dst_stream_cache_policy, bool is_copy);
1331 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1332 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1333 void *si_clear_render_target_shader(struct pipe_context *ctx);
1334 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1335 void *si_create_dcc_retile_cs(struct pipe_context *ctx);
1336 void *si_create_query_result_cs(struct si_context *sctx);
1337
1338 /* si_test_dma.c */
1339 void si_test_dma(struct si_screen *sscreen);
1340
1341 /* si_test_clearbuffer.c */
1342 void si_test_dma_perf(struct si_screen *sscreen);
1343
1344 /* si_uvd.c */
1345 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1346 const struct pipe_video_codec *templ);
1347
1348 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1349 const struct pipe_video_buffer *tmpl);
1350
1351 /* si_viewport.c */
1352 void si_update_vs_viewport_state(struct si_context *ctx);
1353 void si_init_viewport_functions(struct si_context *ctx);
1354
1355 /* si_texture.c */
1356 bool si_prepare_for_dma_blit(struct si_context *sctx,
1357 struct si_texture *dst,
1358 unsigned dst_level, unsigned dstx,
1359 unsigned dsty, unsigned dstz,
1360 struct si_texture *src,
1361 unsigned src_level,
1362 const struct pipe_box *src_box);
1363 void si_eliminate_fast_color_clear(struct si_context *sctx,
1364 struct si_texture *tex);
1365 void si_texture_discard_cmask(struct si_screen *sscreen,
1366 struct si_texture *tex);
1367 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1368 struct pipe_resource *texture,
1369 struct si_texture **staging);
1370 void si_print_texture_info(struct si_screen *sscreen,
1371 struct si_texture *tex, struct u_log_context *log);
1372 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1373 const struct pipe_resource *templ);
1374 bool vi_dcc_formats_compatible(enum pipe_format format1,
1375 enum pipe_format format2);
1376 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1377 unsigned level,
1378 enum pipe_format view_format);
1379 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1380 struct pipe_resource *tex,
1381 unsigned level,
1382 enum pipe_format view_format);
1383 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1384 struct pipe_resource *texture,
1385 const struct pipe_surface *templ,
1386 unsigned width0, unsigned height0,
1387 unsigned width, unsigned height);
1388 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1389 void vi_separate_dcc_try_enable(struct si_context *sctx,
1390 struct si_texture *tex);
1391 void vi_separate_dcc_start_query(struct si_context *sctx,
1392 struct si_texture *tex);
1393 void vi_separate_dcc_stop_query(struct si_context *sctx,
1394 struct si_texture *tex);
1395 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1396 struct si_texture *tex);
1397 bool si_texture_disable_dcc(struct si_context *sctx,
1398 struct si_texture *tex);
1399 void si_init_screen_texture_functions(struct si_screen *sscreen);
1400 void si_init_context_texture_functions(struct si_context *sctx);
1401
1402
1403 /*
1404 * common helpers
1405 */
1406
1407 static inline struct si_resource *si_resource(struct pipe_resource *r)
1408 {
1409 return (struct si_resource*)r;
1410 }
1411
1412 static inline void
1413 si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1414 {
1415 pipe_resource_reference((struct pipe_resource **)ptr,
1416 (struct pipe_resource *)res);
1417 }
1418
1419 static inline void
1420 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1421 {
1422 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1423 }
1424
1425 static inline bool
1426 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1427 {
1428 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
1429 }
1430
1431 static inline unsigned
1432 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1433 {
1434 if (stencil)
1435 return tex->surface.u.legacy.stencil_tiling_index[level];
1436 else
1437 return tex->surface.u.legacy.tiling_index[level];
1438 }
1439
1440 static inline unsigned
1441 si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx)
1442 {
1443 /* Don't count the needed CS space exactly and just use an upper bound.
1444 *
1445 * Also reserve space for stopping queries at the end of IB, because
1446 * the number of active queries is unlimited in theory.
1447 */
1448 return 2048 + sctx->num_cs_dw_queries_suspend;
1449 }
1450
1451 static inline void
1452 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1453 {
1454 if (r) {
1455 /* Add memory usage for need_gfx_cs_space */
1456 sctx->vram += si_resource(r)->vram_usage;
1457 sctx->gtt += si_resource(r)->gart_usage;
1458 }
1459 }
1460
1461 static inline void
1462 si_invalidate_draw_sh_constants(struct si_context *sctx)
1463 {
1464 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1465 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1466 }
1467
1468 static inline unsigned
1469 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1470 {
1471 return 1 << (atom - sctx->atoms.array);
1472 }
1473
1474 static inline void
1475 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1476 {
1477 unsigned bit = si_get_atom_bit(sctx, atom);
1478
1479 if (dirty)
1480 sctx->dirty_atoms |= bit;
1481 else
1482 sctx->dirty_atoms &= ~bit;
1483 }
1484
1485 static inline bool
1486 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1487 {
1488 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1489 }
1490
1491 static inline void
1492 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1493 {
1494 si_set_atom_dirty(sctx, atom, true);
1495 }
1496
1497 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1498 {
1499 if (sctx->gs_shader.cso)
1500 return &sctx->gs_shader;
1501 if (sctx->tes_shader.cso)
1502 return &sctx->tes_shader;
1503
1504 return &sctx->vs_shader;
1505 }
1506
1507 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1508 {
1509 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1510
1511 return vs->cso ? &vs->cso->info : NULL;
1512 }
1513
1514 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1515 {
1516 if (sctx->gs_shader.cso)
1517 return sctx->gs_shader.cso->gs_copy_shader;
1518
1519 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1520 return vs->current ? vs->current : NULL;
1521 }
1522
1523 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1524 unsigned processor)
1525 {
1526 return sscreen->debug_flags & (1 << processor);
1527 }
1528
1529 static inline bool si_get_strmout_en(struct si_context *sctx)
1530 {
1531 return sctx->streamout.streamout_enabled ||
1532 sctx->streamout.prims_gen_query_enabled;
1533 }
1534
1535 static inline unsigned
1536 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1537 {
1538 unsigned alignment, tcc_cache_line_size;
1539
1540 /* If the upload size is less than the cache line size (e.g. 16, 32),
1541 * the whole thing will fit into a cache line if we align it to its size.
1542 * The idea is that multiple small uploads can share a cache line.
1543 * If the upload size is greater, align it to the cache line size.
1544 */
1545 alignment = util_next_power_of_two(upload_size);
1546 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1547 return MIN2(alignment, tcc_cache_line_size);
1548 }
1549
1550 static inline void
1551 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1552 {
1553 if (pipe_reference(&(*dst)->reference, &src->reference))
1554 si_destroy_saved_cs(*dst);
1555
1556 *dst = src;
1557 }
1558
1559 static inline void
1560 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1561 bool shaders_read_metadata, bool dcc_pipe_aligned)
1562 {
1563 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1564 SI_CONTEXT_INV_VMEM_L1;
1565
1566 if (sctx->chip_class >= GFX9) {
1567 /* Single-sample color is coherent with shaders on GFX9, but
1568 * L2 metadata must be flushed if shaders read metadata.
1569 * (DCC, CMASK).
1570 */
1571 if (num_samples >= 2 ||
1572 (shaders_read_metadata && !dcc_pipe_aligned))
1573 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1574 else if (shaders_read_metadata)
1575 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1576 } else {
1577 /* SI-CI-VI */
1578 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1579 }
1580 }
1581
1582 static inline void
1583 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1584 bool include_stencil, bool shaders_read_metadata)
1585 {
1586 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1587 SI_CONTEXT_INV_VMEM_L1;
1588
1589 if (sctx->chip_class >= GFX9) {
1590 /* Single-sample depth (not stencil) is coherent with shaders
1591 * on GFX9, but L2 metadata must be flushed if shaders read
1592 * metadata.
1593 */
1594 if (num_samples >= 2 || include_stencil)
1595 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1596 else if (shaders_read_metadata)
1597 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1598 } else {
1599 /* SI-CI-VI */
1600 sctx->flags |= SI_CONTEXT_INV_GLOBAL_L2;
1601 }
1602 }
1603
1604 static inline bool
1605 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1606 {
1607 return (stencil_sampler && tex->can_sample_s) ||
1608 (!stencil_sampler && tex->can_sample_z);
1609 }
1610
1611 static inline bool
1612 si_htile_enabled(struct si_texture *tex, unsigned level)
1613 {
1614 return tex->htile_offset && level == 0;
1615 }
1616
1617 static inline bool
1618 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level)
1619 {
1620 assert(!tex->tc_compatible_htile || tex->htile_offset);
1621 return tex->tc_compatible_htile && level == 0;
1622 }
1623
1624 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1625 {
1626 if (sctx->ps_uses_fbfetch)
1627 return sctx->framebuffer.nr_color_samples;
1628
1629 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1630 }
1631
1632 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1633 {
1634 if (sctx->queued.named.rasterizer->rasterizer_discard)
1635 return 0;
1636
1637 struct si_shader_selector *ps = sctx->ps_shader.cso;
1638 if (!ps)
1639 return 0;
1640
1641 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1642 sctx->queued.named.blend->cb_target_mask;
1643
1644 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1645 colormask &= ps->colors_written_4bit;
1646 else if (!ps->colors_written_4bit)
1647 colormask = 0; /* color0 writes all cbufs, but it's not written */
1648
1649 return colormask;
1650 }
1651
1652 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1653 (1 << PIPE_PRIM_LINE_LOOP) | \
1654 (1 << PIPE_PRIM_LINE_STRIP) | \
1655 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1656 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1657
1658 static inline bool util_prim_is_lines(unsigned prim)
1659 {
1660 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1661 }
1662
1663 static inline bool util_prim_is_points_or_lines(unsigned prim)
1664 {
1665 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1666 (1 << PIPE_PRIM_POINTS))) != 0;
1667 }
1668
1669 /**
1670 * Return true if there is enough memory in VRAM and GTT for the buffers
1671 * added so far.
1672 *
1673 * \param vram VRAM memory size not added to the buffer list yet
1674 * \param gtt GTT memory size not added to the buffer list yet
1675 */
1676 static inline bool
1677 radeon_cs_memory_below_limit(struct si_screen *screen,
1678 struct radeon_cmdbuf *cs,
1679 uint64_t vram, uint64_t gtt)
1680 {
1681 vram += cs->used_vram;
1682 gtt += cs->used_gart;
1683
1684 /* Anything that goes above the VRAM size should go to GTT. */
1685 if (vram > screen->info.vram_size)
1686 gtt += vram - screen->info.vram_size;
1687
1688 /* Now we just need to check if we have enough GTT. */
1689 return gtt < screen->info.gart_size * 0.7;
1690 }
1691
1692 /**
1693 * Add a buffer to the buffer list for the given command stream (CS).
1694 *
1695 * All buffers used by a CS must be added to the list. This tells the kernel
1696 * driver which buffers are used by GPU commands. Other buffers can
1697 * be swapped out (not accessible) during execution.
1698 *
1699 * The buffer list becomes empty after every context flush and must be
1700 * rebuilt.
1701 */
1702 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1703 struct radeon_cmdbuf *cs,
1704 struct si_resource *bo,
1705 enum radeon_bo_usage usage,
1706 enum radeon_bo_priority priority)
1707 {
1708 assert(usage);
1709 sctx->ws->cs_add_buffer(
1710 cs, bo->buf,
1711 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1712 bo->domains, priority);
1713 }
1714
1715 /**
1716 * Same as above, but also checks memory usage and flushes the context
1717 * accordingly.
1718 *
1719 * When this SHOULD NOT be used:
1720 *
1721 * - if si_context_add_resource_size has been called for the buffer
1722 * followed by *_need_cs_space for checking the memory usage
1723 *
1724 * - if si_need_dma_space has been called for the buffer
1725 *
1726 * - when emitting state packets and draw packets (because preceding packets
1727 * can't be re-emitted at that point)
1728 *
1729 * - if shader resource "enabled_mask" is not up-to-date or there is
1730 * a different constraint disallowing a context flush
1731 */
1732 static inline void
1733 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1734 struct si_resource *bo,
1735 enum radeon_bo_usage usage,
1736 enum radeon_bo_priority priority,
1737 bool check_mem)
1738 {
1739 if (check_mem &&
1740 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1741 sctx->vram + bo->vram_usage,
1742 sctx->gtt + bo->gart_usage))
1743 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1744
1745 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1746 }
1747
1748 #define PRINT_ERR(fmt, args...) \
1749 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1750
1751 #endif