src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef SI_PIPE_H
  27 #define SI_PIPE_H
  28
  29 #include "si_state.h"
  30 #include "util/u_queue.h"
  31
  32 #include <llvm-c/TargetMachine.h>
  33
  34 #ifdef PIPE_ARCH_BIG_ENDIAN
  35 #define SI_BIG_ENDIAN 1
  36 #else
  37 #define SI_BIG_ENDIAN 0
  38 #endif
  39
  40 /* The base vertex and primitive restart can be any number, but we must pick
  41  * one which will mean "unknown" for the purpose of state tracking and
  42  * the number shouldn't be a commonly-used one. */
  43 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  44 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  45 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  46 #define SI_GS_PER_ES 128
  47
  48 /* Instruction cache. */
  49 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  50 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  51 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  52 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  53 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  54 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  55 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  56 /* Framebuffer caches. */
  57 #define SI_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
  58 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
  59 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 6)
  60 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 7)
  61 /* Engine synchronization. */
  62 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 8)
  63 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  64 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  65 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 11)
  66 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 12)
  67
  68 #define SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER (SI_CONTEXT_FLUSH_AND_INV_CB | \
  69                                               SI_CONTEXT_FLUSH_AND_INV_CB_META | \
  70                                               SI_CONTEXT_FLUSH_AND_INV_DB | \
  71                                               SI_CONTEXT_FLUSH_AND_INV_DB_META)
  72
  73 #define SI_ENCODE_TRACE_POINT(id)       (0xcafe0000 | ((id) & 0xffff))
  74 #define SI_IS_TRACE_POINT(x)            (((x) & 0xcafe0000) == 0xcafe0000)
  75 #define SI_GET_TRACE_POINT_ID(x)        ((x) & 0xffff)
  76
  77 #define SI_MAX_BORDER_COLORS    4096
  78
  79 struct si_compute;
  80 struct hash_table;
  81 struct u_suballocator;
  82
  83 struct si_screen {
  84         struct r600_common_screen       b;
  85         unsigned                        gs_table_depth;
  86         unsigned                        tess_offchip_block_dw_size;
  87         bool                            has_distributed_tess;
  88         bool                            has_draw_indirect_multi;
  89
  90         /* Whether shaders are monolithic (1-part) or separate (3-part). */
  91         bool                            use_monolithic_shaders;
  92         bool                            record_llvm_ir;
  93
  94         pipe_mutex                      shader_parts_mutex;
  95         struct si_shader_part           *vs_prologs;
  96         struct si_shader_part           *vs_epilogs;
  97         struct si_shader_part           *tcs_epilogs;
  98         struct si_shader_part           *ps_prologs;
  99         struct si_shader_part           *ps_epilogs;
 100
 101         /* Shader cache in memory.
 102          *
 103          * Design & limitations:
 104          * - The shader cache is per screen (= per process), never saved to
 105          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 106          * - It can only be used with one-variant-per-shader support, in which
 107          *   case only the main (typically middle) part of shaders is cached.
 108          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 109          *   variants of VS and TES are cached, so LS and ES aren't.
 110          * - GS and CS aren't cached, but it's certainly possible to cache
 111          *   those as well.
 112          */
 113         pipe_mutex                      shader_cache_mutex;
 114         struct hash_table               *shader_cache;
 115
 116         /* Shader compiler queue for multithreaded compilation. */
 117         struct util_queue               shader_compiler_queue;
 118         LLVMTargetMachineRef            tm[4]; /* used by the queue only */
 119 };
 120
 121 struct si_blend_color {
 122         struct r600_atom                atom;
 123         struct pipe_blend_color         state;
 124 };
 125
 126 struct si_sampler_view {
 127         struct pipe_sampler_view        base;
 128         struct list_head                list;
 129         /* [0..7] = image descriptor
 130          * [4..7] = buffer descriptor */
 131         uint32_t                        state[8];
 132         uint32_t                        fmask_state[8];
 133         const struct radeon_surf_level  *base_level_info;
 134         unsigned                        base_level;
 135         unsigned                        block_width;
 136         bool is_stencil_sampler;
 137 };
 138
 139 struct si_sampler_state {
 140         uint32_t                        val[4];
 141 };
 142
 143 struct si_cs_shader_state {
 144         struct si_compute               *program;
 145         struct si_compute               *emitted_program;
 146         unsigned                        offset;
 147         bool                            initialized;
 148         bool                            uses_scratch;
 149 };
 150
 151 struct si_textures_info {
 152         struct si_sampler_views         views;
 153         uint32_t                        depth_texture_mask; /* which textures are depth */
 154         uint32_t                        compressed_colortex_mask;
 155 };
 156
 157 struct si_images_info {
 158         struct pipe_image_view          views[SI_NUM_IMAGES];
 159         uint32_t                        compressed_colortex_mask;
 160         unsigned                        enabled_mask;
 161 };
 162
 163 struct si_framebuffer {
 164         struct r600_atom                atom;
 165         struct pipe_framebuffer_state   state;
 166         unsigned                        nr_samples;
 167         unsigned                        log_samples;
 168         unsigned                        cb0_is_integer;
 169         unsigned                        compressed_cb_mask;
 170         unsigned                        spi_shader_col_format;
 171         unsigned                        spi_shader_col_format_alpha;
 172         unsigned                        spi_shader_col_format_blend;
 173         unsigned                        spi_shader_col_format_blend_alpha;
 174         unsigned                        color_is_int8; /* bitmask */
 175         unsigned                        dirty_cbufs;
 176         bool                            dirty_zsbuf;
 177         bool                            any_dst_linear;
 178 };
 179
 180 struct si_clip_state {
 181         struct r600_atom                atom;
 182         struct pipe_clip_state          state;
 183 };
 184
 185 struct si_sample_locs {
 186         struct r600_atom        atom;
 187         unsigned                nr_samples;
 188 };
 189
 190 struct si_sample_mask {
 191         struct r600_atom        atom;
 192         uint16_t                sample_mask;
 193 };
 194
 195 /* A shader state consists of the shader selector, which is a constant state
 196  * object shared by multiple contexts and shouldn't be modified, and
 197  * the current shader variant selected for this context.
 198  */
 199 struct si_shader_ctx_state {
 200         struct si_shader_selector       *cso;
 201         struct si_shader                *current;
 202 };
 203
 204 struct si_context {
 205         struct r600_common_context      b;
 206         struct blitter_context          *blitter;
 207         void                            *custom_dsa_flush;
 208         void                            *custom_blend_resolve;
 209         void                            *custom_blend_decompress;
 210         void                            *custom_blend_fastclear;
 211         void                            *custom_blend_dcc_decompress;
 212         struct si_screen                *screen;
 213
 214         struct radeon_winsys_cs         *ce_ib;
 215         struct radeon_winsys_cs         *ce_preamble_ib;
 216         bool                            ce_need_synchronization;
 217         struct u_suballocator           *ce_suballocator;
 218
 219         struct si_shader_ctx_state      fixed_func_tcs_shader;
 220         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 221         bool                            gfx_flush_in_progress;
 222
 223         /* Atoms (direct states). */
 224         union si_state_atoms            atoms;
 225         unsigned                        dirty_atoms; /* mask */
 226         /* PM4 states (precomputed immutable states) */
 227         union si_state                  queued;
 228         union si_state                  emitted;
 229
 230         /* Atom declarations. */
 231         struct r600_atom                cache_flush;
 232         struct si_framebuffer           framebuffer;
 233         struct si_sample_locs           msaa_sample_locs;
 234         struct r600_atom                db_render_state;
 235         struct r600_atom                msaa_config;
 236         struct si_sample_mask           sample_mask;
 237         struct r600_atom                cb_render_state;
 238         struct si_blend_color           blend_color;
 239         struct r600_atom                clip_regs;
 240         struct si_clip_state            clip_state;
 241         struct si_shader_data           shader_userdata;
 242         struct si_stencil_ref           stencil_ref;
 243         struct r600_atom                spi_map;
 244
 245         /* Precomputed states. */
 246         struct si_pm4_state             *init_config;
 247         struct si_pm4_state             *init_config_gs_rings;
 248         bool                            init_config_has_vgt_flush;
 249         struct si_pm4_state             *vgt_shader_config[4];
 250
 251         /* shaders */
 252         struct si_shader_ctx_state      ps_shader;
 253         struct si_shader_ctx_state      gs_shader;
 254         struct si_shader_ctx_state      vs_shader;
 255         struct si_shader_ctx_state      tcs_shader;
 256         struct si_shader_ctx_state      tes_shader;
 257         struct si_cs_shader_state       cs_shader_state;
 258
 259         /* shader information */
 260         struct si_vertex_element        *vertex_elements;
 261         unsigned                        sprite_coord_enable;
 262         bool                            flatshade;
 263         bool                            do_update_shaders;
 264
 265         /* shader descriptors */
 266         struct si_descriptors           vertex_buffers;
 267         struct si_descriptors           descriptors[SI_NUM_DESCS];
 268         unsigned                        descriptors_dirty;
 269         struct si_buffer_resources      rw_buffers;
 270         struct si_buffer_resources      const_buffers[SI_NUM_SHADERS];
 271         struct si_buffer_resources      shader_buffers[SI_NUM_SHADERS];
 272         struct si_textures_info         samplers[SI_NUM_SHADERS];
 273         struct si_images_info           images[SI_NUM_SHADERS];
 274
 275         /* other shader resources */
 276         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 277         struct pipe_resource            *esgs_ring;
 278         struct pipe_resource            *gsvs_ring;
 279         struct pipe_resource            *tf_ring;
 280         struct pipe_resource            *tess_offchip_ring;
 281         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 282         struct r600_resource            *border_color_buffer;
 283         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 284         unsigned                        border_color_count;
 285
 286         /* Vertex and index buffers. */
 287         bool                            vertex_buffers_dirty;
 288         struct pipe_index_buffer        index_buffer;
 289         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 290
 291         /* MSAA config state. */
 292         int                             ps_iter_samples;
 293         bool                            smoothing_enabled;
 294
 295         /* DB render state. */
 296         bool                    dbcb_depth_copy_enabled;
 297         bool                    dbcb_stencil_copy_enabled;
 298         unsigned                dbcb_copy_sample;
 299         bool                    db_flush_depth_inplace;
 300         bool                    db_flush_stencil_inplace;
 301         bool                    db_depth_clear;
 302         bool                    db_depth_disable_expclear;
 303         bool                    db_stencil_clear;
 304         bool                    db_stencil_disable_expclear;
 305         unsigned                ps_db_shader_control;
 306         bool                    occlusion_queries_disabled;
 307
 308         /* Emitted draw state. */
 309         int                     last_base_vertex;
 310         int                     last_start_instance;
 311         int                     last_sh_base_reg;
 312         int                     last_primitive_restart_en;
 313         int                     last_restart_index;
 314         int                     last_gs_out_prim;
 315         int                     last_prim;
 316         int                     last_multi_vgt_param;
 317         int                     last_ls_hs_config;
 318         int                     last_rast_prim;
 319         unsigned                last_sc_line_stipple;
 320         int                     last_vtx_reuse_depth;
 321         int                     current_rast_prim; /* primitive type after TES, GS */
 322         unsigned                last_gsvs_itemsize;
 323
 324         /* Scratch buffer */
 325         struct r600_resource    *scratch_buffer;
 326         bool                    emit_scratch_reloc;
 327         unsigned                scratch_waves;
 328         unsigned                spi_tmpring_size;
 329
 330         struct r600_resource    *compute_scratch_buffer;
 331
 332         /* Emitted derived tessellation state. */
 333         struct si_shader        *last_ls; /* local shader (VS) */
 334         struct si_shader_selector *last_tcs;
 335         int                     last_num_tcs_input_cp;
 336         int                     last_tes_sh_base;
 337
 338         /* Debug state. */
 339         bool                    is_debug;
 340         struct radeon_saved_cs  last_gfx;
 341         struct r600_resource    *last_trace_buf;
 342         struct r600_resource    *trace_buf;
 343         unsigned                trace_id;
 344         uint64_t                dmesg_timestamp;
 345         unsigned                apitrace_call_number;
 346
 347         /* Other state */
 348         bool need_check_render_feedback;
 349 };
 350
 351 /* cik_sdma.c */
 352 void cik_init_sdma_functions(struct si_context *sctx);
 353
 354 /* si_blit.c */
 355 void si_init_blit_functions(struct si_context *sctx);
 356 void si_decompress_graphics_textures(struct si_context *sctx);
 357 void si_decompress_compute_textures(struct si_context *sctx);
 358 void si_resource_copy_region(struct pipe_context *ctx,
 359                              struct pipe_resource *dst,
 360                              unsigned dst_level,
 361                              unsigned dstx, unsigned dsty, unsigned dstz,
 362                              struct pipe_resource *src,
 363                              unsigned src_level,
 364                              const struct pipe_box *src_box);
 365
 366 /* si_cp_dma.c */
 367 void si_copy_buffer(struct si_context *sctx,
 368                     struct pipe_resource *dst, struct pipe_resource *src,
 369                     uint64_t dst_offset, uint64_t src_offset, unsigned size);
 370 void si_init_cp_dma_functions(struct si_context *sctx);
 371
 372 /* si_debug.c */
 373 void si_init_debug_functions(struct si_context *sctx);
 374 void si_check_vm_faults(struct r600_common_context *ctx,
 375                         struct radeon_saved_cs *saved, enum ring_type ring);
 376 bool si_replace_shader(unsigned num, struct radeon_shader_binary *binary);
 377
 378 /* si_dma.c */
 379 void si_init_dma_functions(struct si_context *sctx);
 380
 381 /* si_hw_context.c */
 382 void si_context_gfx_flush(void *context, unsigned flags,
 383                           struct pipe_fence_handle **fence);
 384 void si_begin_new_cs(struct si_context *ctx);
 385 void si_need_cs_space(struct si_context *ctx);
 386
 387 /* si_compute.c */
 388 void si_init_compute_functions(struct si_context *sctx);
 389
 390 /* si_perfcounters.c */
 391 void si_init_perfcounters(struct si_screen *screen);
 392
 393 /* si_uvd.c */
 394 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 395                                                const struct pipe_video_codec *templ);
 396
 397 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 398                                                  const struct pipe_video_buffer *tmpl);
 399
 400 /*
 401  * common helpers
 402  */
 403
 404 static inline struct r600_resource *
 405 si_resource_create_custom(struct pipe_screen *screen,
 406                           unsigned usage, unsigned size)
 407 {
 408         assert(size);
 409         return r600_resource(pipe_buffer_create(screen,
 410                 PIPE_BIND_CUSTOM, usage, size));
 411 }
 412
 413 static inline void
 414 si_invalidate_draw_sh_constants(struct si_context *sctx)
 415 {
 416         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 417         sctx->last_start_instance = -1; /* reset to an unknown value */
 418         sctx->last_sh_base_reg = -1; /* reset to an unknown value */
 419 }
 420
 421 static inline void
 422 si_set_atom_dirty(struct si_context *sctx,
 423                   struct r600_atom *atom, bool dirty)
 424 {
 425         unsigned bit = 1 << (atom->id - 1);
 426
 427         if (dirty)
 428                 sctx->dirty_atoms |= bit;
 429         else
 430                 sctx->dirty_atoms &= ~bit;
 431 }
 432
 433 static inline bool
 434 si_is_atom_dirty(struct si_context *sctx,
 435                   struct r600_atom *atom)
 436 {
 437         unsigned bit = 1 << (atom->id - 1);
 438
 439         return sctx->dirty_atoms & bit;
 440 }
 441
 442 static inline void
 443 si_mark_atom_dirty(struct si_context *sctx,
 444                    struct r600_atom *atom)
 445 {
 446         si_set_atom_dirty(sctx, atom, true);
 447 }
 448
 449 #endif