radeonsi: Add CE uploader.
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Jerome Glisse
25 */
26 #ifndef SI_PIPE_H
27 #define SI_PIPE_H
28
29 #include "si_state.h"
30
31 #include <llvm-c/TargetMachine.h>
32
33 #ifdef PIPE_ARCH_BIG_ENDIAN
34 #define SI_BIG_ENDIAN 1
35 #else
36 #define SI_BIG_ENDIAN 0
37 #endif
38
39 /* The base vertex and primitive restart can be any number, but we must pick
40 * one which will mean "unknown" for the purpose of state tracking and
41 * the number shouldn't be a commonly-used one. */
42 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
43 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
44 #define SI_NUM_SMOOTH_AA_SAMPLES 8
45 #define SI_GS_PER_ES 128
46
47 /* Instruction cache. */
48 #define SI_CONTEXT_INV_ICACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
49 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
50 #define SI_CONTEXT_INV_SMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 1)
51 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
52 #define SI_CONTEXT_INV_VMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 2)
53 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
54 #define SI_CONTEXT_INV_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 3)
55 /* Framebuffer caches. */
56 #define SI_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
57 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
58 #define SI_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
59 #define SI_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
60 /* Engine synchronization. */
61 #define SI_CONTEXT_VS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
62 #define SI_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 9)
63 #define SI_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 10)
64 #define SI_CONTEXT_VGT_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11)
65 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (R600_CONTEXT_PRIVATE_FLAG << 12)
66 /* Compute only. */
67 #define SI_CONTEXT_FLUSH_WITH_INV_L2 (R600_CONTEXT_PRIVATE_FLAG << 13) /* TODO: merge with TC? */
68 #define SI_CONTEXT_FLAG_COMPUTE (R600_CONTEXT_PRIVATE_FLAG << 14)
69
70 #define SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER (SI_CONTEXT_FLUSH_AND_INV_CB | \
71 SI_CONTEXT_FLUSH_AND_INV_CB_META | \
72 SI_CONTEXT_FLUSH_AND_INV_DB | \
73 SI_CONTEXT_FLUSH_AND_INV_DB_META)
74
75 #define SI_ENCODE_TRACE_POINT(id) (0xcafe0000 | ((id) & 0xffff))
76 #define SI_IS_TRACE_POINT(x) (((x) & 0xcafe0000) == 0xcafe0000)
77 #define SI_GET_TRACE_POINT_ID(x) ((x) & 0xffff)
78
79 #define SI_MAX_BORDER_COLORS 4096
80
81 struct si_compute;
82 struct hash_table;
83 struct u_suballocator;
84
85 struct si_screen {
86 struct r600_common_screen b;
87 unsigned gs_table_depth;
88
89 /* Whether shaders are monolithic (1-part) or separate (3-part). */
90 bool use_monolithic_shaders;
91
92 pipe_mutex shader_parts_mutex;
93 struct si_shader_part *vs_prologs;
94 struct si_shader_part *vs_epilogs;
95 struct si_shader_part *tcs_epilogs;
96 struct si_shader_part *ps_prologs;
97 struct si_shader_part *ps_epilogs;
98
99 /* Shader cache in memory.
100 *
101 * Design & limitations:
102 * - The shader cache is per screen (= per process), never saved to
103 * disk, and skips redundant shader compilations from TGSI to bytecode.
104 * - It can only be used with one-variant-per-shader support, in which
105 * case only the main (typically middle) part of shaders is cached.
106 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
107 * variants of VS and TES are cached, so LS and ES aren't.
108 * - GS and CS aren't cached, but it's certainly possible to cache
109 * those as well.
110 */
111 pipe_mutex shader_cache_mutex;
112 struct hash_table *shader_cache;
113 };
114
115 struct si_blend_color {
116 struct r600_atom atom;
117 struct pipe_blend_color state;
118 };
119
120 struct si_sampler_view {
121 struct pipe_sampler_view base;
122 struct list_head list;
123 /* [0..7] = image descriptor
124 * [4..7] = buffer descriptor */
125 uint32_t state[8];
126 uint32_t fmask_state[8];
127 bool is_stencil_sampler;
128 };
129
130 struct si_sampler_state {
131 uint32_t val[4];
132 };
133
134 struct si_cs_shader_state {
135 struct si_compute *program;
136 };
137
138 struct si_textures_info {
139 struct si_sampler_views views;
140 uint64_t depth_texture_mask; /* which textures are depth */
141 uint64_t compressed_colortex_mask;
142 };
143
144 struct si_images_info {
145 struct si_descriptors desc;
146 struct pipe_image_view views[SI_NUM_IMAGES];
147 uint32_t compressed_colortex_mask;
148 };
149
150 struct si_framebuffer {
151 struct r600_atom atom;
152 struct pipe_framebuffer_state state;
153 unsigned nr_samples;
154 unsigned log_samples;
155 unsigned cb0_is_integer;
156 unsigned compressed_cb_mask;
157 unsigned spi_shader_col_format;
158 unsigned spi_shader_col_format_alpha;
159 unsigned spi_shader_col_format_blend;
160 unsigned spi_shader_col_format_blend_alpha;
161 unsigned color_is_int8; /* bitmask */
162 unsigned dirty_cbufs;
163 bool dirty_zsbuf;
164 };
165
166 struct si_clip_state {
167 struct r600_atom atom;
168 struct pipe_clip_state state;
169 };
170
171 struct si_sample_mask {
172 struct r600_atom atom;
173 uint16_t sample_mask;
174 };
175
176 /* A shader state consists of the shader selector, which is a constant state
177 * object shared by multiple contexts and shouldn't be modified, and
178 * the current shader variant selected for this context.
179 */
180 struct si_shader_ctx_state {
181 struct si_shader_selector *cso;
182 struct si_shader *current;
183 };
184
185 struct si_context {
186 struct r600_common_context b;
187 struct blitter_context *blitter;
188 void *custom_dsa_flush;
189 void *custom_blend_resolve;
190 void *custom_blend_decompress;
191 void *custom_blend_fastclear;
192 void *custom_blend_dcc_decompress;
193 void *pstipple_sampler_state;
194 struct si_screen *screen;
195
196 struct radeon_winsys_cs *ce_ib;
197 struct radeon_winsys_cs *ce_preamble_ib;
198 bool ce_need_synchronization;
199 struct u_suballocator *ce_suballocator;
200
201 struct pipe_fence_handle *last_gfx_fence;
202 struct si_shader_ctx_state fixed_func_tcs_shader;
203 LLVMTargetMachineRef tm;
204 bool gfx_flush_in_progress;
205
206 /* Atoms (direct states). */
207 union si_state_atoms atoms;
208 unsigned dirty_atoms; /* mask */
209 /* PM4 states (precomputed immutable states) */
210 union si_state queued;
211 union si_state emitted;
212
213 /* Atom declarations. */
214 struct r600_atom cache_flush;
215 struct si_framebuffer framebuffer;
216 struct r600_atom msaa_sample_locs;
217 struct r600_atom db_render_state;
218 struct r600_atom msaa_config;
219 struct si_sample_mask sample_mask;
220 struct r600_atom cb_render_state;
221 struct si_blend_color blend_color;
222 struct r600_atom clip_regs;
223 struct si_clip_state clip_state;
224 struct si_shader_data shader_userdata;
225 struct si_stencil_ref stencil_ref;
226 struct r600_atom spi_map;
227
228 /* Precomputed states. */
229 struct si_pm4_state *init_config;
230 struct si_pm4_state *init_config_gs_rings;
231 bool init_config_has_vgt_flush;
232 struct si_pm4_state *vgt_shader_config[4];
233
234 /* shaders */
235 struct si_shader_ctx_state ps_shader;
236 struct si_shader_ctx_state gs_shader;
237 struct si_shader_ctx_state vs_shader;
238 struct si_shader_ctx_state tcs_shader;
239 struct si_shader_ctx_state tes_shader;
240 struct si_cs_shader_state cs_shader_state;
241
242 /* shader information */
243 struct si_vertex_element *vertex_elements;
244 unsigned sprite_coord_enable;
245 bool flatshade;
246
247 /* shader descriptors */
248 struct si_descriptors vertex_buffers;
249 struct si_buffer_resources const_buffers[SI_NUM_SHADERS];
250 struct si_buffer_resources rw_buffers[SI_NUM_SHADERS];
251 struct si_buffer_resources shader_buffers[SI_NUM_SHADERS];
252 struct si_textures_info samplers[SI_NUM_SHADERS];
253 struct si_images_info images[SI_NUM_SHADERS];
254
255 /* other shader resources */
256 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
257 struct pipe_resource *esgs_ring;
258 struct pipe_resource *gsvs_ring;
259 struct pipe_resource *tf_ring;
260 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
261 struct r600_resource *border_color_buffer;
262 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
263 unsigned border_color_count;
264
265 /* Vertex and index buffers. */
266 bool vertex_buffers_dirty;
267 struct pipe_index_buffer index_buffer;
268 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
269
270 /* MSAA config state. */
271 int ps_iter_samples;
272 bool smoothing_enabled;
273
274 /* DB render state. */
275 bool dbcb_depth_copy_enabled;
276 bool dbcb_stencil_copy_enabled;
277 unsigned dbcb_copy_sample;
278 bool db_flush_depth_inplace;
279 bool db_flush_stencil_inplace;
280 bool db_depth_clear;
281 bool db_depth_disable_expclear;
282 bool db_stencil_clear;
283 bool db_stencil_disable_expclear;
284 unsigned ps_db_shader_control;
285 bool occlusion_queries_disabled;
286
287 /* Emitted draw state. */
288 int last_base_vertex;
289 int last_start_instance;
290 int last_sh_base_reg;
291 int last_primitive_restart_en;
292 int last_restart_index;
293 int last_gs_out_prim;
294 int last_prim;
295 int last_multi_vgt_param;
296 int last_ls_hs_config;
297 int last_rast_prim;
298 unsigned last_sc_line_stipple;
299 int current_rast_prim; /* primitive type after TES, GS */
300 unsigned last_gsvs_itemsize;
301
302 /* Scratch buffer */
303 struct r600_resource *scratch_buffer;
304 boolean emit_scratch_reloc;
305 unsigned scratch_waves;
306 unsigned spi_tmpring_size;
307
308 /* Emitted derived tessellation state. */
309 struct si_shader *last_ls; /* local shader (VS) */
310 struct si_shader_selector *last_tcs;
311 int last_num_tcs_input_cp;
312 int last_tes_sh_base;
313
314 /* Debug state. */
315 bool is_debug;
316 uint32_t *last_ib;
317 unsigned last_ib_dw_size;
318 struct r600_resource *last_trace_buf;
319 struct r600_resource *trace_buf;
320 unsigned trace_id;
321 uint64_t dmesg_timestamp;
322 unsigned last_bo_count;
323 struct radeon_bo_list_item *last_bo_list;
324 };
325
326 /* cik_sdma.c */
327 void cik_sdma_copy(struct pipe_context *ctx,
328 struct pipe_resource *dst,
329 unsigned dst_level,
330 unsigned dstx, unsigned dsty, unsigned dstz,
331 struct pipe_resource *src,
332 unsigned src_level,
333 const struct pipe_box *src_box);
334
335 /* si_blit.c */
336 void si_init_blit_functions(struct si_context *sctx);
337 void si_decompress_textures(struct si_context *sctx);
338 void si_resource_copy_region(struct pipe_context *ctx,
339 struct pipe_resource *dst,
340 unsigned dst_level,
341 unsigned dstx, unsigned dsty, unsigned dstz,
342 struct pipe_resource *src,
343 unsigned src_level,
344 const struct pipe_box *src_box);
345
346 /* si_cp_dma.c */
347 void si_copy_buffer(struct si_context *sctx,
348 struct pipe_resource *dst, struct pipe_resource *src,
349 uint64_t dst_offset, uint64_t src_offset, unsigned size,
350 bool is_framebuffer);
351 void si_init_cp_dma_functions(struct si_context *sctx);
352
353 /* si_debug.c */
354 void si_init_debug_functions(struct si_context *sctx);
355 void si_check_vm_faults(struct si_context *sctx);
356 bool si_replace_shader(unsigned num, struct radeon_shader_binary *binary);
357
358 /* si_dma.c */
359 void si_dma_copy(struct pipe_context *ctx,
360 struct pipe_resource *dst,
361 unsigned dst_level,
362 unsigned dstx, unsigned dsty, unsigned dstz,
363 struct pipe_resource *src,
364 unsigned src_level,
365 const struct pipe_box *src_box);
366
367 /* si_hw_context.c */
368 void si_context_gfx_flush(void *context, unsigned flags,
369 struct pipe_fence_handle **fence);
370 void si_begin_new_cs(struct si_context *ctx);
371 void si_need_cs_space(struct si_context *ctx);
372
373 /* si_compute.c */
374 void si_init_compute_functions(struct si_context *sctx);
375
376 /* si_perfcounters.c */
377 void si_init_perfcounters(struct si_screen *screen);
378
379 /* si_uvd.c */
380 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
381 const struct pipe_video_codec *templ);
382
383 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
384 const struct pipe_video_buffer *tmpl);
385
386 /*
387 * common helpers
388 */
389
390 static inline struct r600_resource *
391 si_resource_create_custom(struct pipe_screen *screen,
392 unsigned usage, unsigned size)
393 {
394 assert(size);
395 return r600_resource(pipe_buffer_create(screen,
396 PIPE_BIND_CUSTOM, usage, size));
397 }
398
399 static inline void
400 si_invalidate_draw_sh_constants(struct si_context *sctx)
401 {
402 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
403 sctx->last_start_instance = -1; /* reset to an unknown value */
404 sctx->last_sh_base_reg = -1; /* reset to an unknown value */
405 }
406
407 static inline void
408 si_set_atom_dirty(struct si_context *sctx,
409 struct r600_atom *atom, bool dirty)
410 {
411 unsigned bit = 1 << (atom->id - 1);
412
413 if (dirty)
414 sctx->dirty_atoms |= bit;
415 else
416 sctx->dirty_atoms &= ~bit;
417 }
418
419 static inline void
420 si_mark_atom_dirty(struct si_context *sctx,
421 struct r600_atom *atom)
422 {
423 si_set_atom_dirty(sctx, atom, true);
424 }
425
426 #endif