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radeonsi: make sure that blend state != NULL and remove all NULL checking
[mesa.git] / src / gallium / drivers / radeonsi / si_pipe.h
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #ifndef SI_PIPE_H
26 #define SI_PIPE_H
27
28 #include "si_shader.h"
29 #include "si_state.h"
30
31 #include "util/u_dynarray.h"
32 #include "util/u_idalloc.h"
33 #include "util/u_threaded_context.h"
34
35 #ifdef PIPE_ARCH_BIG_ENDIAN
36 #define SI_BIG_ENDIAN 1
37 #else
38 #define SI_BIG_ENDIAN 0
39 #endif
40
41 #define ATI_VENDOR_ID 0x1002
42 #define SI_PRIM_DISCARD_DEBUG 0
43 #define SI_NOT_QUERY 0xffffffff
44
45 /* The base vertex and primitive restart can be any number, but we must pick
46 * one which will mean "unknown" for the purpose of state tracking and
47 * the number shouldn't be a commonly-used one. */
48 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
49 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
50 #define SI_INSTANCE_COUNT_UNKNOWN INT_MIN
51 #define SI_NUM_SMOOTH_AA_SAMPLES 8
52 #define SI_MAX_POINT_SIZE 2048
53 #define SI_GS_PER_ES 128
54 /* Alignment for optimal CP DMA performance. */
55 #define SI_CPDMA_ALIGNMENT 32
56
57 /* Tunables for compute-based clear_buffer and copy_buffer: */
58 #define SI_COMPUTE_CLEAR_DW_PER_THREAD 4
59 #define SI_COMPUTE_COPY_DW_PER_THREAD 4
60 #define SI_COMPUTE_DST_CACHE_POLICY L2_STREAM
61
62 /* Pipeline & streamout query controls. */
63 #define SI_CONTEXT_START_PIPELINE_STATS (1 << 0)
64 #define SI_CONTEXT_STOP_PIPELINE_STATS (1 << 1)
65 #define SI_CONTEXT_FLUSH_FOR_RENDER_COND (1 << 2)
66 /* Instruction cache. */
67 #define SI_CONTEXT_INV_ICACHE (1 << 3)
68 /* Scalar cache. (GFX6-9: scalar L1; GFX10: scalar L0)
69 * GFX10: This also invalidates the L1 shader array cache. */
70 #define SI_CONTEXT_INV_SCACHE (1 << 4)
71 /* Vector cache. (GFX6-9: vector L1; GFX10: vector L0)
72 * GFX10: This also invalidates the L1 shader array cache. */
73 #define SI_CONTEXT_INV_VCACHE (1 << 5)
74 /* L2 cache + L2 metadata cache writeback & invalidate.
75 * GFX6-8: Used by shaders only. GFX9-10: Used by everything. */
76 #define SI_CONTEXT_INV_L2 (1 << 6)
77 /* L2 writeback (write dirty L2 lines to memory for non-L2 clients).
78 * Only used for coherency with non-L2 clients like CB, DB, CP on GFX6-8.
79 * GFX6-7 will do complete invalidation, because the writeback is unsupported. */
80 #define SI_CONTEXT_WB_L2 (1 << 7)
81 /* Writeback & invalidate the L2 metadata cache only. It can only be coupled with
82 * a CB or DB flush. */
83 #define SI_CONTEXT_INV_L2_METADATA (1 << 8)
84 /* Framebuffer caches. */
85 #define SI_CONTEXT_FLUSH_AND_INV_DB (1 << 9)
86 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (1 << 10)
87 #define SI_CONTEXT_FLUSH_AND_INV_CB (1 << 11)
88 /* Engine synchronization. */
89 #define SI_CONTEXT_VS_PARTIAL_FLUSH (1 << 12)
90 #define SI_CONTEXT_PS_PARTIAL_FLUSH (1 << 13)
91 #define SI_CONTEXT_CS_PARTIAL_FLUSH (1 << 14)
92 #define SI_CONTEXT_VGT_FLUSH (1 << 15)
93 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (1 << 16)
94
95 #define SI_PREFETCH_VBO_DESCRIPTORS (1 << 0)
96 #define SI_PREFETCH_LS (1 << 1)
97 #define SI_PREFETCH_HS (1 << 2)
98 #define SI_PREFETCH_ES (1 << 3)
99 #define SI_PREFETCH_GS (1 << 4)
100 #define SI_PREFETCH_VS (1 << 5)
101 #define SI_PREFETCH_PS (1 << 6)
102
103 #define SI_MAX_BORDER_COLORS 4096
104 #define SI_MAX_VIEWPORTS 16
105 #define SIX_BITS 0x3F
106 #define SI_MAP_BUFFER_ALIGNMENT 64
107 #define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
108
109 #define SI_RESOURCE_FLAG_TRANSFER (PIPE_RESOURCE_FLAG_DRV_PRIV << 0)
110 #define SI_RESOURCE_FLAG_FLUSHED_DEPTH (PIPE_RESOURCE_FLAG_DRV_PRIV << 1)
111 #define SI_RESOURCE_FLAG_FORCE_MSAA_TILING (PIPE_RESOURCE_FLAG_DRV_PRIV << 2)
112 #define SI_RESOURCE_FLAG_DISABLE_DCC (PIPE_RESOURCE_FLAG_DRV_PRIV << 3)
113 #define SI_RESOURCE_FLAG_UNMAPPABLE (PIPE_RESOURCE_FLAG_DRV_PRIV << 4)
114 #define SI_RESOURCE_FLAG_READ_ONLY (PIPE_RESOURCE_FLAG_DRV_PRIV << 5)
115 #define SI_RESOURCE_FLAG_32BIT (PIPE_RESOURCE_FLAG_DRV_PRIV << 6)
116 #define SI_RESOURCE_FLAG_CLEAR (PIPE_RESOURCE_FLAG_DRV_PRIV << 7)
117 /* For const_uploader, upload data via GTT and copy to VRAM on context flush via SDMA. */
118 #define SI_RESOURCE_FLAG_UPLOAD_FLUSH_EXPLICIT_VIA_SDMA (PIPE_RESOURCE_FLAG_DRV_PRIV << 8)
119
120 enum si_clear_code
121 {
122 DCC_CLEAR_COLOR_0000 = 0x00000000,
123 DCC_CLEAR_COLOR_0001 = 0x40404040,
124 DCC_CLEAR_COLOR_1110 = 0x80808080,
125 DCC_CLEAR_COLOR_1111 = 0xC0C0C0C0,
126 DCC_CLEAR_COLOR_REG = 0x20202020,
127 DCC_UNCOMPRESSED = 0xFFFFFFFF,
128 };
129
130 #define SI_IMAGE_ACCESS_AS_BUFFER (1 << 7)
131
132 /* Debug flags. */
133 enum {
134 /* Shader logging options: */
135 DBG_VS = PIPE_SHADER_VERTEX,
136 DBG_PS = PIPE_SHADER_FRAGMENT,
137 DBG_GS = PIPE_SHADER_GEOMETRY,
138 DBG_TCS = PIPE_SHADER_TESS_CTRL,
139 DBG_TES = PIPE_SHADER_TESS_EVAL,
140 DBG_CS = PIPE_SHADER_COMPUTE,
141 DBG_NO_IR,
142 DBG_NO_TGSI,
143 DBG_NO_ASM,
144 DBG_PREOPT_IR,
145
146 /* Shader compiler options the shader cache should be aware of: */
147 DBG_FS_CORRECT_DERIVS_AFTER_KILL,
148 DBG_UNSAFE_MATH,
149 DBG_SI_SCHED,
150 DBG_GISEL,
151 DBG_W32_GE,
152 DBG_W32_PS,
153 DBG_W32_CS,
154 DBG_W64_GE,
155 DBG_W64_PS,
156 DBG_W64_CS,
157
158 /* Shader compiler options (with no effect on the shader cache): */
159 DBG_CHECK_IR,
160 DBG_MONOLITHIC_SHADERS,
161 DBG_NO_OPT_VARIANT,
162
163 /* Information logging options: */
164 DBG_INFO,
165 DBG_TEX,
166 DBG_COMPUTE,
167 DBG_VM,
168
169 /* Driver options: */
170 DBG_FORCE_DMA,
171 DBG_NO_ASYNC_DMA,
172 DBG_NO_WC,
173 DBG_CHECK_VM,
174 DBG_RESERVE_VMID,
175 DBG_ZERO_VRAM,
176
177 /* 3D engine options: */
178 DBG_NO_GFX,
179 DBG_ALWAYS_PD,
180 DBG_PD,
181 DBG_NO_PD,
182 DBG_SWITCH_ON_EOP,
183 DBG_NO_OUT_OF_ORDER,
184 DBG_NO_DPBB,
185 DBG_NO_DFSM,
186 DBG_DPBB,
187 DBG_DFSM,
188 DBG_NO_HYPERZ,
189 DBG_NO_RB_PLUS,
190 DBG_NO_2D_TILING,
191 DBG_NO_TILING,
192 DBG_NO_DCC,
193 DBG_NO_DCC_CLEAR,
194 DBG_NO_DCC_FB,
195 DBG_NO_DCC_MSAA,
196 DBG_NO_FMASK,
197
198 /* Tests: */
199 DBG_TEST_DMA,
200 DBG_TEST_VMFAULT_CP,
201 DBG_TEST_VMFAULT_SDMA,
202 DBG_TEST_VMFAULT_SHADER,
203 DBG_TEST_DMA_PERF,
204 DBG_TEST_GDS,
205 DBG_TEST_GDS_MM,
206 DBG_TEST_GDS_OA_MM,
207 };
208
209 #define DBG_ALL_SHADERS (((1 << (DBG_CS + 1)) - 1))
210 #define DBG(name) (1ull << DBG_##name)
211
212 enum si_cache_policy {
213 L2_BYPASS,
214 L2_STREAM, /* same as SLC=1 */
215 L2_LRU, /* same as SLC=0 */
216 };
217
218 enum si_coherency {
219 SI_COHERENCY_NONE, /* no cache flushes needed */
220 SI_COHERENCY_SHADER,
221 SI_COHERENCY_CB_META,
222 SI_COHERENCY_CP,
223 };
224
225 struct si_compute;
226 struct si_shader_context;
227 struct hash_table;
228 struct u_suballocator;
229
230 /* Only 32-bit buffer allocations are supported, gallium doesn't support more
231 * at the moment.
232 */
233 struct si_resource {
234 struct threaded_resource b;
235
236 /* Winsys objects. */
237 struct pb_buffer *buf;
238 uint64_t gpu_address;
239 /* Memory usage if the buffer placement is optimal. */
240 uint64_t vram_usage;
241 uint64_t gart_usage;
242
243 /* Resource properties. */
244 uint64_t bo_size;
245 unsigned bo_alignment;
246 enum radeon_bo_domain domains;
247 enum radeon_bo_flag flags;
248 unsigned bind_history;
249 int max_forced_staging_uploads;
250
251 /* The buffer range which is initialized (with a write transfer,
252 * streamout, DMA, or as a random access target). The rest of
253 * the buffer is considered invalid and can be mapped unsynchronized.
254 *
255 * This allows unsychronized mapping of a buffer range which hasn't
256 * been used yet. It's for applications which forget to use
257 * the unsynchronized map flag and expect the driver to figure it out.
258 */
259 struct util_range valid_buffer_range;
260
261 /* For buffers only. This indicates that a write operation has been
262 * performed by TC L2, but the cache hasn't been flushed.
263 * Any hw block which doesn't use or bypasses TC L2 should check this
264 * flag and flush the cache before using the buffer.
265 *
266 * For example, TC L2 must be flushed if a buffer which has been
267 * modified by a shader store instruction is about to be used as
268 * an index buffer. The reason is that VGT DMA index fetching doesn't
269 * use TC L2.
270 */
271 bool TC_L2_dirty;
272
273 /* Whether this resource is referenced by bindless handles. */
274 bool texture_handle_allocated;
275 bool image_handle_allocated;
276
277 /* Whether the resource has been exported via resource_get_handle. */
278 unsigned external_usage; /* PIPE_HANDLE_USAGE_* */
279 };
280
281 struct si_transfer {
282 struct threaded_transfer b;
283 struct si_resource *staging;
284 unsigned offset;
285 };
286
287 struct si_texture {
288 struct si_resource buffer;
289
290 struct radeon_surf surface;
291 uint64_t size;
292 struct si_texture *flushed_depth_texture;
293
294 /* One texture allocation can contain these buffers:
295 * - image (pixel data)
296 * - FMASK buffer (MSAA compression)
297 * - CMASK buffer (MSAA compression and/or legacy fast color clear)
298 * - HTILE buffer (Z/S compression and fast Z/S clear)
299 * - DCC buffer (color compression and new fast color clear)
300 * - displayable DCC buffer (if the DCC buffer is not displayable)
301 * - DCC retile mapping buffer (if the DCC buffer is not displayable)
302 */
303 uint64_t fmask_offset;
304 uint64_t cmask_offset;
305 uint64_t cmask_base_address_reg;
306 struct si_resource *cmask_buffer;
307 uint64_t dcc_offset; /* 0 = disabled */
308 uint64_t display_dcc_offset;
309 uint64_t dcc_retile_map_offset;
310 unsigned cb_color_info; /* fast clear enable bit */
311 unsigned color_clear_value[2];
312 unsigned last_msaa_resolve_target_micro_mode;
313 unsigned num_level0_transfers;
314
315 /* Depth buffer compression and fast clear. */
316 uint64_t htile_offset;
317 float depth_clear_value;
318 uint16_t dirty_level_mask; /* each bit says if that mipmap is compressed */
319 uint16_t stencil_dirty_level_mask; /* each bit says if that mipmap is compressed */
320 enum pipe_format db_render_format:16;
321 uint8_t stencil_clear_value;
322 bool tc_compatible_htile:1;
323 bool htile_stencil_disabled:1;
324 bool depth_cleared:1; /* if it was cleared at least once */
325 bool stencil_cleared:1; /* if it was cleared at least once */
326 bool upgraded_depth:1; /* upgraded from unorm to Z32_FLOAT */
327 bool is_depth:1;
328 bool db_compatible:1;
329 bool can_sample_z:1;
330 bool can_sample_s:1;
331
332 /* We need to track DCC dirtiness, because st/dri usually calls
333 * flush_resource twice per frame (not a bug) and we don't wanna
334 * decompress DCC twice. Also, the dirty tracking must be done even
335 * if DCC isn't used, because it's required by the DCC usage analysis
336 * for a possible future enablement.
337 */
338 bool separate_dcc_dirty:1;
339 /* Statistics gathering for the DCC enablement heuristic. */
340 bool dcc_gather_statistics:1;
341 /* Counter that should be non-zero if the texture is bound to a
342 * framebuffer.
343 */
344 unsigned framebuffers_bound;
345 /* Whether the texture is a displayable back buffer and needs DCC
346 * decompression, which is expensive. Therefore, it's enabled only
347 * if statistics suggest that it will pay off and it's allocated
348 * separately. It can't be bound as a sampler by apps. Limited to
349 * target == 2D and last_level == 0. If enabled, dcc_offset contains
350 * the absolute GPUVM address, not the relative one.
351 */
352 struct si_resource *dcc_separate_buffer;
353 /* When DCC is temporarily disabled, the separate buffer is here. */
354 struct si_resource *last_dcc_separate_buffer;
355 /* Estimate of how much this color buffer is written to in units of
356 * full-screen draws: ps_invocations / (width * height)
357 * Shader kills, late Z, and blending with trivial discards make it
358 * inaccurate (we need to count CB updates, not PS invocations).
359 */
360 unsigned ps_draw_ratio;
361 /* The number of clears since the last DCC usage analysis. */
362 unsigned num_slow_clears;
363 };
364
365 struct si_surface {
366 struct pipe_surface base;
367
368 /* These can vary with block-compressed textures. */
369 uint16_t width0;
370 uint16_t height0;
371
372 bool color_initialized:1;
373 bool depth_initialized:1;
374
375 /* Misc. color flags. */
376 bool color_is_int8:1;
377 bool color_is_int10:1;
378 bool dcc_incompatible:1;
379
380 /* Color registers. */
381 unsigned cb_color_info;
382 unsigned cb_color_view;
383 unsigned cb_color_attrib;
384 unsigned cb_color_attrib2; /* GFX9 and later */
385 unsigned cb_color_attrib3; /* GFX10 and later */
386 unsigned cb_dcc_control; /* GFX8 and later */
387 unsigned spi_shader_col_format:8; /* no blending, no alpha-to-coverage. */
388 unsigned spi_shader_col_format_alpha:8; /* alpha-to-coverage */
389 unsigned spi_shader_col_format_blend:8; /* blending without alpha. */
390 unsigned spi_shader_col_format_blend_alpha:8; /* blending with alpha. */
391
392 /* DB registers. */
393 uint64_t db_depth_base; /* DB_Z_READ/WRITE_BASE */
394 uint64_t db_stencil_base;
395 uint64_t db_htile_data_base;
396 unsigned db_depth_info;
397 unsigned db_z_info;
398 unsigned db_z_info2; /* GFX9 only */
399 unsigned db_depth_view;
400 unsigned db_depth_size;
401 unsigned db_depth_slice;
402 unsigned db_stencil_info;
403 unsigned db_stencil_info2; /* GFX9 only */
404 unsigned db_htile_surface;
405 };
406
407 struct si_mmio_counter {
408 unsigned busy;
409 unsigned idle;
410 };
411
412 union si_mmio_counters {
413 struct {
414 /* For global GPU load including SDMA. */
415 struct si_mmio_counter gpu;
416
417 /* GRBM_STATUS */
418 struct si_mmio_counter spi;
419 struct si_mmio_counter gui;
420 struct si_mmio_counter ta;
421 struct si_mmio_counter gds;
422 struct si_mmio_counter vgt;
423 struct si_mmio_counter ia;
424 struct si_mmio_counter sx;
425 struct si_mmio_counter wd;
426 struct si_mmio_counter bci;
427 struct si_mmio_counter sc;
428 struct si_mmio_counter pa;
429 struct si_mmio_counter db;
430 struct si_mmio_counter cp;
431 struct si_mmio_counter cb;
432
433 /* SRBM_STATUS2 */
434 struct si_mmio_counter sdma;
435
436 /* CP_STAT */
437 struct si_mmio_counter pfp;
438 struct si_mmio_counter meq;
439 struct si_mmio_counter me;
440 struct si_mmio_counter surf_sync;
441 struct si_mmio_counter cp_dma;
442 struct si_mmio_counter scratch_ram;
443 } named;
444 unsigned array[0];
445 };
446
447 struct si_memory_object {
448 struct pipe_memory_object b;
449 struct pb_buffer *buf;
450 uint32_t stride;
451 };
452
453 /* Saved CS data for debugging features. */
454 struct radeon_saved_cs {
455 uint32_t *ib;
456 unsigned num_dw;
457
458 struct radeon_bo_list_item *bo_list;
459 unsigned bo_count;
460 };
461
462 struct si_screen {
463 struct pipe_screen b;
464 struct radeon_winsys *ws;
465 struct disk_cache *disk_shader_cache;
466
467 struct radeon_info info;
468 uint64_t debug_flags;
469 char renderer_string[183];
470
471 void (*make_texture_descriptor)(
472 struct si_screen *screen,
473 struct si_texture *tex,
474 bool sampler,
475 enum pipe_texture_target target,
476 enum pipe_format pipe_format,
477 const unsigned char state_swizzle[4],
478 unsigned first_level, unsigned last_level,
479 unsigned first_layer, unsigned last_layer,
480 unsigned width, unsigned height, unsigned depth,
481 uint32_t *state,
482 uint32_t *fmask_state);
483
484 unsigned pa_sc_raster_config;
485 unsigned pa_sc_raster_config_1;
486 unsigned se_tile_repeat;
487 unsigned gs_table_depth;
488 unsigned tess_offchip_block_dw_size;
489 unsigned tess_offchip_ring_size;
490 unsigned tess_factor_ring_size;
491 unsigned vgt_hs_offchip_param;
492 unsigned eqaa_force_coverage_samples;
493 unsigned eqaa_force_z_samples;
494 unsigned eqaa_force_color_samples;
495 bool has_clear_state;
496 bool has_distributed_tess;
497 bool has_draw_indirect_multi;
498 bool has_out_of_order_rast;
499 bool assume_no_z_fights;
500 bool commutative_blend_add;
501 bool has_gfx9_scissor_bug;
502 bool has_msaa_sample_loc_bug;
503 bool has_ls_vgpr_init_bug;
504 bool has_dcc_constant_encode;
505 bool dpbb_allowed;
506 bool dfsm_allowed;
507 bool llvm_has_working_vgpr_indexing;
508
509 struct {
510 #define OPT_BOOL(name, dflt, description) bool name:1;
511 #include "si_debug_options.h"
512 } options;
513
514 /* Whether shaders are monolithic (1-part) or separate (3-part). */
515 bool use_monolithic_shaders;
516 bool record_llvm_ir;
517 bool has_rbplus; /* if RB+ registers exist */
518 bool rbplus_allowed; /* if RB+ is allowed */
519 bool dcc_msaa_allowed;
520 bool cpdma_prefetch_writes_memory;
521
522 struct slab_parent_pool pool_transfers;
523
524 /* Texture filter settings. */
525 int force_aniso; /* -1 = disabled */
526
527 /* Auxiliary context. Mainly used to initialize resources.
528 * It must be locked prior to using and flushed before unlocking. */
529 struct pipe_context *aux_context;
530 mtx_t aux_context_lock;
531
532 /* This must be in the screen, because UE4 uses one context for
533 * compilation and another one for rendering.
534 */
535 unsigned num_compilations;
536 /* Along with ST_DEBUG=precompile, this should show if applications
537 * are loading shaders on demand. This is a monotonic counter.
538 */
539 unsigned num_shaders_created;
540 unsigned num_shader_cache_hits;
541
542 /* GPU load thread. */
543 mtx_t gpu_load_mutex;
544 thrd_t gpu_load_thread;
545 union si_mmio_counters mmio_counters;
546 volatile unsigned gpu_load_stop_thread; /* bool */
547
548 /* Performance counters. */
549 struct si_perfcounters *perfcounters;
550
551 /* If pipe_screen wants to recompute and re-emit the framebuffer,
552 * sampler, and image states of all contexts, it should atomically
553 * increment this.
554 *
555 * Each context will compare this with its own last known value of
556 * the counter before drawing and re-emit the states accordingly.
557 */
558 unsigned dirty_tex_counter;
559 unsigned dirty_buf_counter;
560
561 /* Atomically increment this counter when an existing texture's
562 * metadata is enabled or disabled in a way that requires changing
563 * contexts' compressed texture binding masks.
564 */
565 unsigned compressed_colortex_counter;
566
567 struct {
568 /* Context flags to set so that all writes from earlier jobs
569 * in the CP are seen by L2 clients.
570 */
571 unsigned cp_to_L2;
572
573 /* Context flags to set so that all writes from earlier jobs
574 * that end in L2 are seen by CP.
575 */
576 unsigned L2_to_cp;
577 } barrier_flags;
578
579 mtx_t shader_parts_mutex;
580 struct si_shader_part *vs_prologs;
581 struct si_shader_part *tcs_epilogs;
582 struct si_shader_part *gs_prologs;
583 struct si_shader_part *ps_prologs;
584 struct si_shader_part *ps_epilogs;
585
586 /* Shader cache in memory.
587 *
588 * Design & limitations:
589 * - The shader cache is per screen (= per process), never saved to
590 * disk, and skips redundant shader compilations from TGSI to bytecode.
591 * - It can only be used with one-variant-per-shader support, in which
592 * case only the main (typically middle) part of shaders is cached.
593 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
594 * variants of VS and TES are cached, so LS and ES aren't.
595 * - GS and CS aren't cached, but it's certainly possible to cache
596 * those as well.
597 */
598 mtx_t shader_cache_mutex;
599 struct hash_table *shader_cache;
600
601 /* Shader compiler queue for multithreaded compilation. */
602 struct util_queue shader_compiler_queue;
603 /* Use at most 3 normal compiler threads on quadcore and better.
604 * Hyperthreaded CPUs report the number of threads, but we want
605 * the number of cores. We only need this many threads for shader-db. */
606 struct ac_llvm_compiler compiler[24]; /* used by the queue only */
607
608 struct util_queue shader_compiler_queue_low_priority;
609 /* Use at most 2 low priority threads on quadcore and better.
610 * We want to minimize the impact on multithreaded Mesa. */
611 struct ac_llvm_compiler compiler_lowp[10];
612
613 unsigned compute_wave_size;
614 unsigned ps_wave_size;
615 unsigned ge_wave_size;
616 };
617
618 struct si_blend_color {
619 struct pipe_blend_color state;
620 bool any_nonzeros;
621 };
622
623 struct si_sampler_view {
624 struct pipe_sampler_view base;
625 /* [0..7] = image descriptor
626 * [4..7] = buffer descriptor */
627 uint32_t state[8];
628 uint32_t fmask_state[8];
629 const struct legacy_surf_level *base_level_info;
630 ubyte base_level;
631 ubyte block_width;
632 bool is_stencil_sampler;
633 bool is_integer;
634 bool dcc_incompatible;
635 };
636
637 #define SI_SAMPLER_STATE_MAGIC 0x34f1c35a
638
639 struct si_sampler_state {
640 #ifndef NDEBUG
641 unsigned magic;
642 #endif
643 uint32_t val[4];
644 uint32_t integer_val[4];
645 uint32_t upgraded_depth_val[4];
646 };
647
648 struct si_cs_shader_state {
649 struct si_compute *program;
650 struct si_compute *emitted_program;
651 unsigned offset;
652 bool initialized;
653 bool uses_scratch;
654 };
655
656 struct si_samplers {
657 struct pipe_sampler_view *views[SI_NUM_SAMPLERS];
658 struct si_sampler_state *sampler_states[SI_NUM_SAMPLERS];
659
660 /* The i-th bit is set if that element is enabled (non-NULL resource). */
661 unsigned enabled_mask;
662 uint32_t needs_depth_decompress_mask;
663 uint32_t needs_color_decompress_mask;
664 };
665
666 struct si_images {
667 struct pipe_image_view views[SI_NUM_IMAGES];
668 uint32_t needs_color_decompress_mask;
669 unsigned enabled_mask;
670 };
671
672 struct si_framebuffer {
673 struct pipe_framebuffer_state state;
674 unsigned colorbuf_enabled_4bit;
675 unsigned spi_shader_col_format;
676 unsigned spi_shader_col_format_alpha;
677 unsigned spi_shader_col_format_blend;
678 unsigned spi_shader_col_format_blend_alpha;
679 ubyte nr_samples:5; /* at most 16xAA */
680 ubyte log_samples:3; /* at most 4 = 16xAA */
681 ubyte nr_color_samples; /* at most 8xAA */
682 ubyte compressed_cb_mask;
683 ubyte uncompressed_cb_mask;
684 ubyte color_is_int8;
685 ubyte color_is_int10;
686 ubyte dirty_cbufs;
687 ubyte dcc_overwrite_combiner_watermark;
688 ubyte min_bytes_per_pixel;
689 bool dirty_zsbuf;
690 bool any_dst_linear;
691 bool CB_has_shader_readable_metadata;
692 bool DB_has_shader_readable_metadata;
693 bool all_DCC_pipe_aligned;
694 };
695
696 enum si_quant_mode {
697 /* This is the list we want to support. */
698 SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH,
699 SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH,
700 SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH,
701 };
702
703 struct si_signed_scissor {
704 int minx;
705 int miny;
706 int maxx;
707 int maxy;
708 enum si_quant_mode quant_mode;
709 };
710
711 struct si_viewports {
712 struct pipe_viewport_state states[SI_MAX_VIEWPORTS];
713 struct si_signed_scissor as_scissor[SI_MAX_VIEWPORTS];
714 bool y_inverted;
715 };
716
717 struct si_clip_state {
718 struct pipe_clip_state state;
719 bool any_nonzeros;
720 };
721
722 struct si_streamout_target {
723 struct pipe_stream_output_target b;
724
725 /* The buffer where BUFFER_FILLED_SIZE is stored. */
726 struct si_resource *buf_filled_size;
727 unsigned buf_filled_size_offset;
728 bool buf_filled_size_valid;
729
730 unsigned stride_in_dw;
731 };
732
733 struct si_streamout {
734 bool begin_emitted;
735
736 unsigned enabled_mask;
737 unsigned num_targets;
738 struct si_streamout_target *targets[PIPE_MAX_SO_BUFFERS];
739
740 unsigned append_bitmask;
741 bool suspended;
742
743 /* External state which comes from the vertex shader,
744 * it must be set explicitly when binding a shader. */
745 uint16_t *stride_in_dw;
746 unsigned enabled_stream_buffers_mask; /* stream0 buffers0-3 in 4 LSB */
747
748 /* The state of VGT_STRMOUT_BUFFER_(CONFIG|EN). */
749 unsigned hw_enabled_mask;
750
751 /* The state of VGT_STRMOUT_(CONFIG|EN). */
752 bool streamout_enabled;
753 bool prims_gen_query_enabled;
754 int num_prims_gen_queries;
755 };
756
757 /* A shader state consists of the shader selector, which is a constant state
758 * object shared by multiple contexts and shouldn't be modified, and
759 * the current shader variant selected for this context.
760 */
761 struct si_shader_ctx_state {
762 struct si_shader_selector *cso;
763 struct si_shader *current;
764 };
765
766 #define SI_NUM_VGT_PARAM_KEY_BITS 12
767 #define SI_NUM_VGT_PARAM_STATES (1 << SI_NUM_VGT_PARAM_KEY_BITS)
768
769 /* The IA_MULTI_VGT_PARAM key used to index the table of precomputed values.
770 * Some fields are set by state-change calls, most are set by draw_vbo.
771 */
772 union si_vgt_param_key {
773 struct {
774 #ifdef PIPE_ARCH_LITTLE_ENDIAN
775 unsigned prim:4;
776 unsigned uses_instancing:1;
777 unsigned multi_instances_smaller_than_primgroup:1;
778 unsigned primitive_restart:1;
779 unsigned count_from_stream_output:1;
780 unsigned line_stipple_enabled:1;
781 unsigned uses_tess:1;
782 unsigned tess_uses_prim_id:1;
783 unsigned uses_gs:1;
784 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
785 #else /* PIPE_ARCH_BIG_ENDIAN */
786 unsigned _pad:32 - SI_NUM_VGT_PARAM_KEY_BITS;
787 unsigned uses_gs:1;
788 unsigned tess_uses_prim_id:1;
789 unsigned uses_tess:1;
790 unsigned line_stipple_enabled:1;
791 unsigned count_from_stream_output:1;
792 unsigned primitive_restart:1;
793 unsigned multi_instances_smaller_than_primgroup:1;
794 unsigned uses_instancing:1;
795 unsigned prim:4;
796 #endif
797 } u;
798 uint32_t index;
799 };
800
801 #define SI_NUM_VGT_STAGES_KEY_BITS 4
802 #define SI_NUM_VGT_STAGES_STATES (1 << SI_NUM_VGT_STAGES_KEY_BITS)
803
804 /* The VGT_SHADER_STAGES key used to index the table of precomputed values.
805 * Some fields are set by state-change calls, most are set by draw_vbo.
806 */
807 union si_vgt_stages_key {
808 struct {
809 #ifdef PIPE_ARCH_LITTLE_ENDIAN
810 unsigned tess:1;
811 unsigned gs:1;
812 unsigned ngg:1; /* gfx10+ */
813 unsigned streamout:1; /* only used with NGG */
814 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
815 #else /* PIPE_ARCH_BIG_ENDIAN */
816 unsigned _pad:32 - SI_NUM_VGT_STAGES_KEY_BITS;
817 unsigned streamout:1;
818 unsigned ngg:1;
819 unsigned gs:1;
820 unsigned tess:1;
821 #endif
822 } u;
823 uint32_t index;
824 };
825
826 struct si_texture_handle
827 {
828 unsigned desc_slot;
829 bool desc_dirty;
830 struct pipe_sampler_view *view;
831 struct si_sampler_state sstate;
832 };
833
834 struct si_image_handle
835 {
836 unsigned desc_slot;
837 bool desc_dirty;
838 struct pipe_image_view view;
839 };
840
841 struct si_saved_cs {
842 struct pipe_reference reference;
843 struct si_context *ctx;
844 struct radeon_saved_cs gfx;
845 struct radeon_saved_cs compute;
846 struct si_resource *trace_buf;
847 unsigned trace_id;
848
849 unsigned gfx_last_dw;
850 unsigned compute_last_dw;
851 bool flushed;
852 int64_t time_flush;
853 };
854
855 struct si_sdma_upload {
856 struct si_resource *dst;
857 struct si_resource *src;
858 unsigned src_offset;
859 unsigned dst_offset;
860 unsigned size;
861 };
862
863 struct si_context {
864 struct pipe_context b; /* base class */
865
866 enum radeon_family family;
867 enum chip_class chip_class;
868
869 struct radeon_winsys *ws;
870 struct radeon_winsys_ctx *ctx;
871 struct radeon_cmdbuf *gfx_cs; /* compute IB if graphics is disabled */
872 struct radeon_cmdbuf *dma_cs;
873 struct pipe_fence_handle *last_gfx_fence;
874 struct pipe_fence_handle *last_sdma_fence;
875 struct si_resource *eop_bug_scratch;
876 struct u_upload_mgr *cached_gtt_allocator;
877 struct threaded_context *tc;
878 struct u_suballocator *allocator_zeroed_memory;
879 struct slab_child_pool pool_transfers;
880 struct slab_child_pool pool_transfers_unsync; /* for threaded_context */
881 struct pipe_device_reset_callback device_reset_callback;
882 struct u_log_context *log;
883 void *query_result_shader;
884 void *sh_query_result_shader;
885
886 void (*emit_cache_flush)(struct si_context *ctx);
887
888 struct blitter_context *blitter;
889 void *noop_blend;
890 void *custom_dsa_flush;
891 void *custom_blend_resolve;
892 void *custom_blend_fmask_decompress;
893 void *custom_blend_eliminate_fastclear;
894 void *custom_blend_dcc_decompress;
895 void *vs_blit_pos;
896 void *vs_blit_pos_layered;
897 void *vs_blit_color;
898 void *vs_blit_color_layered;
899 void *vs_blit_texcoord;
900 void *cs_clear_buffer;
901 void *cs_copy_buffer;
902 void *cs_copy_image;
903 void *cs_copy_image_1d_array;
904 void *cs_clear_render_target;
905 void *cs_clear_render_target_1d_array;
906 void *cs_dcc_retile;
907 struct si_screen *screen;
908 struct pipe_debug_callback debug;
909 struct ac_llvm_compiler compiler; /* only non-threaded compilation */
910 struct si_shader_ctx_state fixed_func_tcs_shader;
911 /* Offset 0: EOP flush number; Offset 4: GDS prim restart counter */
912 struct si_resource *wait_mem_scratch;
913 unsigned wait_mem_number;
914 uint16_t prefetch_L2_mask;
915
916 bool has_graphics;
917 bool gfx_flush_in_progress:1;
918 bool gfx_last_ib_is_busy:1;
919 bool compute_is_busy:1;
920
921 unsigned num_gfx_cs_flushes;
922 unsigned initial_gfx_cs_size;
923 unsigned last_dirty_tex_counter;
924 unsigned last_dirty_buf_counter;
925 unsigned last_compressed_colortex_counter;
926 unsigned last_num_draw_calls;
927 unsigned flags; /* flush flags */
928 /* Current unaccounted memory usage. */
929 uint64_t vram;
930 uint64_t gtt;
931
932 /* Compute-based primitive discard. */
933 unsigned prim_discard_vertex_count_threshold;
934 struct pb_buffer *gds;
935 struct pb_buffer *gds_oa;
936 struct radeon_cmdbuf *prim_discard_compute_cs;
937 unsigned compute_gds_offset;
938 struct si_shader *compute_ib_last_shader;
939 uint32_t compute_rewind_va;
940 unsigned compute_num_prims_in_batch;
941 bool preserve_prim_restart_gds_at_flush;
942 /* index_ring is divided into 2 halves for doublebuffering. */
943 struct si_resource *index_ring;
944 unsigned index_ring_base; /* offset of a per-IB portion */
945 unsigned index_ring_offset; /* offset within a per-IB portion */
946 unsigned index_ring_size_per_ib; /* max available size per IB */
947 bool prim_discard_compute_ib_initialized;
948 /* For tracking the last execution barrier - it can be either
949 * a WRITE_DATA packet or a fence. */
950 uint32_t *last_pkt3_write_data;
951 struct si_resource *barrier_buf;
952 unsigned barrier_buf_offset;
953 struct pipe_fence_handle *last_ib_barrier_fence;
954 struct si_resource *last_ib_barrier_buf;
955 unsigned last_ib_barrier_buf_offset;
956
957 /* Atoms (direct states). */
958 union si_state_atoms atoms;
959 unsigned dirty_atoms; /* mask */
960 /* PM4 states (precomputed immutable states) */
961 unsigned dirty_states;
962 union si_state queued;
963 union si_state emitted;
964
965 /* Atom declarations. */
966 struct si_framebuffer framebuffer;
967 unsigned sample_locs_num_samples;
968 uint16_t sample_mask;
969 unsigned last_cb_target_mask;
970 struct si_blend_color blend_color;
971 struct si_clip_state clip_state;
972 struct si_shader_data shader_pointers;
973 struct si_stencil_ref stencil_ref;
974 struct pipe_scissor_state scissors[SI_MAX_VIEWPORTS];
975 struct si_streamout streamout;
976 struct si_viewports viewports;
977 unsigned num_window_rectangles;
978 bool window_rectangles_include;
979 struct pipe_scissor_state window_rectangles[4];
980
981 /* Precomputed states. */
982 struct si_pm4_state *init_config;
983 struct si_pm4_state *init_config_gs_rings;
984 bool init_config_has_vgt_flush;
985 struct si_pm4_state *vgt_shader_config[SI_NUM_VGT_STAGES_STATES];
986
987 /* shaders */
988 struct si_shader_ctx_state ps_shader;
989 struct si_shader_ctx_state gs_shader;
990 struct si_shader_ctx_state vs_shader;
991 struct si_shader_ctx_state tcs_shader;
992 struct si_shader_ctx_state tes_shader;
993 struct si_shader_ctx_state cs_prim_discard_state;
994 struct si_cs_shader_state cs_shader_state;
995
996 /* shader information */
997 struct si_vertex_elements *vertex_elements;
998 unsigned sprite_coord_enable;
999 unsigned cs_max_waves_per_sh;
1000 bool flatshade;
1001 bool do_update_shaders;
1002
1003 /* vertex buffer descriptors */
1004 uint32_t *vb_descriptors_gpu_list;
1005 struct si_resource *vb_descriptors_buffer;
1006 unsigned vb_descriptors_offset;
1007
1008 /* shader descriptors */
1009 struct si_descriptors descriptors[SI_NUM_DESCS];
1010 unsigned descriptors_dirty;
1011 unsigned shader_pointers_dirty;
1012 unsigned shader_needs_decompress_mask;
1013 struct si_buffer_resources rw_buffers;
1014 struct si_buffer_resources const_and_shader_buffers[SI_NUM_SHADERS];
1015 struct si_samplers samplers[SI_NUM_SHADERS];
1016 struct si_images images[SI_NUM_SHADERS];
1017 bool bo_list_add_all_resident_resources;
1018 bool bo_list_add_all_gfx_resources;
1019 bool bo_list_add_all_compute_resources;
1020
1021 /* other shader resources */
1022 struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on GFX7 */
1023 struct pipe_resource *esgs_ring;
1024 struct pipe_resource *gsvs_ring;
1025 struct pipe_resource *tess_rings;
1026 union pipe_color_union *border_color_table; /* in CPU memory, any endian */
1027 struct si_resource *border_color_buffer;
1028 union pipe_color_union *border_color_map; /* in VRAM (slow access), little endian */
1029 unsigned border_color_count;
1030 unsigned num_vs_blit_sgprs;
1031 uint32_t vs_blit_sh_data[SI_VS_BLIT_SGPRS_POS_TEXCOORD];
1032 uint32_t cs_user_data[4];
1033
1034 /* Vertex and index buffers. */
1035 bool vertex_buffers_dirty;
1036 bool vertex_buffer_pointer_dirty;
1037 struct pipe_vertex_buffer vertex_buffer[SI_NUM_VERTEX_BUFFERS];
1038 uint16_t vertex_buffer_unaligned; /* bitmask of not dword-aligned buffers */
1039
1040 /* MSAA config state. */
1041 int ps_iter_samples;
1042 bool ps_uses_fbfetch;
1043 bool smoothing_enabled;
1044
1045 /* DB render state. */
1046 unsigned ps_db_shader_control;
1047 unsigned dbcb_copy_sample;
1048 bool dbcb_depth_copy_enabled:1;
1049 bool dbcb_stencil_copy_enabled:1;
1050 bool db_flush_depth_inplace:1;
1051 bool db_flush_stencil_inplace:1;
1052 bool db_depth_clear:1;
1053 bool db_depth_disable_expclear:1;
1054 bool db_stencil_clear:1;
1055 bool db_stencil_disable_expclear:1;
1056 bool occlusion_queries_disabled:1;
1057 bool generate_mipmap_for_depth:1;
1058
1059 /* Emitted draw state. */
1060 bool gs_tri_strip_adj_fix:1;
1061 bool ls_vgpr_fix:1;
1062 bool prim_discard_cs_instancing:1;
1063 bool ngg:1;
1064 int last_index_size;
1065 int last_base_vertex;
1066 int last_start_instance;
1067 int last_instance_count;
1068 int last_drawid;
1069 int last_sh_base_reg;
1070 int last_primitive_restart_en;
1071 int last_restart_index;
1072 int last_prim;
1073 int last_multi_vgt_param;
1074 int last_rast_prim;
1075 int last_flatshade_first;
1076 int last_binning_enabled;
1077 unsigned last_sc_line_stipple;
1078 unsigned current_vs_state;
1079 unsigned last_vs_state;
1080 enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */
1081
1082 /* Scratch buffer */
1083 struct si_resource *scratch_buffer;
1084 unsigned scratch_waves;
1085 unsigned spi_tmpring_size;
1086
1087 struct si_resource *compute_scratch_buffer;
1088
1089 /* Emitted derived tessellation state. */
1090 /* Local shader (VS), or HS if LS-HS are merged. */
1091 struct si_shader *last_ls;
1092 struct si_shader_selector *last_tcs;
1093 int last_num_tcs_input_cp;
1094 int last_tes_sh_base;
1095 bool last_tess_uses_primid;
1096 unsigned last_num_patches;
1097 int last_ls_hs_config;
1098
1099 /* Debug state. */
1100 bool is_debug;
1101 struct si_saved_cs *current_saved_cs;
1102 uint64_t dmesg_timestamp;
1103 unsigned apitrace_call_number;
1104
1105 /* Other state */
1106 bool need_check_render_feedback;
1107 bool decompression_enabled;
1108 bool dpbb_force_off;
1109 bool vs_writes_viewport_index;
1110 bool vs_disables_clipping_viewport;
1111
1112 /* Precomputed IA_MULTI_VGT_PARAM */
1113 union si_vgt_param_key ia_multi_vgt_param_key;
1114 unsigned ia_multi_vgt_param[SI_NUM_VGT_PARAM_STATES];
1115
1116 /* Bindless descriptors. */
1117 struct si_descriptors bindless_descriptors;
1118 struct util_idalloc bindless_used_slots;
1119 unsigned num_bindless_descriptors;
1120 bool bindless_descriptors_dirty;
1121 bool graphics_bindless_pointer_dirty;
1122 bool compute_bindless_pointer_dirty;
1123
1124 /* Allocated bindless handles */
1125 struct hash_table *tex_handles;
1126 struct hash_table *img_handles;
1127
1128 /* Resident bindless handles */
1129 struct util_dynarray resident_tex_handles;
1130 struct util_dynarray resident_img_handles;
1131
1132 /* Resident bindless handles which need decompression */
1133 struct util_dynarray resident_tex_needs_color_decompress;
1134 struct util_dynarray resident_img_needs_color_decompress;
1135 struct util_dynarray resident_tex_needs_depth_decompress;
1136
1137 /* Bindless state */
1138 bool uses_bindless_samplers;
1139 bool uses_bindless_images;
1140
1141 /* MSAA sample locations.
1142 * The first index is the sample index.
1143 * The second index is the coordinate: X, Y. */
1144 struct {
1145 float x1[1][2];
1146 float x2[2][2];
1147 float x4[4][2];
1148 float x8[8][2];
1149 float x16[16][2];
1150 } sample_positions;
1151 struct pipe_resource *sample_pos_buffer;
1152
1153 /* Misc stats. */
1154 unsigned num_draw_calls;
1155 unsigned num_decompress_calls;
1156 unsigned num_mrt_draw_calls;
1157 unsigned num_prim_restart_calls;
1158 unsigned num_spill_draw_calls;
1159 unsigned num_compute_calls;
1160 unsigned num_spill_compute_calls;
1161 unsigned num_dma_calls;
1162 unsigned num_cp_dma_calls;
1163 unsigned num_vs_flushes;
1164 unsigned num_ps_flushes;
1165 unsigned num_cs_flushes;
1166 unsigned num_cb_cache_flushes;
1167 unsigned num_db_cache_flushes;
1168 unsigned num_L2_invalidates;
1169 unsigned num_L2_writebacks;
1170 unsigned num_resident_handles;
1171 uint64_t num_alloc_tex_transfer_bytes;
1172 unsigned last_tex_ps_draw_ratio; /* for query */
1173 unsigned compute_num_verts_accepted;
1174 unsigned compute_num_verts_rejected;
1175 unsigned compute_num_verts_ineligible; /* due to low vertex count */
1176 unsigned context_roll;
1177
1178 /* Queries. */
1179 /* Maintain the list of active queries for pausing between IBs. */
1180 int num_occlusion_queries;
1181 int num_perfect_occlusion_queries;
1182 int num_pipeline_stat_queries;
1183 struct list_head active_queries;
1184 unsigned num_cs_dw_queries_suspend;
1185
1186 /* Render condition. */
1187 struct pipe_query *render_cond;
1188 unsigned render_cond_mode;
1189 bool render_cond_invert;
1190 bool render_cond_force_off; /* for u_blitter */
1191
1192 /* For uploading data via GTT and copy to VRAM on context flush via SDMA. */
1193 bool sdma_uploads_in_progress;
1194 struct si_sdma_upload *sdma_uploads;
1195 unsigned num_sdma_uploads;
1196 unsigned max_sdma_uploads;
1197
1198 /* Shader-based queries. */
1199 struct list_head shader_query_buffers;
1200 unsigned num_active_shader_queries;
1201
1202 /* Statistics gathering for the DCC enablement heuristic. It can't be
1203 * in si_texture because si_texture can be shared by multiple
1204 * contexts. This is for back buffers only. We shouldn't get too many
1205 * of those.
1206 *
1207 * X11 DRI3 rotates among a finite set of back buffers. They should
1208 * all fit in this array. If they don't, separate DCC might never be
1209 * enabled by DCC stat gathering.
1210 */
1211 struct {
1212 struct si_texture *tex;
1213 /* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
1214 struct pipe_query *ps_stats[3];
1215 /* If all slots are used and another slot is needed,
1216 * the least recently used slot is evicted based on this. */
1217 int64_t last_use_timestamp;
1218 bool query_active;
1219 } dcc_stats[5];
1220
1221 /* Copy one resource to another using async DMA. */
1222 void (*dma_copy)(struct pipe_context *ctx,
1223 struct pipe_resource *dst,
1224 unsigned dst_level,
1225 unsigned dst_x, unsigned dst_y, unsigned dst_z,
1226 struct pipe_resource *src,
1227 unsigned src_level,
1228 const struct pipe_box *src_box);
1229
1230 struct si_tracked_regs tracked_regs;
1231 };
1232
1233 /* cik_sdma.c */
1234 void cik_init_sdma_functions(struct si_context *sctx);
1235
1236 /* si_blit.c */
1237 enum si_blitter_op /* bitmask */
1238 {
1239 SI_SAVE_TEXTURES = 1,
1240 SI_SAVE_FRAMEBUFFER = 2,
1241 SI_SAVE_FRAGMENT_STATE = 4,
1242 SI_DISABLE_RENDER_COND = 8,
1243 };
1244
1245 void si_blitter_begin(struct si_context *sctx, enum si_blitter_op op);
1246 void si_blitter_end(struct si_context *sctx);
1247 void si_init_blit_functions(struct si_context *sctx);
1248 void si_decompress_textures(struct si_context *sctx, unsigned shader_mask);
1249 void si_resource_copy_region(struct pipe_context *ctx,
1250 struct pipe_resource *dst,
1251 unsigned dst_level,
1252 unsigned dstx, unsigned dsty, unsigned dstz,
1253 struct pipe_resource *src,
1254 unsigned src_level,
1255 const struct pipe_box *src_box);
1256 void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
1257
1258 /* si_buffer.c */
1259 bool si_rings_is_buffer_referenced(struct si_context *sctx,
1260 struct pb_buffer *buf,
1261 enum radeon_bo_usage usage);
1262 void *si_buffer_map_sync_with_rings(struct si_context *sctx,
1263 struct si_resource *resource,
1264 unsigned usage);
1265 void si_init_resource_fields(struct si_screen *sscreen,
1266 struct si_resource *res,
1267 uint64_t size, unsigned alignment);
1268 bool si_alloc_resource(struct si_screen *sscreen,
1269 struct si_resource *res);
1270 struct pipe_resource *pipe_aligned_buffer_create(struct pipe_screen *screen,
1271 unsigned flags, unsigned usage,
1272 unsigned size, unsigned alignment);
1273 struct si_resource *si_aligned_buffer_create(struct pipe_screen *screen,
1274 unsigned flags, unsigned usage,
1275 unsigned size, unsigned alignment);
1276 void si_replace_buffer_storage(struct pipe_context *ctx,
1277 struct pipe_resource *dst,
1278 struct pipe_resource *src);
1279 void si_init_screen_buffer_functions(struct si_screen *sscreen);
1280 void si_init_buffer_functions(struct si_context *sctx);
1281
1282 /* si_clear.c */
1283 enum pipe_format si_simplify_cb_format(enum pipe_format format);
1284 bool vi_alpha_is_on_msb(struct si_screen *sscreen, enum pipe_format format);
1285 bool vi_dcc_clear_level(struct si_context *sctx,
1286 struct si_texture *tex,
1287 unsigned level, unsigned clear_value);
1288 void si_init_clear_functions(struct si_context *sctx);
1289
1290 /* si_compute_blit.c */
1291 unsigned si_get_flush_flags(struct si_context *sctx, enum si_coherency coher,
1292 enum si_cache_policy cache_policy);
1293 void si_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1294 uint64_t offset, uint64_t size, uint32_t *clear_value,
1295 uint32_t clear_value_size, enum si_coherency coher,
1296 bool force_cpdma);
1297 void si_copy_buffer(struct si_context *sctx,
1298 struct pipe_resource *dst, struct pipe_resource *src,
1299 uint64_t dst_offset, uint64_t src_offset, unsigned size);
1300 void si_compute_copy_image(struct si_context *sctx,
1301 struct pipe_resource *dst,
1302 unsigned dst_level,
1303 struct pipe_resource *src,
1304 unsigned src_level,
1305 unsigned dstx, unsigned dsty, unsigned dstz,
1306 const struct pipe_box *src_box);
1307 void si_compute_clear_render_target(struct pipe_context *ctx,
1308 struct pipe_surface *dstsurf,
1309 const union pipe_color_union *color,
1310 unsigned dstx, unsigned dsty,
1311 unsigned width, unsigned height,
1312 bool render_condition_enabled);
1313 void si_retile_dcc(struct si_context *sctx, struct si_texture *tex);
1314 void si_init_compute_blit_functions(struct si_context *sctx);
1315
1316 /* si_cp_dma.c */
1317 #define SI_CPDMA_SKIP_CHECK_CS_SPACE (1 << 0) /* don't call need_cs_space */
1318 #define SI_CPDMA_SKIP_SYNC_AFTER (1 << 1) /* don't wait for DMA after the copy */
1319 #define SI_CPDMA_SKIP_SYNC_BEFORE (1 << 2) /* don't wait for DMA before the copy (RAW hazards) */
1320 #define SI_CPDMA_SKIP_GFX_SYNC (1 << 3) /* don't flush caches and don't wait for PS/CS */
1321 #define SI_CPDMA_SKIP_BO_LIST_UPDATE (1 << 4) /* don't update the BO list */
1322 #define SI_CPDMA_SKIP_ALL (SI_CPDMA_SKIP_CHECK_CS_SPACE | \
1323 SI_CPDMA_SKIP_SYNC_AFTER | \
1324 SI_CPDMA_SKIP_SYNC_BEFORE | \
1325 SI_CPDMA_SKIP_GFX_SYNC | \
1326 SI_CPDMA_SKIP_BO_LIST_UPDATE)
1327
1328 void si_cp_dma_wait_for_idle(struct si_context *sctx);
1329 void si_cp_dma_clear_buffer(struct si_context *sctx, struct radeon_cmdbuf *cs,
1330 struct pipe_resource *dst, uint64_t offset,
1331 uint64_t size, unsigned value, unsigned user_flags,
1332 enum si_coherency coher, enum si_cache_policy cache_policy);
1333 void si_cp_dma_copy_buffer(struct si_context *sctx,
1334 struct pipe_resource *dst, struct pipe_resource *src,
1335 uint64_t dst_offset, uint64_t src_offset, unsigned size,
1336 unsigned user_flags, enum si_coherency coher,
1337 enum si_cache_policy cache_policy);
1338 void cik_prefetch_TC_L2_async(struct si_context *sctx, struct pipe_resource *buf,
1339 uint64_t offset, unsigned size);
1340 void cik_emit_prefetch_L2(struct si_context *sctx, bool vertex_stage_only);
1341 void si_test_gds(struct si_context *sctx);
1342 void si_cp_write_data(struct si_context *sctx, struct si_resource *buf,
1343 unsigned offset, unsigned size, unsigned dst_sel,
1344 unsigned engine, const void *data);
1345 void si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs,
1346 unsigned dst_sel, struct si_resource *dst, unsigned dst_offset,
1347 unsigned src_sel, struct si_resource *src, unsigned src_offset);
1348
1349 /* si_debug.c */
1350 void si_save_cs(struct radeon_winsys *ws, struct radeon_cmdbuf *cs,
1351 struct radeon_saved_cs *saved, bool get_buffer_list);
1352 void si_clear_saved_cs(struct radeon_saved_cs *saved);
1353 void si_destroy_saved_cs(struct si_saved_cs *scs);
1354 void si_auto_log_cs(void *data, struct u_log_context *log);
1355 void si_log_hw_flush(struct si_context *sctx);
1356 void si_log_draw_state(struct si_context *sctx, struct u_log_context *log);
1357 void si_log_compute_state(struct si_context *sctx, struct u_log_context *log);
1358 void si_init_debug_functions(struct si_context *sctx);
1359 void si_check_vm_faults(struct si_context *sctx,
1360 struct radeon_saved_cs *saved, enum ring_type ring);
1361 bool si_replace_shader(unsigned num, struct si_shader_binary *binary);
1362
1363 /* si_dma.c */
1364 void si_init_dma_functions(struct si_context *sctx);
1365
1366 /* si_dma_cs.c */
1367 void si_dma_emit_timestamp(struct si_context *sctx, struct si_resource *dst,
1368 uint64_t offset);
1369 void si_sdma_clear_buffer(struct si_context *sctx, struct pipe_resource *dst,
1370 uint64_t offset, uint64_t size, unsigned clear_value);
1371 void si_need_dma_space(struct si_context *ctx, unsigned num_dw,
1372 struct si_resource *dst, struct si_resource *src);
1373 void si_flush_dma_cs(struct si_context *ctx, unsigned flags,
1374 struct pipe_fence_handle **fence);
1375 void si_screen_clear_buffer(struct si_screen *sscreen, struct pipe_resource *dst,
1376 uint64_t offset, uint64_t size, unsigned value);
1377
1378 /* si_fence.c */
1379 void si_cp_release_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1380 unsigned event, unsigned event_flags,
1381 unsigned dst_sel, unsigned int_sel, unsigned data_sel,
1382 struct si_resource *buf, uint64_t va,
1383 uint32_t new_fence, unsigned query_type);
1384 unsigned si_cp_write_fence_dwords(struct si_screen *screen);
1385 void si_cp_wait_mem(struct si_context *ctx, struct radeon_cmdbuf *cs,
1386 uint64_t va, uint32_t ref, uint32_t mask, unsigned flags);
1387 void si_init_fence_functions(struct si_context *ctx);
1388 void si_init_screen_fence_functions(struct si_screen *screen);
1389 struct pipe_fence_handle *si_create_fence(struct pipe_context *ctx,
1390 struct tc_unflushed_batch_token *tc_token);
1391
1392 /* si_get.c */
1393 void si_init_screen_get_functions(struct si_screen *sscreen);
1394
1395 /* si_gfx_cs.c */
1396 void si_flush_gfx_cs(struct si_context *ctx, unsigned flags,
1397 struct pipe_fence_handle **fence);
1398 void si_allocate_gds(struct si_context *ctx);
1399 void si_begin_new_gfx_cs(struct si_context *ctx);
1400 void si_need_gfx_cs_space(struct si_context *ctx);
1401 void si_unref_sdma_uploads(struct si_context *sctx);
1402
1403 /* si_gpu_load.c */
1404 void si_gpu_load_kill_thread(struct si_screen *sscreen);
1405 uint64_t si_begin_counter(struct si_screen *sscreen, unsigned type);
1406 unsigned si_end_counter(struct si_screen *sscreen, unsigned type,
1407 uint64_t begin);
1408
1409 /* si_compute.c */
1410 void si_emit_initial_compute_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
1411 void si_init_compute_functions(struct si_context *sctx);
1412
1413 /* si_compute_prim_discard.c */
1414 enum si_prim_discard_outcome {
1415 SI_PRIM_DISCARD_ENABLED,
1416 SI_PRIM_DISCARD_DISABLED,
1417 SI_PRIM_DISCARD_DRAW_SPLIT,
1418 };
1419
1420 void si_build_prim_discard_compute_shader(struct si_shader_context *ctx);
1421 enum si_prim_discard_outcome
1422 si_prepare_prim_discard_or_split_draw(struct si_context *sctx,
1423 const struct pipe_draw_info *info,
1424 bool primitive_restart);
1425 void si_compute_signal_gfx(struct si_context *sctx);
1426 void si_dispatch_prim_discard_cs_and_draw(struct si_context *sctx,
1427 const struct pipe_draw_info *info,
1428 unsigned index_size,
1429 unsigned base_vertex,
1430 uint64_t input_indexbuf_va,
1431 unsigned input_indexbuf_max_elements);
1432 void si_initialize_prim_discard_tunables(struct si_context *sctx);
1433
1434 /* si_perfcounters.c */
1435 void si_init_perfcounters(struct si_screen *screen);
1436 void si_destroy_perfcounters(struct si_screen *screen);
1437
1438 /* si_pipe.c */
1439 bool si_check_device_reset(struct si_context *sctx);
1440
1441 /* si_query.c */
1442 void si_init_screen_query_functions(struct si_screen *sscreen);
1443 void si_init_query_functions(struct si_context *sctx);
1444 void si_suspend_queries(struct si_context *sctx);
1445 void si_resume_queries(struct si_context *sctx);
1446
1447 /* si_shaderlib_tgsi.c */
1448 void *si_get_blitter_vs(struct si_context *sctx, enum blitter_attrib_type type,
1449 unsigned num_layers);
1450 void *si_create_fixed_func_tcs(struct si_context *sctx);
1451 void *si_create_dma_compute_shader(struct pipe_context *ctx,
1452 unsigned num_dwords_per_thread,
1453 bool dst_stream_cache_policy, bool is_copy);
1454 void *si_create_copy_image_compute_shader(struct pipe_context *ctx);
1455 void *si_create_copy_image_compute_shader_1d_array(struct pipe_context *ctx);
1456 void *si_clear_render_target_shader(struct pipe_context *ctx);
1457 void *si_clear_render_target_shader_1d_array(struct pipe_context *ctx);
1458 void *si_create_dcc_retile_cs(struct pipe_context *ctx);
1459 void *si_create_query_result_cs(struct si_context *sctx);
1460 void *gfx10_create_sh_query_result_cs(struct si_context *sctx);
1461
1462 /* gfx10_query.c */
1463 void gfx10_init_query(struct si_context *sctx);
1464 void gfx10_destroy_query(struct si_context *sctx);
1465
1466 /* si_test_dma.c */
1467 void si_test_dma(struct si_screen *sscreen);
1468
1469 /* si_test_clearbuffer.c */
1470 void si_test_dma_perf(struct si_screen *sscreen);
1471
1472 /* si_uvd.c */
1473 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
1474 const struct pipe_video_codec *templ);
1475
1476 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
1477 const struct pipe_video_buffer *tmpl);
1478
1479 /* si_viewport.c */
1480 void si_update_vs_viewport_state(struct si_context *ctx);
1481 void si_init_viewport_functions(struct si_context *ctx);
1482
1483 /* si_texture.c */
1484 bool si_prepare_for_dma_blit(struct si_context *sctx,
1485 struct si_texture *dst,
1486 unsigned dst_level, unsigned dstx,
1487 unsigned dsty, unsigned dstz,
1488 struct si_texture *src,
1489 unsigned src_level,
1490 const struct pipe_box *src_box);
1491 void si_eliminate_fast_color_clear(struct si_context *sctx,
1492 struct si_texture *tex);
1493 void si_texture_discard_cmask(struct si_screen *sscreen,
1494 struct si_texture *tex);
1495 bool si_init_flushed_depth_texture(struct pipe_context *ctx,
1496 struct pipe_resource *texture);
1497 void si_print_texture_info(struct si_screen *sscreen,
1498 struct si_texture *tex, struct u_log_context *log);
1499 struct pipe_resource *si_texture_create(struct pipe_screen *screen,
1500 const struct pipe_resource *templ);
1501 bool vi_dcc_formats_compatible(struct si_screen *sscreen,
1502 enum pipe_format format1,
1503 enum pipe_format format2);
1504 bool vi_dcc_formats_are_incompatible(struct pipe_resource *tex,
1505 unsigned level,
1506 enum pipe_format view_format);
1507 void vi_disable_dcc_if_incompatible_format(struct si_context *sctx,
1508 struct pipe_resource *tex,
1509 unsigned level,
1510 enum pipe_format view_format);
1511 struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
1512 struct pipe_resource *texture,
1513 const struct pipe_surface *templ,
1514 unsigned width0, unsigned height0,
1515 unsigned width, unsigned height);
1516 unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
1517 void vi_separate_dcc_try_enable(struct si_context *sctx,
1518 struct si_texture *tex);
1519 void vi_separate_dcc_start_query(struct si_context *sctx,
1520 struct si_texture *tex);
1521 void vi_separate_dcc_stop_query(struct si_context *sctx,
1522 struct si_texture *tex);
1523 void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
1524 struct si_texture *tex);
1525 bool si_texture_disable_dcc(struct si_context *sctx,
1526 struct si_texture *tex);
1527 void si_init_screen_texture_functions(struct si_screen *sscreen);
1528 void si_init_context_texture_functions(struct si_context *sctx);
1529
1530
1531 /*
1532 * common helpers
1533 */
1534
1535 static inline struct si_resource *si_resource(struct pipe_resource *r)
1536 {
1537 return (struct si_resource*)r;
1538 }
1539
1540 static inline void
1541 si_resource_reference(struct si_resource **ptr, struct si_resource *res)
1542 {
1543 pipe_resource_reference((struct pipe_resource **)ptr,
1544 (struct pipe_resource *)res);
1545 }
1546
1547 static inline void
1548 si_texture_reference(struct si_texture **ptr, struct si_texture *res)
1549 {
1550 pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
1551 }
1552
1553 static inline bool
1554 vi_dcc_enabled(struct si_texture *tex, unsigned level)
1555 {
1556 return tex->dcc_offset && level < tex->surface.num_dcc_levels;
1557 }
1558
1559 static inline unsigned
1560 si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
1561 {
1562 if (stencil)
1563 return tex->surface.u.legacy.stencil_tiling_index[level];
1564 else
1565 return tex->surface.u.legacy.tiling_index[level];
1566 }
1567
1568 static inline unsigned
1569 si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx)
1570 {
1571 /* Don't count the needed CS space exactly and just use an upper bound.
1572 *
1573 * Also reserve space for stopping queries at the end of IB, because
1574 * the number of active queries is unlimited in theory.
1575 */
1576 return 2048 + sctx->num_cs_dw_queries_suspend;
1577 }
1578
1579 static inline void
1580 si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
1581 {
1582 if (r) {
1583 /* Add memory usage for need_gfx_cs_space */
1584 sctx->vram += si_resource(r)->vram_usage;
1585 sctx->gtt += si_resource(r)->gart_usage;
1586 }
1587 }
1588
1589 static inline void
1590 si_invalidate_draw_sh_constants(struct si_context *sctx)
1591 {
1592 sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
1593 sctx->last_instance_count = SI_INSTANCE_COUNT_UNKNOWN;
1594 }
1595
1596 static inline unsigned
1597 si_get_atom_bit(struct si_context *sctx, struct si_atom *atom)
1598 {
1599 return 1 << (atom - sctx->atoms.array);
1600 }
1601
1602 static inline void
1603 si_set_atom_dirty(struct si_context *sctx, struct si_atom *atom, bool dirty)
1604 {
1605 unsigned bit = si_get_atom_bit(sctx, atom);
1606
1607 if (dirty)
1608 sctx->dirty_atoms |= bit;
1609 else
1610 sctx->dirty_atoms &= ~bit;
1611 }
1612
1613 static inline bool
1614 si_is_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1615 {
1616 return (sctx->dirty_atoms & si_get_atom_bit(sctx, atom)) != 0;
1617 }
1618
1619 static inline void
1620 si_mark_atom_dirty(struct si_context *sctx, struct si_atom *atom)
1621 {
1622 si_set_atom_dirty(sctx, atom, true);
1623 }
1624
1625 static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
1626 {
1627 if (sctx->gs_shader.cso)
1628 return &sctx->gs_shader;
1629 if (sctx->tes_shader.cso)
1630 return &sctx->tes_shader;
1631
1632 return &sctx->vs_shader;
1633 }
1634
1635 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
1636 {
1637 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1638
1639 return vs->cso ? &vs->cso->info : NULL;
1640 }
1641
1642 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
1643 {
1644 if (sctx->gs_shader.cso &&
1645 sctx->gs_shader.current &&
1646 !sctx->gs_shader.current->key.as_ngg)
1647 return sctx->gs_shader.cso->gs_copy_shader;
1648
1649 struct si_shader_ctx_state *vs = si_get_vs(sctx);
1650 return vs->current ? vs->current : NULL;
1651 }
1652
1653 static inline bool si_can_dump_shader(struct si_screen *sscreen,
1654 unsigned processor)
1655 {
1656 return sscreen->debug_flags & (1 << processor);
1657 }
1658
1659 static inline bool si_get_strmout_en(struct si_context *sctx)
1660 {
1661 return sctx->streamout.streamout_enabled ||
1662 sctx->streamout.prims_gen_query_enabled;
1663 }
1664
1665 static inline unsigned
1666 si_optimal_tcc_alignment(struct si_context *sctx, unsigned upload_size)
1667 {
1668 unsigned alignment, tcc_cache_line_size;
1669
1670 /* If the upload size is less than the cache line size (e.g. 16, 32),
1671 * the whole thing will fit into a cache line if we align it to its size.
1672 * The idea is that multiple small uploads can share a cache line.
1673 * If the upload size is greater, align it to the cache line size.
1674 */
1675 alignment = util_next_power_of_two(upload_size);
1676 tcc_cache_line_size = sctx->screen->info.tcc_cache_line_size;
1677 return MIN2(alignment, tcc_cache_line_size);
1678 }
1679
1680 static inline void
1681 si_saved_cs_reference(struct si_saved_cs **dst, struct si_saved_cs *src)
1682 {
1683 if (pipe_reference(&(*dst)->reference, &src->reference))
1684 si_destroy_saved_cs(*dst);
1685
1686 *dst = src;
1687 }
1688
1689 static inline void
1690 si_make_CB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1691 bool shaders_read_metadata, bool dcc_pipe_aligned)
1692 {
1693 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
1694 SI_CONTEXT_INV_VCACHE;
1695
1696 if (sctx->chip_class >= GFX10) {
1697 if (shaders_read_metadata)
1698 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1699 } else if (sctx->chip_class == GFX9) {
1700 /* Single-sample color is coherent with shaders on GFX9, but
1701 * L2 metadata must be flushed if shaders read metadata.
1702 * (DCC, CMASK).
1703 */
1704 if (num_samples >= 2 ||
1705 (shaders_read_metadata && !dcc_pipe_aligned))
1706 sctx->flags |= SI_CONTEXT_INV_L2;
1707 else if (shaders_read_metadata)
1708 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1709 } else {
1710 /* GFX6-GFX8 */
1711 sctx->flags |= SI_CONTEXT_INV_L2;
1712 }
1713 }
1714
1715 static inline void
1716 si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
1717 bool include_stencil, bool shaders_read_metadata)
1718 {
1719 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB |
1720 SI_CONTEXT_INV_VCACHE;
1721
1722 if (sctx->chip_class >= GFX10) {
1723 if (shaders_read_metadata)
1724 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1725 } else if (sctx->chip_class == GFX9) {
1726 /* Single-sample depth (not stencil) is coherent with shaders
1727 * on GFX9, but L2 metadata must be flushed if shaders read
1728 * metadata.
1729 */
1730 if (num_samples >= 2 || include_stencil)
1731 sctx->flags |= SI_CONTEXT_INV_L2;
1732 else if (shaders_read_metadata)
1733 sctx->flags |= SI_CONTEXT_INV_L2_METADATA;
1734 } else {
1735 /* GFX6-GFX8 */
1736 sctx->flags |= SI_CONTEXT_INV_L2;
1737 }
1738 }
1739
1740 static inline bool
1741 si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
1742 {
1743 return (stencil_sampler && tex->can_sample_s) ||
1744 (!stencil_sampler && tex->can_sample_z);
1745 }
1746
1747 static inline bool
1748 si_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1749 {
1750 if (zs_mask == PIPE_MASK_S && tex->htile_stencil_disabled)
1751 return false;
1752
1753 return tex->htile_offset && level == 0;
1754 }
1755
1756 static inline bool
1757 vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level, unsigned zs_mask)
1758 {
1759 assert(!tex->tc_compatible_htile || tex->htile_offset);
1760 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask);
1761 }
1762
1763 static inline unsigned si_get_ps_iter_samples(struct si_context *sctx)
1764 {
1765 if (sctx->ps_uses_fbfetch)
1766 return sctx->framebuffer.nr_color_samples;
1767
1768 return MIN2(sctx->ps_iter_samples, sctx->framebuffer.nr_color_samples);
1769 }
1770
1771 static inline unsigned si_get_total_colormask(struct si_context *sctx)
1772 {
1773 if (sctx->queued.named.rasterizer->rasterizer_discard)
1774 return 0;
1775
1776 struct si_shader_selector *ps = sctx->ps_shader.cso;
1777 if (!ps)
1778 return 0;
1779
1780 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit &
1781 sctx->queued.named.blend->cb_target_mask;
1782
1783 if (!ps->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS])
1784 colormask &= ps->colors_written_4bit;
1785 else if (!ps->colors_written_4bit)
1786 colormask = 0; /* color0 writes all cbufs, but it's not written */
1787
1788 return colormask;
1789 }
1790
1791 #define UTIL_ALL_PRIM_LINE_MODES ((1 << PIPE_PRIM_LINES) | \
1792 (1 << PIPE_PRIM_LINE_LOOP) | \
1793 (1 << PIPE_PRIM_LINE_STRIP) | \
1794 (1 << PIPE_PRIM_LINES_ADJACENCY) | \
1795 (1 << PIPE_PRIM_LINE_STRIP_ADJACENCY))
1796
1797 static inline bool util_prim_is_lines(unsigned prim)
1798 {
1799 return ((1 << prim) & UTIL_ALL_PRIM_LINE_MODES) != 0;
1800 }
1801
1802 static inline bool util_prim_is_points_or_lines(unsigned prim)
1803 {
1804 return ((1 << prim) & (UTIL_ALL_PRIM_LINE_MODES |
1805 (1 << PIPE_PRIM_POINTS))) != 0;
1806 }
1807
1808 static inline bool util_rast_prim_is_triangles(unsigned prim)
1809 {
1810 return ((1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1811 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1812 (1 << PIPE_PRIM_TRIANGLE_FAN) |
1813 (1 << PIPE_PRIM_QUADS) |
1814 (1 << PIPE_PRIM_QUAD_STRIP) |
1815 (1 << PIPE_PRIM_POLYGON) |
1816 (1 << PIPE_PRIM_TRIANGLES_ADJACENCY) |
1817 (1 << PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY)));
1818 }
1819
1820 /**
1821 * Return true if there is enough memory in VRAM and GTT for the buffers
1822 * added so far.
1823 *
1824 * \param vram VRAM memory size not added to the buffer list yet
1825 * \param gtt GTT memory size not added to the buffer list yet
1826 */
1827 static inline bool
1828 radeon_cs_memory_below_limit(struct si_screen *screen,
1829 struct radeon_cmdbuf *cs,
1830 uint64_t vram, uint64_t gtt)
1831 {
1832 vram += cs->used_vram;
1833 gtt += cs->used_gart;
1834
1835 /* Anything that goes above the VRAM size should go to GTT. */
1836 if (vram > screen->info.vram_size)
1837 gtt += vram - screen->info.vram_size;
1838
1839 /* Now we just need to check if we have enough GTT. */
1840 return gtt < screen->info.gart_size * 0.7;
1841 }
1842
1843 /**
1844 * Add a buffer to the buffer list for the given command stream (CS).
1845 *
1846 * All buffers used by a CS must be added to the list. This tells the kernel
1847 * driver which buffers are used by GPU commands. Other buffers can
1848 * be swapped out (not accessible) during execution.
1849 *
1850 * The buffer list becomes empty after every context flush and must be
1851 * rebuilt.
1852 */
1853 static inline void radeon_add_to_buffer_list(struct si_context *sctx,
1854 struct radeon_cmdbuf *cs,
1855 struct si_resource *bo,
1856 enum radeon_bo_usage usage,
1857 enum radeon_bo_priority priority)
1858 {
1859 assert(usage);
1860 sctx->ws->cs_add_buffer(
1861 cs, bo->buf,
1862 (enum radeon_bo_usage)(usage | RADEON_USAGE_SYNCHRONIZED),
1863 bo->domains, priority);
1864 }
1865
1866 /**
1867 * Same as above, but also checks memory usage and flushes the context
1868 * accordingly.
1869 *
1870 * When this SHOULD NOT be used:
1871 *
1872 * - if si_context_add_resource_size has been called for the buffer
1873 * followed by *_need_cs_space for checking the memory usage
1874 *
1875 * - if si_need_dma_space has been called for the buffer
1876 *
1877 * - when emitting state packets and draw packets (because preceding packets
1878 * can't be re-emitted at that point)
1879 *
1880 * - if shader resource "enabled_mask" is not up-to-date or there is
1881 * a different constraint disallowing a context flush
1882 */
1883 static inline void
1884 radeon_add_to_gfx_buffer_list_check_mem(struct si_context *sctx,
1885 struct si_resource *bo,
1886 enum radeon_bo_usage usage,
1887 enum radeon_bo_priority priority,
1888 bool check_mem)
1889 {
1890 if (check_mem &&
1891 !radeon_cs_memory_below_limit(sctx->screen, sctx->gfx_cs,
1892 sctx->vram + bo->vram_usage,
1893 sctx->gtt + bo->gart_usage))
1894 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1895
1896 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, bo, usage, priority);
1897 }
1898
1899 static inline bool si_compute_prim_discard_enabled(struct si_context *sctx)
1900 {
1901 return sctx->prim_discard_vertex_count_threshold != UINT_MAX;
1902 }
1903
1904 static inline unsigned si_get_wave_size(struct si_screen *sscreen,
1905 enum pipe_shader_type shader_type,
1906 bool ngg, bool es)
1907 {
1908 if (shader_type == PIPE_SHADER_COMPUTE)
1909 return sscreen->compute_wave_size;
1910 else if (shader_type == PIPE_SHADER_FRAGMENT)
1911 return sscreen->ps_wave_size;
1912 else if ((shader_type == PIPE_SHADER_TESS_EVAL && es && !ngg) ||
1913 (shader_type == PIPE_SHADER_GEOMETRY && !ngg)) /* legacy GS only supports Wave64 */
1914 return 64;
1915 else
1916 return sscreen->ge_wave_size;
1917 }
1918
1919 static inline unsigned si_get_shader_wave_size(struct si_shader *shader)
1920 {
1921 return si_get_wave_size(shader->selector->screen, shader->selector->type,
1922 shader->key.as_ngg, shader->key.as_es);
1923 }
1924
1925 #define PRINT_ERR(fmt, args...) \
1926 fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, ##args)
1927
1928 #endif