2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include "util/u_queue.h"
32 #include <llvm-c/TargetMachine.h>
34 #ifdef PIPE_ARCH_BIG_ENDIAN
35 #define SI_BIG_ENDIAN 1
37 #define SI_BIG_ENDIAN 0
40 /* The base vertex and primitive restart can be any number, but we must pick
41 * one which will mean "unknown" for the purpose of state tracking and
42 * the number shouldn't be a commonly-used one. */
43 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
44 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
45 #define SI_NUM_SMOOTH_AA_SAMPLES 8
46 #define SI_GS_PER_ES 128
48 /* Instruction cache. */
49 #define SI_CONTEXT_INV_ICACHE (R600_CONTEXT_PRIVATE_FLAG << 0)
50 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
51 #define SI_CONTEXT_INV_SMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 1)
52 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
53 #define SI_CONTEXT_INV_VMEM_L1 (R600_CONTEXT_PRIVATE_FLAG << 2)
54 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
55 #define SI_CONTEXT_INV_GLOBAL_L2 (R600_CONTEXT_PRIVATE_FLAG << 3)
56 /* Framebuffer caches. */
57 #define SI_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
58 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
59 #define SI_CONTEXT_FLUSH_AND_INV_DB (R600_CONTEXT_PRIVATE_FLAG << 6)
60 #define SI_CONTEXT_FLUSH_AND_INV_CB (R600_CONTEXT_PRIVATE_FLAG << 7)
61 /* Engine synchronization. */
62 #define SI_CONTEXT_VS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 8)
63 #define SI_CONTEXT_PS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 9)
64 #define SI_CONTEXT_CS_PARTIAL_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 10)
65 #define SI_CONTEXT_VGT_FLUSH (R600_CONTEXT_PRIVATE_FLAG << 11)
66 #define SI_CONTEXT_VGT_STREAMOUT_SYNC (R600_CONTEXT_PRIVATE_FLAG << 12)
68 #define SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER (SI_CONTEXT_FLUSH_AND_INV_CB | \
69 SI_CONTEXT_FLUSH_AND_INV_CB_META | \
70 SI_CONTEXT_FLUSH_AND_INV_DB | \
71 SI_CONTEXT_FLUSH_AND_INV_DB_META)
73 #define SI_ENCODE_TRACE_POINT(id) (0xcafe0000 | ((id) & 0xffff))
74 #define SI_IS_TRACE_POINT(x) (((x) & 0xcafe0000) == 0xcafe0000)
75 #define SI_GET_TRACE_POINT_ID(x) ((x) & 0xffff)
77 #define SI_MAX_BORDER_COLORS 4096
81 struct u_suballocator
;
84 struct r600_common_screen b
;
85 unsigned gs_table_depth
;
86 unsigned tess_offchip_block_dw_size
;
87 bool has_distributed_tess
;
89 /* Whether shaders are monolithic (1-part) or separate (3-part). */
90 bool use_monolithic_shaders
;
93 pipe_mutex shader_parts_mutex
;
94 struct si_shader_part
*vs_prologs
;
95 struct si_shader_part
*vs_epilogs
;
96 struct si_shader_part
*tcs_epilogs
;
97 struct si_shader_part
*ps_prologs
;
98 struct si_shader_part
*ps_epilogs
;
100 /* Shader cache in memory.
102 * Design & limitations:
103 * - The shader cache is per screen (= per process), never saved to
104 * disk, and skips redundant shader compilations from TGSI to bytecode.
105 * - It can only be used with one-variant-per-shader support, in which
106 * case only the main (typically middle) part of shaders is cached.
107 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
108 * variants of VS and TES are cached, so LS and ES aren't.
109 * - GS and CS aren't cached, but it's certainly possible to cache
112 pipe_mutex shader_cache_mutex
;
113 struct hash_table
*shader_cache
;
115 /* Shader compiler queue for multithreaded compilation. */
116 struct util_queue shader_compiler_queue
;
117 LLVMTargetMachineRef tm
[4]; /* used by the queue only */
120 struct si_blend_color
{
121 struct r600_atom atom
;
122 struct pipe_blend_color state
;
125 struct si_sampler_view
{
126 struct pipe_sampler_view base
;
127 struct list_head list
;
128 /* [0..7] = image descriptor
129 * [4..7] = buffer descriptor */
131 uint32_t fmask_state
[8];
132 const struct radeon_surf_level
*base_level_info
;
134 unsigned block_width
;
135 bool is_stencil_sampler
;
138 struct si_sampler_state
{
142 struct si_cs_shader_state
{
143 struct si_compute
*program
;
144 struct si_compute
*emitted_program
;
150 struct si_textures_info
{
151 struct si_sampler_views views
;
152 uint32_t depth_texture_mask
; /* which textures are depth */
153 uint32_t compressed_colortex_mask
;
156 struct si_images_info
{
157 struct pipe_image_view views
[SI_NUM_IMAGES
];
158 uint32_t compressed_colortex_mask
;
159 unsigned enabled_mask
;
162 struct si_framebuffer
{
163 struct r600_atom atom
;
164 struct pipe_framebuffer_state state
;
166 unsigned log_samples
;
167 unsigned cb0_is_integer
;
168 unsigned compressed_cb_mask
;
169 unsigned spi_shader_col_format
;
170 unsigned spi_shader_col_format_alpha
;
171 unsigned spi_shader_col_format_blend
;
172 unsigned spi_shader_col_format_blend_alpha
;
173 unsigned color_is_int8
; /* bitmask */
174 unsigned dirty_cbufs
;
179 struct si_clip_state
{
180 struct r600_atom atom
;
181 struct pipe_clip_state state
;
184 struct si_sample_locs
{
185 struct r600_atom atom
;
189 struct si_sample_mask
{
190 struct r600_atom atom
;
191 uint16_t sample_mask
;
194 /* A shader state consists of the shader selector, which is a constant state
195 * object shared by multiple contexts and shouldn't be modified, and
196 * the current shader variant selected for this context.
198 struct si_shader_ctx_state
{
199 struct si_shader_selector
*cso
;
200 struct si_shader
*current
;
204 struct r600_common_context b
;
205 struct blitter_context
*blitter
;
206 void *custom_dsa_flush
;
207 void *custom_blend_resolve
;
208 void *custom_blend_decompress
;
209 void *custom_blend_fastclear
;
210 void *custom_blend_dcc_decompress
;
211 struct si_screen
*screen
;
213 struct radeon_winsys_cs
*ce_ib
;
214 struct radeon_winsys_cs
*ce_preamble_ib
;
215 bool ce_need_synchronization
;
216 struct u_suballocator
*ce_suballocator
;
218 struct pipe_fence_handle
*last_gfx_fence
;
219 struct si_shader_ctx_state fixed_func_tcs_shader
;
220 LLVMTargetMachineRef tm
; /* only non-threaded compilation */
221 bool gfx_flush_in_progress
;
223 /* Atoms (direct states). */
224 union si_state_atoms atoms
;
225 unsigned dirty_atoms
; /* mask */
226 /* PM4 states (precomputed immutable states) */
227 union si_state queued
;
228 union si_state emitted
;
230 /* Atom declarations. */
231 struct r600_atom cache_flush
;
232 struct si_framebuffer framebuffer
;
233 struct si_sample_locs msaa_sample_locs
;
234 struct r600_atom db_render_state
;
235 struct r600_atom msaa_config
;
236 struct si_sample_mask sample_mask
;
237 struct r600_atom cb_render_state
;
238 struct si_blend_color blend_color
;
239 struct r600_atom clip_regs
;
240 struct si_clip_state clip_state
;
241 struct si_shader_data shader_userdata
;
242 struct si_stencil_ref stencil_ref
;
243 struct r600_atom spi_map
;
245 /* Precomputed states. */
246 struct si_pm4_state
*init_config
;
247 struct si_pm4_state
*init_config_gs_rings
;
248 bool init_config_has_vgt_flush
;
249 struct si_pm4_state
*vgt_shader_config
[4];
252 struct si_shader_ctx_state ps_shader
;
253 struct si_shader_ctx_state gs_shader
;
254 struct si_shader_ctx_state vs_shader
;
255 struct si_shader_ctx_state tcs_shader
;
256 struct si_shader_ctx_state tes_shader
;
257 struct si_cs_shader_state cs_shader_state
;
259 /* shader information */
260 struct si_vertex_element
*vertex_elements
;
261 unsigned sprite_coord_enable
;
264 /* shader descriptors */
265 struct si_descriptors vertex_buffers
;
266 struct si_descriptors descriptors
[SI_NUM_DESCS
];
267 unsigned descriptors_dirty
;
268 struct si_buffer_resources rw_buffers
;
269 struct si_buffer_resources const_buffers
[SI_NUM_SHADERS
];
270 struct si_buffer_resources shader_buffers
[SI_NUM_SHADERS
];
271 struct si_textures_info samplers
[SI_NUM_SHADERS
];
272 struct si_images_info images
[SI_NUM_SHADERS
];
274 /* other shader resources */
275 struct pipe_constant_buffer null_const_buf
; /* used for set_constant_buffer(NULL) on CIK */
276 struct pipe_resource
*esgs_ring
;
277 struct pipe_resource
*gsvs_ring
;
278 struct pipe_resource
*tf_ring
;
279 struct pipe_resource
*tess_offchip_ring
;
280 union pipe_color_union
*border_color_table
; /* in CPU memory, any endian */
281 struct r600_resource
*border_color_buffer
;
282 union pipe_color_union
*border_color_map
; /* in VRAM (slow access), little endian */
283 unsigned border_color_count
;
285 /* Vertex and index buffers. */
286 bool vertex_buffers_dirty
;
287 struct pipe_index_buffer index_buffer
;
288 struct pipe_vertex_buffer vertex_buffer
[SI_NUM_VERTEX_BUFFERS
];
290 /* MSAA config state. */
292 bool smoothing_enabled
;
294 /* DB render state. */
295 bool dbcb_depth_copy_enabled
;
296 bool dbcb_stencil_copy_enabled
;
297 unsigned dbcb_copy_sample
;
298 bool db_flush_depth_inplace
;
299 bool db_flush_stencil_inplace
;
301 bool db_depth_disable_expclear
;
302 bool db_stencil_clear
;
303 bool db_stencil_disable_expclear
;
304 unsigned ps_db_shader_control
;
305 bool occlusion_queries_disabled
;
307 /* Emitted draw state. */
308 int last_base_vertex
;
309 int last_start_instance
;
310 int last_sh_base_reg
;
311 int last_primitive_restart_en
;
312 int last_restart_index
;
313 int last_gs_out_prim
;
315 int last_multi_vgt_param
;
316 int last_ls_hs_config
;
318 unsigned last_sc_line_stipple
;
319 int last_vtx_reuse_depth
;
320 int current_rast_prim
; /* primitive type after TES, GS */
321 unsigned last_gsvs_itemsize
;
324 struct r600_resource
*scratch_buffer
;
325 bool emit_scratch_reloc
;
326 unsigned scratch_waves
;
327 unsigned spi_tmpring_size
;
329 struct r600_resource
*compute_scratch_buffer
;
331 /* Emitted derived tessellation state. */
332 struct si_shader
*last_ls
; /* local shader (VS) */
333 struct si_shader_selector
*last_tcs
;
334 int last_num_tcs_input_cp
;
335 int last_tes_sh_base
;
339 struct radeon_saved_cs last_gfx
;
340 struct r600_resource
*last_trace_buf
;
341 struct r600_resource
*trace_buf
;
343 uint64_t dmesg_timestamp
;
344 unsigned apitrace_call_number
;
347 bool need_check_render_feedback
;
351 void cik_init_sdma_functions(struct si_context
*sctx
);
354 void si_init_blit_functions(struct si_context
*sctx
);
355 void si_decompress_graphics_textures(struct si_context
*sctx
);
356 void si_decompress_compute_textures(struct si_context
*sctx
);
357 void si_resource_copy_region(struct pipe_context
*ctx
,
358 struct pipe_resource
*dst
,
360 unsigned dstx
, unsigned dsty
, unsigned dstz
,
361 struct pipe_resource
*src
,
363 const struct pipe_box
*src_box
);
366 void si_copy_buffer(struct si_context
*sctx
,
367 struct pipe_resource
*dst
, struct pipe_resource
*src
,
368 uint64_t dst_offset
, uint64_t src_offset
, unsigned size
);
369 void si_init_cp_dma_functions(struct si_context
*sctx
);
372 void si_init_debug_functions(struct si_context
*sctx
);
373 void si_check_vm_faults(struct r600_common_context
*ctx
,
374 struct radeon_saved_cs
*saved
, enum ring_type ring
);
375 bool si_replace_shader(unsigned num
, struct radeon_shader_binary
*binary
);
378 void si_init_dma_functions(struct si_context
*sctx
);
380 /* si_hw_context.c */
381 void si_context_gfx_flush(void *context
, unsigned flags
,
382 struct pipe_fence_handle
**fence
);
383 void si_begin_new_cs(struct si_context
*ctx
);
384 void si_need_cs_space(struct si_context
*ctx
);
387 void si_init_compute_functions(struct si_context
*sctx
);
389 /* si_perfcounters.c */
390 void si_init_perfcounters(struct si_screen
*screen
);
393 struct pipe_video_codec
*si_uvd_create_decoder(struct pipe_context
*context
,
394 const struct pipe_video_codec
*templ
);
396 struct pipe_video_buffer
*si_video_buffer_create(struct pipe_context
*pipe
,
397 const struct pipe_video_buffer
*tmpl
);
403 static inline struct r600_resource
*
404 si_resource_create_custom(struct pipe_screen
*screen
,
405 unsigned usage
, unsigned size
)
408 return r600_resource(pipe_buffer_create(screen
,
409 PIPE_BIND_CUSTOM
, usage
, size
));
413 si_invalidate_draw_sh_constants(struct si_context
*sctx
)
415 sctx
->last_base_vertex
= SI_BASE_VERTEX_UNKNOWN
;
416 sctx
->last_start_instance
= -1; /* reset to an unknown value */
417 sctx
->last_sh_base_reg
= -1; /* reset to an unknown value */
421 si_set_atom_dirty(struct si_context
*sctx
,
422 struct r600_atom
*atom
, bool dirty
)
424 unsigned bit
= 1 << (atom
->id
- 1);
427 sctx
->dirty_atoms
|= bit
;
429 sctx
->dirty_atoms
&= ~bit
;
433 si_is_atom_dirty(struct si_context
*sctx
,
434 struct r600_atom
*atom
)
436 unsigned bit
= 1 << (atom
->id
- 1);
438 return sctx
->dirty_atoms
& bit
;
442 si_mark_atom_dirty(struct si_context
*sctx
,
443 struct r600_atom
*atom
)
445 si_set_atom_dirty(sctx
, atom
, true);