src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef SI_PIPE_H
  27 #define SI_PIPE_H
  28
  29 #include "si_state.h"
  30
  31 #include <llvm-c/TargetMachine.h>
  32
  33 #ifdef PIPE_ARCH_BIG_ENDIAN
  34 #define SI_BIG_ENDIAN 1
  35 #else
  36 #define SI_BIG_ENDIAN 0
  37 #endif
  38
  39 /* The base vertex and primitive restart can be any number, but we must pick
  40  * one which will mean "unknown" for the purpose of state tracking and
  41  * the number shouldn't be a commonly-used one. */
  42 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  43 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  44 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  45 #define SI_GS_PER_ES 128
  46
  47 /* Instruction cache. */
  48 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  49 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  50 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  51 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  52 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  53 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  54 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  55 /* Framebuffer caches. */
  56 #define SI_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 4)
  57 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
  58 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 6)
  59 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 7)
  60 /* Engine synchronization. */
  61 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 8)
  62 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  63 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  64 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 11)
  65 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 12)
  66
  67 #define SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER (SI_CONTEXT_FLUSH_AND_INV_CB | \
  68                                               SI_CONTEXT_FLUSH_AND_INV_CB_META | \
  69                                               SI_CONTEXT_FLUSH_AND_INV_DB | \
  70                                               SI_CONTEXT_FLUSH_AND_INV_DB_META)
  71
  72 #define SI_ENCODE_TRACE_POINT(id)       (0xcafe0000 | ((id) & 0xffff))
  73 #define SI_IS_TRACE_POINT(x)            (((x) & 0xcafe0000) == 0xcafe0000)
  74 #define SI_GET_TRACE_POINT_ID(x)        ((x) & 0xffff)
  75
  76 #define SI_MAX_BORDER_COLORS    4096
  77
  78 struct si_compute;
  79 struct hash_table;
  80 struct u_suballocator;
  81
  82 struct si_screen {
  83         struct r600_common_screen       b;
  84         unsigned                        gs_table_depth;
  85         unsigned                        tess_offchip_block_dw_size;
  86         bool                            has_distributed_tess;
  87
  88         /* Whether shaders are monolithic (1-part) or separate (3-part). */
  89         bool                            use_monolithic_shaders;
  90
  91         pipe_mutex                      shader_parts_mutex;
  92         struct si_shader_part           *vs_prologs;
  93         struct si_shader_part           *vs_epilogs;
  94         struct si_shader_part           *tcs_epilogs;
  95         struct si_shader_part           *ps_prologs;
  96         struct si_shader_part           *ps_epilogs;
  97
  98         /* Shader cache in memory.
  99          *
 100          * Design & limitations:
 101          * - The shader cache is per screen (= per process), never saved to
 102          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 103          * - It can only be used with one-variant-per-shader support, in which
 104          *   case only the main (typically middle) part of shaders is cached.
 105          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 106          *   variants of VS and TES are cached, so LS and ES aren't.
 107          * - GS and CS aren't cached, but it's certainly possible to cache
 108          *   those as well.
 109          */
 110         pipe_mutex                      shader_cache_mutex;
 111         struct hash_table               *shader_cache;
 112 };
 113
 114 struct si_blend_color {
 115         struct r600_atom                atom;
 116         struct pipe_blend_color         state;
 117 };
 118
 119 struct si_sampler_view {
 120         struct pipe_sampler_view        base;
 121         struct list_head                list;
 122         /* [0..7] = image descriptor
 123          * [4..7] = buffer descriptor */
 124         uint32_t                        state[8];
 125         uint32_t                        fmask_state[8];
 126         const struct radeon_surf_level  *base_level_info;
 127         unsigned                        base_level;
 128         unsigned                        block_width;
 129         bool is_stencil_sampler;
 130 };
 131
 132 struct si_sampler_state {
 133         uint32_t                        val[4];
 134 };
 135
 136 struct si_cs_shader_state {
 137         struct si_compute               *program;
 138         struct si_compute               *emitted_program;
 139         unsigned                        offset;
 140         bool                            initialized;
 141         bool                            uses_scratch;
 142 };
 143
 144 struct si_textures_info {
 145         struct si_sampler_views         views;
 146         uint32_t                        depth_texture_mask; /* which textures are depth */
 147         uint32_t                        compressed_colortex_mask;
 148 };
 149
 150 struct si_images_info {
 151         struct pipe_image_view          views[SI_NUM_IMAGES];
 152         uint32_t                        compressed_colortex_mask;
 153         unsigned                        enabled_mask;
 154 };
 155
 156 struct si_framebuffer {
 157         struct r600_atom                atom;
 158         struct pipe_framebuffer_state   state;
 159         unsigned                        nr_samples;
 160         unsigned                        log_samples;
 161         unsigned                        cb0_is_integer;
 162         unsigned                        compressed_cb_mask;
 163         unsigned                        spi_shader_col_format;
 164         unsigned                        spi_shader_col_format_alpha;
 165         unsigned                        spi_shader_col_format_blend;
 166         unsigned                        spi_shader_col_format_blend_alpha;
 167         unsigned                        color_is_int8; /* bitmask */
 168         unsigned                        dirty_cbufs;
 169         bool                            dirty_zsbuf;
 170         bool                            any_dst_linear;
 171 };
 172
 173 struct si_clip_state {
 174         struct r600_atom                atom;
 175         struct pipe_clip_state          state;
 176 };
 177
 178 struct si_sample_mask {
 179         struct r600_atom        atom;
 180         uint16_t                sample_mask;
 181 };
 182
 183 /* A shader state consists of the shader selector, which is a constant state
 184  * object shared by multiple contexts and shouldn't be modified, and
 185  * the current shader variant selected for this context.
 186  */
 187 struct si_shader_ctx_state {
 188         struct si_shader_selector       *cso;
 189         struct si_shader                *current;
 190 };
 191
 192 struct si_context {
 193         struct r600_common_context      b;
 194         struct blitter_context          *blitter;
 195         void                            *custom_dsa_flush;
 196         void                            *custom_blend_resolve;
 197         void                            *custom_blend_decompress;
 198         void                            *custom_blend_fastclear;
 199         void                            *custom_blend_dcc_decompress;
 200         struct si_screen                *screen;
 201
 202         struct radeon_winsys_cs         *ce_ib;
 203         struct radeon_winsys_cs         *ce_preamble_ib;
 204         bool                            ce_need_synchronization;
 205         struct u_suballocator           *ce_suballocator;
 206
 207         struct pipe_fence_handle        *last_gfx_fence;
 208         struct si_shader_ctx_state      fixed_func_tcs_shader;
 209         LLVMTargetMachineRef            tm;
 210         bool                            gfx_flush_in_progress;
 211
 212         /* Atoms (direct states). */
 213         union si_state_atoms            atoms;
 214         unsigned                        dirty_atoms; /* mask */
 215         /* PM4 states (precomputed immutable states) */
 216         union si_state                  queued;
 217         union si_state                  emitted;
 218
 219         /* Atom declarations. */
 220         struct r600_atom                cache_flush;
 221         struct si_framebuffer           framebuffer;
 222         struct r600_atom                msaa_sample_locs;
 223         struct r600_atom                db_render_state;
 224         struct r600_atom                msaa_config;
 225         struct si_sample_mask           sample_mask;
 226         struct r600_atom                cb_render_state;
 227         struct si_blend_color           blend_color;
 228         struct r600_atom                clip_regs;
 229         struct si_clip_state            clip_state;
 230         struct si_shader_data           shader_userdata;
 231         struct si_stencil_ref           stencil_ref;
 232         struct r600_atom                spi_map;
 233
 234         /* Precomputed states. */
 235         struct si_pm4_state             *init_config;
 236         struct si_pm4_state             *init_config_gs_rings;
 237         bool                            init_config_has_vgt_flush;
 238         struct si_pm4_state             *vgt_shader_config[4];
 239
 240         /* shaders */
 241         struct si_shader_ctx_state      ps_shader;
 242         struct si_shader_ctx_state      gs_shader;
 243         struct si_shader_ctx_state      vs_shader;
 244         struct si_shader_ctx_state      tcs_shader;
 245         struct si_shader_ctx_state      tes_shader;
 246         struct si_cs_shader_state       cs_shader_state;
 247
 248         /* shader information */
 249         struct si_vertex_element        *vertex_elements;
 250         unsigned                        sprite_coord_enable;
 251         bool                            flatshade;
 252
 253         /* shader descriptors */
 254         struct si_descriptors           vertex_buffers;
 255         struct si_descriptors           descriptors[SI_NUM_DESCS];
 256         unsigned                        descriptors_dirty;
 257         struct si_buffer_resources      rw_buffers;
 258         struct si_buffer_resources      const_buffers[SI_NUM_SHADERS];
 259         struct si_buffer_resources      shader_buffers[SI_NUM_SHADERS];
 260         struct si_textures_info         samplers[SI_NUM_SHADERS];
 261         struct si_images_info           images[SI_NUM_SHADERS];
 262
 263         /* other shader resources */
 264         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 265         struct pipe_resource            *esgs_ring;
 266         struct pipe_resource            *gsvs_ring;
 267         struct pipe_resource            *tf_ring;
 268         struct pipe_resource            *tess_offchip_ring;
 269         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 270         struct r600_resource            *border_color_buffer;
 271         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 272         unsigned                        border_color_count;
 273
 274         /* Vertex and index buffers. */
 275         bool                            vertex_buffers_dirty;
 276         struct pipe_index_buffer        index_buffer;
 277         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 278
 279         /* MSAA config state. */
 280         int                             ps_iter_samples;
 281         bool                            smoothing_enabled;
 282
 283         /* DB render state. */
 284         bool                    dbcb_depth_copy_enabled;
 285         bool                    dbcb_stencil_copy_enabled;
 286         unsigned                dbcb_copy_sample;
 287         bool                    db_flush_depth_inplace;
 288         bool                    db_flush_stencil_inplace;
 289         bool                    db_depth_clear;
 290         bool                    db_depth_disable_expclear;
 291         bool                    db_stencil_clear;
 292         bool                    db_stencil_disable_expclear;
 293         unsigned                ps_db_shader_control;
 294         bool                    occlusion_queries_disabled;
 295
 296         /* Emitted draw state. */
 297         int                     last_base_vertex;
 298         int                     last_start_instance;
 299         int                     last_sh_base_reg;
 300         int                     last_primitive_restart_en;
 301         int                     last_restart_index;
 302         int                     last_gs_out_prim;
 303         int                     last_prim;
 304         int                     last_multi_vgt_param;
 305         int                     last_ls_hs_config;
 306         int                     last_rast_prim;
 307         unsigned                last_sc_line_stipple;
 308         int                     last_vtx_reuse_depth;
 309         int                     current_rast_prim; /* primitive type after TES, GS */
 310         unsigned                last_gsvs_itemsize;
 311
 312         /* Scratch buffer */
 313         struct r600_resource    *scratch_buffer;
 314         bool                    emit_scratch_reloc;
 315         unsigned                scratch_waves;
 316         unsigned                spi_tmpring_size;
 317
 318         struct r600_resource    *compute_scratch_buffer;
 319
 320         /* Emitted derived tessellation state. */
 321         struct si_shader        *last_ls; /* local shader (VS) */
 322         struct si_shader_selector *last_tcs;
 323         int                     last_num_tcs_input_cp;
 324         int                     last_tes_sh_base;
 325
 326         /* Debug state. */
 327         bool                    is_debug;
 328         struct radeon_saved_cs  last_gfx;
 329         struct r600_resource    *last_trace_buf;
 330         struct r600_resource    *trace_buf;
 331         unsigned                trace_id;
 332         uint64_t                dmesg_timestamp;
 333
 334         /* Other state */
 335         bool need_check_render_feedback;
 336 };
 337
 338 /* cik_sdma.c */
 339 void cik_init_sdma_functions(struct si_context *sctx);
 340
 341 /* si_blit.c */
 342 void si_init_blit_functions(struct si_context *sctx);
 343 void si_decompress_graphics_textures(struct si_context *sctx);
 344 void si_decompress_compute_textures(struct si_context *sctx);
 345 void si_resource_copy_region(struct pipe_context *ctx,
 346                              struct pipe_resource *dst,
 347                              unsigned dst_level,
 348                              unsigned dstx, unsigned dsty, unsigned dstz,
 349                              struct pipe_resource *src,
 350                              unsigned src_level,
 351                              const struct pipe_box *src_box);
 352
 353 /* si_cp_dma.c */
 354 void si_copy_buffer(struct si_context *sctx,
 355                     struct pipe_resource *dst, struct pipe_resource *src,
 356                     uint64_t dst_offset, uint64_t src_offset, unsigned size);
 357 void si_init_cp_dma_functions(struct si_context *sctx);
 358
 359 /* si_debug.c */
 360 void si_init_debug_functions(struct si_context *sctx);
 361 void si_check_vm_faults(struct r600_common_context *ctx,
 362                         struct radeon_saved_cs *saved, enum ring_type ring);
 363 bool si_replace_shader(unsigned num, struct radeon_shader_binary *binary);
 364
 365 /* si_dma.c */
 366 void si_init_dma_functions(struct si_context *sctx);
 367
 368 /* si_hw_context.c */
 369 void si_context_gfx_flush(void *context, unsigned flags,
 370                           struct pipe_fence_handle **fence);
 371 void si_begin_new_cs(struct si_context *ctx);
 372 void si_need_cs_space(struct si_context *ctx);
 373
 374 /* si_compute.c */
 375 void si_init_compute_functions(struct si_context *sctx);
 376
 377 /* si_perfcounters.c */
 378 void si_init_perfcounters(struct si_screen *screen);
 379
 380 /* si_uvd.c */
 381 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 382                                                const struct pipe_video_codec *templ);
 383
 384 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 385                                                  const struct pipe_video_buffer *tmpl);
 386
 387 /*
 388  * common helpers
 389  */
 390
 391 static inline struct r600_resource *
 392 si_resource_create_custom(struct pipe_screen *screen,
 393                           unsigned usage, unsigned size)
 394 {
 395         assert(size);
 396         return r600_resource(pipe_buffer_create(screen,
 397                 PIPE_BIND_CUSTOM, usage, size));
 398 }
 399
 400 static inline void
 401 si_invalidate_draw_sh_constants(struct si_context *sctx)
 402 {
 403         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 404         sctx->last_start_instance = -1; /* reset to an unknown value */
 405         sctx->last_sh_base_reg = -1; /* reset to an unknown value */
 406 }
 407
 408 static inline void
 409 si_set_atom_dirty(struct si_context *sctx,
 410                   struct r600_atom *atom, bool dirty)
 411 {
 412         unsigned bit = 1 << (atom->id - 1);
 413
 414         if (dirty)
 415                 sctx->dirty_atoms |= bit;
 416         else
 417                 sctx->dirty_atoms &= ~bit;
 418 }
 419
 420 static inline bool
 421 si_is_atom_dirty(struct si_context *sctx,
 422                   struct r600_atom *atom)
 423 {
 424         unsigned bit = 1 << (atom->id - 1);
 425
 426         return sctx->dirty_atoms & bit;
 427 }
 428
 429 static inline void
 430 si_mark_atom_dirty(struct si_context *sctx,
 431                    struct r600_atom *atom)
 432 {
 433         si_set_atom_dirty(sctx, atom, true);
 434 }
 435
 436 #endif