src/gallium/drivers/radeonsi/si_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef SI_PIPE_H
  27 #define SI_PIPE_H
  28
  29 #include "si_shader.h"
  30
  31 #ifdef PIPE_ARCH_BIG_ENDIAN
  32 #define SI_BIG_ENDIAN 1
  33 #else
  34 #define SI_BIG_ENDIAN 0
  35 #endif
  36
  37 /* The base vertex and primitive restart can be any number, but we must pick
  38  * one which will mean "unknown" for the purpose of state tracking and
  39  * the number shouldn't be a commonly-used one. */
  40 #define SI_BASE_VERTEX_UNKNOWN INT_MIN
  41 #define SI_RESTART_INDEX_UNKNOWN INT_MIN
  42 #define SI_NUM_SMOOTH_AA_SAMPLES 8
  43 #define SI_GS_PER_ES 128
  44
  45 /* Instruction cache. */
  46 #define SI_CONTEXT_INV_ICACHE           (R600_CONTEXT_PRIVATE_FLAG << 0)
  47 /* SMEM L1, other names: KCACHE, constant cache, DCACHE, data cache */
  48 #define SI_CONTEXT_INV_SMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 1)
  49 /* VMEM L1 can optionally be bypassed (GLC=1). Other names: TC L1 */
  50 #define SI_CONTEXT_INV_VMEM_L1          (R600_CONTEXT_PRIVATE_FLAG << 2)
  51 /* Used by everything except CB/DB, can be bypassed (SLC=1). Other names: TC L2 */
  52 #define SI_CONTEXT_INV_GLOBAL_L2        (R600_CONTEXT_PRIVATE_FLAG << 3)
  53 /* Write dirty L2 lines back to memory (shader and CP DMA stores), but don't
  54  * invalidate L2. SI-CIK can't do it, so they will do complete invalidation. */
  55 #define SI_CONTEXT_WRITEBACK_GLOBAL_L2  (R600_CONTEXT_PRIVATE_FLAG << 4)
  56 /* Framebuffer caches. */
  57 #define SI_CONTEXT_FLUSH_AND_INV_CB_META (R600_CONTEXT_PRIVATE_FLAG << 5)
  58 #define SI_CONTEXT_FLUSH_AND_INV_DB_META (R600_CONTEXT_PRIVATE_FLAG << 6)
  59 #define SI_CONTEXT_FLUSH_AND_INV_DB     (R600_CONTEXT_PRIVATE_FLAG << 7)
  60 #define SI_CONTEXT_FLUSH_AND_INV_CB     (R600_CONTEXT_PRIVATE_FLAG << 8)
  61 /* Engine synchronization. */
  62 #define SI_CONTEXT_VS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 9)
  63 #define SI_CONTEXT_PS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 10)
  64 #define SI_CONTEXT_CS_PARTIAL_FLUSH     (R600_CONTEXT_PRIVATE_FLAG << 11)
  65 #define SI_CONTEXT_VGT_FLUSH            (R600_CONTEXT_PRIVATE_FLAG << 12)
  66 #define SI_CONTEXT_VGT_STREAMOUT_SYNC   (R600_CONTEXT_PRIVATE_FLAG << 13)
  67
  68 #define SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER (SI_CONTEXT_FLUSH_AND_INV_CB | \
  69                                               SI_CONTEXT_FLUSH_AND_INV_CB_META | \
  70                                               SI_CONTEXT_FLUSH_AND_INV_DB | \
  71                                               SI_CONTEXT_FLUSH_AND_INV_DB_META)
  72
  73 #define SI_ENCODE_TRACE_POINT(id)       (0xcafe0000 | ((id) & 0xffff))
  74 #define SI_IS_TRACE_POINT(x)            (((x) & 0xcafe0000) == 0xcafe0000)
  75 #define SI_GET_TRACE_POINT_ID(x)        ((x) & 0xffff)
  76
  77 #define SI_MAX_BORDER_COLORS    4096
  78
  79 struct si_compute;
  80 struct hash_table;
  81 struct u_suballocator;
  82
  83 struct si_screen {
  84         struct r600_common_screen       b;
  85         unsigned                        gs_table_depth;
  86         unsigned                        tess_offchip_block_dw_size;
  87         bool                            has_distributed_tess;
  88         bool                            has_draw_indirect_multi;
  89         bool                            has_ds_bpermute;
  90
  91         /* Whether shaders are monolithic (1-part) or separate (3-part). */
  92         bool                            use_monolithic_shaders;
  93         bool                            record_llvm_ir;
  94
  95         pipe_mutex                      shader_parts_mutex;
  96         struct si_shader_part           *vs_prologs;
  97         struct si_shader_part           *vs_epilogs;
  98         struct si_shader_part           *tcs_epilogs;
  99         struct si_shader_part           *gs_prologs;
 100         struct si_shader_part           *ps_prologs;
 101         struct si_shader_part           *ps_epilogs;
 102
 103         /* Shader cache in memory.
 104          *
 105          * Design & limitations:
 106          * - The shader cache is per screen (= per process), never saved to
 107          *   disk, and skips redundant shader compilations from TGSI to bytecode.
 108          * - It can only be used with one-variant-per-shader support, in which
 109          *   case only the main (typically middle) part of shaders is cached.
 110          * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 111          *   variants of VS and TES are cached, so LS and ES aren't.
 112          * - GS and CS aren't cached, but it's certainly possible to cache
 113          *   those as well.
 114          */
 115         pipe_mutex                      shader_cache_mutex;
 116         struct hash_table               *shader_cache;
 117
 118         /* Shader compiler queue for multithreaded compilation. */
 119         struct util_queue               shader_compiler_queue;
 120         LLVMTargetMachineRef            tm[4]; /* used by the queue only */
 121 };
 122
 123 struct si_blend_color {
 124         struct r600_atom                atom;
 125         struct pipe_blend_color         state;
 126 };
 127
 128 struct si_sampler_view {
 129         struct pipe_sampler_view        base;
 130         /* [0..7] = image descriptor
 131          * [4..7] = buffer descriptor */
 132         uint32_t                        state[8];
 133         uint32_t                        fmask_state[8];
 134         const struct radeon_surf_level  *base_level_info;
 135         unsigned                        base_level;
 136         unsigned                        block_width;
 137         bool is_stencil_sampler;
 138 };
 139
 140 struct si_sampler_state {
 141         uint32_t                        val[4];
 142 };
 143
 144 struct si_cs_shader_state {
 145         struct si_compute               *program;
 146         struct si_compute               *emitted_program;
 147         unsigned                        offset;
 148         bool                            initialized;
 149         bool                            uses_scratch;
 150 };
 151
 152 struct si_textures_info {
 153         struct si_sampler_views         views;
 154         uint32_t                        depth_texture_mask; /* which textures are depth */
 155         uint32_t                        compressed_colortex_mask;
 156 };
 157
 158 struct si_images_info {
 159         struct pipe_image_view          views[SI_NUM_IMAGES];
 160         uint32_t                        compressed_colortex_mask;
 161         unsigned                        enabled_mask;
 162 };
 163
 164 struct si_framebuffer {
 165         struct r600_atom                atom;
 166         struct pipe_framebuffer_state   state;
 167         unsigned                        nr_samples;
 168         unsigned                        log_samples;
 169         unsigned                        compressed_cb_mask;
 170         unsigned                        spi_shader_col_format;
 171         unsigned                        spi_shader_col_format_alpha;
 172         unsigned                        spi_shader_col_format_blend;
 173         unsigned                        spi_shader_col_format_blend_alpha;
 174         unsigned                        color_is_int8; /* bitmask */
 175         unsigned                        dirty_cbufs;
 176         bool                            dirty_zsbuf;
 177         bool                            any_dst_linear;
 178 };
 179
 180 struct si_clip_state {
 181         struct r600_atom                atom;
 182         struct pipe_clip_state          state;
 183 };
 184
 185 struct si_sample_locs {
 186         struct r600_atom        atom;
 187         unsigned                nr_samples;
 188 };
 189
 190 struct si_sample_mask {
 191         struct r600_atom        atom;
 192         uint16_t                sample_mask;
 193 };
 194
 195 /* A shader state consists of the shader selector, which is a constant state
 196  * object shared by multiple contexts and shouldn't be modified, and
 197  * the current shader variant selected for this context.
 198  */
 199 struct si_shader_ctx_state {
 200         struct si_shader_selector       *cso;
 201         struct si_shader                *current;
 202 };
 203
 204 struct si_context {
 205         struct r600_common_context      b;
 206         struct blitter_context          *blitter;
 207         void                            *custom_dsa_flush;
 208         void                            *custom_blend_resolve;
 209         void                            *custom_blend_decompress;
 210         void                            *custom_blend_fastclear;
 211         void                            *custom_blend_dcc_decompress;
 212         struct si_screen                *screen;
 213
 214         struct radeon_winsys_cs         *ce_ib;
 215         struct radeon_winsys_cs         *ce_preamble_ib;
 216         bool                            ce_need_synchronization;
 217         struct u_suballocator           *ce_suballocator;
 218
 219         struct si_shader_ctx_state      fixed_func_tcs_shader;
 220         LLVMTargetMachineRef            tm; /* only non-threaded compilation */
 221         bool                            gfx_flush_in_progress;
 222         bool                            compute_is_busy;
 223
 224         /* Atoms (direct states). */
 225         union si_state_atoms            atoms;
 226         unsigned                        dirty_atoms; /* mask */
 227         /* PM4 states (precomputed immutable states) */
 228         union si_state                  queued;
 229         union si_state                  emitted;
 230
 231         /* Atom declarations. */
 232         struct si_framebuffer           framebuffer;
 233         struct si_sample_locs           msaa_sample_locs;
 234         struct r600_atom                db_render_state;
 235         struct r600_atom                msaa_config;
 236         struct si_sample_mask           sample_mask;
 237         struct r600_atom                cb_render_state;
 238         struct si_blend_color           blend_color;
 239         struct r600_atom                clip_regs;
 240         struct si_clip_state            clip_state;
 241         struct si_shader_data           shader_userdata;
 242         struct si_stencil_ref           stencil_ref;
 243         struct r600_atom                spi_map;
 244
 245         /* Precomputed states. */
 246         struct si_pm4_state             *init_config;
 247         struct si_pm4_state             *init_config_gs_rings;
 248         bool                            init_config_has_vgt_flush;
 249         struct si_pm4_state             *vgt_shader_config[4];
 250
 251         /* shaders */
 252         struct si_shader_ctx_state      ps_shader;
 253         struct si_shader_ctx_state      gs_shader;
 254         struct si_shader_ctx_state      vs_shader;
 255         struct si_shader_ctx_state      tcs_shader;
 256         struct si_shader_ctx_state      tes_shader;
 257         struct si_cs_shader_state       cs_shader_state;
 258
 259         /* shader information */
 260         struct si_vertex_element        *vertex_elements;
 261         unsigned                        sprite_coord_enable;
 262         bool                            flatshade;
 263         bool                            do_update_shaders;
 264
 265         /* shader descriptors */
 266         struct si_descriptors           vertex_buffers;
 267         struct si_descriptors           descriptors[SI_NUM_DESCS];
 268         unsigned                        descriptors_dirty;
 269         struct si_buffer_resources      rw_buffers;
 270         struct si_buffer_resources      const_buffers[SI_NUM_SHADERS];
 271         struct si_buffer_resources      shader_buffers[SI_NUM_SHADERS];
 272         struct si_textures_info         samplers[SI_NUM_SHADERS];
 273         struct si_images_info           images[SI_NUM_SHADERS];
 274
 275         /* other shader resources */
 276         struct pipe_constant_buffer     null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
 277         struct pipe_resource            *esgs_ring;
 278         struct pipe_resource            *gsvs_ring;
 279         struct pipe_resource            *tf_ring;
 280         struct pipe_resource            *tess_offchip_ring;
 281         union pipe_color_union          *border_color_table; /* in CPU memory, any endian */
 282         struct r600_resource            *border_color_buffer;
 283         union pipe_color_union          *border_color_map; /* in VRAM (slow access), little endian */
 284         unsigned                        border_color_count;
 285
 286         /* Vertex and index buffers. */
 287         bool                            vertex_buffers_dirty;
 288         struct pipe_index_buffer        index_buffer;
 289         struct pipe_vertex_buffer       vertex_buffer[SI_NUM_VERTEX_BUFFERS];
 290
 291         /* MSAA config state. */
 292         int                             ps_iter_samples;
 293         bool                            smoothing_enabled;
 294
 295         /* DB render state. */
 296         bool                    dbcb_depth_copy_enabled;
 297         bool                    dbcb_stencil_copy_enabled;
 298         unsigned                dbcb_copy_sample;
 299         bool                    db_flush_depth_inplace;
 300         bool                    db_flush_stencil_inplace;
 301         bool                    db_depth_clear;
 302         bool                    db_depth_disable_expclear;
 303         bool                    db_stencil_clear;
 304         bool                    db_stencil_disable_expclear;
 305         unsigned                ps_db_shader_control;
 306         bool                    occlusion_queries_disabled;
 307
 308         /* Emitted draw state. */
 309         int                     last_index_size;
 310         int                     last_base_vertex;
 311         int                     last_start_instance;
 312         int                     last_drawid;
 313         int                     last_sh_base_reg;
 314         int                     last_primitive_restart_en;
 315         int                     last_restart_index;
 316         int                     last_gs_out_prim;
 317         int                     last_prim;
 318         int                     last_multi_vgt_param;
 319         int                     last_rast_prim;
 320         unsigned                last_sc_line_stipple;
 321         int                     last_vtx_reuse_depth;
 322         int                     current_rast_prim; /* primitive type after TES, GS */
 323         bool                    gs_tri_strip_adj_fix;
 324         unsigned                last_gsvs_itemsize;
 325
 326         /* Scratch buffer */
 327         struct r600_resource    *scratch_buffer;
 328         bool                    emit_scratch_reloc;
 329         unsigned                scratch_waves;
 330         unsigned                spi_tmpring_size;
 331
 332         struct r600_resource    *compute_scratch_buffer;
 333
 334         /* Emitted derived tessellation state. */
 335         struct si_shader        *last_ls; /* local shader (VS) */
 336         struct si_shader_selector *last_tcs;
 337         int                     last_num_tcs_input_cp;
 338         int                     last_tes_sh_base;
 339         unsigned                last_num_patches;
 340
 341         /* Debug state. */
 342         bool                    is_debug;
 343         struct radeon_saved_cs  last_gfx;
 344         struct r600_resource    *last_trace_buf;
 345         struct r600_resource    *trace_buf;
 346         unsigned                trace_id;
 347         uint64_t                dmesg_timestamp;
 348         unsigned                apitrace_call_number;
 349
 350         /* Other state */
 351         bool need_check_render_feedback;
 352 };
 353
 354 /* cik_sdma.c */
 355 void cik_init_sdma_functions(struct si_context *sctx);
 356
 357 /* si_blit.c */
 358 void si_init_blit_functions(struct si_context *sctx);
 359 void si_decompress_graphics_textures(struct si_context *sctx);
 360 void si_decompress_compute_textures(struct si_context *sctx);
 361 void si_resource_copy_region(struct pipe_context *ctx,
 362                              struct pipe_resource *dst,
 363                              unsigned dst_level,
 364                              unsigned dstx, unsigned dsty, unsigned dstz,
 365                              struct pipe_resource *src,
 366                              unsigned src_level,
 367                              const struct pipe_box *src_box);
 368
 369 /* si_cp_dma.c */
 370 void si_copy_buffer(struct si_context *sctx,
 371                     struct pipe_resource *dst, struct pipe_resource *src,
 372                     uint64_t dst_offset, uint64_t src_offset, unsigned size);
 373 void si_init_cp_dma_functions(struct si_context *sctx);
 374
 375 /* si_debug.c */
 376 void si_init_debug_functions(struct si_context *sctx);
 377 void si_check_vm_faults(struct r600_common_context *ctx,
 378                         struct radeon_saved_cs *saved, enum ring_type ring);
 379 bool si_replace_shader(unsigned num, struct radeon_shader_binary *binary);
 380
 381 /* si_dma.c */
 382 void si_init_dma_functions(struct si_context *sctx);
 383
 384 /* si_hw_context.c */
 385 void si_context_gfx_flush(void *context, unsigned flags,
 386                           struct pipe_fence_handle **fence);
 387 void si_begin_new_cs(struct si_context *ctx);
 388 void si_need_cs_space(struct si_context *ctx);
 389
 390 /* si_compute.c */
 391 void si_init_compute_functions(struct si_context *sctx);
 392
 393 /* si_perfcounters.c */
 394 void si_init_perfcounters(struct si_screen *screen);
 395
 396 /* si_uvd.c */
 397 struct pipe_video_codec *si_uvd_create_decoder(struct pipe_context *context,
 398                                                const struct pipe_video_codec *templ);
 399
 400 struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
 401                                                  const struct pipe_video_buffer *tmpl);
 402
 403 /*
 404  * common helpers
 405  */
 406
 407 static inline void
 408 si_invalidate_draw_sh_constants(struct si_context *sctx)
 409 {
 410         sctx->last_base_vertex = SI_BASE_VERTEX_UNKNOWN;
 411 }
 412
 413 static inline void
 414 si_set_atom_dirty(struct si_context *sctx,
 415                   struct r600_atom *atom, bool dirty)
 416 {
 417         unsigned bit = 1 << (atom->id - 1);
 418
 419         if (dirty)
 420                 sctx->dirty_atoms |= bit;
 421         else
 422                 sctx->dirty_atoms &= ~bit;
 423 }
 424
 425 static inline bool
 426 si_is_atom_dirty(struct si_context *sctx,
 427                   struct r600_atom *atom)
 428 {
 429         unsigned bit = 1 << (atom->id - 1);
 430
 431         return sctx->dirty_atoms & bit;
 432 }
 433
 434 static inline void
 435 si_mark_atom_dirty(struct si_context *sctx,
 436                    struct r600_atom *atom)
 437 {
 438         si_set_atom_dirty(sctx, atom, true);
 439 }
 440
 441 static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
 442 {
 443         if (sctx->gs_shader.cso)
 444                 return &sctx->gs_shader.cso->info;
 445         else if (sctx->tes_shader.cso)
 446                 return &sctx->tes_shader.cso->info;
 447         else if (sctx->vs_shader.cso)
 448                 return &sctx->vs_shader.cso->info;
 449         else
 450                 return NULL;
 451 }
 452
 453 static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
 454 {
 455         if (sctx->gs_shader.current)
 456                 return sctx->gs_shader.cso->gs_copy_shader;
 457         else if (sctx->tes_shader.current)
 458                 return sctx->tes_shader.current;
 459         else
 460                 return sctx->vs_shader.current;
 461 }
 462
 463 static inline bool si_vs_exports_prim_id(struct si_shader *shader)
 464 {
 465         if (shader->selector->type == PIPE_SHADER_VERTEX)
 466                 return shader->key.vs.epilog.export_prim_id;
 467         else if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
 468                 return shader->key.tes.epilog.export_prim_id;
 469         else
 470                 return false;
 471 }
 472
 473 #endif