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[mesa.git] / src / gallium / drivers / radeonsi / si_query.c
1 /*
2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2014 Marek Olšák <marek.olsak@amd.com>
4 * Copyright 2018 Advanced Micro Devices, Inc.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * on the rights to use, copy, modify, merge, publish, distribute, sub
11 * license, and/or sell copies of the Software, and to permit persons to whom
12 * the Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
24 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 */
26
27 #include "si_pipe.h"
28 #include "si_query.h"
29 #include "util/u_memory.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/os_time.h"
32 #include "util/u_suballoc.h"
33 #include "amd/common/sid.h"
34
35 #define SI_MAX_STREAMS 4
36
37 static const struct si_query_ops query_hw_ops;
38
39 struct si_hw_query_params {
40 unsigned start_offset;
41 unsigned end_offset;
42 unsigned fence_offset;
43 unsigned pair_stride;
44 unsigned pair_count;
45 };
46
47 /* Queries without buffer handling or suspend/resume. */
48 struct si_query_sw {
49 struct si_query b;
50
51 uint64_t begin_result;
52 uint64_t end_result;
53
54 uint64_t begin_time;
55 uint64_t end_time;
56
57 /* Fence for GPU_FINISHED. */
58 struct pipe_fence_handle *fence;
59 };
60
61 static void si_query_sw_destroy(struct si_screen *sscreen,
62 struct si_query *squery)
63 {
64 struct si_query_sw *query = (struct si_query_sw *)squery;
65
66 sscreen->b.fence_reference(&sscreen->b, &query->fence, NULL);
67 FREE(query);
68 }
69
70 static enum radeon_value_id winsys_id_from_type(unsigned type)
71 {
72 switch (type) {
73 case SI_QUERY_REQUESTED_VRAM: return RADEON_REQUESTED_VRAM_MEMORY;
74 case SI_QUERY_REQUESTED_GTT: return RADEON_REQUESTED_GTT_MEMORY;
75 case SI_QUERY_MAPPED_VRAM: return RADEON_MAPPED_VRAM;
76 case SI_QUERY_MAPPED_GTT: return RADEON_MAPPED_GTT;
77 case SI_QUERY_BUFFER_WAIT_TIME: return RADEON_BUFFER_WAIT_TIME_NS;
78 case SI_QUERY_NUM_MAPPED_BUFFERS: return RADEON_NUM_MAPPED_BUFFERS;
79 case SI_QUERY_NUM_GFX_IBS: return RADEON_NUM_GFX_IBS;
80 case SI_QUERY_NUM_SDMA_IBS: return RADEON_NUM_SDMA_IBS;
81 case SI_QUERY_GFX_BO_LIST_SIZE: return RADEON_GFX_BO_LIST_COUNTER;
82 case SI_QUERY_GFX_IB_SIZE: return RADEON_GFX_IB_SIZE_COUNTER;
83 case SI_QUERY_NUM_BYTES_MOVED: return RADEON_NUM_BYTES_MOVED;
84 case SI_QUERY_NUM_EVICTIONS: return RADEON_NUM_EVICTIONS;
85 case SI_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: return RADEON_NUM_VRAM_CPU_PAGE_FAULTS;
86 case SI_QUERY_VRAM_USAGE: return RADEON_VRAM_USAGE;
87 case SI_QUERY_VRAM_VIS_USAGE: return RADEON_VRAM_VIS_USAGE;
88 case SI_QUERY_GTT_USAGE: return RADEON_GTT_USAGE;
89 case SI_QUERY_GPU_TEMPERATURE: return RADEON_GPU_TEMPERATURE;
90 case SI_QUERY_CURRENT_GPU_SCLK: return RADEON_CURRENT_SCLK;
91 case SI_QUERY_CURRENT_GPU_MCLK: return RADEON_CURRENT_MCLK;
92 case SI_QUERY_CS_THREAD_BUSY: return RADEON_CS_THREAD_TIME;
93 default: unreachable("query type does not correspond to winsys id");
94 }
95 }
96
97 static int64_t si_finish_dma_get_cpu_time(struct si_context *sctx)
98 {
99 struct pipe_fence_handle *fence = NULL;
100
101 si_flush_dma_cs(sctx, 0, &fence);
102 if (fence) {
103 sctx->ws->fence_wait(sctx->ws, fence, PIPE_TIMEOUT_INFINITE);
104 sctx->ws->fence_reference(&fence, NULL);
105 }
106
107 return os_time_get_nano();
108 }
109
110 static bool si_query_sw_begin(struct si_context *sctx,
111 struct si_query *squery)
112 {
113 struct si_query_sw *query = (struct si_query_sw *)squery;
114 enum radeon_value_id ws_id;
115
116 switch(query->b.type) {
117 case PIPE_QUERY_TIMESTAMP_DISJOINT:
118 case PIPE_QUERY_GPU_FINISHED:
119 break;
120 case SI_QUERY_TIME_ELAPSED_SDMA_SI:
121 query->begin_result = si_finish_dma_get_cpu_time(sctx);
122 break;
123 case SI_QUERY_DRAW_CALLS:
124 query->begin_result = sctx->num_draw_calls;
125 break;
126 case SI_QUERY_DECOMPRESS_CALLS:
127 query->begin_result = sctx->num_decompress_calls;
128 break;
129 case SI_QUERY_MRT_DRAW_CALLS:
130 query->begin_result = sctx->num_mrt_draw_calls;
131 break;
132 case SI_QUERY_PRIM_RESTART_CALLS:
133 query->begin_result = sctx->num_prim_restart_calls;
134 break;
135 case SI_QUERY_SPILL_DRAW_CALLS:
136 query->begin_result = sctx->num_spill_draw_calls;
137 break;
138 case SI_QUERY_COMPUTE_CALLS:
139 query->begin_result = sctx->num_compute_calls;
140 break;
141 case SI_QUERY_SPILL_COMPUTE_CALLS:
142 query->begin_result = sctx->num_spill_compute_calls;
143 break;
144 case SI_QUERY_DMA_CALLS:
145 query->begin_result = sctx->num_dma_calls;
146 break;
147 case SI_QUERY_CP_DMA_CALLS:
148 query->begin_result = sctx->num_cp_dma_calls;
149 break;
150 case SI_QUERY_NUM_VS_FLUSHES:
151 query->begin_result = sctx->num_vs_flushes;
152 break;
153 case SI_QUERY_NUM_PS_FLUSHES:
154 query->begin_result = sctx->num_ps_flushes;
155 break;
156 case SI_QUERY_NUM_CS_FLUSHES:
157 query->begin_result = sctx->num_cs_flushes;
158 break;
159 case SI_QUERY_NUM_CB_CACHE_FLUSHES:
160 query->begin_result = sctx->num_cb_cache_flushes;
161 break;
162 case SI_QUERY_NUM_DB_CACHE_FLUSHES:
163 query->begin_result = sctx->num_db_cache_flushes;
164 break;
165 case SI_QUERY_NUM_L2_INVALIDATES:
166 query->begin_result = sctx->num_L2_invalidates;
167 break;
168 case SI_QUERY_NUM_L2_WRITEBACKS:
169 query->begin_result = sctx->num_L2_writebacks;
170 break;
171 case SI_QUERY_NUM_RESIDENT_HANDLES:
172 query->begin_result = sctx->num_resident_handles;
173 break;
174 case SI_QUERY_TC_OFFLOADED_SLOTS:
175 query->begin_result = sctx->tc ? sctx->tc->num_offloaded_slots : 0;
176 break;
177 case SI_QUERY_TC_DIRECT_SLOTS:
178 query->begin_result = sctx->tc ? sctx->tc->num_direct_slots : 0;
179 break;
180 case SI_QUERY_TC_NUM_SYNCS:
181 query->begin_result = sctx->tc ? sctx->tc->num_syncs : 0;
182 break;
183 case SI_QUERY_REQUESTED_VRAM:
184 case SI_QUERY_REQUESTED_GTT:
185 case SI_QUERY_MAPPED_VRAM:
186 case SI_QUERY_MAPPED_GTT:
187 case SI_QUERY_VRAM_USAGE:
188 case SI_QUERY_VRAM_VIS_USAGE:
189 case SI_QUERY_GTT_USAGE:
190 case SI_QUERY_GPU_TEMPERATURE:
191 case SI_QUERY_CURRENT_GPU_SCLK:
192 case SI_QUERY_CURRENT_GPU_MCLK:
193 case SI_QUERY_BACK_BUFFER_PS_DRAW_RATIO:
194 case SI_QUERY_NUM_MAPPED_BUFFERS:
195 query->begin_result = 0;
196 break;
197 case SI_QUERY_BUFFER_WAIT_TIME:
198 case SI_QUERY_GFX_IB_SIZE:
199 case SI_QUERY_NUM_GFX_IBS:
200 case SI_QUERY_NUM_SDMA_IBS:
201 case SI_QUERY_NUM_BYTES_MOVED:
202 case SI_QUERY_NUM_EVICTIONS:
203 case SI_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: {
204 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
205 query->begin_result = sctx->ws->query_value(sctx->ws, ws_id);
206 break;
207 }
208 case SI_QUERY_GFX_BO_LIST_SIZE:
209 ws_id = winsys_id_from_type(query->b.type);
210 query->begin_result = sctx->ws->query_value(sctx->ws, ws_id);
211 query->begin_time = sctx->ws->query_value(sctx->ws,
212 RADEON_NUM_GFX_IBS);
213 break;
214 case SI_QUERY_CS_THREAD_BUSY:
215 ws_id = winsys_id_from_type(query->b.type);
216 query->begin_result = sctx->ws->query_value(sctx->ws, ws_id);
217 query->begin_time = os_time_get_nano();
218 break;
219 case SI_QUERY_GALLIUM_THREAD_BUSY:
220 query->begin_result =
221 sctx->tc ? util_queue_get_thread_time_nano(&sctx->tc->queue, 0) : 0;
222 query->begin_time = os_time_get_nano();
223 break;
224 case SI_QUERY_GPU_LOAD:
225 case SI_QUERY_GPU_SHADERS_BUSY:
226 case SI_QUERY_GPU_TA_BUSY:
227 case SI_QUERY_GPU_GDS_BUSY:
228 case SI_QUERY_GPU_VGT_BUSY:
229 case SI_QUERY_GPU_IA_BUSY:
230 case SI_QUERY_GPU_SX_BUSY:
231 case SI_QUERY_GPU_WD_BUSY:
232 case SI_QUERY_GPU_BCI_BUSY:
233 case SI_QUERY_GPU_SC_BUSY:
234 case SI_QUERY_GPU_PA_BUSY:
235 case SI_QUERY_GPU_DB_BUSY:
236 case SI_QUERY_GPU_CP_BUSY:
237 case SI_QUERY_GPU_CB_BUSY:
238 case SI_QUERY_GPU_SDMA_BUSY:
239 case SI_QUERY_GPU_PFP_BUSY:
240 case SI_QUERY_GPU_MEQ_BUSY:
241 case SI_QUERY_GPU_ME_BUSY:
242 case SI_QUERY_GPU_SURF_SYNC_BUSY:
243 case SI_QUERY_GPU_CP_DMA_BUSY:
244 case SI_QUERY_GPU_SCRATCH_RAM_BUSY:
245 query->begin_result = si_begin_counter(sctx->screen,
246 query->b.type);
247 break;
248 case SI_QUERY_NUM_COMPILATIONS:
249 query->begin_result = p_atomic_read(&sctx->screen->num_compilations);
250 break;
251 case SI_QUERY_NUM_SHADERS_CREATED:
252 query->begin_result = p_atomic_read(&sctx->screen->num_shaders_created);
253 break;
254 case SI_QUERY_NUM_SHADER_CACHE_HITS:
255 query->begin_result =
256 p_atomic_read(&sctx->screen->num_shader_cache_hits);
257 break;
258 case SI_QUERY_PD_NUM_PRIMS_ACCEPTED:
259 query->begin_result = sctx->compute_num_verts_accepted;
260 break;
261 case SI_QUERY_PD_NUM_PRIMS_REJECTED:
262 query->begin_result = sctx->compute_num_verts_rejected;
263 break;
264 case SI_QUERY_PD_NUM_PRIMS_INELIGIBLE:
265 query->begin_result = sctx->compute_num_verts_ineligible;
266 break;
267 case SI_QUERY_GPIN_ASIC_ID:
268 case SI_QUERY_GPIN_NUM_SIMD:
269 case SI_QUERY_GPIN_NUM_RB:
270 case SI_QUERY_GPIN_NUM_SPI:
271 case SI_QUERY_GPIN_NUM_SE:
272 break;
273 default:
274 unreachable("si_query_sw_begin: bad query type");
275 }
276
277 return true;
278 }
279
280 static bool si_query_sw_end(struct si_context *sctx,
281 struct si_query *squery)
282 {
283 struct si_query_sw *query = (struct si_query_sw *)squery;
284 enum radeon_value_id ws_id;
285
286 switch(query->b.type) {
287 case PIPE_QUERY_TIMESTAMP_DISJOINT:
288 break;
289 case PIPE_QUERY_GPU_FINISHED:
290 sctx->b.flush(&sctx->b, &query->fence, PIPE_FLUSH_DEFERRED);
291 break;
292 case SI_QUERY_TIME_ELAPSED_SDMA_SI:
293 query->end_result = si_finish_dma_get_cpu_time(sctx);
294 break;
295 case SI_QUERY_DRAW_CALLS:
296 query->end_result = sctx->num_draw_calls;
297 break;
298 case SI_QUERY_DECOMPRESS_CALLS:
299 query->end_result = sctx->num_decompress_calls;
300 break;
301 case SI_QUERY_MRT_DRAW_CALLS:
302 query->end_result = sctx->num_mrt_draw_calls;
303 break;
304 case SI_QUERY_PRIM_RESTART_CALLS:
305 query->end_result = sctx->num_prim_restart_calls;
306 break;
307 case SI_QUERY_SPILL_DRAW_CALLS:
308 query->end_result = sctx->num_spill_draw_calls;
309 break;
310 case SI_QUERY_COMPUTE_CALLS:
311 query->end_result = sctx->num_compute_calls;
312 break;
313 case SI_QUERY_SPILL_COMPUTE_CALLS:
314 query->end_result = sctx->num_spill_compute_calls;
315 break;
316 case SI_QUERY_DMA_CALLS:
317 query->end_result = sctx->num_dma_calls;
318 break;
319 case SI_QUERY_CP_DMA_CALLS:
320 query->end_result = sctx->num_cp_dma_calls;
321 break;
322 case SI_QUERY_NUM_VS_FLUSHES:
323 query->end_result = sctx->num_vs_flushes;
324 break;
325 case SI_QUERY_NUM_PS_FLUSHES:
326 query->end_result = sctx->num_ps_flushes;
327 break;
328 case SI_QUERY_NUM_CS_FLUSHES:
329 query->end_result = sctx->num_cs_flushes;
330 break;
331 case SI_QUERY_NUM_CB_CACHE_FLUSHES:
332 query->end_result = sctx->num_cb_cache_flushes;
333 break;
334 case SI_QUERY_NUM_DB_CACHE_FLUSHES:
335 query->end_result = sctx->num_db_cache_flushes;
336 break;
337 case SI_QUERY_NUM_L2_INVALIDATES:
338 query->end_result = sctx->num_L2_invalidates;
339 break;
340 case SI_QUERY_NUM_L2_WRITEBACKS:
341 query->end_result = sctx->num_L2_writebacks;
342 break;
343 case SI_QUERY_NUM_RESIDENT_HANDLES:
344 query->end_result = sctx->num_resident_handles;
345 break;
346 case SI_QUERY_TC_OFFLOADED_SLOTS:
347 query->end_result = sctx->tc ? sctx->tc->num_offloaded_slots : 0;
348 break;
349 case SI_QUERY_TC_DIRECT_SLOTS:
350 query->end_result = sctx->tc ? sctx->tc->num_direct_slots : 0;
351 break;
352 case SI_QUERY_TC_NUM_SYNCS:
353 query->end_result = sctx->tc ? sctx->tc->num_syncs : 0;
354 break;
355 case SI_QUERY_REQUESTED_VRAM:
356 case SI_QUERY_REQUESTED_GTT:
357 case SI_QUERY_MAPPED_VRAM:
358 case SI_QUERY_MAPPED_GTT:
359 case SI_QUERY_VRAM_USAGE:
360 case SI_QUERY_VRAM_VIS_USAGE:
361 case SI_QUERY_GTT_USAGE:
362 case SI_QUERY_GPU_TEMPERATURE:
363 case SI_QUERY_CURRENT_GPU_SCLK:
364 case SI_QUERY_CURRENT_GPU_MCLK:
365 case SI_QUERY_BUFFER_WAIT_TIME:
366 case SI_QUERY_GFX_IB_SIZE:
367 case SI_QUERY_NUM_MAPPED_BUFFERS:
368 case SI_QUERY_NUM_GFX_IBS:
369 case SI_QUERY_NUM_SDMA_IBS:
370 case SI_QUERY_NUM_BYTES_MOVED:
371 case SI_QUERY_NUM_EVICTIONS:
372 case SI_QUERY_NUM_VRAM_CPU_PAGE_FAULTS: {
373 enum radeon_value_id ws_id = winsys_id_from_type(query->b.type);
374 query->end_result = sctx->ws->query_value(sctx->ws, ws_id);
375 break;
376 }
377 case SI_QUERY_GFX_BO_LIST_SIZE:
378 ws_id = winsys_id_from_type(query->b.type);
379 query->end_result = sctx->ws->query_value(sctx->ws, ws_id);
380 query->end_time = sctx->ws->query_value(sctx->ws,
381 RADEON_NUM_GFX_IBS);
382 break;
383 case SI_QUERY_CS_THREAD_BUSY:
384 ws_id = winsys_id_from_type(query->b.type);
385 query->end_result = sctx->ws->query_value(sctx->ws, ws_id);
386 query->end_time = os_time_get_nano();
387 break;
388 case SI_QUERY_GALLIUM_THREAD_BUSY:
389 query->end_result =
390 sctx->tc ? util_queue_get_thread_time_nano(&sctx->tc->queue, 0) : 0;
391 query->end_time = os_time_get_nano();
392 break;
393 case SI_QUERY_GPU_LOAD:
394 case SI_QUERY_GPU_SHADERS_BUSY:
395 case SI_QUERY_GPU_TA_BUSY:
396 case SI_QUERY_GPU_GDS_BUSY:
397 case SI_QUERY_GPU_VGT_BUSY:
398 case SI_QUERY_GPU_IA_BUSY:
399 case SI_QUERY_GPU_SX_BUSY:
400 case SI_QUERY_GPU_WD_BUSY:
401 case SI_QUERY_GPU_BCI_BUSY:
402 case SI_QUERY_GPU_SC_BUSY:
403 case SI_QUERY_GPU_PA_BUSY:
404 case SI_QUERY_GPU_DB_BUSY:
405 case SI_QUERY_GPU_CP_BUSY:
406 case SI_QUERY_GPU_CB_BUSY:
407 case SI_QUERY_GPU_SDMA_BUSY:
408 case SI_QUERY_GPU_PFP_BUSY:
409 case SI_QUERY_GPU_MEQ_BUSY:
410 case SI_QUERY_GPU_ME_BUSY:
411 case SI_QUERY_GPU_SURF_SYNC_BUSY:
412 case SI_QUERY_GPU_CP_DMA_BUSY:
413 case SI_QUERY_GPU_SCRATCH_RAM_BUSY:
414 query->end_result = si_end_counter(sctx->screen,
415 query->b.type,
416 query->begin_result);
417 query->begin_result = 0;
418 break;
419 case SI_QUERY_NUM_COMPILATIONS:
420 query->end_result = p_atomic_read(&sctx->screen->num_compilations);
421 break;
422 case SI_QUERY_NUM_SHADERS_CREATED:
423 query->end_result = p_atomic_read(&sctx->screen->num_shaders_created);
424 break;
425 case SI_QUERY_BACK_BUFFER_PS_DRAW_RATIO:
426 query->end_result = sctx->last_tex_ps_draw_ratio;
427 break;
428 case SI_QUERY_NUM_SHADER_CACHE_HITS:
429 query->end_result =
430 p_atomic_read(&sctx->screen->num_shader_cache_hits);
431 break;
432 case SI_QUERY_PD_NUM_PRIMS_ACCEPTED:
433 query->end_result = sctx->compute_num_verts_accepted;
434 break;
435 case SI_QUERY_PD_NUM_PRIMS_REJECTED:
436 query->end_result = sctx->compute_num_verts_rejected;
437 break;
438 case SI_QUERY_PD_NUM_PRIMS_INELIGIBLE:
439 query->end_result = sctx->compute_num_verts_ineligible;
440 break;
441 case SI_QUERY_GPIN_ASIC_ID:
442 case SI_QUERY_GPIN_NUM_SIMD:
443 case SI_QUERY_GPIN_NUM_RB:
444 case SI_QUERY_GPIN_NUM_SPI:
445 case SI_QUERY_GPIN_NUM_SE:
446 break;
447 default:
448 unreachable("si_query_sw_end: bad query type");
449 }
450
451 return true;
452 }
453
454 static bool si_query_sw_get_result(struct si_context *sctx,
455 struct si_query *squery,
456 bool wait,
457 union pipe_query_result *result)
458 {
459 struct si_query_sw *query = (struct si_query_sw *)squery;
460
461 switch (query->b.type) {
462 case PIPE_QUERY_TIMESTAMP_DISJOINT:
463 /* Convert from cycles per millisecond to cycles per second (Hz). */
464 result->timestamp_disjoint.frequency =
465 (uint64_t)sctx->screen->info.clock_crystal_freq * 1000;
466 result->timestamp_disjoint.disjoint = false;
467 return true;
468 case PIPE_QUERY_GPU_FINISHED: {
469 struct pipe_screen *screen = sctx->b.screen;
470 struct pipe_context *ctx = squery->b.flushed ? NULL : &sctx->b;
471
472 result->b = screen->fence_finish(screen, ctx, query->fence,
473 wait ? PIPE_TIMEOUT_INFINITE : 0);
474 return result->b;
475 }
476
477 case SI_QUERY_GFX_BO_LIST_SIZE:
478 result->u64 = (query->end_result - query->begin_result) /
479 (query->end_time - query->begin_time);
480 return true;
481 case SI_QUERY_CS_THREAD_BUSY:
482 case SI_QUERY_GALLIUM_THREAD_BUSY:
483 result->u64 = (query->end_result - query->begin_result) * 100 /
484 (query->end_time - query->begin_time);
485 return true;
486 case SI_QUERY_PD_NUM_PRIMS_ACCEPTED:
487 case SI_QUERY_PD_NUM_PRIMS_REJECTED:
488 case SI_QUERY_PD_NUM_PRIMS_INELIGIBLE:
489 result->u64 = ((unsigned)query->end_result -
490 (unsigned)query->begin_result) / 3;
491 return true;
492 case SI_QUERY_GPIN_ASIC_ID:
493 result->u32 = 0;
494 return true;
495 case SI_QUERY_GPIN_NUM_SIMD:
496 result->u32 = sctx->screen->info.num_good_compute_units;
497 return true;
498 case SI_QUERY_GPIN_NUM_RB:
499 result->u32 = sctx->screen->info.num_render_backends;
500 return true;
501 case SI_QUERY_GPIN_NUM_SPI:
502 result->u32 = 1; /* all supported chips have one SPI per SE */
503 return true;
504 case SI_QUERY_GPIN_NUM_SE:
505 result->u32 = sctx->screen->info.max_se;
506 return true;
507 }
508
509 result->u64 = query->end_result - query->begin_result;
510
511 switch (query->b.type) {
512 case SI_QUERY_BUFFER_WAIT_TIME:
513 case SI_QUERY_GPU_TEMPERATURE:
514 result->u64 /= 1000;
515 break;
516 case SI_QUERY_CURRENT_GPU_SCLK:
517 case SI_QUERY_CURRENT_GPU_MCLK:
518 result->u64 *= 1000000;
519 break;
520 }
521
522 return true;
523 }
524
525
526 static const struct si_query_ops sw_query_ops = {
527 .destroy = si_query_sw_destroy,
528 .begin = si_query_sw_begin,
529 .end = si_query_sw_end,
530 .get_result = si_query_sw_get_result,
531 .get_result_resource = NULL
532 };
533
534 static struct pipe_query *si_query_sw_create(unsigned query_type)
535 {
536 struct si_query_sw *query;
537
538 query = CALLOC_STRUCT(si_query_sw);
539 if (!query)
540 return NULL;
541
542 query->b.type = query_type;
543 query->b.ops = &sw_query_ops;
544
545 return (struct pipe_query *)query;
546 }
547
548 void si_query_buffer_destroy(struct si_screen *sscreen, struct si_query_buffer *buffer)
549 {
550 struct si_query_buffer *prev = buffer->previous;
551
552 /* Release all query buffers. */
553 while (prev) {
554 struct si_query_buffer *qbuf = prev;
555 prev = prev->previous;
556 si_resource_reference(&qbuf->buf, NULL);
557 FREE(qbuf);
558 }
559
560 si_resource_reference(&buffer->buf, NULL);
561 }
562
563 void si_query_buffer_reset(struct si_context *sctx, struct si_query_buffer *buffer)
564 {
565 /* Discard all query buffers except for the oldest. */
566 while (buffer->previous) {
567 struct si_query_buffer *qbuf = buffer->previous;
568 buffer->previous = qbuf->previous;
569
570 si_resource_reference(&buffer->buf, NULL);
571 buffer->buf = qbuf->buf; /* move ownership */
572 FREE(qbuf);
573 }
574 buffer->results_end = 0;
575
576 if (!buffer->buf)
577 return;
578
579 /* Discard even the oldest buffer if it can't be mapped without a stall. */
580 if (si_rings_is_buffer_referenced(sctx, buffer->buf->buf, RADEON_USAGE_READWRITE) ||
581 !sctx->ws->buffer_wait(buffer->buf->buf, 0, RADEON_USAGE_READWRITE)) {
582 si_resource_reference(&buffer->buf, NULL);
583 } else {
584 buffer->unprepared = true;
585 }
586 }
587
588 bool si_query_buffer_alloc(struct si_context *sctx, struct si_query_buffer *buffer,
589 bool (*prepare_buffer)(struct si_context *, struct si_query_buffer*),
590 unsigned size)
591 {
592 bool unprepared = buffer->unprepared;
593 buffer->unprepared = false;
594
595 if (!buffer->buf || buffer->results_end + size > buffer->buf->b.b.width0) {
596 if (buffer->buf) {
597 struct si_query_buffer *qbuf = MALLOC_STRUCT(si_query_buffer);
598 memcpy(qbuf, buffer, sizeof(*qbuf));
599 buffer->previous = qbuf;
600 }
601 buffer->results_end = 0;
602
603 /* Queries are normally read by the CPU after
604 * being written by the gpu, hence staging is probably a good
605 * usage pattern.
606 */
607 struct si_screen *screen = sctx->screen;
608 unsigned buf_size = MAX2(size, screen->info.min_alloc_size);
609 buffer->buf = si_resource(
610 pipe_buffer_create(&screen->b, 0, PIPE_USAGE_STAGING, buf_size));
611 if (unlikely(!buffer->buf))
612 return false;
613 unprepared = true;
614 }
615
616 if (unprepared && prepare_buffer) {
617 if (unlikely(!prepare_buffer(sctx, buffer))) {
618 si_resource_reference(&buffer->buf, NULL);
619 return false;
620 }
621 }
622
623 return true;
624 }
625
626
627 void si_query_hw_destroy(struct si_screen *sscreen,
628 struct si_query *squery)
629 {
630 struct si_query_hw *query = (struct si_query_hw *)squery;
631
632 si_query_buffer_destroy(sscreen, &query->buffer);
633 si_resource_reference(&query->workaround_buf, NULL);
634 FREE(squery);
635 }
636
637 static bool si_query_hw_prepare_buffer(struct si_context *sctx,
638 struct si_query_buffer *qbuf)
639 {
640 static const struct si_query_hw si_query_hw_s;
641 struct si_query_hw *query = container_of(qbuf, &si_query_hw_s, buffer);
642 struct si_screen *screen = sctx->screen;
643
644 /* The caller ensures that the buffer is currently unused by the GPU. */
645 uint32_t *results = screen->ws->buffer_map(qbuf->buf->buf, NULL,
646 PIPE_TRANSFER_WRITE |
647 PIPE_TRANSFER_UNSYNCHRONIZED);
648 if (!results)
649 return false;
650
651 memset(results, 0, qbuf->buf->b.b.width0);
652
653 if (query->b.type == PIPE_QUERY_OCCLUSION_COUNTER ||
654 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE ||
655 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
656 unsigned max_rbs = screen->info.num_render_backends;
657 unsigned enabled_rb_mask = screen->info.enabled_rb_mask;
658 unsigned num_results;
659 unsigned i, j;
660
661 /* Set top bits for unused backends. */
662 num_results = qbuf->buf->b.b.width0 / query->result_size;
663 for (j = 0; j < num_results; j++) {
664 for (i = 0; i < max_rbs; i++) {
665 if (!(enabled_rb_mask & (1<<i))) {
666 results[(i * 4)+1] = 0x80000000;
667 results[(i * 4)+3] = 0x80000000;
668 }
669 }
670 results += 4 * max_rbs;
671 }
672 }
673
674 return true;
675 }
676
677 static void si_query_hw_get_result_resource(struct si_context *sctx,
678 struct si_query *squery,
679 bool wait,
680 enum pipe_query_value_type result_type,
681 int index,
682 struct pipe_resource *resource,
683 unsigned offset);
684
685 static void si_query_hw_do_emit_start(struct si_context *sctx,
686 struct si_query_hw *query,
687 struct si_resource *buffer,
688 uint64_t va);
689 static void si_query_hw_do_emit_stop(struct si_context *sctx,
690 struct si_query_hw *query,
691 struct si_resource *buffer,
692 uint64_t va);
693 static void si_query_hw_add_result(struct si_screen *sscreen,
694 struct si_query_hw *, void *buffer,
695 union pipe_query_result *result);
696 static void si_query_hw_clear_result(struct si_query_hw *,
697 union pipe_query_result *);
698
699 static struct si_query_hw_ops query_hw_default_hw_ops = {
700 .prepare_buffer = si_query_hw_prepare_buffer,
701 .emit_start = si_query_hw_do_emit_start,
702 .emit_stop = si_query_hw_do_emit_stop,
703 .clear_result = si_query_hw_clear_result,
704 .add_result = si_query_hw_add_result,
705 };
706
707 static struct pipe_query *si_query_hw_create(struct si_screen *sscreen,
708 unsigned query_type,
709 unsigned index)
710 {
711 struct si_query_hw *query = CALLOC_STRUCT(si_query_hw);
712 if (!query)
713 return NULL;
714
715 query->b.type = query_type;
716 query->b.ops = &query_hw_ops;
717 query->ops = &query_hw_default_hw_ops;
718
719 switch (query_type) {
720 case PIPE_QUERY_OCCLUSION_COUNTER:
721 case PIPE_QUERY_OCCLUSION_PREDICATE:
722 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
723 query->result_size = 16 * sscreen->info.num_render_backends;
724 query->result_size += 16; /* for the fence + alignment */
725 query->b.num_cs_dw_suspend = 6 + si_cp_write_fence_dwords(sscreen);
726 break;
727 case SI_QUERY_TIME_ELAPSED_SDMA:
728 /* GET_GLOBAL_TIMESTAMP only works if the offset is a multiple of 32. */
729 query->result_size = 64;
730 break;
731 case PIPE_QUERY_TIME_ELAPSED:
732 query->result_size = 24;
733 query->b.num_cs_dw_suspend = 8 + si_cp_write_fence_dwords(sscreen);
734 break;
735 case PIPE_QUERY_TIMESTAMP:
736 query->result_size = 16;
737 query->b.num_cs_dw_suspend = 8 + si_cp_write_fence_dwords(sscreen);
738 query->flags = SI_QUERY_HW_FLAG_NO_START;
739 break;
740 case PIPE_QUERY_PRIMITIVES_EMITTED:
741 case PIPE_QUERY_PRIMITIVES_GENERATED:
742 case PIPE_QUERY_SO_STATISTICS:
743 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
744 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
745 query->result_size = 32;
746 query->b.num_cs_dw_suspend = 6;
747 query->stream = index;
748 break;
749 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
750 /* NumPrimitivesWritten, PrimitiveStorageNeeded. */
751 query->result_size = 32 * SI_MAX_STREAMS;
752 query->b.num_cs_dw_suspend = 6 * SI_MAX_STREAMS;
753 break;
754 case PIPE_QUERY_PIPELINE_STATISTICS:
755 /* 11 values on GCN. */
756 query->result_size = 11 * 16;
757 query->result_size += 8; /* for the fence + alignment */
758 query->b.num_cs_dw_suspend = 6 + si_cp_write_fence_dwords(sscreen);
759 break;
760 default:
761 assert(0);
762 FREE(query);
763 return NULL;
764 }
765
766 return (struct pipe_query *)query;
767 }
768
769 static void si_update_occlusion_query_state(struct si_context *sctx,
770 unsigned type, int diff)
771 {
772 if (type == PIPE_QUERY_OCCLUSION_COUNTER ||
773 type == PIPE_QUERY_OCCLUSION_PREDICATE ||
774 type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
775 bool old_enable = sctx->num_occlusion_queries != 0;
776 bool old_perfect_enable =
777 sctx->num_perfect_occlusion_queries != 0;
778 bool enable, perfect_enable;
779
780 sctx->num_occlusion_queries += diff;
781 assert(sctx->num_occlusion_queries >= 0);
782
783 if (type != PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE) {
784 sctx->num_perfect_occlusion_queries += diff;
785 assert(sctx->num_perfect_occlusion_queries >= 0);
786 }
787
788 enable = sctx->num_occlusion_queries != 0;
789 perfect_enable = sctx->num_perfect_occlusion_queries != 0;
790
791 if (enable != old_enable || perfect_enable != old_perfect_enable) {
792 si_set_occlusion_query_state(sctx, old_perfect_enable);
793 }
794 }
795 }
796
797 static unsigned event_type_for_stream(unsigned stream)
798 {
799 switch (stream) {
800 default:
801 case 0: return V_028A90_SAMPLE_STREAMOUTSTATS;
802 case 1: return V_028A90_SAMPLE_STREAMOUTSTATS1;
803 case 2: return V_028A90_SAMPLE_STREAMOUTSTATS2;
804 case 3: return V_028A90_SAMPLE_STREAMOUTSTATS3;
805 }
806 }
807
808 static void emit_sample_streamout(struct radeon_cmdbuf *cs, uint64_t va,
809 unsigned stream)
810 {
811 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
812 radeon_emit(cs, EVENT_TYPE(event_type_for_stream(stream)) | EVENT_INDEX(3));
813 radeon_emit(cs, va);
814 radeon_emit(cs, va >> 32);
815 }
816
817 static void si_query_hw_do_emit_start(struct si_context *sctx,
818 struct si_query_hw *query,
819 struct si_resource *buffer,
820 uint64_t va)
821 {
822 struct radeon_cmdbuf *cs = sctx->gfx_cs;
823
824 switch (query->b.type) {
825 case SI_QUERY_TIME_ELAPSED_SDMA:
826 si_dma_emit_timestamp(sctx, buffer, va - buffer->gpu_address);
827 return;
828 case PIPE_QUERY_OCCLUSION_COUNTER:
829 case PIPE_QUERY_OCCLUSION_PREDICATE:
830 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
831 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
832 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
833 radeon_emit(cs, va);
834 radeon_emit(cs, va >> 32);
835 break;
836 case PIPE_QUERY_PRIMITIVES_EMITTED:
837 case PIPE_QUERY_PRIMITIVES_GENERATED:
838 case PIPE_QUERY_SO_STATISTICS:
839 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
840 emit_sample_streamout(cs, va, query->stream);
841 break;
842 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
843 for (unsigned stream = 0; stream < SI_MAX_STREAMS; ++stream)
844 emit_sample_streamout(cs, va + 32 * stream, stream);
845 break;
846 case PIPE_QUERY_TIME_ELAPSED:
847 si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0,
848 EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
849 EOP_DATA_SEL_TIMESTAMP, NULL, va,
850 0, query->b.type);
851 break;
852 case PIPE_QUERY_PIPELINE_STATISTICS:
853 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
854 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
855 radeon_emit(cs, va);
856 radeon_emit(cs, va >> 32);
857 break;
858 default:
859 assert(0);
860 }
861 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, query->buffer.buf, RADEON_USAGE_WRITE,
862 RADEON_PRIO_QUERY);
863 }
864
865 static void si_query_hw_emit_start(struct si_context *sctx,
866 struct si_query_hw *query)
867 {
868 uint64_t va;
869
870 if (!si_query_buffer_alloc(sctx, &query->buffer, query->ops->prepare_buffer,
871 query->result_size))
872 return;
873
874 si_update_occlusion_query_state(sctx, query->b.type, 1);
875 si_update_prims_generated_query_state(sctx, query->b.type, 1);
876
877 if (query->b.type == PIPE_QUERY_PIPELINE_STATISTICS)
878 sctx->num_pipeline_stat_queries++;
879
880 if (query->b.type != SI_QUERY_TIME_ELAPSED_SDMA)
881 si_need_gfx_cs_space(sctx);
882
883 va = query->buffer.buf->gpu_address + query->buffer.results_end;
884 query->ops->emit_start(sctx, query, query->buffer.buf, va);
885 }
886
887 static void si_query_hw_do_emit_stop(struct si_context *sctx,
888 struct si_query_hw *query,
889 struct si_resource *buffer,
890 uint64_t va)
891 {
892 struct radeon_cmdbuf *cs = sctx->gfx_cs;
893 uint64_t fence_va = 0;
894
895 switch (query->b.type) {
896 case SI_QUERY_TIME_ELAPSED_SDMA:
897 si_dma_emit_timestamp(sctx, buffer, va + 32 - buffer->gpu_address);
898 return;
899 case PIPE_QUERY_OCCLUSION_COUNTER:
900 case PIPE_QUERY_OCCLUSION_PREDICATE:
901 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
902 va += 8;
903 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
904 radeon_emit(cs, EVENT_TYPE(V_028A90_ZPASS_DONE) | EVENT_INDEX(1));
905 radeon_emit(cs, va);
906 radeon_emit(cs, va >> 32);
907
908 fence_va = va + sctx->screen->info.num_render_backends * 16 - 8;
909 break;
910 case PIPE_QUERY_PRIMITIVES_EMITTED:
911 case PIPE_QUERY_PRIMITIVES_GENERATED:
912 case PIPE_QUERY_SO_STATISTICS:
913 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
914 va += 16;
915 emit_sample_streamout(cs, va, query->stream);
916 break;
917 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
918 va += 16;
919 for (unsigned stream = 0; stream < SI_MAX_STREAMS; ++stream)
920 emit_sample_streamout(cs, va + 32 * stream, stream);
921 break;
922 case PIPE_QUERY_TIME_ELAPSED:
923 va += 8;
924 /* fall through */
925 case PIPE_QUERY_TIMESTAMP:
926 si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0,
927 EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
928 EOP_DATA_SEL_TIMESTAMP, NULL, va,
929 0, query->b.type);
930 fence_va = va + 8;
931 break;
932 case PIPE_QUERY_PIPELINE_STATISTICS: {
933 unsigned sample_size = (query->result_size - 8) / 2;
934
935 va += sample_size;
936 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0));
937 radeon_emit(cs, EVENT_TYPE(V_028A90_SAMPLE_PIPELINESTAT) | EVENT_INDEX(2));
938 radeon_emit(cs, va);
939 radeon_emit(cs, va >> 32);
940
941 fence_va = va + sample_size;
942 break;
943 }
944 default:
945 assert(0);
946 }
947 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, query->buffer.buf, RADEON_USAGE_WRITE,
948 RADEON_PRIO_QUERY);
949
950 if (fence_va) {
951 si_cp_release_mem(sctx, cs, V_028A90_BOTTOM_OF_PIPE_TS, 0,
952 EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
953 EOP_DATA_SEL_VALUE_32BIT,
954 query->buffer.buf, fence_va, 0x80000000,
955 query->b.type);
956 }
957 }
958
959 static void si_query_hw_emit_stop(struct si_context *sctx,
960 struct si_query_hw *query)
961 {
962 uint64_t va;
963
964 /* The queries which need begin already called this in begin_query. */
965 if (query->flags & SI_QUERY_HW_FLAG_NO_START) {
966 si_need_gfx_cs_space(sctx);
967 if (!si_query_buffer_alloc(sctx, &query->buffer, query->ops->prepare_buffer,
968 query->result_size))
969 return;
970 }
971
972 if (!query->buffer.buf)
973 return; // previous buffer allocation failure
974
975 /* emit end query */
976 va = query->buffer.buf->gpu_address + query->buffer.results_end;
977
978 query->ops->emit_stop(sctx, query, query->buffer.buf, va);
979
980 query->buffer.results_end += query->result_size;
981
982 si_update_occlusion_query_state(sctx, query->b.type, -1);
983 si_update_prims_generated_query_state(sctx, query->b.type, -1);
984
985 if (query->b.type == PIPE_QUERY_PIPELINE_STATISTICS)
986 sctx->num_pipeline_stat_queries--;
987 }
988
989 static void emit_set_predicate(struct si_context *ctx,
990 struct si_resource *buf, uint64_t va,
991 uint32_t op)
992 {
993 struct radeon_cmdbuf *cs = ctx->gfx_cs;
994
995 if (ctx->chip_class >= GFX9) {
996 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 2, 0));
997 radeon_emit(cs, op);
998 radeon_emit(cs, va);
999 radeon_emit(cs, va >> 32);
1000 } else {
1001 radeon_emit(cs, PKT3(PKT3_SET_PREDICATION, 1, 0));
1002 radeon_emit(cs, va);
1003 radeon_emit(cs, op | ((va >> 32) & 0xFF));
1004 }
1005 radeon_add_to_buffer_list(ctx, ctx->gfx_cs, buf, RADEON_USAGE_READ,
1006 RADEON_PRIO_QUERY);
1007 }
1008
1009 static void si_emit_query_predication(struct si_context *ctx)
1010 {
1011 struct si_query_hw *query = (struct si_query_hw *)ctx->render_cond;
1012 struct si_query_buffer *qbuf;
1013 uint32_t op;
1014 bool flag_wait, invert;
1015
1016 if (!query)
1017 return;
1018
1019 invert = ctx->render_cond_invert;
1020 flag_wait = ctx->render_cond_mode == PIPE_RENDER_COND_WAIT ||
1021 ctx->render_cond_mode == PIPE_RENDER_COND_BY_REGION_WAIT;
1022
1023 if (query->workaround_buf) {
1024 op = PRED_OP(PREDICATION_OP_BOOL64);
1025 } else {
1026 switch (query->b.type) {
1027 case PIPE_QUERY_OCCLUSION_COUNTER:
1028 case PIPE_QUERY_OCCLUSION_PREDICATE:
1029 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1030 op = PRED_OP(PREDICATION_OP_ZPASS);
1031 break;
1032 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1033 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
1034 op = PRED_OP(PREDICATION_OP_PRIMCOUNT);
1035 invert = !invert;
1036 break;
1037 default:
1038 assert(0);
1039 return;
1040 }
1041 }
1042
1043 /* if true then invert, see GL_ARB_conditional_render_inverted */
1044 if (invert)
1045 op |= PREDICATION_DRAW_NOT_VISIBLE; /* Draw if not visible or overflow */
1046 else
1047 op |= PREDICATION_DRAW_VISIBLE; /* Draw if visible or no overflow */
1048
1049 /* Use the value written by compute shader as a workaround. Note that
1050 * the wait flag does not apply in this predication mode.
1051 *
1052 * The shader outputs the result value to L2. Workarounds only affect GFX8
1053 * and later, where the CP reads data from L2, so we don't need an
1054 * additional flush.
1055 */
1056 if (query->workaround_buf) {
1057 uint64_t va = query->workaround_buf->gpu_address + query->workaround_offset;
1058 emit_set_predicate(ctx, query->workaround_buf, va, op);
1059 return;
1060 }
1061
1062 op |= flag_wait ? PREDICATION_HINT_WAIT : PREDICATION_HINT_NOWAIT_DRAW;
1063
1064 /* emit predicate packets for all data blocks */
1065 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
1066 unsigned results_base = 0;
1067 uint64_t va_base = qbuf->buf->gpu_address;
1068
1069 while (results_base < qbuf->results_end) {
1070 uint64_t va = va_base + results_base;
1071
1072 if (query->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE) {
1073 for (unsigned stream = 0; stream < SI_MAX_STREAMS; ++stream) {
1074 emit_set_predicate(ctx, qbuf->buf, va + 32 * stream, op);
1075
1076 /* set CONTINUE bit for all packets except the first */
1077 op |= PREDICATION_CONTINUE;
1078 }
1079 } else {
1080 emit_set_predicate(ctx, qbuf->buf, va, op);
1081 op |= PREDICATION_CONTINUE;
1082 }
1083
1084 results_base += query->result_size;
1085 }
1086 }
1087 }
1088
1089 static struct pipe_query *si_create_query(struct pipe_context *ctx, unsigned query_type, unsigned index)
1090 {
1091 struct si_screen *sscreen =
1092 (struct si_screen *)ctx->screen;
1093
1094 if (query_type == PIPE_QUERY_TIMESTAMP_DISJOINT ||
1095 query_type == PIPE_QUERY_GPU_FINISHED ||
1096 (query_type >= PIPE_QUERY_DRIVER_SPECIFIC &&
1097 query_type != SI_QUERY_TIME_ELAPSED_SDMA))
1098 return si_query_sw_create(query_type);
1099
1100 return si_query_hw_create(sscreen, query_type, index);
1101 }
1102
1103 static void si_destroy_query(struct pipe_context *ctx, struct pipe_query *query)
1104 {
1105 struct si_context *sctx = (struct si_context *)ctx;
1106 struct si_query *squery = (struct si_query *)query;
1107
1108 squery->ops->destroy(sctx->screen, squery);
1109 }
1110
1111 static boolean si_begin_query(struct pipe_context *ctx,
1112 struct pipe_query *query)
1113 {
1114 struct si_context *sctx = (struct si_context *)ctx;
1115 struct si_query *squery = (struct si_query *)query;
1116
1117 return squery->ops->begin(sctx, squery);
1118 }
1119
1120 bool si_query_hw_begin(struct si_context *sctx,
1121 struct si_query *squery)
1122 {
1123 struct si_query_hw *query = (struct si_query_hw *)squery;
1124
1125 if (query->flags & SI_QUERY_HW_FLAG_NO_START) {
1126 assert(0);
1127 return false;
1128 }
1129
1130 if (!(query->flags & SI_QUERY_HW_FLAG_BEGIN_RESUMES))
1131 si_query_buffer_reset(sctx, &query->buffer);
1132
1133 si_resource_reference(&query->workaround_buf, NULL);
1134
1135 si_query_hw_emit_start(sctx, query);
1136 if (!query->buffer.buf)
1137 return false;
1138
1139 LIST_ADDTAIL(&query->b.active_list, &sctx->active_queries);
1140 sctx->num_cs_dw_queries_suspend += query->b.num_cs_dw_suspend;
1141 return true;
1142 }
1143
1144 static bool si_end_query(struct pipe_context *ctx, struct pipe_query *query)
1145 {
1146 struct si_context *sctx = (struct si_context *)ctx;
1147 struct si_query *squery = (struct si_query *)query;
1148
1149 return squery->ops->end(sctx, squery);
1150 }
1151
1152 bool si_query_hw_end(struct si_context *sctx,
1153 struct si_query *squery)
1154 {
1155 struct si_query_hw *query = (struct si_query_hw *)squery;
1156
1157 if (query->flags & SI_QUERY_HW_FLAG_NO_START)
1158 si_query_buffer_reset(sctx, &query->buffer);
1159
1160 si_query_hw_emit_stop(sctx, query);
1161
1162 if (!(query->flags & SI_QUERY_HW_FLAG_NO_START)) {
1163 LIST_DELINIT(&query->b.active_list);
1164 sctx->num_cs_dw_queries_suspend -= query->b.num_cs_dw_suspend;
1165 }
1166
1167 if (!query->buffer.buf)
1168 return false;
1169
1170 return true;
1171 }
1172
1173 static void si_get_hw_query_params(struct si_context *sctx,
1174 struct si_query_hw *squery, int index,
1175 struct si_hw_query_params *params)
1176 {
1177 unsigned max_rbs = sctx->screen->info.num_render_backends;
1178
1179 params->pair_stride = 0;
1180 params->pair_count = 1;
1181
1182 switch (squery->b.type) {
1183 case PIPE_QUERY_OCCLUSION_COUNTER:
1184 case PIPE_QUERY_OCCLUSION_PREDICATE:
1185 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE:
1186 params->start_offset = 0;
1187 params->end_offset = 8;
1188 params->fence_offset = max_rbs * 16;
1189 params->pair_stride = 16;
1190 params->pair_count = max_rbs;
1191 break;
1192 case PIPE_QUERY_TIME_ELAPSED:
1193 params->start_offset = 0;
1194 params->end_offset = 8;
1195 params->fence_offset = 16;
1196 break;
1197 case PIPE_QUERY_TIMESTAMP:
1198 params->start_offset = 0;
1199 params->end_offset = 0;
1200 params->fence_offset = 8;
1201 break;
1202 case PIPE_QUERY_PRIMITIVES_EMITTED:
1203 params->start_offset = 8;
1204 params->end_offset = 24;
1205 params->fence_offset = params->end_offset + 4;
1206 break;
1207 case PIPE_QUERY_PRIMITIVES_GENERATED:
1208 params->start_offset = 0;
1209 params->end_offset = 16;
1210 params->fence_offset = params->end_offset + 4;
1211 break;
1212 case PIPE_QUERY_SO_STATISTICS:
1213 params->start_offset = 8 - index * 8;
1214 params->end_offset = 24 - index * 8;
1215 params->fence_offset = params->end_offset + 4;
1216 break;
1217 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
1218 params->pair_count = SI_MAX_STREAMS;
1219 params->pair_stride = 32;
1220 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1221 params->start_offset = 0;
1222 params->end_offset = 16;
1223
1224 /* We can re-use the high dword of the last 64-bit value as a
1225 * fence: it is initialized as 0, and the high bit is set by
1226 * the write of the streamout stats event.
1227 */
1228 params->fence_offset = squery->result_size - 4;
1229 break;
1230 case PIPE_QUERY_PIPELINE_STATISTICS:
1231 {
1232 static const unsigned offsets[] = {56, 48, 24, 32, 40, 16, 8, 0, 64, 72, 80};
1233 params->start_offset = offsets[index];
1234 params->end_offset = 88 + offsets[index];
1235 params->fence_offset = 2 * 88;
1236 break;
1237 }
1238 default:
1239 unreachable("si_get_hw_query_params unsupported");
1240 }
1241 }
1242
1243 static unsigned si_query_read_result(void *map, unsigned start_index, unsigned end_index,
1244 bool test_status_bit)
1245 {
1246 uint32_t *current_result = (uint32_t*)map;
1247 uint64_t start, end;
1248
1249 start = (uint64_t)current_result[start_index] |
1250 (uint64_t)current_result[start_index+1] << 32;
1251 end = (uint64_t)current_result[end_index] |
1252 (uint64_t)current_result[end_index+1] << 32;
1253
1254 if (!test_status_bit ||
1255 ((start & 0x8000000000000000UL) && (end & 0x8000000000000000UL))) {
1256 return end - start;
1257 }
1258 return 0;
1259 }
1260
1261 static void si_query_hw_add_result(struct si_screen *sscreen,
1262 struct si_query_hw *query,
1263 void *buffer,
1264 union pipe_query_result *result)
1265 {
1266 unsigned max_rbs = sscreen->info.num_render_backends;
1267
1268 switch (query->b.type) {
1269 case PIPE_QUERY_OCCLUSION_COUNTER: {
1270 for (unsigned i = 0; i < max_rbs; ++i) {
1271 unsigned results_base = i * 16;
1272 result->u64 +=
1273 si_query_read_result(buffer + results_base, 0, 2, true);
1274 }
1275 break;
1276 }
1277 case PIPE_QUERY_OCCLUSION_PREDICATE:
1278 case PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE: {
1279 for (unsigned i = 0; i < max_rbs; ++i) {
1280 unsigned results_base = i * 16;
1281 result->b = result->b ||
1282 si_query_read_result(buffer + results_base, 0, 2, true) != 0;
1283 }
1284 break;
1285 }
1286 case PIPE_QUERY_TIME_ELAPSED:
1287 result->u64 += si_query_read_result(buffer, 0, 2, false);
1288 break;
1289 case SI_QUERY_TIME_ELAPSED_SDMA:
1290 result->u64 += si_query_read_result(buffer, 0, 32/4, false);
1291 break;
1292 case PIPE_QUERY_TIMESTAMP:
1293 result->u64 = *(uint64_t*)buffer;
1294 break;
1295 case PIPE_QUERY_PRIMITIVES_EMITTED:
1296 /* SAMPLE_STREAMOUTSTATS stores this structure:
1297 * {
1298 * u64 NumPrimitivesWritten;
1299 * u64 PrimitiveStorageNeeded;
1300 * }
1301 * We only need NumPrimitivesWritten here. */
1302 result->u64 += si_query_read_result(buffer, 2, 6, true);
1303 break;
1304 case PIPE_QUERY_PRIMITIVES_GENERATED:
1305 /* Here we read PrimitiveStorageNeeded. */
1306 result->u64 += si_query_read_result(buffer, 0, 4, true);
1307 break;
1308 case PIPE_QUERY_SO_STATISTICS:
1309 result->so_statistics.num_primitives_written +=
1310 si_query_read_result(buffer, 2, 6, true);
1311 result->so_statistics.primitives_storage_needed +=
1312 si_query_read_result(buffer, 0, 4, true);
1313 break;
1314 case PIPE_QUERY_SO_OVERFLOW_PREDICATE:
1315 result->b = result->b ||
1316 si_query_read_result(buffer, 2, 6, true) !=
1317 si_query_read_result(buffer, 0, 4, true);
1318 break;
1319 case PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE:
1320 for (unsigned stream = 0; stream < SI_MAX_STREAMS; ++stream) {
1321 result->b = result->b ||
1322 si_query_read_result(buffer, 2, 6, true) !=
1323 si_query_read_result(buffer, 0, 4, true);
1324 buffer = (char *)buffer + 32;
1325 }
1326 break;
1327 case PIPE_QUERY_PIPELINE_STATISTICS:
1328 result->pipeline_statistics.ps_invocations +=
1329 si_query_read_result(buffer, 0, 22, false);
1330 result->pipeline_statistics.c_primitives +=
1331 si_query_read_result(buffer, 2, 24, false);
1332 result->pipeline_statistics.c_invocations +=
1333 si_query_read_result(buffer, 4, 26, false);
1334 result->pipeline_statistics.vs_invocations +=
1335 si_query_read_result(buffer, 6, 28, false);
1336 result->pipeline_statistics.gs_invocations +=
1337 si_query_read_result(buffer, 8, 30, false);
1338 result->pipeline_statistics.gs_primitives +=
1339 si_query_read_result(buffer, 10, 32, false);
1340 result->pipeline_statistics.ia_primitives +=
1341 si_query_read_result(buffer, 12, 34, false);
1342 result->pipeline_statistics.ia_vertices +=
1343 si_query_read_result(buffer, 14, 36, false);
1344 result->pipeline_statistics.hs_invocations +=
1345 si_query_read_result(buffer, 16, 38, false);
1346 result->pipeline_statistics.ds_invocations +=
1347 si_query_read_result(buffer, 18, 40, false);
1348 result->pipeline_statistics.cs_invocations +=
1349 si_query_read_result(buffer, 20, 42, false);
1350 #if 0 /* for testing */
1351 printf("Pipeline stats: IA verts=%llu, IA prims=%llu, VS=%llu, HS=%llu, "
1352 "DS=%llu, GS=%llu, GS prims=%llu, Clipper=%llu, "
1353 "Clipper prims=%llu, PS=%llu, CS=%llu\n",
1354 result->pipeline_statistics.ia_vertices,
1355 result->pipeline_statistics.ia_primitives,
1356 result->pipeline_statistics.vs_invocations,
1357 result->pipeline_statistics.hs_invocations,
1358 result->pipeline_statistics.ds_invocations,
1359 result->pipeline_statistics.gs_invocations,
1360 result->pipeline_statistics.gs_primitives,
1361 result->pipeline_statistics.c_invocations,
1362 result->pipeline_statistics.c_primitives,
1363 result->pipeline_statistics.ps_invocations,
1364 result->pipeline_statistics.cs_invocations);
1365 #endif
1366 break;
1367 default:
1368 assert(0);
1369 }
1370 }
1371
1372 void si_query_hw_suspend(struct si_context *sctx, struct si_query *query)
1373 {
1374 si_query_hw_emit_stop(sctx, (struct si_query_hw *)query);
1375 }
1376
1377 void si_query_hw_resume(struct si_context *sctx, struct si_query *query)
1378 {
1379 si_query_hw_emit_start(sctx, (struct si_query_hw *)query);
1380 }
1381
1382 static const struct si_query_ops query_hw_ops = {
1383 .destroy = si_query_hw_destroy,
1384 .begin = si_query_hw_begin,
1385 .end = si_query_hw_end,
1386 .get_result = si_query_hw_get_result,
1387 .get_result_resource = si_query_hw_get_result_resource,
1388
1389 .suspend = si_query_hw_suspend,
1390 .resume = si_query_hw_resume,
1391 };
1392
1393 static boolean si_get_query_result(struct pipe_context *ctx,
1394 struct pipe_query *query, boolean wait,
1395 union pipe_query_result *result)
1396 {
1397 struct si_context *sctx = (struct si_context *)ctx;
1398 struct si_query *squery = (struct si_query *)query;
1399
1400 return squery->ops->get_result(sctx, squery, wait, result);
1401 }
1402
1403 static void si_get_query_result_resource(struct pipe_context *ctx,
1404 struct pipe_query *query,
1405 boolean wait,
1406 enum pipe_query_value_type result_type,
1407 int index,
1408 struct pipe_resource *resource,
1409 unsigned offset)
1410 {
1411 struct si_context *sctx = (struct si_context *)ctx;
1412 struct si_query *squery = (struct si_query *)query;
1413
1414 squery->ops->get_result_resource(sctx, squery, wait, result_type, index,
1415 resource, offset);
1416 }
1417
1418 static void si_query_hw_clear_result(struct si_query_hw *query,
1419 union pipe_query_result *result)
1420 {
1421 util_query_clear_result(result, query->b.type);
1422 }
1423
1424 bool si_query_hw_get_result(struct si_context *sctx,
1425 struct si_query *squery,
1426 bool wait, union pipe_query_result *result)
1427 {
1428 struct si_screen *sscreen = sctx->screen;
1429 struct si_query_hw *query = (struct si_query_hw *)squery;
1430 struct si_query_buffer *qbuf;
1431
1432 query->ops->clear_result(query, result);
1433
1434 for (qbuf = &query->buffer; qbuf; qbuf = qbuf->previous) {
1435 unsigned usage = PIPE_TRANSFER_READ |
1436 (wait ? 0 : PIPE_TRANSFER_DONTBLOCK);
1437 unsigned results_base = 0;
1438 void *map;
1439
1440 if (squery->b.flushed)
1441 map = sctx->ws->buffer_map(qbuf->buf->buf, NULL, usage);
1442 else
1443 map = si_buffer_map_sync_with_rings(sctx, qbuf->buf, usage);
1444
1445 if (!map)
1446 return false;
1447
1448 while (results_base != qbuf->results_end) {
1449 query->ops->add_result(sscreen, query, map + results_base,
1450 result);
1451 results_base += query->result_size;
1452 }
1453 }
1454
1455 /* Convert the time to expected units. */
1456 if (squery->type == PIPE_QUERY_TIME_ELAPSED ||
1457 squery->type == SI_QUERY_TIME_ELAPSED_SDMA ||
1458 squery->type == PIPE_QUERY_TIMESTAMP) {
1459 result->u64 = (1000000 * result->u64) / sscreen->info.clock_crystal_freq;
1460 }
1461 return true;
1462 }
1463
1464 static void si_restore_qbo_state(struct si_context *sctx,
1465 struct si_qbo_state *st)
1466 {
1467 sctx->b.bind_compute_state(&sctx->b, st->saved_compute);
1468
1469 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1470 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1471
1472 sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo,
1473 st->saved_ssbo_writable_mask);
1474 for (unsigned i = 0; i < 3; ++i)
1475 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1476 }
1477
1478 static void si_query_hw_get_result_resource(struct si_context *sctx,
1479 struct si_query *squery,
1480 bool wait,
1481 enum pipe_query_value_type result_type,
1482 int index,
1483 struct pipe_resource *resource,
1484 unsigned offset)
1485 {
1486 struct si_query_hw *query = (struct si_query_hw *)squery;
1487 struct si_query_buffer *qbuf;
1488 struct si_query_buffer *qbuf_prev;
1489 struct pipe_resource *tmp_buffer = NULL;
1490 unsigned tmp_buffer_offset = 0;
1491 struct si_qbo_state saved_state = {};
1492 struct pipe_grid_info grid = {};
1493 struct pipe_constant_buffer constant_buffer = {};
1494 struct pipe_shader_buffer ssbo[3];
1495 struct si_hw_query_params params;
1496 struct {
1497 uint32_t end_offset;
1498 uint32_t result_stride;
1499 uint32_t result_count;
1500 uint32_t config;
1501 uint32_t fence_offset;
1502 uint32_t pair_stride;
1503 uint32_t pair_count;
1504 } consts;
1505
1506 if (!sctx->query_result_shader) {
1507 sctx->query_result_shader = si_create_query_result_cs(sctx);
1508 if (!sctx->query_result_shader)
1509 return;
1510 }
1511
1512 if (query->buffer.previous) {
1513 u_suballocator_alloc(sctx->allocator_zeroed_memory, 16, 16,
1514 &tmp_buffer_offset, &tmp_buffer);
1515 if (!tmp_buffer)
1516 return;
1517 }
1518
1519 si_save_qbo_state(sctx, &saved_state);
1520
1521 si_get_hw_query_params(sctx, query, index >= 0 ? index : 0, &params);
1522 consts.end_offset = params.end_offset - params.start_offset;
1523 consts.fence_offset = params.fence_offset - params.start_offset;
1524 consts.result_stride = query->result_size;
1525 consts.pair_stride = params.pair_stride;
1526 consts.pair_count = params.pair_count;
1527
1528 constant_buffer.buffer_size = sizeof(consts);
1529 constant_buffer.user_buffer = &consts;
1530
1531 ssbo[1].buffer = tmp_buffer;
1532 ssbo[1].buffer_offset = tmp_buffer_offset;
1533 ssbo[1].buffer_size = 16;
1534
1535 ssbo[2] = ssbo[1];
1536
1537 sctx->b.bind_compute_state(&sctx->b, sctx->query_result_shader);
1538
1539 grid.block[0] = 1;
1540 grid.block[1] = 1;
1541 grid.block[2] = 1;
1542 grid.grid[0] = 1;
1543 grid.grid[1] = 1;
1544 grid.grid[2] = 1;
1545
1546 consts.config = 0;
1547 if (index < 0)
1548 consts.config |= 4;
1549 if (query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE ||
1550 query->b.type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE)
1551 consts.config |= 8;
1552 else if (query->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE ||
1553 query->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE)
1554 consts.config |= 8 | 256;
1555 else if (query->b.type == PIPE_QUERY_TIMESTAMP ||
1556 query->b.type == PIPE_QUERY_TIME_ELAPSED)
1557 consts.config |= 32;
1558
1559 switch (result_type) {
1560 case PIPE_QUERY_TYPE_U64:
1561 case PIPE_QUERY_TYPE_I64:
1562 consts.config |= 64;
1563 break;
1564 case PIPE_QUERY_TYPE_I32:
1565 consts.config |= 128;
1566 break;
1567 case PIPE_QUERY_TYPE_U32:
1568 break;
1569 }
1570
1571 sctx->flags |= sctx->screen->barrier_flags.cp_to_L2;
1572
1573 for (qbuf = &query->buffer; qbuf; qbuf = qbuf_prev) {
1574 if (query->b.type != PIPE_QUERY_TIMESTAMP) {
1575 qbuf_prev = qbuf->previous;
1576 consts.result_count = qbuf->results_end / query->result_size;
1577 consts.config &= ~3;
1578 if (qbuf != &query->buffer)
1579 consts.config |= 1;
1580 if (qbuf->previous)
1581 consts.config |= 2;
1582 } else {
1583 /* Only read the last timestamp. */
1584 qbuf_prev = NULL;
1585 consts.result_count = 0;
1586 consts.config |= 16;
1587 params.start_offset += qbuf->results_end - query->result_size;
1588 }
1589
1590 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &constant_buffer);
1591
1592 ssbo[0].buffer = &qbuf->buf->b.b;
1593 ssbo[0].buffer_offset = params.start_offset;
1594 ssbo[0].buffer_size = qbuf->results_end - params.start_offset;
1595
1596 if (!qbuf->previous) {
1597 ssbo[2].buffer = resource;
1598 ssbo[2].buffer_offset = offset;
1599 ssbo[2].buffer_size = 8;
1600
1601 si_resource(resource)->TC_L2_dirty = true;
1602 }
1603
1604 sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, ssbo,
1605 1 << 2);
1606
1607 if (wait && qbuf == &query->buffer) {
1608 uint64_t va;
1609
1610 /* Wait for result availability. Wait only for readiness
1611 * of the last entry, since the fence writes should be
1612 * serialized in the CP.
1613 */
1614 va = qbuf->buf->gpu_address + qbuf->results_end - query->result_size;
1615 va += params.fence_offset;
1616
1617 si_cp_wait_mem(sctx, sctx->gfx_cs, va, 0x80000000,
1618 0x80000000, WAIT_REG_MEM_EQUAL);
1619 }
1620
1621 sctx->b.launch_grid(&sctx->b, &grid);
1622 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
1623 }
1624
1625 si_restore_qbo_state(sctx, &saved_state);
1626 pipe_resource_reference(&tmp_buffer, NULL);
1627 }
1628
1629 static void si_render_condition(struct pipe_context *ctx,
1630 struct pipe_query *query,
1631 boolean condition,
1632 enum pipe_render_cond_flag mode)
1633 {
1634 struct si_context *sctx = (struct si_context *)ctx;
1635 struct si_query_hw *squery = (struct si_query_hw *)query;
1636 struct si_atom *atom = &sctx->atoms.s.render_cond;
1637
1638 if (query) {
1639 bool needs_workaround = false;
1640
1641 /* There was a firmware regression in GFX8 which causes successive
1642 * SET_PREDICATION packets to give the wrong answer for
1643 * non-inverted stream overflow predication.
1644 */
1645 if (((sctx->chip_class == GFX8 && sctx->screen->info.pfp_fw_feature < 49) ||
1646 (sctx->chip_class == GFX9 && sctx->screen->info.pfp_fw_feature < 38)) &&
1647 !condition &&
1648 (squery->b.type == PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE ||
1649 (squery->b.type == PIPE_QUERY_SO_OVERFLOW_PREDICATE &&
1650 (squery->buffer.previous ||
1651 squery->buffer.results_end > squery->result_size)))) {
1652 needs_workaround = true;
1653 }
1654
1655 if (needs_workaround && !squery->workaround_buf) {
1656 bool old_force_off = sctx->render_cond_force_off;
1657 sctx->render_cond_force_off = true;
1658
1659 u_suballocator_alloc(
1660 sctx->allocator_zeroed_memory, 8, 8,
1661 &squery->workaround_offset,
1662 (struct pipe_resource **)&squery->workaround_buf);
1663
1664 /* Reset to NULL to avoid a redundant SET_PREDICATION
1665 * from launching the compute grid.
1666 */
1667 sctx->render_cond = NULL;
1668
1669 ctx->get_query_result_resource(
1670 ctx, query, true, PIPE_QUERY_TYPE_U64, 0,
1671 &squery->workaround_buf->b.b, squery->workaround_offset);
1672
1673 /* Settings this in the render cond atom is too late,
1674 * so set it here. */
1675 sctx->flags |= sctx->screen->barrier_flags.L2_to_cp |
1676 SI_CONTEXT_FLUSH_FOR_RENDER_COND;
1677
1678 sctx->render_cond_force_off = old_force_off;
1679 }
1680 }
1681
1682 sctx->render_cond = query;
1683 sctx->render_cond_invert = condition;
1684 sctx->render_cond_mode = mode;
1685
1686 si_set_atom_dirty(sctx, atom, query != NULL);
1687 }
1688
1689 void si_suspend_queries(struct si_context *sctx)
1690 {
1691 struct si_query *query;
1692
1693 LIST_FOR_EACH_ENTRY(query, &sctx->active_queries, active_list)
1694 query->ops->suspend(sctx, query);
1695 }
1696
1697 void si_resume_queries(struct si_context *sctx)
1698 {
1699 struct si_query *query;
1700
1701 /* Check CS space here. Resuming must not be interrupted by flushes. */
1702 si_need_gfx_cs_space(sctx);
1703
1704 LIST_FOR_EACH_ENTRY(query, &sctx->active_queries, active_list)
1705 query->ops->resume(sctx, query);
1706 }
1707
1708 #define XFULL(name_, query_type_, type_, result_type_, group_id_) \
1709 { \
1710 .name = name_, \
1711 .query_type = SI_QUERY_##query_type_, \
1712 .type = PIPE_DRIVER_QUERY_TYPE_##type_, \
1713 .result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_##result_type_, \
1714 .group_id = group_id_ \
1715 }
1716
1717 #define X(name_, query_type_, type_, result_type_) \
1718 XFULL(name_, query_type_, type_, result_type_, ~(unsigned)0)
1719
1720 #define XG(group_, name_, query_type_, type_, result_type_) \
1721 XFULL(name_, query_type_, type_, result_type_, SI_QUERY_GROUP_##group_)
1722
1723 static struct pipe_driver_query_info si_driver_query_list[] = {
1724 X("num-compilations", NUM_COMPILATIONS, UINT64, CUMULATIVE),
1725 X("num-shaders-created", NUM_SHADERS_CREATED, UINT64, CUMULATIVE),
1726 X("num-shader-cache-hits", NUM_SHADER_CACHE_HITS, UINT64, CUMULATIVE),
1727 X("draw-calls", DRAW_CALLS, UINT64, AVERAGE),
1728 X("decompress-calls", DECOMPRESS_CALLS, UINT64, AVERAGE),
1729 X("MRT-draw-calls", MRT_DRAW_CALLS, UINT64, AVERAGE),
1730 X("prim-restart-calls", PRIM_RESTART_CALLS, UINT64, AVERAGE),
1731 X("spill-draw-calls", SPILL_DRAW_CALLS, UINT64, AVERAGE),
1732 X("compute-calls", COMPUTE_CALLS, UINT64, AVERAGE),
1733 X("spill-compute-calls", SPILL_COMPUTE_CALLS, UINT64, AVERAGE),
1734 X("dma-calls", DMA_CALLS, UINT64, AVERAGE),
1735 X("cp-dma-calls", CP_DMA_CALLS, UINT64, AVERAGE),
1736 X("num-vs-flushes", NUM_VS_FLUSHES, UINT64, AVERAGE),
1737 X("num-ps-flushes", NUM_PS_FLUSHES, UINT64, AVERAGE),
1738 X("num-cs-flushes", NUM_CS_FLUSHES, UINT64, AVERAGE),
1739 X("num-CB-cache-flushes", NUM_CB_CACHE_FLUSHES, UINT64, AVERAGE),
1740 X("num-DB-cache-flushes", NUM_DB_CACHE_FLUSHES, UINT64, AVERAGE),
1741 X("num-L2-invalidates", NUM_L2_INVALIDATES, UINT64, AVERAGE),
1742 X("num-L2-writebacks", NUM_L2_WRITEBACKS, UINT64, AVERAGE),
1743 X("num-resident-handles", NUM_RESIDENT_HANDLES, UINT64, AVERAGE),
1744 X("tc-offloaded-slots", TC_OFFLOADED_SLOTS, UINT64, AVERAGE),
1745 X("tc-direct-slots", TC_DIRECT_SLOTS, UINT64, AVERAGE),
1746 X("tc-num-syncs", TC_NUM_SYNCS, UINT64, AVERAGE),
1747 X("CS-thread-busy", CS_THREAD_BUSY, UINT64, AVERAGE),
1748 X("gallium-thread-busy", GALLIUM_THREAD_BUSY, UINT64, AVERAGE),
1749 X("requested-VRAM", REQUESTED_VRAM, BYTES, AVERAGE),
1750 X("requested-GTT", REQUESTED_GTT, BYTES, AVERAGE),
1751 X("mapped-VRAM", MAPPED_VRAM, BYTES, AVERAGE),
1752 X("mapped-GTT", MAPPED_GTT, BYTES, AVERAGE),
1753 X("buffer-wait-time", BUFFER_WAIT_TIME, MICROSECONDS, CUMULATIVE),
1754 X("num-mapped-buffers", NUM_MAPPED_BUFFERS, UINT64, AVERAGE),
1755 X("num-GFX-IBs", NUM_GFX_IBS, UINT64, AVERAGE),
1756 X("num-SDMA-IBs", NUM_SDMA_IBS, UINT64, AVERAGE),
1757 X("GFX-BO-list-size", GFX_BO_LIST_SIZE, UINT64, AVERAGE),
1758 X("GFX-IB-size", GFX_IB_SIZE, UINT64, AVERAGE),
1759 X("num-bytes-moved", NUM_BYTES_MOVED, BYTES, CUMULATIVE),
1760 X("num-evictions", NUM_EVICTIONS, UINT64, CUMULATIVE),
1761 X("VRAM-CPU-page-faults", NUM_VRAM_CPU_PAGE_FAULTS, UINT64, CUMULATIVE),
1762 X("VRAM-usage", VRAM_USAGE, BYTES, AVERAGE),
1763 X("VRAM-vis-usage", VRAM_VIS_USAGE, BYTES, AVERAGE),
1764 X("GTT-usage", GTT_USAGE, BYTES, AVERAGE),
1765 X("back-buffer-ps-draw-ratio", BACK_BUFFER_PS_DRAW_RATIO, UINT64, AVERAGE),
1766
1767 /* GPIN queries are for the benefit of old versions of GPUPerfStudio,
1768 * which use it as a fallback path to detect the GPU type.
1769 *
1770 * Note: The names of these queries are significant for GPUPerfStudio
1771 * (and possibly their order as well). */
1772 XG(GPIN, "GPIN_000", GPIN_ASIC_ID, UINT, AVERAGE),
1773 XG(GPIN, "GPIN_001", GPIN_NUM_SIMD, UINT, AVERAGE),
1774 XG(GPIN, "GPIN_002", GPIN_NUM_RB, UINT, AVERAGE),
1775 XG(GPIN, "GPIN_003", GPIN_NUM_SPI, UINT, AVERAGE),
1776 XG(GPIN, "GPIN_004", GPIN_NUM_SE, UINT, AVERAGE),
1777
1778 X("temperature", GPU_TEMPERATURE, UINT64, AVERAGE),
1779 X("shader-clock", CURRENT_GPU_SCLK, HZ, AVERAGE),
1780 X("memory-clock", CURRENT_GPU_MCLK, HZ, AVERAGE),
1781
1782 /* The following queries must be at the end of the list because their
1783 * availability is adjusted dynamically based on the DRM version. */
1784 X("GPU-load", GPU_LOAD, UINT64, AVERAGE),
1785 X("GPU-shaders-busy", GPU_SHADERS_BUSY, UINT64, AVERAGE),
1786 X("GPU-ta-busy", GPU_TA_BUSY, UINT64, AVERAGE),
1787 X("GPU-gds-busy", GPU_GDS_BUSY, UINT64, AVERAGE),
1788 X("GPU-vgt-busy", GPU_VGT_BUSY, UINT64, AVERAGE),
1789 X("GPU-ia-busy", GPU_IA_BUSY, UINT64, AVERAGE),
1790 X("GPU-sx-busy", GPU_SX_BUSY, UINT64, AVERAGE),
1791 X("GPU-wd-busy", GPU_WD_BUSY, UINT64, AVERAGE),
1792 X("GPU-bci-busy", GPU_BCI_BUSY, UINT64, AVERAGE),
1793 X("GPU-sc-busy", GPU_SC_BUSY, UINT64, AVERAGE),
1794 X("GPU-pa-busy", GPU_PA_BUSY, UINT64, AVERAGE),
1795 X("GPU-db-busy", GPU_DB_BUSY, UINT64, AVERAGE),
1796 X("GPU-cp-busy", GPU_CP_BUSY, UINT64, AVERAGE),
1797 X("GPU-cb-busy", GPU_CB_BUSY, UINT64, AVERAGE),
1798
1799 /* SRBM_STATUS2 */
1800 X("GPU-sdma-busy", GPU_SDMA_BUSY, UINT64, AVERAGE),
1801
1802 /* CP_STAT */
1803 X("GPU-pfp-busy", GPU_PFP_BUSY, UINT64, AVERAGE),
1804 X("GPU-meq-busy", GPU_MEQ_BUSY, UINT64, AVERAGE),
1805 X("GPU-me-busy", GPU_ME_BUSY, UINT64, AVERAGE),
1806 X("GPU-surf-sync-busy", GPU_SURF_SYNC_BUSY, UINT64, AVERAGE),
1807 X("GPU-cp-dma-busy", GPU_CP_DMA_BUSY, UINT64, AVERAGE),
1808 X("GPU-scratch-ram-busy", GPU_SCRATCH_RAM_BUSY, UINT64, AVERAGE),
1809
1810 X("pd-num-prims-accepted", PD_NUM_PRIMS_ACCEPTED, UINT64, AVERAGE),
1811 X("pd-num-prims-rejected", PD_NUM_PRIMS_REJECTED, UINT64, AVERAGE),
1812 X("pd-num-prims-ineligible", PD_NUM_PRIMS_INELIGIBLE,UINT64, AVERAGE),
1813 };
1814
1815 #undef X
1816 #undef XG
1817 #undef XFULL
1818
1819 static unsigned si_get_num_queries(struct si_screen *sscreen)
1820 {
1821 /* amdgpu */
1822 if (sscreen->info.is_amdgpu) {
1823 if (sscreen->info.chip_class >= GFX8)
1824 return ARRAY_SIZE(si_driver_query_list);
1825 else
1826 return ARRAY_SIZE(si_driver_query_list) - 7;
1827 }
1828
1829 /* radeon */
1830 if (sscreen->info.has_read_registers_query) {
1831 if (sscreen->info.chip_class == GFX7)
1832 return ARRAY_SIZE(si_driver_query_list) - 6;
1833 else
1834 return ARRAY_SIZE(si_driver_query_list) - 7;
1835 }
1836
1837 return ARRAY_SIZE(si_driver_query_list) - 21;
1838 }
1839
1840 static int si_get_driver_query_info(struct pipe_screen *screen,
1841 unsigned index,
1842 struct pipe_driver_query_info *info)
1843 {
1844 struct si_screen *sscreen = (struct si_screen*)screen;
1845 unsigned num_queries = si_get_num_queries(sscreen);
1846
1847 if (!info) {
1848 unsigned num_perfcounters =
1849 si_get_perfcounter_info(sscreen, 0, NULL);
1850
1851 return num_queries + num_perfcounters;
1852 }
1853
1854 if (index >= num_queries)
1855 return si_get_perfcounter_info(sscreen, index - num_queries, info);
1856
1857 *info = si_driver_query_list[index];
1858
1859 switch (info->query_type) {
1860 case SI_QUERY_REQUESTED_VRAM:
1861 case SI_QUERY_VRAM_USAGE:
1862 case SI_QUERY_MAPPED_VRAM:
1863 info->max_value.u64 = sscreen->info.vram_size;
1864 break;
1865 case SI_QUERY_REQUESTED_GTT:
1866 case SI_QUERY_GTT_USAGE:
1867 case SI_QUERY_MAPPED_GTT:
1868 info->max_value.u64 = sscreen->info.gart_size;
1869 break;
1870 case SI_QUERY_GPU_TEMPERATURE:
1871 info->max_value.u64 = 125;
1872 break;
1873 case SI_QUERY_VRAM_VIS_USAGE:
1874 info->max_value.u64 = sscreen->info.vram_vis_size;
1875 break;
1876 }
1877
1878 if (info->group_id != ~(unsigned)0 && sscreen->perfcounters)
1879 info->group_id += sscreen->perfcounters->num_groups;
1880
1881 return 1;
1882 }
1883
1884 /* Note: Unfortunately, GPUPerfStudio hardcodes the order of hardware
1885 * performance counter groups, so be careful when changing this and related
1886 * functions.
1887 */
1888 static int si_get_driver_query_group_info(struct pipe_screen *screen,
1889 unsigned index,
1890 struct pipe_driver_query_group_info *info)
1891 {
1892 struct si_screen *sscreen = (struct si_screen *)screen;
1893 unsigned num_pc_groups = 0;
1894
1895 if (sscreen->perfcounters)
1896 num_pc_groups = sscreen->perfcounters->num_groups;
1897
1898 if (!info)
1899 return num_pc_groups + SI_NUM_SW_QUERY_GROUPS;
1900
1901 if (index < num_pc_groups)
1902 return si_get_perfcounter_group_info(sscreen, index, info);
1903
1904 index -= num_pc_groups;
1905 if (index >= SI_NUM_SW_QUERY_GROUPS)
1906 return 0;
1907
1908 info->name = "GPIN";
1909 info->max_active_queries = 5;
1910 info->num_queries = 5;
1911 return 1;
1912 }
1913
1914 void si_init_query_functions(struct si_context *sctx)
1915 {
1916 sctx->b.create_query = si_create_query;
1917 sctx->b.create_batch_query = si_create_batch_query;
1918 sctx->b.destroy_query = si_destroy_query;
1919 sctx->b.begin_query = si_begin_query;
1920 sctx->b.end_query = si_end_query;
1921 sctx->b.get_query_result = si_get_query_result;
1922 sctx->b.get_query_result_resource = si_get_query_result_resource;
1923
1924 if (sctx->has_graphics) {
1925 sctx->atoms.s.render_cond.emit = si_emit_query_predication;
1926 sctx->b.render_condition = si_render_condition;
1927 }
1928
1929 LIST_INITHEAD(&sctx->active_queries);
1930 }
1931
1932 void si_init_screen_query_functions(struct si_screen *sscreen)
1933 {
1934 sscreen->b.get_driver_query_info = si_get_driver_query_info;
1935 sscreen->b.get_driver_query_group_info = si_get_driver_query_group_info;
1936 }