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radeonsi: get tgsi_shader_info only once before compilation
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "radeon/radeon_llvm.h"
36 #include "radeon/radeon_llvm_emit.h"
37 #include "util/u_memory.h"
38 #include "tgsi/tgsi_parse.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "si_pipe.h"
43 #include "si_shader.h"
44 #include "sid.h"
45
46 #include <errno.h>
47
48 struct si_shader_output_values
49 {
50 LLVMValueRef values[4];
51 unsigned name;
52 unsigned index;
53 unsigned sid;
54 unsigned usage;
55 };
56
57 struct si_shader_context
58 {
59 struct radeon_llvm_context radeon_bld;
60 struct tgsi_parse_context parse;
61 struct tgsi_token * tokens;
62 struct si_shader *shader;
63 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
64 int param_streamout_config;
65 int param_streamout_write_index;
66 int param_streamout_offset[4];
67 int param_vertex_id;
68 int param_instance_id;
69 LLVMValueRef const_md;
70 LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS];
71 LLVMValueRef ddxy_lds;
72 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
73 LLVMValueRef *resources;
74 LLVMValueRef *samplers;
75 LLVMValueRef so_buffers[4];
76 LLVMValueRef gs_next_vertex;
77 };
78
79 static struct si_shader_context * si_shader_context(
80 struct lp_build_tgsi_context * bld_base)
81 {
82 return (struct si_shader_context *)bld_base;
83 }
84
85
86 #define PERSPECTIVE_BASE 0
87 #define LINEAR_BASE 9
88
89 #define SAMPLE_OFFSET 0
90 #define CENTER_OFFSET 2
91 #define CENTROID_OFSET 4
92
93 #define USE_SGPR_MAX_SUFFIX_LEN 5
94 #define CONST_ADDR_SPACE 2
95 #define LOCAL_ADDR_SPACE 3
96 #define USER_SGPR_ADDR_SPACE 8
97
98
99 #define SENDMSG_GS 2
100 #define SENDMSG_GS_DONE 3
101
102 #define SENDMSG_GS_OP_NOP (0 << 4)
103 #define SENDMSG_GS_OP_CUT (1 << 4)
104 #define SENDMSG_GS_OP_EMIT (2 << 4)
105 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
106
107 /**
108 * Returns a unique index for a semantic name and index. The index must be
109 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
110 * calculated.
111 */
112 static unsigned get_unique_index(unsigned semantic_name, unsigned index)
113 {
114 switch (semantic_name) {
115 case TGSI_SEMANTIC_POSITION:
116 return 0;
117 case TGSI_SEMANTIC_PSIZE:
118 return 1;
119 case TGSI_SEMANTIC_CLIPDIST:
120 assert(index <= 1);
121 return 2 + index;
122 case TGSI_SEMANTIC_CLIPVERTEX:
123 return 4;
124 case TGSI_SEMANTIC_COLOR:
125 assert(index <= 1);
126 return 5 + index;
127 case TGSI_SEMANTIC_BCOLOR:
128 assert(index <= 1);
129 return 7 + index;
130 case TGSI_SEMANTIC_FOG:
131 return 9;
132 case TGSI_SEMANTIC_EDGEFLAG:
133 return 10;
134 case TGSI_SEMANTIC_GENERIC:
135 assert(index <= 63-11);
136 return 11 + index;
137 default:
138 assert(0);
139 return 63;
140 }
141 }
142
143 /**
144 * Given a semantic name and index of a parameter and a mask of used parameters
145 * (inputs or outputs), return the index of the parameter in the list of all
146 * used parameters.
147 *
148 * For example, assume this list of parameters:
149 * POSITION, PSIZE, GENERIC0, GENERIC2
150 * which has the mask:
151 * 11000000000101
152 * Then:
153 * querying POSITION returns 0,
154 * querying PSIZE returns 1,
155 * querying GENERIC0 returns 2,
156 * querying GENERIC2 returns 3.
157 *
158 * Which can be used as an offset to a parameter buffer in units of vec4s.
159 */
160 static int get_param_index(unsigned semantic_name, unsigned index,
161 uint64_t mask)
162 {
163 unsigned unique_index = get_unique_index(semantic_name, index);
164 int i, param_index = 0;
165
166 /* If not present... */
167 if (!((1llu << unique_index) & mask))
168 return -1;
169
170 for (i = 0; mask; i++) {
171 uint64_t bit = 1llu << i;
172
173 if (bit & mask) {
174 if (i == unique_index)
175 return param_index;
176
177 mask &= ~bit;
178 param_index++;
179 }
180 }
181
182 assert(!"unreachable");
183 return -1;
184 }
185
186 /**
187 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
188 *
189 * @param offset The offset parameter specifies the number of
190 * elements to offset, not the number of bytes or dwords. An element is the
191 * the type pointed to by the base_ptr parameter (e.g. int is the element of
192 * an int* pointer)
193 *
194 * When LLVM lowers the load instruction, it will convert the element offset
195 * into a dword offset automatically.
196 *
197 */
198 static LLVMValueRef build_indexed_load(
199 struct si_shader_context * si_shader_ctx,
200 LLVMValueRef base_ptr,
201 LLVMValueRef offset)
202 {
203 struct lp_build_context * base = &si_shader_ctx->radeon_bld.soa.bld_base.base;
204
205 LLVMValueRef indices[2] = {
206 LLVMConstInt(LLVMInt64TypeInContext(base->gallivm->context), 0, false),
207 offset
208 };
209 LLVMValueRef computed_ptr = LLVMBuildGEP(
210 base->gallivm->builder, base_ptr, indices, 2, "");
211
212 LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, computed_ptr, "");
213 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
214 return result;
215 }
216
217 static LLVMValueRef get_instance_index_for_fetch(
218 struct radeon_llvm_context * radeon_bld,
219 unsigned divisor)
220 {
221 struct si_shader_context *si_shader_ctx =
222 si_shader_context(&radeon_bld->soa.bld_base);
223 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
224
225 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
226 si_shader_ctx->param_instance_id);
227 result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
228 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
229
230 if (divisor > 1)
231 result = LLVMBuildUDiv(gallivm->builder, result,
232 lp_build_const_int32(gallivm, divisor), "");
233
234 return result;
235 }
236
237 static int si_store_shader_io_attribs(struct si_shader *shader,
238 const struct tgsi_full_declaration *d)
239 {
240 int i = -1;
241
242 switch (d->Declaration.File) {
243 case TGSI_FILE_INPUT:
244 i = shader->ninput++;
245 assert(i < Elements(shader->input));
246 shader->input[i].name = d->Semantic.Name;
247 shader->input[i].sid = d->Semantic.Index;
248 shader->input[i].index = d->Range.First;
249 shader->input[i].interpolate = d->Interp.Interpolate;
250 shader->input[i].centroid = d->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID;
251 return -1;
252
253 case TGSI_FILE_OUTPUT:
254 i = shader->noutput++;
255 assert(i < Elements(shader->output));
256 shader->output[i].name = d->Semantic.Name;
257 shader->output[i].sid = d->Semantic.Index;
258 shader->output[i].index = d->Range.First;
259 shader->output[i].usage = d->Declaration.UsageMask;
260 break;
261 }
262
263 return i;
264 }
265
266 static void declare_input_vs(
267 struct radeon_llvm_context *radeon_bld,
268 unsigned input_index,
269 const struct tgsi_full_declaration *decl)
270 {
271 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
272 struct gallivm_state *gallivm = base->gallivm;
273 struct si_shader_context *si_shader_ctx =
274 si_shader_context(&radeon_bld->soa.bld_base);
275 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
276
277 unsigned chan;
278
279 LLVMValueRef t_list_ptr;
280 LLVMValueRef t_offset;
281 LLVMValueRef t_list;
282 LLVMValueRef attribute_offset;
283 LLVMValueRef buffer_index;
284 LLVMValueRef args[3];
285 LLVMTypeRef vec4_type;
286 LLVMValueRef input;
287
288 /* Load the T list */
289 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFER);
290
291 t_offset = lp_build_const_int32(gallivm, input_index);
292
293 t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
294
295 /* Build the attribute offset */
296 attribute_offset = lp_build_const_int32(gallivm, 0);
297
298 if (divisor) {
299 /* Build index from instance ID, start instance and divisor */
300 si_shader_ctx->shader->uses_instanceid = true;
301 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
302 } else {
303 /* Load the buffer index for vertices. */
304 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
305 si_shader_ctx->param_vertex_id);
306 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
307 SI_PARAM_BASE_VERTEX);
308 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
309 }
310
311 vec4_type = LLVMVectorType(base->elem_type, 4);
312 args[0] = t_list;
313 args[1] = attribute_offset;
314 args[2] = buffer_index;
315 input = build_intrinsic(gallivm->builder,
316 "llvm.SI.vs.load.input", vec4_type, args, 3,
317 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
318
319 /* Break up the vec4 into individual components */
320 for (chan = 0; chan < 4; chan++) {
321 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
322 /* XXX: Use a helper function for this. There is one in
323 * tgsi_llvm.c. */
324 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
325 LLVMBuildExtractElement(gallivm->builder,
326 input, llvm_chan, "");
327 }
328 }
329
330 static void declare_input_gs(
331 struct radeon_llvm_context *radeon_bld,
332 unsigned input_index,
333 const struct tgsi_full_declaration *decl)
334 {
335 struct si_shader_context *si_shader_ctx =
336 si_shader_context(&radeon_bld->soa.bld_base);
337 struct si_shader *shader = si_shader_ctx->shader;
338
339 si_store_shader_io_attribs(shader, decl);
340
341 if (decl->Semantic.Name != TGSI_SEMANTIC_PRIMID) {
342 shader->gs_used_inputs |=
343 1llu << get_unique_index(decl->Semantic.Name,
344 decl->Semantic.Index);
345 shader->nparam++;
346 }
347 }
348
349 static LLVMValueRef fetch_input_gs(
350 struct lp_build_tgsi_context *bld_base,
351 const struct tgsi_full_src_register *reg,
352 enum tgsi_opcode_type type,
353 unsigned swizzle)
354 {
355 struct lp_build_context *base = &bld_base->base;
356 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
357 struct si_shader *shader = si_shader_ctx->shader;
358 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
359 struct gallivm_state *gallivm = base->gallivm;
360 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
361 LLVMValueRef vtx_offset;
362 LLVMValueRef t_list_ptr;
363 LLVMValueRef t_list;
364 LLVMValueRef args[9];
365 unsigned vtx_offset_param;
366 struct si_shader_input *input = &shader->input[reg->Register.Index];
367
368 if (swizzle != ~0 &&
369 shader->input[reg->Register.Index].name == TGSI_SEMANTIC_PRIMID) {
370 if (swizzle == 0)
371 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
372 SI_PARAM_PRIMITIVE_ID);
373 else
374 return uint->zero;
375 }
376
377 if (!reg->Register.Dimension)
378 return NULL;
379
380 if (swizzle == ~0) {
381 LLVMValueRef values[TGSI_NUM_CHANNELS];
382 unsigned chan;
383 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
384 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
385 }
386 return lp_build_gather_values(bld_base->base.gallivm, values,
387 TGSI_NUM_CHANNELS);
388 }
389
390 /* Get the vertex offset parameter */
391 vtx_offset_param = reg->Dimension.Index;
392 if (vtx_offset_param < 2) {
393 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
394 } else {
395 assert(vtx_offset_param < 6);
396 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
397 }
398 vtx_offset = lp_build_mul_imm(uint,
399 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
400 vtx_offset_param),
401 4);
402
403 /* Load the ESGS ring resource descriptor */
404 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
405 SI_PARAM_RW_BUFFERS);
406 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
407 lp_build_const_int32(gallivm, SI_RING_ESGS));
408
409 args[0] = t_list;
410 args[1] = vtx_offset;
411 args[2] = lp_build_const_int32(gallivm,
412 (get_param_index(input->name, input->sid,
413 shader->gs_used_inputs) * 4 +
414 swizzle) * 256);
415 args[3] = uint->zero;
416 args[4] = uint->one; /* OFFEN */
417 args[5] = uint->zero; /* IDXEN */
418 args[6] = uint->one; /* GLC */
419 args[7] = uint->zero; /* SLC */
420 args[8] = uint->zero; /* TFE */
421
422 return LLVMBuildBitCast(gallivm->builder,
423 build_intrinsic(gallivm->builder,
424 "llvm.SI.buffer.load.dword.i32.i32",
425 i32, args, 9,
426 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
427 tgsi2llvmtype(bld_base, type), "");
428 }
429
430 static void declare_input_fs(
431 struct radeon_llvm_context *radeon_bld,
432 unsigned input_index,
433 const struct tgsi_full_declaration *decl)
434 {
435 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
436 struct si_shader_context *si_shader_ctx =
437 si_shader_context(&radeon_bld->soa.bld_base);
438 struct si_shader *shader = si_shader_ctx->shader;
439 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
440 struct gallivm_state *gallivm = base->gallivm;
441 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
442 LLVMValueRef main_fn = radeon_bld->main_fn;
443
444 LLVMValueRef interp_param;
445 const char * intr_name;
446
447 /* This value is:
448 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
449 * quad begins a new primitive. Bit 0 always needs
450 * to be unset)
451 * [32:16] ParamOffset
452 *
453 */
454 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
455 LLVMValueRef attr_number;
456
457 unsigned chan;
458
459 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
460 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
461 unsigned soa_index =
462 radeon_llvm_reg_index_soa(input_index, chan);
463 radeon_bld->inputs[soa_index] =
464 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
465
466 if (chan == 3)
467 /* RCP for fragcoord.w */
468 radeon_bld->inputs[soa_index] =
469 LLVMBuildFDiv(gallivm->builder,
470 lp_build_const_float(gallivm, 1.0f),
471 radeon_bld->inputs[soa_index],
472 "");
473 }
474 return;
475 }
476
477 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
478 LLVMValueRef face, is_face_positive;
479
480 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
481
482 is_face_positive = LLVMBuildFCmp(gallivm->builder,
483 LLVMRealUGT, face,
484 lp_build_const_float(gallivm, 0.0f),
485 "");
486
487 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
488 LLVMBuildSelect(gallivm->builder,
489 is_face_positive,
490 lp_build_const_float(gallivm, 1.0f),
491 lp_build_const_float(gallivm, 0.0f),
492 "");
493 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
494 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
495 lp_build_const_float(gallivm, 0.0f);
496 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
497 lp_build_const_float(gallivm, 1.0f);
498
499 return;
500 }
501
502 shader->input[input_index].param_offset = shader->nparam++;
503 attr_number = lp_build_const_int32(gallivm,
504 shader->input[input_index].param_offset);
505
506 switch (decl->Interp.Interpolate) {
507 case TGSI_INTERPOLATE_CONSTANT:
508 interp_param = 0;
509 break;
510 case TGSI_INTERPOLATE_LINEAR:
511 if (si_shader_ctx->shader->key.ps.interp_at_sample)
512 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_SAMPLE);
513 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
514 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTROID);
515 else
516 interp_param = LLVMGetParam(main_fn, SI_PARAM_LINEAR_CENTER);
517 break;
518 case TGSI_INTERPOLATE_COLOR:
519 if (si_shader_ctx->shader->key.ps.flatshade) {
520 interp_param = 0;
521 break;
522 }
523 /* fall through to perspective */
524 case TGSI_INTERPOLATE_PERSPECTIVE:
525 if (si_shader_ctx->shader->key.ps.interp_at_sample)
526 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_SAMPLE);
527 else if (decl->Interp.Location == TGSI_INTERPOLATE_LOC_CENTROID)
528 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTROID);
529 else
530 interp_param = LLVMGetParam(main_fn, SI_PARAM_PERSP_CENTER);
531 break;
532 default:
533 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
534 return;
535 }
536
537 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
538
539 /* XXX: Could there be more than TGSI_NUM_CHANNELS (4) ? */
540 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
541 si_shader_ctx->shader->key.ps.color_two_side) {
542 LLVMValueRef args[4];
543 LLVMValueRef face, is_face_positive;
544 LLVMValueRef back_attr_number =
545 lp_build_const_int32(gallivm,
546 shader->input[input_index].param_offset + 1);
547
548 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
549
550 is_face_positive = LLVMBuildFCmp(gallivm->builder,
551 LLVMRealUGT, face,
552 lp_build_const_float(gallivm, 0.0f),
553 "");
554
555 args[2] = params;
556 args[3] = interp_param;
557 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
558 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
559 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
560 LLVMValueRef front, back;
561
562 args[0] = llvm_chan;
563 args[1] = attr_number;
564 front = build_intrinsic(gallivm->builder, intr_name,
565 input_type, args, args[3] ? 4 : 3,
566 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
567
568 args[1] = back_attr_number;
569 back = build_intrinsic(gallivm->builder, intr_name,
570 input_type, args, args[3] ? 4 : 3,
571 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
572
573 radeon_bld->inputs[soa_index] =
574 LLVMBuildSelect(gallivm->builder,
575 is_face_positive,
576 front,
577 back,
578 "");
579 }
580
581 shader->nparam++;
582 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
583 LLVMValueRef args[4];
584
585 args[0] = uint->zero;
586 args[1] = attr_number;
587 args[2] = params;
588 args[3] = interp_param;
589 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
590 build_intrinsic(gallivm->builder, intr_name,
591 input_type, args, args[3] ? 4 : 3,
592 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
593 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
594 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
595 lp_build_const_float(gallivm, 0.0f);
596 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
597 lp_build_const_float(gallivm, 1.0f);
598 } else {
599 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
600 LLVMValueRef args[4];
601 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
602 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
603 args[0] = llvm_chan;
604 args[1] = attr_number;
605 args[2] = params;
606 args[3] = interp_param;
607 radeon_bld->inputs[soa_index] =
608 build_intrinsic(gallivm->builder, intr_name,
609 input_type, args, args[3] ? 4 : 3,
610 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
611 }
612 }
613 }
614
615 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
616 {
617 struct gallivm_state *gallivm = &radeon_bld->gallivm;
618 LLVMValueRef value = LLVMGetParam(radeon_bld->main_fn,
619 SI_PARAM_ANCILLARY);
620 value = LLVMBuildLShr(gallivm->builder, value,
621 lp_build_const_int32(gallivm, 8), "");
622 value = LLVMBuildAnd(gallivm->builder, value,
623 lp_build_const_int32(gallivm, 0xf), "");
624 return value;
625 }
626
627 static LLVMValueRef load_const(LLVMBuilderRef builder, LLVMValueRef resource,
628 LLVMValueRef offset, LLVMTypeRef return_type)
629 {
630 LLVMValueRef args[2] = {resource, offset};
631
632 return build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
633 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
634 }
635
636 static void declare_system_value(
637 struct radeon_llvm_context * radeon_bld,
638 unsigned index,
639 const struct tgsi_full_declaration *decl)
640 {
641 struct si_shader_context *si_shader_ctx =
642 si_shader_context(&radeon_bld->soa.bld_base);
643 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
644 struct gallivm_state *gallivm = &radeon_bld->gallivm;
645 LLVMValueRef value = 0;
646
647 switch (decl->Semantic.Name) {
648 case TGSI_SEMANTIC_INSTANCEID:
649 value = LLVMGetParam(radeon_bld->main_fn,
650 si_shader_ctx->param_instance_id);
651 break;
652
653 case TGSI_SEMANTIC_VERTEXID:
654 value = LLVMGetParam(radeon_bld->main_fn,
655 si_shader_ctx->param_vertex_id);
656 break;
657
658 case TGSI_SEMANTIC_SAMPLEID:
659 value = get_sample_id(radeon_bld);
660 break;
661
662 case TGSI_SEMANTIC_SAMPLEPOS:
663 {
664 LLVMBuilderRef builder = gallivm->builder;
665 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
666 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
667 LLVMValueRef resource = build_indexed_load(si_shader_ctx, desc, buf_index);
668
669 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
670 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, get_sample_id(radeon_bld), 8);
671 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
672
673 LLVMValueRef pos[4] = {
674 load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
675 load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
676 lp_build_const_float(gallivm, 0),
677 lp_build_const_float(gallivm, 0)
678 };
679 value = lp_build_gather_values(gallivm, pos, 4);
680 break;
681 }
682
683 default:
684 assert(!"unknown system value");
685 return;
686 }
687
688 radeon_bld->system_values[index] = value;
689 }
690
691 static LLVMValueRef fetch_constant(
692 struct lp_build_tgsi_context * bld_base,
693 const struct tgsi_full_src_register *reg,
694 enum tgsi_opcode_type type,
695 unsigned swizzle)
696 {
697 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
698 struct lp_build_context * base = &bld_base->base;
699 const struct tgsi_ind_register *ireg = &reg->Indirect;
700 unsigned buf, idx;
701
702 LLVMValueRef addr;
703 LLVMValueRef result;
704
705 if (swizzle == LP_CHAN_ALL) {
706 unsigned chan;
707 LLVMValueRef values[4];
708 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
709 values[chan] = fetch_constant(bld_base, reg, type, chan);
710
711 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
712 }
713
714 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
715 idx = reg->Register.Index * 4 + swizzle;
716
717 if (!reg->Register.Indirect)
718 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
719
720 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
721 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
722 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
723 addr = lp_build_add(&bld_base->uint_bld, addr,
724 lp_build_const_int32(base->gallivm, idx * 4));
725
726 result = load_const(base->gallivm->builder, si_shader_ctx->const_resource[buf],
727 addr, base->elem_type);
728
729 return bitcast(bld_base, type, result);
730 }
731
732 /* Initialize arguments for the shader export intrinsic */
733 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
734 LLVMValueRef *values,
735 unsigned target,
736 LLVMValueRef *args)
737 {
738 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
739 struct lp_build_context *uint =
740 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
741 struct lp_build_context *base = &bld_base->base;
742 unsigned compressed = 0;
743 unsigned chan;
744
745 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
746 int cbuf = target - V_008DFC_SQ_EXP_MRT;
747
748 if (cbuf >= 0 && cbuf < 8) {
749 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
750
751 if (compressed)
752 si_shader_ctx->shader->spi_shader_col_format |=
753 V_028714_SPI_SHADER_FP16_ABGR << (4 * cbuf);
754 else
755 si_shader_ctx->shader->spi_shader_col_format |=
756 V_028714_SPI_SHADER_32_ABGR << (4 * cbuf);
757
758 si_shader_ctx->shader->cb_shader_mask |= 0xf << (4 * cbuf);
759 }
760 }
761
762 if (compressed) {
763 /* Pixel shader needs to pack output values before export */
764 for (chan = 0; chan < 2; chan++ ) {
765 args[0] = values[2 * chan];
766 args[1] = values[2 * chan + 1];
767 args[chan + 5] =
768 build_intrinsic(base->gallivm->builder,
769 "llvm.SI.packf16",
770 LLVMInt32TypeInContext(base->gallivm->context),
771 args, 2,
772 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
773 args[chan + 7] = args[chan + 5] =
774 LLVMBuildBitCast(base->gallivm->builder,
775 args[chan + 5],
776 LLVMFloatTypeInContext(base->gallivm->context),
777 "");
778 }
779
780 /* Set COMPR flag */
781 args[4] = uint->one;
782 } else {
783 for (chan = 0; chan < 4; chan++ )
784 /* +5 because the first output value will be
785 * the 6th argument to the intrinsic. */
786 args[chan + 5] = values[chan];
787
788 /* Clear COMPR flag */
789 args[4] = uint->zero;
790 }
791
792 /* XXX: This controls which components of the output
793 * registers actually get exported. (e.g bit 0 means export
794 * X component, bit 1 means export Y component, etc.) I'm
795 * hard coding this to 0xf for now. In the future, we might
796 * want to do something else. */
797 args[0] = lp_build_const_int32(base->gallivm, 0xf);
798
799 /* Specify whether the EXEC mask represents the valid mask */
800 args[1] = uint->zero;
801
802 /* Specify whether this is the last export */
803 args[2] = uint->zero;
804
805 /* Specify the target we are exporting */
806 args[3] = lp_build_const_int32(base->gallivm, target);
807
808 /* XXX: We probably need to keep track of the output
809 * values, so we know what we are passing to the next
810 * stage. */
811 }
812
813 /* Load from output pointers and initialize arguments for the shader export intrinsic */
814 static void si_llvm_init_export_args_load(struct lp_build_tgsi_context *bld_base,
815 LLVMValueRef *out_ptr,
816 unsigned target,
817 LLVMValueRef *args)
818 {
819 struct gallivm_state *gallivm = bld_base->base.gallivm;
820 LLVMValueRef values[4];
821 int i;
822
823 for (i = 0; i < 4; i++)
824 values[i] = LLVMBuildLoad(gallivm->builder, out_ptr[i], "");
825
826 si_llvm_init_export_args(bld_base, values, target, args);
827 }
828
829 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
830 LLVMValueRef *out_ptr)
831 {
832 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
833 struct gallivm_state *gallivm = bld_base->base.gallivm;
834
835 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
836 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
837 SI_PARAM_ALPHA_REF);
838
839 LLVMValueRef alpha_pass =
840 lp_build_cmp(&bld_base->base,
841 si_shader_ctx->shader->key.ps.alpha_func,
842 LLVMBuildLoad(gallivm->builder, out_ptr[3], ""),
843 alpha_ref);
844 LLVMValueRef arg =
845 lp_build_select(&bld_base->base,
846 alpha_pass,
847 lp_build_const_float(gallivm, 1.0f),
848 lp_build_const_float(gallivm, -1.0f));
849
850 build_intrinsic(gallivm->builder,
851 "llvm.AMDGPU.kill",
852 LLVMVoidTypeInContext(gallivm->context),
853 &arg, 1, 0);
854 } else {
855 build_intrinsic(gallivm->builder,
856 "llvm.AMDGPU.kilp",
857 LLVMVoidTypeInContext(gallivm->context),
858 NULL, 0, 0);
859 }
860
861 si_shader_ctx->shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
862 }
863
864 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
865 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
866 {
867 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
868 struct si_shader *shader = si_shader_ctx->shader;
869 struct lp_build_context *base = &bld_base->base;
870 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
871 unsigned reg_index;
872 unsigned chan;
873 unsigned const_chan;
874 LLVMValueRef base_elt;
875 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
876 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
877 LLVMValueRef const_resource = build_indexed_load(si_shader_ctx, ptr, constbuf_index);
878
879 for (reg_index = 0; reg_index < 2; reg_index ++) {
880 LLVMValueRef *args = pos[2 + reg_index];
881
882 if (!(shader->key.vs.ucps_enabled & (1 << reg_index)))
883 continue;
884
885 shader->clip_dist_write |= 0xf << (4 * reg_index);
886
887 args[5] =
888 args[6] =
889 args[7] =
890 args[8] = lp_build_const_float(base->gallivm, 0.0f);
891
892 /* Compute dot products of position and user clip plane vectors */
893 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
894 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
895 args[1] = lp_build_const_int32(base->gallivm,
896 ((reg_index * 4 + chan) * 4 +
897 const_chan) * 4);
898 base_elt = load_const(base->gallivm->builder, const_resource,
899 args[1], base->elem_type);
900 args[5 + chan] =
901 lp_build_add(base, args[5 + chan],
902 lp_build_mul(base, base_elt,
903 out_elts[const_chan]));
904 }
905 }
906
907 args[0] = lp_build_const_int32(base->gallivm, 0xf);
908 args[1] = uint->zero;
909 args[2] = uint->zero;
910 args[3] = lp_build_const_int32(base->gallivm,
911 V_008DFC_SQ_EXP_POS + 2 + reg_index);
912 args[4] = uint->zero;
913 }
914 }
915
916 static void si_dump_streamout(struct pipe_stream_output_info *so)
917 {
918 unsigned i;
919
920 if (so->num_outputs)
921 fprintf(stderr, "STREAMOUT\n");
922
923 for (i = 0; i < so->num_outputs; i++) {
924 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
925 so->output[i].start_component;
926 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
927 i, so->output[i].output_buffer,
928 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
929 so->output[i].register_index,
930 mask & 1 ? "x" : "",
931 mask & 2 ? "y" : "",
932 mask & 4 ? "z" : "",
933 mask & 8 ? "w" : "");
934 }
935 }
936
937 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
938 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
939 * or v4i32 (num_channels=3,4). */
940 static void build_tbuffer_store(struct si_shader_context *shader,
941 LLVMValueRef rsrc,
942 LLVMValueRef vdata,
943 unsigned num_channels,
944 LLVMValueRef vaddr,
945 LLVMValueRef soffset,
946 unsigned inst_offset,
947 unsigned dfmt,
948 unsigned nfmt,
949 unsigned offen,
950 unsigned idxen,
951 unsigned glc,
952 unsigned slc,
953 unsigned tfe)
954 {
955 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
956 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
957 LLVMValueRef args[] = {
958 rsrc,
959 vdata,
960 LLVMConstInt(i32, num_channels, 0),
961 vaddr,
962 soffset,
963 LLVMConstInt(i32, inst_offset, 0),
964 LLVMConstInt(i32, dfmt, 0),
965 LLVMConstInt(i32, nfmt, 0),
966 LLVMConstInt(i32, offen, 0),
967 LLVMConstInt(i32, idxen, 0),
968 LLVMConstInt(i32, glc, 0),
969 LLVMConstInt(i32, slc, 0),
970 LLVMConstInt(i32, tfe, 0)
971 };
972
973 /* The instruction offset field has 12 bits */
974 assert(offen || inst_offset < (1 << 12));
975
976 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
977 unsigned func = CLAMP(num_channels, 1, 3) - 1;
978 const char *types[] = {"i32", "v2i32", "v4i32"};
979 char name[256];
980 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
981
982 lp_build_intrinsic(gallivm->builder, name,
983 LLVMVoidTypeInContext(gallivm->context),
984 args, Elements(args));
985 }
986
987 static void build_streamout_store(struct si_shader_context *shader,
988 LLVMValueRef rsrc,
989 LLVMValueRef vdata,
990 unsigned num_channels,
991 LLVMValueRef vaddr,
992 LLVMValueRef soffset,
993 unsigned inst_offset)
994 {
995 static unsigned dfmt[] = {
996 V_008F0C_BUF_DATA_FORMAT_32,
997 V_008F0C_BUF_DATA_FORMAT_32_32,
998 V_008F0C_BUF_DATA_FORMAT_32_32_32,
999 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1000 };
1001 assert(num_channels >= 1 && num_channels <= 4);
1002
1003 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
1004 inst_offset, dfmt[num_channels-1],
1005 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1006 }
1007
1008 /* On SI, the vertex shader is responsible for writing streamout data
1009 * to buffers. */
1010 static void si_llvm_emit_streamout(struct si_shader_context *shader,
1011 struct si_shader_output_values *outputs,
1012 unsigned noutput)
1013 {
1014 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1015 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1016 LLVMBuilderRef builder = gallivm->builder;
1017 int i, j;
1018 struct lp_build_if_state if_ctx;
1019
1020 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1021
1022 LLVMValueRef so_param =
1023 LLVMGetParam(shader->radeon_bld.main_fn,
1024 shader->param_streamout_config);
1025
1026 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1027 LLVMValueRef so_vtx_count =
1028 LLVMBuildAnd(builder,
1029 LLVMBuildLShr(builder, so_param,
1030 LLVMConstInt(i32, 16, 0), ""),
1031 LLVMConstInt(i32, 127, 0), "");
1032
1033 LLVMValueRef tid = build_intrinsic(builder, "llvm.SI.tid", i32,
1034 NULL, 0, LLVMReadNoneAttribute);
1035
1036 /* can_emit = tid < so_vtx_count; */
1037 LLVMValueRef can_emit =
1038 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1039
1040 /* Emit the streamout code conditionally. This actually avoids
1041 * out-of-bounds buffer access. The hw tells us via the SGPR
1042 * (so_vtx_count) which threads are allowed to emit streamout data. */
1043 lp_build_if(&if_ctx, gallivm, can_emit);
1044 {
1045 /* The buffer offset is computed as follows:
1046 * ByteOffset = streamout_offset[buffer_id]*4 +
1047 * (streamout_write_index + thread_id)*stride[buffer_id] +
1048 * attrib_offset
1049 */
1050
1051 LLVMValueRef so_write_index =
1052 LLVMGetParam(shader->radeon_bld.main_fn,
1053 shader->param_streamout_write_index);
1054
1055 /* Compute (streamout_write_index + thread_id). */
1056 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1057
1058 /* Compute the write offset for each enabled buffer. */
1059 LLVMValueRef so_write_offset[4] = {};
1060 for (i = 0; i < 4; i++) {
1061 if (!so->stride[i])
1062 continue;
1063
1064 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1065 shader->param_streamout_offset[i]);
1066 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1067
1068 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1069 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1070 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1071 }
1072
1073 /* Write streamout data. */
1074 for (i = 0; i < so->num_outputs; i++) {
1075 unsigned buf_idx = so->output[i].output_buffer;
1076 unsigned reg = so->output[i].register_index;
1077 unsigned start = so->output[i].start_component;
1078 unsigned num_comps = so->output[i].num_components;
1079 LLVMValueRef out[4];
1080
1081 assert(num_comps && num_comps <= 4);
1082 if (!num_comps || num_comps > 4)
1083 continue;
1084
1085 /* Load the output as int. */
1086 for (j = 0; j < num_comps; j++) {
1087 unsigned outidx = 0;
1088
1089 while (outidx < noutput && outputs[outidx].index != reg)
1090 outidx++;
1091
1092 if (outidx < noutput)
1093 out[j] = LLVMBuildBitCast(builder,
1094 outputs[outidx].values[start+j],
1095 i32, "");
1096 else
1097 out[j] = NULL;
1098 }
1099
1100 if (!out[0])
1101 continue;
1102
1103 /* Pack the output. */
1104 LLVMValueRef vdata = NULL;
1105
1106 switch (num_comps) {
1107 case 1: /* as i32 */
1108 vdata = out[0];
1109 break;
1110 case 2: /* as v2i32 */
1111 case 3: /* as v4i32 (aligned to 4) */
1112 case 4: /* as v4i32 */
1113 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1114 for (j = 0; j < num_comps; j++) {
1115 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1116 LLVMConstInt(i32, j, 0), "");
1117 }
1118 break;
1119 }
1120
1121 build_streamout_store(shader, shader->so_buffers[buf_idx],
1122 vdata, num_comps,
1123 so_write_offset[buf_idx],
1124 LLVMConstInt(i32, 0, 0),
1125 so->output[i].dst_offset*4);
1126 }
1127 }
1128 lp_build_endif(&if_ctx);
1129 }
1130
1131
1132 /* Generate export instructions for hardware VS shader stage */
1133 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1134 struct si_shader_output_values *outputs,
1135 unsigned noutput)
1136 {
1137 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1138 struct si_shader * shader = si_shader_ctx->shader;
1139 struct lp_build_context * base = &bld_base->base;
1140 struct lp_build_context * uint =
1141 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1142 LLVMValueRef args[9];
1143 LLVMValueRef pos_args[4][9] = { { 0 } };
1144 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL;
1145 unsigned semantic_name, semantic_index, semantic_usage;
1146 unsigned target;
1147 unsigned param_count = 0;
1148 unsigned pos_idx;
1149 int i;
1150
1151 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1152 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1153 }
1154
1155 for (i = 0; i < noutput; i++) {
1156 semantic_name = outputs[i].name;
1157 semantic_index = outputs[i].sid;
1158 semantic_usage = outputs[i].usage;
1159
1160 handle_semantic:
1161 /* Select the correct target */
1162 switch(semantic_name) {
1163 case TGSI_SEMANTIC_PSIZE:
1164 shader->vs_out_misc_write = true;
1165 shader->vs_out_point_size = true;
1166 psize_value = outputs[i].values[0];
1167 continue;
1168 case TGSI_SEMANTIC_EDGEFLAG:
1169 shader->vs_out_misc_write = true;
1170 shader->vs_out_edgeflag = true;
1171 edgeflag_value = outputs[i].values[0];
1172 continue;
1173 case TGSI_SEMANTIC_LAYER:
1174 shader->vs_out_misc_write = true;
1175 shader->vs_out_layer = true;
1176 layer_value = outputs[i].values[0];
1177 continue;
1178 case TGSI_SEMANTIC_POSITION:
1179 target = V_008DFC_SQ_EXP_POS;
1180 break;
1181 case TGSI_SEMANTIC_COLOR:
1182 case TGSI_SEMANTIC_BCOLOR:
1183 target = V_008DFC_SQ_EXP_PARAM + param_count;
1184 shader->output[i].param_offset = param_count;
1185 param_count++;
1186 break;
1187 case TGSI_SEMANTIC_CLIPDIST:
1188 if (!(si_shader_ctx->shader->key.vs.ucps_enabled &
1189 (1 << semantic_index)))
1190 continue;
1191 shader->clip_dist_write |=
1192 semantic_usage << (semantic_index << 2);
1193 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1194 break;
1195 case TGSI_SEMANTIC_CLIPVERTEX:
1196 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1197 continue;
1198 case TGSI_SEMANTIC_PRIMID:
1199 case TGSI_SEMANTIC_FOG:
1200 case TGSI_SEMANTIC_GENERIC:
1201 target = V_008DFC_SQ_EXP_PARAM + param_count;
1202 shader->output[i].param_offset = param_count;
1203 param_count++;
1204 break;
1205 default:
1206 target = 0;
1207 fprintf(stderr,
1208 "Warning: SI unhandled vs output type:%d\n",
1209 semantic_name);
1210 }
1211
1212 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1213
1214 if (target >= V_008DFC_SQ_EXP_POS &&
1215 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1216 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1217 args, sizeof(args));
1218 } else {
1219 lp_build_intrinsic(base->gallivm->builder,
1220 "llvm.SI.export",
1221 LLVMVoidTypeInContext(base->gallivm->context),
1222 args, 9);
1223 }
1224
1225 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1226 semantic_name = TGSI_SEMANTIC_GENERIC;
1227 goto handle_semantic;
1228 }
1229 }
1230
1231 /* We need to add the position output manually if it's missing. */
1232 if (!pos_args[0][0]) {
1233 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1234 pos_args[0][1] = uint->zero; /* EXEC mask */
1235 pos_args[0][2] = uint->zero; /* last export? */
1236 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1237 pos_args[0][4] = uint->zero; /* COMPR flag */
1238 pos_args[0][5] = base->zero; /* X */
1239 pos_args[0][6] = base->zero; /* Y */
1240 pos_args[0][7] = base->zero; /* Z */
1241 pos_args[0][8] = base->one; /* W */
1242 }
1243
1244 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1245 if (shader->vs_out_misc_write) {
1246 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1247 shader->vs_out_point_size |
1248 (shader->vs_out_edgeflag << 1) |
1249 (shader->vs_out_layer << 2));
1250 pos_args[1][1] = uint->zero; /* EXEC mask */
1251 pos_args[1][2] = uint->zero; /* last export? */
1252 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1253 pos_args[1][4] = uint->zero; /* COMPR flag */
1254 pos_args[1][5] = base->zero; /* X */
1255 pos_args[1][6] = base->zero; /* Y */
1256 pos_args[1][7] = base->zero; /* Z */
1257 pos_args[1][8] = base->zero; /* W */
1258
1259 if (shader->vs_out_point_size)
1260 pos_args[1][5] = psize_value;
1261
1262 if (shader->vs_out_edgeflag) {
1263 /* The output is a float, but the hw expects an integer
1264 * with the first bit containing the edge flag. */
1265 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1266 edgeflag_value,
1267 bld_base->uint_bld.elem_type, "");
1268 edgeflag_value = lp_build_min(&bld_base->int_bld,
1269 edgeflag_value,
1270 bld_base->int_bld.one);
1271
1272 /* The LLVM intrinsic expects a float. */
1273 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1274 edgeflag_value,
1275 base->elem_type, "");
1276 }
1277
1278 if (shader->vs_out_layer)
1279 pos_args[1][7] = layer_value;
1280 }
1281
1282 for (i = 0; i < 4; i++)
1283 if (pos_args[i][0])
1284 shader->nr_pos_exports++;
1285
1286 pos_idx = 0;
1287 for (i = 0; i < 4; i++) {
1288 if (!pos_args[i][0])
1289 continue;
1290
1291 /* Specify the target we are exporting */
1292 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1293
1294 if (pos_idx == shader->nr_pos_exports)
1295 /* Specify that this is the last export */
1296 pos_args[i][2] = uint->one;
1297
1298 lp_build_intrinsic(base->gallivm->builder,
1299 "llvm.SI.export",
1300 LLVMVoidTypeInContext(base->gallivm->context),
1301 pos_args[i], 9);
1302 }
1303 }
1304
1305 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1306 {
1307 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1308 struct gallivm_state *gallivm = bld_base->base.gallivm;
1309 struct si_shader *es = si_shader_ctx->shader;
1310 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1311 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1312 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1313 SI_PARAM_ES2GS_OFFSET);
1314 LLVMValueRef t_list_ptr;
1315 LLVMValueRef t_list;
1316 unsigned chan;
1317 int i;
1318
1319 while (!tgsi_parse_end_of_tokens(parse)) {
1320 struct tgsi_full_declaration *d =
1321 &parse->FullToken.FullDeclaration;
1322
1323 tgsi_parse_token(parse);
1324
1325 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1326 continue;
1327
1328 si_store_shader_io_attribs(es, d);
1329 }
1330
1331 /* Load the ESGS ring resource descriptor */
1332 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1333 SI_PARAM_RW_BUFFERS);
1334 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
1335 lp_build_const_int32(gallivm, SI_RING_ESGS));
1336
1337 for (i = 0; i < es->noutput; i++) {
1338 LLVMValueRef *out_ptr =
1339 si_shader_ctx->radeon_bld.soa.outputs[es->output[i].index];
1340 int param_index = get_param_index(es->output[i].name,
1341 es->output[i].sid,
1342 es->key.vs.gs_used_inputs);
1343
1344 if (param_index < 0)
1345 continue;
1346
1347 for (chan = 0; chan < 4; chan++) {
1348 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1349 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1350
1351 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
1352 LLVMGetUndef(i32), soffset,
1353 (4 * param_index + chan) * 4,
1354 V_008F0C_BUF_DATA_FORMAT_32,
1355 V_008F0C_BUF_NUM_FORMAT_UINT,
1356 0, 0, 1, 1, 0);
1357 }
1358 }
1359 }
1360
1361 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1362 {
1363 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1364 struct gallivm_state *gallivm = bld_base->base.gallivm;
1365 LLVMValueRef args[2];
1366
1367 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
1368 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
1369 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
1370 LLVMVoidTypeInContext(gallivm->context), args, 2,
1371 LLVMNoUnwindAttribute);
1372 }
1373
1374 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
1375 {
1376 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1377 struct gallivm_state *gallivm = bld_base->base.gallivm;
1378 struct si_shader *shader = si_shader_ctx->shader;
1379 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1380 struct si_shader_output_values *outputs = NULL;
1381 unsigned noutput = 0;
1382 int i;
1383
1384 while (!tgsi_parse_end_of_tokens(parse)) {
1385 struct tgsi_full_declaration *d =
1386 &parse->FullToken.FullDeclaration;
1387 unsigned index;
1388
1389 tgsi_parse_token(parse);
1390
1391 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1392 continue;
1393
1394 i = si_store_shader_io_attribs(shader, d);
1395 if (i < 0)
1396 continue;
1397
1398 outputs = REALLOC(outputs, noutput * sizeof(outputs[0]),
1399 (noutput + 1) * sizeof(outputs[0]));
1400 for (index = d->Range.First; index <= d->Range.Last; index++) {
1401 outputs[noutput].index = index;
1402 outputs[noutput].name = d->Semantic.Name;
1403 outputs[noutput].sid = d->Semantic.Index;
1404 outputs[noutput].usage = d->Declaration.UsageMask;
1405
1406 for (i = 0; i < 4; i++)
1407 outputs[noutput].values[i] =
1408 LLVMBuildLoad(gallivm->builder,
1409 si_shader_ctx->radeon_bld.soa.outputs[index][i],
1410 "");
1411 }
1412 noutput++;
1413 }
1414
1415 si_llvm_export_vs(bld_base, outputs, noutput);
1416 FREE(outputs);
1417 }
1418
1419 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
1420 {
1421 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1422 struct si_shader * shader = si_shader_ctx->shader;
1423 struct lp_build_context * base = &bld_base->base;
1424 struct lp_build_context * uint =
1425 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1426 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
1427 LLVMValueRef args[9];
1428 LLVMValueRef last_args[9] = { 0 };
1429 unsigned semantic_name;
1430 int depth_index = -1, stencil_index = -1, samplemask_index = -1;
1431 int i;
1432
1433 while (!tgsi_parse_end_of_tokens(parse)) {
1434 struct tgsi_full_declaration *d =
1435 &parse->FullToken.FullDeclaration;
1436 unsigned target;
1437 unsigned index;
1438
1439 tgsi_parse_token(parse);
1440
1441 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_PROPERTY &&
1442 parse->FullToken.FullProperty.Property.PropertyName ==
1443 TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS)
1444 shader->fs_write_all = TRUE;
1445
1446 if (parse->FullToken.Token.Type != TGSI_TOKEN_TYPE_DECLARATION)
1447 continue;
1448
1449 i = si_store_shader_io_attribs(shader, d);
1450 if (i < 0)
1451 continue;
1452
1453 semantic_name = d->Semantic.Name;
1454 for (index = d->Range.First; index <= d->Range.Last; index++) {
1455 /* Select the correct target */
1456 switch(semantic_name) {
1457 case TGSI_SEMANTIC_POSITION:
1458 depth_index = index;
1459 continue;
1460 case TGSI_SEMANTIC_STENCIL:
1461 stencil_index = index;
1462 continue;
1463 case TGSI_SEMANTIC_SAMPLEMASK:
1464 samplemask_index = index;
1465 continue;
1466 case TGSI_SEMANTIC_COLOR:
1467 target = V_008DFC_SQ_EXP_MRT + d->Semantic.Index;
1468 if (si_shader_ctx->shader->key.ps.alpha_to_one)
1469 LLVMBuildStore(bld_base->base.gallivm->builder,
1470 bld_base->base.one,
1471 si_shader_ctx->radeon_bld.soa.outputs[index][3]);
1472
1473 if (d->Semantic.Index == 0 &&
1474 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
1475 si_alpha_test(bld_base,
1476 si_shader_ctx->radeon_bld.soa.outputs[index]);
1477 break;
1478 default:
1479 target = 0;
1480 fprintf(stderr,
1481 "Warning: SI unhandled fs output type:%d\n",
1482 semantic_name);
1483 }
1484
1485 si_llvm_init_export_args_load(bld_base,
1486 si_shader_ctx->radeon_bld.soa.outputs[index],
1487 target, args);
1488
1489 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1490 /* If there is an export instruction waiting to be emitted, do so now. */
1491 if (last_args[0]) {
1492 lp_build_intrinsic(base->gallivm->builder,
1493 "llvm.SI.export",
1494 LLVMVoidTypeInContext(base->gallivm->context),
1495 last_args, 9);
1496 }
1497
1498 /* This instruction will be emitted at the end of the shader. */
1499 memcpy(last_args, args, sizeof(args));
1500
1501 /* Handle FS_COLOR0_WRITES_ALL_CBUFS. */
1502 if (shader->fs_write_all && shader->output[i].sid == 0 &&
1503 si_shader_ctx->shader->key.ps.nr_cbufs > 1) {
1504 for (int c = 1; c < si_shader_ctx->shader->key.ps.nr_cbufs; c++) {
1505 si_llvm_init_export_args_load(bld_base,
1506 si_shader_ctx->radeon_bld.soa.outputs[index],
1507 V_008DFC_SQ_EXP_MRT + c, args);
1508 lp_build_intrinsic(base->gallivm->builder,
1509 "llvm.SI.export",
1510 LLVMVoidTypeInContext(base->gallivm->context),
1511 args, 9);
1512 }
1513 }
1514 } else {
1515 lp_build_intrinsic(base->gallivm->builder,
1516 "llvm.SI.export",
1517 LLVMVoidTypeInContext(base->gallivm->context),
1518 args, 9);
1519 }
1520 }
1521 }
1522
1523 if (depth_index >= 0 || stencil_index >= 0 || samplemask_index >= 0) {
1524 LLVMValueRef out_ptr;
1525 unsigned mask = 0;
1526
1527 /* Specify the target we are exporting */
1528 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
1529
1530 args[5] = base->zero; /* R, depth */
1531 args[6] = base->zero; /* G, stencil test value[0:7], stencil op value[8:15] */
1532 args[7] = base->zero; /* B, sample mask */
1533 args[8] = base->zero; /* A, alpha to mask */
1534
1535 if (depth_index >= 0) {
1536 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[depth_index][2];
1537 args[5] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1538 mask |= 0x1;
1539 si_shader_ctx->shader->db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1540 }
1541
1542 if (stencil_index >= 0) {
1543 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[stencil_index][1];
1544 args[6] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1545 /* Only setting the stencil component bit (0x2) here
1546 * breaks some stencil piglit tests
1547 */
1548 mask |= 0x3;
1549 si_shader_ctx->shader->db_shader_control |=
1550 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(1);
1551 }
1552
1553 if (samplemask_index >= 0) {
1554 out_ptr = si_shader_ctx->radeon_bld.soa.outputs[samplemask_index][0];
1555 args[7] = LLVMBuildLoad(base->gallivm->builder, out_ptr, "");
1556 mask |= 0xf; /* Set all components. */
1557 si_shader_ctx->shader->db_shader_control |= S_02880C_MASK_EXPORT_ENABLE(1);
1558 }
1559
1560 if (samplemask_index >= 0)
1561 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
1562 else if (stencil_index >= 0)
1563 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
1564 else
1565 si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
1566
1567 /* Specify which components to enable */
1568 args[0] = lp_build_const_int32(base->gallivm, mask);
1569
1570 args[1] =
1571 args[2] =
1572 args[4] = uint->zero;
1573
1574 if (last_args[0])
1575 lp_build_intrinsic(base->gallivm->builder,
1576 "llvm.SI.export",
1577 LLVMVoidTypeInContext(base->gallivm->context),
1578 args, 9);
1579 else
1580 memcpy(last_args, args, sizeof(args));
1581 }
1582
1583 if (!last_args[0]) {
1584 /* Specify which components to enable */
1585 last_args[0] = lp_build_const_int32(base->gallivm, 0x0);
1586
1587 /* Specify the target we are exporting */
1588 last_args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRT);
1589
1590 /* Set COMPR flag to zero to export data as 32-bit */
1591 last_args[4] = uint->zero;
1592
1593 /* dummy bits */
1594 last_args[5]= uint->zero;
1595 last_args[6]= uint->zero;
1596 last_args[7]= uint->zero;
1597 last_args[8]= uint->zero;
1598 }
1599
1600 /* Specify whether the EXEC mask represents the valid mask */
1601 last_args[1] = uint->one;
1602
1603 /* Specify that this is the last export */
1604 last_args[2] = lp_build_const_int32(base->gallivm, 1);
1605
1606 lp_build_intrinsic(base->gallivm->builder,
1607 "llvm.SI.export",
1608 LLVMVoidTypeInContext(base->gallivm->context),
1609 last_args, 9);
1610 }
1611
1612 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
1613 struct lp_build_tgsi_context * bld_base,
1614 struct lp_build_emit_data * emit_data);
1615
1616 static bool tgsi_is_shadow_sampler(unsigned target)
1617 {
1618 return target == TGSI_TEXTURE_SHADOW1D ||
1619 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1620 target == TGSI_TEXTURE_SHADOW2D ||
1621 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1622 target == TGSI_TEXTURE_SHADOWCUBE ||
1623 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
1624 target == TGSI_TEXTURE_SHADOWRECT;
1625 }
1626
1627 static const struct lp_build_tgsi_action tex_action;
1628
1629 static void tex_fetch_args(
1630 struct lp_build_tgsi_context * bld_base,
1631 struct lp_build_emit_data * emit_data)
1632 {
1633 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1634 struct gallivm_state *gallivm = bld_base->base.gallivm;
1635 const struct tgsi_full_instruction * inst = emit_data->inst;
1636 unsigned opcode = inst->Instruction.Opcode;
1637 unsigned target = inst->Texture.Texture;
1638 LLVMValueRef coords[4];
1639 LLVMValueRef address[16];
1640 int ref_pos;
1641 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
1642 unsigned count = 0;
1643 unsigned chan;
1644 unsigned sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1645 unsigned sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
1646 bool has_offset = HAVE_LLVM >= 0x0305 ? inst->Texture.NumOffsets > 0 : false;
1647
1648 if (target == TGSI_TEXTURE_BUFFER) {
1649 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
1650 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
1651 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
1652 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
1653
1654 /* Bitcast and truncate v8i32 to v16i8. */
1655 LLVMValueRef res = si_shader_ctx->resources[sampler_index];
1656 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
1657 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.zero, "");
1658 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
1659
1660 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
1661 emit_data->args[0] = res;
1662 emit_data->args[1] = bld_base->uint_bld.zero;
1663 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
1664 emit_data->arg_count = 3;
1665 return;
1666 }
1667
1668 /* Fetch and project texture coordinates */
1669 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
1670 for (chan = 0; chan < 3; chan++ ) {
1671 coords[chan] = lp_build_emit_fetch(bld_base,
1672 emit_data->inst, 0,
1673 chan);
1674 if (opcode == TGSI_OPCODE_TXP)
1675 coords[chan] = lp_build_emit_llvm_binary(bld_base,
1676 TGSI_OPCODE_DIV,
1677 coords[chan],
1678 coords[3]);
1679 }
1680
1681 if (opcode == TGSI_OPCODE_TXP)
1682 coords[3] = bld_base->base.one;
1683
1684 /* Pack offsets. */
1685 if (has_offset && opcode != TGSI_OPCODE_TXF) {
1686 /* The offsets are six-bit signed integers packed like this:
1687 * X=[5:0], Y=[13:8], and Z=[21:16].
1688 */
1689 LLVMValueRef offset[3], pack;
1690
1691 assert(inst->Texture.NumOffsets == 1);
1692
1693 for (chan = 0; chan < 3; chan++) {
1694 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
1695 emit_data->inst, 0, chan);
1696 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
1697 lp_build_const_int32(gallivm, 0x3f), "");
1698 if (chan)
1699 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
1700 lp_build_const_int32(gallivm, chan*8), "");
1701 }
1702
1703 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
1704 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
1705 address[count++] = pack;
1706 }
1707
1708 /* Pack LOD bias value */
1709 if (opcode == TGSI_OPCODE_TXB)
1710 address[count++] = coords[3];
1711 if (opcode == TGSI_OPCODE_TXB2)
1712 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1713
1714 /* Pack depth comparison value */
1715 if (tgsi_is_shadow_sampler(target) && opcode != TGSI_OPCODE_LODQ) {
1716 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1717 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1718 } else {
1719 assert(ref_pos >= 0);
1720 address[count++] = coords[ref_pos];
1721 }
1722 }
1723
1724 if (target == TGSI_TEXTURE_CUBE ||
1725 target == TGSI_TEXTURE_CUBE_ARRAY ||
1726 target == TGSI_TEXTURE_SHADOWCUBE ||
1727 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1728 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords);
1729
1730 /* Pack user derivatives */
1731 if (opcode == TGSI_OPCODE_TXD) {
1732 int num_deriv_channels, param;
1733
1734 switch (target) {
1735 case TGSI_TEXTURE_3D:
1736 num_deriv_channels = 3;
1737 break;
1738 case TGSI_TEXTURE_2D:
1739 case TGSI_TEXTURE_SHADOW2D:
1740 case TGSI_TEXTURE_RECT:
1741 case TGSI_TEXTURE_SHADOWRECT:
1742 case TGSI_TEXTURE_2D_ARRAY:
1743 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1744 case TGSI_TEXTURE_CUBE:
1745 case TGSI_TEXTURE_SHADOWCUBE:
1746 case TGSI_TEXTURE_CUBE_ARRAY:
1747 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1748 num_deriv_channels = 2;
1749 break;
1750 case TGSI_TEXTURE_1D:
1751 case TGSI_TEXTURE_SHADOW1D:
1752 case TGSI_TEXTURE_1D_ARRAY:
1753 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1754 num_deriv_channels = 1;
1755 break;
1756 default:
1757 assert(0); /* no other targets are valid here */
1758 }
1759
1760 for (param = 1; param <= 2; param++)
1761 for (chan = 0; chan < num_deriv_channels; chan++)
1762 address[count++] = lp_build_emit_fetch(bld_base, inst, param, chan);
1763 }
1764
1765 /* Pack texture coordinates */
1766 address[count++] = coords[0];
1767 if (num_coords > 1)
1768 address[count++] = coords[1];
1769 if (num_coords > 2)
1770 address[count++] = coords[2];
1771
1772 /* Pack LOD or sample index */
1773 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
1774 address[count++] = coords[3];
1775 else if (opcode == TGSI_OPCODE_TXL2)
1776 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
1777
1778 if (count > 16) {
1779 assert(!"Cannot handle more than 16 texture address parameters");
1780 count = 16;
1781 }
1782
1783 for (chan = 0; chan < count; chan++ ) {
1784 address[chan] = LLVMBuildBitCast(gallivm->builder,
1785 address[chan],
1786 LLVMInt32TypeInContext(gallivm->context),
1787 "");
1788 }
1789
1790 /* Adjust the sample index according to FMASK.
1791 *
1792 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
1793 * which is the identity mapping. Each nibble says which physical sample
1794 * should be fetched to get that sample.
1795 *
1796 * For example, 0x11111100 means there are only 2 samples stored and
1797 * the second sample covers 3/4 of the pixel. When reading samples 0
1798 * and 1, return physical sample 0 (determined by the first two 0s
1799 * in FMASK), otherwise return physical sample 1.
1800 *
1801 * The sample index should be adjusted as follows:
1802 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
1803 */
1804 if (target == TGSI_TEXTURE_2D_MSAA ||
1805 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1806 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1807 struct lp_build_emit_data txf_emit_data = *emit_data;
1808 LLVMValueRef txf_address[4];
1809 unsigned txf_count = count;
1810 struct tgsi_full_instruction inst = {};
1811
1812 memcpy(txf_address, address, sizeof(txf_address));
1813
1814 if (target == TGSI_TEXTURE_2D_MSAA) {
1815 txf_address[2] = bld_base->uint_bld.zero;
1816 }
1817 txf_address[3] = bld_base->uint_bld.zero;
1818
1819 /* Pad to a power-of-two size. */
1820 while (txf_count < util_next_power_of_two(txf_count))
1821 txf_address[txf_count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1822
1823 /* Read FMASK using TXF. */
1824 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
1825 inst.Texture.Texture = target == TGSI_TEXTURE_2D_MSAA ? TGSI_TEXTURE_2D : TGSI_TEXTURE_2D_ARRAY;
1826 txf_emit_data.inst = &inst;
1827 txf_emit_data.chan = 0;
1828 txf_emit_data.dst_type = LLVMVectorType(
1829 LLVMInt32TypeInContext(gallivm->context), 4);
1830 txf_emit_data.args[0] = lp_build_gather_values(gallivm, txf_address, txf_count);
1831 txf_emit_data.args[1] = si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index];
1832 txf_emit_data.args[2] = lp_build_const_int32(gallivm, inst.Texture.Texture);
1833 txf_emit_data.arg_count = 3;
1834
1835 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
1836
1837 /* Initialize some constants. */
1838 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
1839 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
1840
1841 /* Apply the formula. */
1842 LLVMValueRef fmask =
1843 LLVMBuildExtractElement(gallivm->builder,
1844 txf_emit_data.output[0],
1845 uint_bld->zero, "");
1846
1847 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
1848
1849 LLVMValueRef sample_index4 =
1850 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
1851
1852 LLVMValueRef shifted_fmask =
1853 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
1854
1855 LLVMValueRef final_sample =
1856 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
1857
1858 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
1859 * resource descriptor is 0 (invalid),
1860 */
1861 LLVMValueRef fmask_desc =
1862 LLVMBuildBitCast(gallivm->builder,
1863 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + sampler_index],
1864 LLVMVectorType(uint_bld->elem_type, 8), "");
1865
1866 LLVMValueRef fmask_word1 =
1867 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
1868 uint_bld->one, "");
1869
1870 LLVMValueRef word1_is_nonzero =
1871 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1872 fmask_word1, uint_bld->zero, "");
1873
1874 /* Replace the MSAA sample index. */
1875 address[sample_chan] =
1876 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
1877 final_sample, address[sample_chan], "");
1878 }
1879
1880 /* Resource */
1881 emit_data->args[1] = si_shader_ctx->resources[sampler_index];
1882
1883 if (opcode == TGSI_OPCODE_TXF) {
1884 /* add tex offsets */
1885 if (inst->Texture.NumOffsets) {
1886 struct lp_build_context *uint_bld = &bld_base->uint_bld;
1887 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
1888 const struct tgsi_texture_offset * off = inst->TexOffsets;
1889
1890 assert(inst->Texture.NumOffsets == 1);
1891
1892 switch (target) {
1893 case TGSI_TEXTURE_3D:
1894 address[2] = lp_build_add(uint_bld, address[2],
1895 bld->immediates[off->Index][off->SwizzleZ]);
1896 /* fall through */
1897 case TGSI_TEXTURE_2D:
1898 case TGSI_TEXTURE_SHADOW2D:
1899 case TGSI_TEXTURE_RECT:
1900 case TGSI_TEXTURE_SHADOWRECT:
1901 case TGSI_TEXTURE_2D_ARRAY:
1902 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1903 address[1] =
1904 lp_build_add(uint_bld, address[1],
1905 bld->immediates[off->Index][off->SwizzleY]);
1906 /* fall through */
1907 case TGSI_TEXTURE_1D:
1908 case TGSI_TEXTURE_SHADOW1D:
1909 case TGSI_TEXTURE_1D_ARRAY:
1910 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1911 address[0] =
1912 lp_build_add(uint_bld, address[0],
1913 bld->immediates[off->Index][off->SwizzleX]);
1914 break;
1915 /* texture offsets do not apply to other texture targets */
1916 }
1917 }
1918
1919 emit_data->args[2] = lp_build_const_int32(gallivm, target);
1920 emit_data->arg_count = 3;
1921
1922 emit_data->dst_type = LLVMVectorType(
1923 LLVMInt32TypeInContext(gallivm->context),
1924 4);
1925 } else if (opcode == TGSI_OPCODE_TG4 ||
1926 opcode == TGSI_OPCODE_LODQ ||
1927 has_offset) {
1928 unsigned is_array = target == TGSI_TEXTURE_1D_ARRAY ||
1929 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
1930 target == TGSI_TEXTURE_2D_ARRAY ||
1931 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
1932 target == TGSI_TEXTURE_CUBE_ARRAY ||
1933 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY;
1934 unsigned is_rect = target == TGSI_TEXTURE_RECT;
1935 unsigned dmask = 0xf;
1936
1937 if (opcode == TGSI_OPCODE_TG4) {
1938 unsigned gather_comp = 0;
1939
1940 /* DMASK was repurposed for GATHER4. 4 components are always
1941 * returned and DMASK works like a swizzle - it selects
1942 * the component to fetch. The only valid DMASK values are
1943 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1944 * (red,red,red,red) etc.) The ISA document doesn't mention
1945 * this.
1946 */
1947
1948 /* Get the component index from src1.x for Gather4. */
1949 if (!tgsi_is_shadow_sampler(target)) {
1950 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
1951 LLVMValueRef comp_imm;
1952 struct tgsi_src_register src1 = inst->Src[1].Register;
1953
1954 assert(src1.File == TGSI_FILE_IMMEDIATE);
1955
1956 comp_imm = imms[src1.Index][src1.SwizzleX];
1957 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1958 gather_comp = CLAMP(gather_comp, 0, 3);
1959 }
1960
1961 dmask = 1 << gather_comp;
1962 }
1963
1964 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1965 emit_data->args[3] = lp_build_const_int32(gallivm, dmask);
1966 emit_data->args[4] = lp_build_const_int32(gallivm, is_rect); /* unorm */
1967 emit_data->args[5] = lp_build_const_int32(gallivm, 0); /* r128 */
1968 emit_data->args[6] = lp_build_const_int32(gallivm, is_array); /* da */
1969 emit_data->args[7] = lp_build_const_int32(gallivm, 0); /* glc */
1970 emit_data->args[8] = lp_build_const_int32(gallivm, 0); /* slc */
1971 emit_data->args[9] = lp_build_const_int32(gallivm, 0); /* tfe */
1972 emit_data->args[10] = lp_build_const_int32(gallivm, 0); /* lwe */
1973
1974 emit_data->arg_count = 11;
1975
1976 emit_data->dst_type = LLVMVectorType(
1977 LLVMFloatTypeInContext(gallivm->context),
1978 4);
1979 } else {
1980 emit_data->args[2] = si_shader_ctx->samplers[sampler_index];
1981 emit_data->args[3] = lp_build_const_int32(gallivm, target);
1982 emit_data->arg_count = 4;
1983
1984 emit_data->dst_type = LLVMVectorType(
1985 LLVMFloatTypeInContext(gallivm->context),
1986 4);
1987 }
1988
1989 /* The fetch opcode has been converted to a 2D array fetch.
1990 * This simplifies the LLVM backend. */
1991 if (target == TGSI_TEXTURE_CUBE_ARRAY)
1992 target = TGSI_TEXTURE_2D_ARRAY;
1993 else if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
1994 target = TGSI_TEXTURE_SHADOW2D_ARRAY;
1995
1996 /* Pad to power of two vector */
1997 while (count < util_next_power_of_two(count))
1998 address[count++] = LLVMGetUndef(LLVMInt32TypeInContext(gallivm->context));
1999
2000 emit_data->args[0] = lp_build_gather_values(gallivm, address, count);
2001 }
2002
2003 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2004 struct lp_build_tgsi_context * bld_base,
2005 struct lp_build_emit_data * emit_data)
2006 {
2007 struct lp_build_context * base = &bld_base->base;
2008 unsigned opcode = emit_data->inst->Instruction.Opcode;
2009 unsigned target = emit_data->inst->Texture.Texture;
2010 char intr_name[127];
2011 bool has_offset = HAVE_LLVM >= 0x0305 ?
2012 emit_data->inst->Texture.NumOffsets > 0 : false;
2013
2014 if (target == TGSI_TEXTURE_BUFFER) {
2015 emit_data->output[emit_data->chan] = build_intrinsic(
2016 base->gallivm->builder,
2017 "llvm.SI.vs.load.input", emit_data->dst_type,
2018 emit_data->args, emit_data->arg_count,
2019 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2020 return;
2021 }
2022
2023 if (opcode == TGSI_OPCODE_TG4 ||
2024 opcode == TGSI_OPCODE_LODQ ||
2025 (opcode != TGSI_OPCODE_TXF && has_offset)) {
2026 bool is_shadow = tgsi_is_shadow_sampler(target);
2027 const char *name = "llvm.SI.image.sample";
2028 const char *infix = "";
2029
2030 switch (opcode) {
2031 case TGSI_OPCODE_TEX:
2032 case TGSI_OPCODE_TEX2:
2033 case TGSI_OPCODE_TXP:
2034 break;
2035 case TGSI_OPCODE_TXB:
2036 case TGSI_OPCODE_TXB2:
2037 infix = ".b";
2038 break;
2039 case TGSI_OPCODE_TXL:
2040 case TGSI_OPCODE_TXL2:
2041 infix = ".l";
2042 break;
2043 case TGSI_OPCODE_TXD:
2044 infix = ".d";
2045 break;
2046 case TGSI_OPCODE_TG4:
2047 name = "llvm.SI.gather4";
2048 break;
2049 case TGSI_OPCODE_LODQ:
2050 name = "llvm.SI.getlod";
2051 is_shadow = false;
2052 has_offset = false;
2053 break;
2054 default:
2055 assert(0);
2056 return;
2057 }
2058
2059 /* Add the type and suffixes .c, .o if needed. */
2060 sprintf(intr_name, "%s%s%s%s.v%ui32", name,
2061 is_shadow ? ".c" : "", infix, has_offset ? ".o" : "",
2062 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2063
2064 emit_data->output[emit_data->chan] = build_intrinsic(
2065 base->gallivm->builder, intr_name, emit_data->dst_type,
2066 emit_data->args, emit_data->arg_count,
2067 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2068 } else {
2069 LLVMTypeRef i8, v16i8, v32i8;
2070 const char *name;
2071
2072 switch (opcode) {
2073 case TGSI_OPCODE_TEX:
2074 case TGSI_OPCODE_TEX2:
2075 case TGSI_OPCODE_TXP:
2076 name = "llvm.SI.sample";
2077 break;
2078 case TGSI_OPCODE_TXB:
2079 case TGSI_OPCODE_TXB2:
2080 name = "llvm.SI.sampleb";
2081 break;
2082 case TGSI_OPCODE_TXD:
2083 name = "llvm.SI.sampled";
2084 break;
2085 case TGSI_OPCODE_TXF:
2086 name = "llvm.SI.imageload";
2087 break;
2088 case TGSI_OPCODE_TXL:
2089 case TGSI_OPCODE_TXL2:
2090 name = "llvm.SI.samplel";
2091 break;
2092 default:
2093 assert(0);
2094 return;
2095 }
2096
2097 i8 = LLVMInt8TypeInContext(base->gallivm->context);
2098 v16i8 = LLVMVectorType(i8, 16);
2099 v32i8 = LLVMVectorType(i8, 32);
2100
2101 emit_data->args[1] = LLVMBuildBitCast(base->gallivm->builder,
2102 emit_data->args[1], v32i8, "");
2103 if (opcode != TGSI_OPCODE_TXF) {
2104 emit_data->args[2] = LLVMBuildBitCast(base->gallivm->builder,
2105 emit_data->args[2], v16i8, "");
2106 }
2107
2108 sprintf(intr_name, "%s.v%ui32", name,
2109 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2110
2111 emit_data->output[emit_data->chan] = build_intrinsic(
2112 base->gallivm->builder, intr_name, emit_data->dst_type,
2113 emit_data->args, emit_data->arg_count,
2114 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2115 }
2116 }
2117
2118 static void txq_fetch_args(
2119 struct lp_build_tgsi_context * bld_base,
2120 struct lp_build_emit_data * emit_data)
2121 {
2122 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2123 const struct tgsi_full_instruction *inst = emit_data->inst;
2124 struct gallivm_state *gallivm = bld_base->base.gallivm;
2125 unsigned target = inst->Texture.Texture;
2126
2127 if (target == TGSI_TEXTURE_BUFFER) {
2128 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2129 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2130
2131 /* Read the size from the buffer descriptor directly. */
2132 LLVMValueRef size = si_shader_ctx->resources[inst->Src[1].Register.Index];
2133 size = LLVMBuildBitCast(gallivm->builder, size, v8i32, "");
2134 size = LLVMBuildExtractElement(gallivm->builder, size,
2135 lp_build_const_int32(gallivm, 2), "");
2136 emit_data->args[0] = size;
2137 return;
2138 }
2139
2140 /* Mip level */
2141 emit_data->args[0] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2142
2143 /* Resource */
2144 emit_data->args[1] = si_shader_ctx->resources[inst->Src[1].Register.Index];
2145
2146 /* Texture target */
2147 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2148 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2149 target = TGSI_TEXTURE_2D_ARRAY;
2150
2151 emit_data->args[2] = lp_build_const_int32(bld_base->base.gallivm,
2152 target);
2153
2154 emit_data->arg_count = 3;
2155
2156 emit_data->dst_type = LLVMVectorType(
2157 LLVMInt32TypeInContext(bld_base->base.gallivm->context),
2158 4);
2159 }
2160
2161 static void build_txq_intrinsic(const struct lp_build_tgsi_action * action,
2162 struct lp_build_tgsi_context * bld_base,
2163 struct lp_build_emit_data * emit_data)
2164 {
2165 unsigned target = emit_data->inst->Texture.Texture;
2166
2167 if (target == TGSI_TEXTURE_BUFFER) {
2168 /* Just return the buffer size. */
2169 emit_data->output[emit_data->chan] = emit_data->args[0];
2170 return;
2171 }
2172
2173 build_tgsi_intrinsic_nomem(action, bld_base, emit_data);
2174
2175 /* Divide the number of layers by 6 to get the number of cubes. */
2176 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
2177 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2178 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2179 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2180 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2181
2182 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2183 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2184 z = LLVMBuildSDiv(builder, z, six, "");
2185
2186 emit_data->output[emit_data->chan] =
2187 LLVMBuildInsertElement(builder, v4, z, two, "");
2188 }
2189 }
2190
2191 static void si_llvm_emit_ddxy(
2192 const struct lp_build_tgsi_action * action,
2193 struct lp_build_tgsi_context * bld_base,
2194 struct lp_build_emit_data * emit_data)
2195 {
2196 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2197 struct gallivm_state *gallivm = bld_base->base.gallivm;
2198 struct lp_build_context * base = &bld_base->base;
2199 const struct tgsi_full_instruction *inst = emit_data->inst;
2200 unsigned opcode = inst->Instruction.Opcode;
2201 LLVMValueRef indices[2];
2202 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2203 LLVMValueRef tl, trbl, result[4];
2204 LLVMTypeRef i32;
2205 unsigned swizzle[4];
2206 unsigned c;
2207
2208 i32 = LLVMInt32TypeInContext(gallivm->context);
2209
2210 indices[0] = bld_base->uint_bld.zero;
2211 indices[1] = build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2212 NULL, 0, LLVMReadNoneAttribute);
2213 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2214 indices, 2, "");
2215
2216 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2217 lp_build_const_int32(gallivm, 0xfffffffc), "");
2218 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2219 indices, 2, "");
2220
2221 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2222 lp_build_const_int32(gallivm,
2223 opcode == TGSI_OPCODE_DDX ? 1 : 2),
2224 "");
2225 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->ddxy_lds,
2226 indices, 2, "");
2227
2228 for (c = 0; c < 4; ++c) {
2229 unsigned i;
2230
2231 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2232 for (i = 0; i < c; ++i) {
2233 if (swizzle[i] == swizzle[c]) {
2234 result[c] = result[i];
2235 break;
2236 }
2237 }
2238 if (i != c)
2239 continue;
2240
2241 LLVMBuildStore(gallivm->builder,
2242 LLVMBuildBitCast(gallivm->builder,
2243 lp_build_emit_fetch(bld_base, inst, 0, c),
2244 i32, ""),
2245 store_ptr);
2246
2247 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2248 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2249
2250 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2251 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2252
2253 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2254 }
2255
2256 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
2257 }
2258
2259 /* Emit one vertex from the geometry shader */
2260 static void si_llvm_emit_vertex(
2261 const struct lp_build_tgsi_action *action,
2262 struct lp_build_tgsi_context *bld_base,
2263 struct lp_build_emit_data *emit_data)
2264 {
2265 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2266 struct lp_build_context *uint = &bld_base->uint_bld;
2267 struct si_shader *shader = si_shader_ctx->shader;
2268 struct gallivm_state *gallivm = bld_base->base.gallivm;
2269 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2270 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2271 SI_PARAM_GS2VS_OFFSET);
2272 LLVMValueRef gs_next_vertex;
2273 LLVMValueRef can_emit, kill;
2274 LLVMValueRef t_list_ptr;
2275 LLVMValueRef t_list;
2276 LLVMValueRef args[2];
2277 unsigned chan;
2278 int i;
2279
2280 /* Load the GSVS ring resource descriptor */
2281 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2282 SI_PARAM_RW_BUFFERS);
2283 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
2284 lp_build_const_int32(gallivm, SI_RING_GSVS));
2285
2286 if (shader->noutput == 0) {
2287 struct tgsi_parse_context *parse = &si_shader_ctx->parse;
2288
2289 while (!tgsi_parse_end_of_tokens(parse)) {
2290 tgsi_parse_token(parse);
2291
2292 if (parse->FullToken.Token.Type == TGSI_TOKEN_TYPE_DECLARATION) {
2293 struct tgsi_full_declaration *d = &parse->FullToken.FullDeclaration;
2294
2295 if (d->Declaration.File == TGSI_FILE_OUTPUT)
2296 si_store_shader_io_attribs(shader, d);
2297 }
2298 }
2299 }
2300
2301 /* Write vertex attribute values to GSVS ring */
2302 gs_next_vertex = LLVMBuildLoad(gallivm->builder, si_shader_ctx->gs_next_vertex, "");
2303
2304 /* If this thread has already emitted the declared maximum number of
2305 * vertices, kill it: excessive vertex emissions are not supposed to
2306 * have any effect, and GS threads have no externally observable
2307 * effects other than emitting vertices.
2308 */
2309 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
2310 lp_build_const_int32(gallivm,
2311 shader->gs_max_out_vertices), "");
2312 kill = lp_build_select(&bld_base->base, can_emit,
2313 lp_build_const_float(gallivm, 1.0f),
2314 lp_build_const_float(gallivm, -1.0f));
2315 build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2316 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
2317
2318 for (i = 0; i < shader->noutput; i++) {
2319 LLVMValueRef *out_ptr =
2320 si_shader_ctx->radeon_bld.soa.outputs[shader->output[i].index];
2321
2322 for (chan = 0; chan < 4; chan++) {
2323 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2324 LLVMValueRef voffset =
2325 lp_build_const_int32(gallivm, (i * 4 + chan) *
2326 shader->gs_max_out_vertices);
2327
2328 voffset = lp_build_add(uint, voffset, gs_next_vertex);
2329 voffset = lp_build_mul_imm(uint, voffset, 4);
2330
2331 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2332
2333 build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
2334 voffset, soffset, 0,
2335 V_008F0C_BUF_DATA_FORMAT_32,
2336 V_008F0C_BUF_NUM_FORMAT_UINT,
2337 1, 0, 1, 1, 0);
2338 }
2339 }
2340 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
2341 lp_build_const_int32(gallivm, 1));
2342 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex);
2343
2344 /* Signal vertex emission */
2345 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS);
2346 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2347 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2348 LLVMVoidTypeInContext(gallivm->context), args, 2,
2349 LLVMNoUnwindAttribute);
2350 }
2351
2352 /* Cut one primitive from the geometry shader */
2353 static void si_llvm_emit_primitive(
2354 const struct lp_build_tgsi_action *action,
2355 struct lp_build_tgsi_context *bld_base,
2356 struct lp_build_emit_data *emit_data)
2357 {
2358 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2359 struct gallivm_state *gallivm = bld_base->base.gallivm;
2360 LLVMValueRef args[2];
2361
2362 /* Signal primitive cut */
2363 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS);
2364 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2365 build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2366 LLVMVoidTypeInContext(gallivm->context), args, 2,
2367 LLVMNoUnwindAttribute);
2368 }
2369
2370 static const struct lp_build_tgsi_action tex_action = {
2371 .fetch_args = tex_fetch_args,
2372 .emit = build_tex_intrinsic,
2373 };
2374
2375 static const struct lp_build_tgsi_action txq_action = {
2376 .fetch_args = txq_fetch_args,
2377 .emit = build_txq_intrinsic,
2378 .intr_name = "llvm.SI.resinfo"
2379 };
2380
2381 static void create_meta_data(struct si_shader_context *si_shader_ctx)
2382 {
2383 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
2384 LLVMValueRef args[3];
2385
2386 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
2387 args[1] = 0;
2388 args[2] = lp_build_const_int32(gallivm, 1);
2389
2390 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
2391 }
2392
2393 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
2394 {
2395 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
2396 CONST_ADDR_SPACE);
2397 }
2398
2399 static void create_function(struct si_shader_context *si_shader_ctx)
2400 {
2401 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2402 struct gallivm_state *gallivm = bld_base->base.gallivm;
2403 struct si_shader *shader = si_shader_ctx->shader;
2404 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
2405 unsigned i, last_sgpr, num_params;
2406
2407 i8 = LLVMInt8TypeInContext(gallivm->context);
2408 i32 = LLVMInt32TypeInContext(gallivm->context);
2409 f32 = LLVMFloatTypeInContext(gallivm->context);
2410 v2i32 = LLVMVectorType(i32, 2);
2411 v3i32 = LLVMVectorType(i32, 3);
2412 v4i32 = LLVMVectorType(i32, 4);
2413 v8i32 = LLVMVectorType(i32, 8);
2414 v16i8 = LLVMVectorType(i8, 16);
2415
2416 params[SI_PARAM_CONST] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
2417 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
2418 params[SI_PARAM_SAMPLER] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
2419 params[SI_PARAM_RESOURCE] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
2420
2421 switch (si_shader_ctx->type) {
2422 case TGSI_PROCESSOR_VERTEX:
2423 params[SI_PARAM_VERTEX_BUFFER] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
2424 params[SI_PARAM_BASE_VERTEX] = i32;
2425 params[SI_PARAM_START_INSTANCE] = i32;
2426 num_params = SI_PARAM_START_INSTANCE+1;
2427 if (shader->key.vs.as_es) {
2428 params[SI_PARAM_ES2GS_OFFSET] = i32;
2429 num_params++;
2430 } else {
2431 /* The locations of the other parameters are assigned dynamically. */
2432
2433 /* Streamout SGPRs. */
2434 if (shader->selector->so.num_outputs) {
2435 params[si_shader_ctx->param_streamout_config = num_params++] = i32;
2436 params[si_shader_ctx->param_streamout_write_index = num_params++] = i32;
2437 }
2438 /* A streamout buffer offset is loaded if the stride is non-zero. */
2439 for (i = 0; i < 4; i++) {
2440 if (!shader->selector->so.stride[i])
2441 continue;
2442
2443 params[si_shader_ctx->param_streamout_offset[i] = num_params++] = i32;
2444 }
2445 }
2446
2447 last_sgpr = num_params-1;
2448
2449 /* VGPRs */
2450 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
2451 params[num_params++] = i32; /* unused*/
2452 params[num_params++] = i32; /* unused */
2453 params[si_shader_ctx->param_instance_id = num_params++] = i32;
2454 break;
2455
2456 case TGSI_PROCESSOR_GEOMETRY:
2457 params[SI_PARAM_GS2VS_OFFSET] = i32;
2458 params[SI_PARAM_GS_WAVE_ID] = i32;
2459 last_sgpr = SI_PARAM_GS_WAVE_ID;
2460
2461 /* VGPRs */
2462 params[SI_PARAM_VTX0_OFFSET] = i32;
2463 params[SI_PARAM_VTX1_OFFSET] = i32;
2464 params[SI_PARAM_PRIMITIVE_ID] = i32;
2465 params[SI_PARAM_VTX2_OFFSET] = i32;
2466 params[SI_PARAM_VTX3_OFFSET] = i32;
2467 params[SI_PARAM_VTX4_OFFSET] = i32;
2468 params[SI_PARAM_VTX5_OFFSET] = i32;
2469 params[SI_PARAM_GS_INSTANCE_ID] = i32;
2470 num_params = SI_PARAM_GS_INSTANCE_ID+1;
2471 break;
2472
2473 case TGSI_PROCESSOR_FRAGMENT:
2474 params[SI_PARAM_ALPHA_REF] = f32;
2475 params[SI_PARAM_PRIM_MASK] = i32;
2476 last_sgpr = SI_PARAM_PRIM_MASK;
2477 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
2478 params[SI_PARAM_PERSP_CENTER] = v2i32;
2479 params[SI_PARAM_PERSP_CENTROID] = v2i32;
2480 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
2481 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
2482 params[SI_PARAM_LINEAR_CENTER] = v2i32;
2483 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
2484 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
2485 params[SI_PARAM_POS_X_FLOAT] = f32;
2486 params[SI_PARAM_POS_Y_FLOAT] = f32;
2487 params[SI_PARAM_POS_Z_FLOAT] = f32;
2488 params[SI_PARAM_POS_W_FLOAT] = f32;
2489 params[SI_PARAM_FRONT_FACE] = f32;
2490 params[SI_PARAM_ANCILLARY] = i32;
2491 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
2492 params[SI_PARAM_POS_FIXED_PT] = f32;
2493 num_params = SI_PARAM_POS_FIXED_PT+1;
2494 break;
2495
2496 default:
2497 assert(0 && "unimplemented shader");
2498 return;
2499 }
2500
2501 assert(num_params <= Elements(params));
2502 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
2503 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
2504
2505 for (i = 0; i <= last_sgpr; ++i) {
2506 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
2507 switch (i) {
2508 default:
2509 LLVMAddAttribute(P, LLVMInRegAttribute);
2510 break;
2511 /* We tell llvm that array inputs are passed by value to allow Sinking pass
2512 * to move load. Inputs are constant so this is fine. */
2513 case SI_PARAM_CONST:
2514 case SI_PARAM_SAMPLER:
2515 case SI_PARAM_RESOURCE:
2516 LLVMAddAttribute(P, LLVMByValAttribute);
2517 break;
2518 }
2519 }
2520
2521 if (bld_base->info &&
2522 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
2523 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0))
2524 si_shader_ctx->ddxy_lds =
2525 LLVMAddGlobalInAddressSpace(gallivm->module,
2526 LLVMArrayType(i32, 64),
2527 "ddxy_lds",
2528 LOCAL_ADDR_SPACE);
2529 }
2530
2531 static void preload_constants(struct si_shader_context *si_shader_ctx)
2532 {
2533 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2534 struct gallivm_state * gallivm = bld_base->base.gallivm;
2535 const struct tgsi_shader_info * info = bld_base->info;
2536 unsigned buf;
2537 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST);
2538
2539 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
2540 unsigned i, num_const = info->const_file_max[buf] + 1;
2541
2542 if (num_const == 0)
2543 continue;
2544
2545 /* Allocate space for the constant values */
2546 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
2547
2548 /* Load the resource descriptor */
2549 si_shader_ctx->const_resource[buf] =
2550 build_indexed_load(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
2551
2552 /* Load the constants, we rely on the code sinking to do the rest */
2553 for (i = 0; i < num_const * 4; ++i) {
2554 si_shader_ctx->constants[buf][i] =
2555 load_const(gallivm->builder,
2556 si_shader_ctx->const_resource[buf],
2557 lp_build_const_int32(gallivm, i * 4),
2558 bld_base->base.elem_type);
2559 }
2560 }
2561 }
2562
2563 static void preload_samplers(struct si_shader_context *si_shader_ctx)
2564 {
2565 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2566 struct gallivm_state * gallivm = bld_base->base.gallivm;
2567 const struct tgsi_shader_info * info = bld_base->info;
2568
2569 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
2570
2571 LLVMValueRef res_ptr, samp_ptr;
2572 LLVMValueRef offset;
2573
2574 if (num_samplers == 0)
2575 return;
2576
2577 /* Allocate space for the values */
2578 si_shader_ctx->resources = CALLOC(SI_NUM_SAMPLER_VIEWS, sizeof(LLVMValueRef));
2579 si_shader_ctx->samplers = CALLOC(num_samplers, sizeof(LLVMValueRef));
2580
2581 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_RESOURCE);
2582 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER);
2583
2584 /* Load the resources and samplers, we rely on the code sinking to do the rest */
2585 for (i = 0; i < num_samplers; ++i) {
2586 /* Resource */
2587 offset = lp_build_const_int32(gallivm, i);
2588 si_shader_ctx->resources[i] = build_indexed_load(si_shader_ctx, res_ptr, offset);
2589
2590 /* Sampler */
2591 offset = lp_build_const_int32(gallivm, i);
2592 si_shader_ctx->samplers[i] = build_indexed_load(si_shader_ctx, samp_ptr, offset);
2593
2594 /* FMASK resource */
2595 if (info->is_msaa_sampler[i]) {
2596 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
2597 si_shader_ctx->resources[SI_FMASK_TEX_OFFSET + i] =
2598 build_indexed_load(si_shader_ctx, res_ptr, offset);
2599 }
2600 }
2601 }
2602
2603 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
2604 {
2605 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2606 struct gallivm_state * gallivm = bld_base->base.gallivm;
2607 unsigned i;
2608
2609 if (si_shader_ctx->type != TGSI_PROCESSOR_VERTEX ||
2610 si_shader_ctx->shader->key.vs.as_es ||
2611 !si_shader_ctx->shader->selector->so.num_outputs)
2612 return;
2613
2614 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2615 SI_PARAM_RW_BUFFERS);
2616
2617 /* Load the resources, we rely on the code sinking to do the rest */
2618 for (i = 0; i < 4; ++i) {
2619 if (si_shader_ctx->shader->selector->so.stride[i]) {
2620 LLVMValueRef offset = lp_build_const_int32(gallivm,
2621 SI_SO_BUF_OFFSET + i);
2622
2623 si_shader_ctx->so_buffers[i] = build_indexed_load(si_shader_ctx, buf_ptr, offset);
2624 }
2625 }
2626 }
2627
2628 int si_compile_llvm(struct si_screen *sscreen, struct si_shader *shader,
2629 LLVMModuleRef mod)
2630 {
2631 unsigned r; /* llvm_compile result */
2632 unsigned i;
2633 unsigned char *ptr;
2634 struct radeon_shader_binary binary;
2635 bool dump = r600_can_dump_shader(&sscreen->b,
2636 shader->selector ? shader->selector->tokens : NULL);
2637 const char * gpu_family = r600_get_llvm_processor_name(sscreen->b.family);
2638 unsigned code_size;
2639
2640 /* Use LLVM to compile shader */
2641 memset(&binary, 0, sizeof(binary));
2642 r = radeon_llvm_compile(mod, &binary, gpu_family, dump);
2643
2644 /* Output binary dump if rscreen->debug_flags are set */
2645 if (dump && ! binary.disassembled) {
2646 fprintf(stderr, "SI CODE:\n");
2647 for (i = 0; i < binary.code_size; i+=4 ) {
2648 fprintf(stderr, "%02x%02x%02x%02x\n", binary.code[i + 3],
2649 binary.code[i + 2], binary.code[i + 1],
2650 binary.code[i]);
2651 }
2652 }
2653
2654 /* XXX: We may be able to emit some of these values directly rather than
2655 * extracting fields to be emitted later.
2656 */
2657 /* Parse config data in compiled binary */
2658 for (i = 0; i < binary.config_size; i+= 8) {
2659 unsigned reg = util_le32_to_cpu(*(uint32_t*)(binary.config + i));
2660 unsigned value = util_le32_to_cpu(*(uint32_t*)(binary.config + i + 4));
2661 switch (reg) {
2662 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
2663 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
2664 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
2665 case R_00B848_COMPUTE_PGM_RSRC1:
2666 shader->num_sgprs = (G_00B028_SGPRS(value) + 1) * 8;
2667 shader->num_vgprs = (G_00B028_VGPRS(value) + 1) * 4;
2668 break;
2669 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
2670 shader->lds_size = G_00B02C_EXTRA_LDS_SIZE(value);
2671 break;
2672 case R_00B84C_COMPUTE_PGM_RSRC2:
2673 shader->lds_size = G_00B84C_LDS_SIZE(value);
2674 break;
2675 case R_0286CC_SPI_PS_INPUT_ENA:
2676 shader->spi_ps_input_ena = value;
2677 break;
2678 case R_00B860_COMPUTE_TMPRING_SIZE:
2679 /* WAVESIZE is in units of 256 dwords. */
2680 shader->scratch_bytes_per_wave =
2681 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
2682 break;
2683 default:
2684 fprintf(stderr, "Warning: Compiler emitted unknown "
2685 "config register: 0x%x\n", reg);
2686 break;
2687 }
2688 }
2689
2690 /* copy new shader */
2691 code_size = binary.code_size + binary.rodata_size;
2692 r600_resource_reference(&shader->bo, NULL);
2693 shader->bo = si_resource_create_custom(&sscreen->b.b, PIPE_USAGE_IMMUTABLE,
2694 code_size);
2695 if (shader->bo == NULL) {
2696 return -ENOMEM;
2697 }
2698
2699 ptr = sscreen->b.ws->buffer_map(shader->bo->cs_buf, NULL, PIPE_TRANSFER_WRITE);
2700 util_memcpy_cpu_to_le32(ptr, binary.code, binary.code_size);
2701 if (binary.rodata_size > 0) {
2702 ptr += binary.code_size;
2703 util_memcpy_cpu_to_le32(ptr, binary.rodata, binary.rodata_size);
2704 }
2705
2706 sscreen->b.ws->buffer_unmap(shader->bo->cs_buf);
2707
2708 free(binary.code);
2709 free(binary.config);
2710 free(binary.rodata);
2711
2712 return r;
2713 }
2714
2715 /* Generate code for the hardware VS shader stage to go with a geometry shader */
2716 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
2717 struct si_shader_context *si_shader_ctx,
2718 bool dump)
2719 {
2720 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
2721 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
2722 struct lp_build_context *base = &bld_base->base;
2723 struct lp_build_context *uint = &bld_base->uint_bld;
2724 struct si_shader *shader = si_shader_ctx->shader;
2725 struct si_shader *gs = si_shader_ctx->shader->selector->current;
2726 struct si_shader_output_values *outputs;
2727 LLVMValueRef t_list_ptr, t_list;
2728 LLVMValueRef args[9];
2729 int i, r;
2730
2731 outputs = MALLOC(gs->noutput * sizeof(outputs[0]));
2732
2733 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
2734
2735 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
2736
2737 create_meta_data(si_shader_ctx);
2738 create_function(si_shader_ctx);
2739 preload_streamout_buffers(si_shader_ctx);
2740
2741 /* Load the GSVS ring resource descriptor */
2742 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2743 SI_PARAM_RW_BUFFERS);
2744 t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
2745 lp_build_const_int32(gallivm, SI_RING_GSVS));
2746
2747 args[0] = t_list;
2748 args[1] = lp_build_mul_imm(uint,
2749 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2750 si_shader_ctx->param_vertex_id),
2751 4);
2752 args[3] = uint->zero;
2753 args[4] = uint->one; /* OFFEN */
2754 args[5] = uint->zero; /* IDXEN */
2755 args[6] = uint->one; /* GLC */
2756 args[7] = uint->one; /* SLC */
2757 args[8] = uint->zero; /* TFE */
2758
2759 /* Fetch vertex data from GSVS ring */
2760 for (i = 0; i < gs->noutput; ++i) {
2761 struct si_shader_output *out = gs->output + i;
2762 unsigned chan;
2763
2764 shader->output[i] = *out;
2765
2766 outputs[i].name = out->name;
2767 outputs[i].index = out->index;
2768 outputs[i].sid = out->sid;
2769 outputs[i].usage = out->usage;
2770
2771 for (chan = 0; chan < 4; chan++) {
2772 args[2] = lp_build_const_int32(gallivm,
2773 (i * 4 + chan) *
2774 gs->gs_max_out_vertices * 16 * 4);
2775
2776 outputs[i].values[chan] =
2777 LLVMBuildBitCast(gallivm->builder,
2778 build_intrinsic(gallivm->builder,
2779 "llvm.SI.buffer.load.dword.i32.i32",
2780 LLVMInt32TypeInContext(gallivm->context),
2781 args, 9,
2782 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
2783 base->elem_type, "");
2784 }
2785 }
2786 shader->noutput = gs->noutput;
2787
2788 si_llvm_export_vs(bld_base, outputs, gs->noutput);
2789
2790 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
2791
2792 if (dump)
2793 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
2794
2795 r = si_compile_llvm(sscreen, si_shader_ctx->shader,
2796 bld_base->base.gallivm->module);
2797
2798 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
2799
2800 FREE(outputs);
2801 return r;
2802 }
2803
2804 int si_shader_create(struct si_screen *sscreen, struct si_shader *shader)
2805 {
2806 struct si_shader_selector *sel = shader->selector;
2807 struct si_shader_context si_shader_ctx;
2808 struct lp_build_tgsi_context * bld_base;
2809 LLVMModuleRef mod;
2810 int r = 0;
2811 bool dump = r600_can_dump_shader(&sscreen->b, sel->tokens);
2812
2813 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
2814 * conversion fails. */
2815 if (dump) {
2816 tgsi_dump(sel->tokens, 0);
2817 si_dump_streamout(&sel->so);
2818 }
2819
2820 assert(shader->noutput == 0);
2821 assert(shader->nparam == 0);
2822 assert(shader->ninput == 0);
2823
2824 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
2825 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
2826 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
2827
2828 if (sel->info.uses_kill)
2829 shader->db_shader_control |= S_02880C_KILL_ENABLE(1);
2830
2831 shader->uses_instanceid = sel->info.uses_instanceid;
2832 bld_base->info = &sel->info;
2833 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
2834
2835 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
2836 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
2837 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
2838 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
2839 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
2840 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
2841 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
2842 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
2843 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
2844 bld_base->op_actions[TGSI_OPCODE_TXQ] = txq_action;
2845 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
2846 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
2847
2848 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
2849 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
2850
2851 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
2852 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
2853
2854 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
2855 si_shader_ctx.tokens = sel->tokens;
2856 tgsi_parse_init(&si_shader_ctx.parse, si_shader_ctx.tokens);
2857 si_shader_ctx.shader = shader;
2858 si_shader_ctx.type = si_shader_ctx.parse.FullHeader.Processor.Processor;
2859
2860 switch (si_shader_ctx.type) {
2861 case TGSI_PROCESSOR_VERTEX:
2862 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
2863 if (shader->key.vs.as_es) {
2864 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
2865 } else {
2866 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
2867 }
2868 break;
2869 case TGSI_PROCESSOR_GEOMETRY: {
2870 int i;
2871
2872 si_shader_ctx.radeon_bld.load_input = declare_input_gs;
2873 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
2874 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
2875
2876 for (i = 0; i < sel->info.num_properties; i++) {
2877 switch (sel->info.properties[i].name) {
2878 case TGSI_PROPERTY_GS_INPUT_PRIM:
2879 shader->gs_input_prim = sel->info.properties[i].data[0];
2880 break;
2881 case TGSI_PROPERTY_GS_OUTPUT_PRIM:
2882 shader->gs_output_prim = sel->info.properties[i].data[0];
2883 break;
2884 case TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES:
2885 shader->gs_max_out_vertices = sel->info.properties[i].data[0];
2886 break;
2887 }
2888 }
2889 break;
2890 }
2891 case TGSI_PROCESSOR_FRAGMENT: {
2892 int i;
2893
2894 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
2895 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
2896
2897 for (i = 0; i < sel->info.num_properties; i++) {
2898 switch (sel->info.properties[i].name) {
2899 case TGSI_PROPERTY_FS_DEPTH_LAYOUT:
2900 switch (sel->info.properties[i].data[0]) {
2901 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2902 shader->db_shader_control |=
2903 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2904 break;
2905 case TGSI_FS_DEPTH_LAYOUT_LESS:
2906 shader->db_shader_control |=
2907 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2908 break;
2909 }
2910 break;
2911 }
2912 }
2913 break;
2914 }
2915 default:
2916 assert(!"Unsupported shader type");
2917 return -1;
2918 }
2919
2920 create_meta_data(&si_shader_ctx);
2921 create_function(&si_shader_ctx);
2922 preload_constants(&si_shader_ctx);
2923 preload_samplers(&si_shader_ctx);
2924 preload_streamout_buffers(&si_shader_ctx);
2925
2926 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2927 si_shader_ctx.gs_next_vertex =
2928 lp_build_alloca(bld_base->base.gallivm,
2929 bld_base->uint_bld.elem_type, "");
2930 }
2931
2932 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
2933 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
2934 goto out;
2935 }
2936
2937 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
2938
2939 mod = bld_base->base.gallivm->module;
2940 r = si_compile_llvm(sscreen, shader, mod);
2941 if (r) {
2942 fprintf(stderr, "LLVM failed to compile shader\n");
2943 goto out;
2944 }
2945
2946 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
2947
2948 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
2949 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
2950 shader->gs_copy_shader->selector = shader->selector;
2951 shader->gs_copy_shader->key = shader->key;
2952 si_shader_ctx.shader = shader->gs_copy_shader;
2953 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx, dump))) {
2954 free(shader->gs_copy_shader);
2955 shader->gs_copy_shader = NULL;
2956 goto out;
2957 }
2958 }
2959
2960 tgsi_parse_free(&si_shader_ctx.parse);
2961
2962 out:
2963 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
2964 FREE(si_shader_ctx.constants[i]);
2965 FREE(si_shader_ctx.resources);
2966 FREE(si_shader_ctx.samplers);
2967
2968 return r;
2969 }
2970
2971 void si_shader_destroy(struct pipe_context *ctx, struct si_shader *shader)
2972 {
2973 if (shader->gs_copy_shader)
2974 si_shader_destroy(ctx, shader->gs_copy_shader);
2975
2976 r600_resource_reference(&shader->bo, NULL);
2977 r600_resource_reference(&shader->scratch_bo, NULL);
2978 }