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radeonsi: emit VS_STATE register explicitly from si_draw_vbo
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "util/u_memory.h"
37 #include "util/u_string.h"
38 #include "tgsi/tgsi_build.h"
39 #include "tgsi/tgsi_util.h"
40 #include "tgsi/tgsi_dump.h"
41
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "si_shader_internal.h"
45 #include "si_pipe.h"
46 #include "sid.h"
47
48
49 static const char *scratch_rsrc_dword0_symbol =
50 "SCRATCH_RSRC_DWORD0";
51
52 static const char *scratch_rsrc_dword1_symbol =
53 "SCRATCH_RSRC_DWORD1";
54
55 struct si_shader_output_values
56 {
57 LLVMValueRef values[4];
58 unsigned semantic_name;
59 unsigned semantic_index;
60 ubyte vertex_stream[4];
61 };
62
63 static void si_init_shader_ctx(struct si_shader_context *ctx,
64 struct si_screen *sscreen,
65 struct si_shader *shader,
66 LLVMTargetMachineRef tm);
67
68 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
69 struct lp_build_tgsi_context *bld_base,
70 struct lp_build_emit_data *emit_data);
71
72 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
73 FILE *f);
74
75 static unsigned llvm_get_type_size(LLVMTypeRef type);
76
77 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
78 union si_shader_part_key *key);
79 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
80 union si_shader_part_key *key);
81 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
82 union si_shader_part_key *key);
83 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
84 union si_shader_part_key *key);
85 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
86 union si_shader_part_key *key);
87
88 /* Ideally pass the sample mask input to the PS epilog as v13, which
89 * is its usual location, so that the shader doesn't have to add v_mov.
90 */
91 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
92
93 /* The VS location of the PrimitiveID input is the same in the epilog,
94 * so that the main shader part doesn't have to move it.
95 */
96 #define VS_EPILOG_PRIMID_LOC 2
97
98 enum {
99 CONST_ADDR_SPACE = 2,
100 LOCAL_ADDR_SPACE = 3,
101 };
102
103 /**
104 * Returns a unique index for a semantic name and index. The index must be
105 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
106 * calculated.
107 */
108 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
109 {
110 switch (semantic_name) {
111 case TGSI_SEMANTIC_POSITION:
112 return 0;
113 case TGSI_SEMANTIC_PSIZE:
114 return 1;
115 case TGSI_SEMANTIC_CLIPDIST:
116 assert(index <= 1);
117 return 2 + index;
118 case TGSI_SEMANTIC_GENERIC:
119 if (index <= 63-4)
120 return 4 + index;
121
122 assert(!"invalid generic index");
123 return 0;
124
125 /* patch indices are completely separate and thus start from 0 */
126 case TGSI_SEMANTIC_TESSOUTER:
127 return 0;
128 case TGSI_SEMANTIC_TESSINNER:
129 return 1;
130 case TGSI_SEMANTIC_PATCH:
131 return 2 + index;
132
133 default:
134 assert(!"invalid semantic name");
135 return 0;
136 }
137 }
138
139 unsigned si_shader_io_get_unique_index2(unsigned name, unsigned index)
140 {
141 switch (name) {
142 case TGSI_SEMANTIC_FOG:
143 return 0;
144 case TGSI_SEMANTIC_LAYER:
145 return 1;
146 case TGSI_SEMANTIC_VIEWPORT_INDEX:
147 return 2;
148 case TGSI_SEMANTIC_PRIMID:
149 return 3;
150 case TGSI_SEMANTIC_COLOR: /* these alias */
151 case TGSI_SEMANTIC_BCOLOR:
152 return 4 + index;
153 case TGSI_SEMANTIC_TEXCOORD:
154 return 6 + index;
155 default:
156 assert(!"invalid semantic name");
157 return 0;
158 }
159 }
160
161 /**
162 * Get the value of a shader input parameter and extract a bitfield.
163 */
164 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
165 unsigned param, unsigned rshift,
166 unsigned bitwidth)
167 {
168 struct gallivm_state *gallivm = &ctx->gallivm;
169 LLVMValueRef value = LLVMGetParam(ctx->main_fn,
170 param);
171
172 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
173 value = bitcast(&ctx->bld_base,
174 TGSI_TYPE_UNSIGNED, value);
175
176 if (rshift)
177 value = LLVMBuildLShr(gallivm->builder, value,
178 LLVMConstInt(ctx->i32, rshift, 0), "");
179
180 if (rshift + bitwidth < 32) {
181 unsigned mask = (1 << bitwidth) - 1;
182 value = LLVMBuildAnd(gallivm->builder, value,
183 LLVMConstInt(ctx->i32, mask, 0), "");
184 }
185
186 return value;
187 }
188
189 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
190 {
191 switch (ctx->type) {
192 case PIPE_SHADER_TESS_CTRL:
193 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
194
195 case PIPE_SHADER_TESS_EVAL:
196 return LLVMGetParam(ctx->main_fn,
197 ctx->param_tes_rel_patch_id);
198
199 default:
200 assert(0);
201 return NULL;
202 }
203 }
204
205 /* Tessellation shaders pass outputs to the next shader using LDS.
206 *
207 * LS outputs = TCS inputs
208 * TCS outputs = TES inputs
209 *
210 * The LDS layout is:
211 * - TCS inputs for patch 0
212 * - TCS inputs for patch 1
213 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
214 * - ...
215 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
216 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
217 * - TCS outputs for patch 1
218 * - Per-patch TCS outputs for patch 1
219 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
220 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
221 * - ...
222 *
223 * All three shaders VS(LS), TCS, TES share the same LDS space.
224 */
225
226 static LLVMValueRef
227 get_tcs_in_patch_stride(struct si_shader_context *ctx)
228 {
229 if (ctx->type == PIPE_SHADER_VERTEX)
230 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
231 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
232 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
233 else {
234 assert(0);
235 return NULL;
236 }
237 }
238
239 static LLVMValueRef
240 get_tcs_out_patch_stride(struct si_shader_context *ctx)
241 {
242 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
243 }
244
245 static LLVMValueRef
246 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
247 {
248 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
249 unpack_param(ctx,
250 SI_PARAM_TCS_OUT_OFFSETS,
251 0, 16),
252 4);
253 }
254
255 static LLVMValueRef
256 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
257 {
258 return lp_build_mul_imm(&ctx->bld_base.uint_bld,
259 unpack_param(ctx,
260 SI_PARAM_TCS_OUT_OFFSETS,
261 16, 16),
262 4);
263 }
264
265 static LLVMValueRef
266 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
267 {
268 struct gallivm_state *gallivm = &ctx->gallivm;
269 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
270 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
271
272 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
273 }
274
275 static LLVMValueRef
276 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
277 {
278 struct gallivm_state *gallivm = &ctx->gallivm;
279 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
280 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
281 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
282
283 return LLVMBuildAdd(gallivm->builder, patch0_offset,
284 LLVMBuildMul(gallivm->builder, patch_stride,
285 rel_patch_id, ""),
286 "");
287 }
288
289 static LLVMValueRef
290 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
291 {
292 struct gallivm_state *gallivm = &ctx->gallivm;
293 LLVMValueRef patch0_patch_data_offset =
294 get_tcs_out_patch0_patch_data_offset(ctx);
295 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
296 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
297
298 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
299 LLVMBuildMul(gallivm->builder, patch_stride,
300 rel_patch_id, ""),
301 "");
302 }
303
304 static LLVMValueRef get_instance_index_for_fetch(
305 struct si_shader_context *ctx,
306 unsigned param_start_instance, unsigned divisor)
307 {
308 struct gallivm_state *gallivm = &ctx->gallivm;
309
310 LLVMValueRef result = LLVMGetParam(ctx->main_fn,
311 ctx->param_instance_id);
312
313 /* The division must be done before START_INSTANCE is added. */
314 if (divisor > 1)
315 result = LLVMBuildUDiv(gallivm->builder, result,
316 LLVMConstInt(ctx->i32, divisor, 0), "");
317
318 return LLVMBuildAdd(gallivm->builder, result,
319 LLVMGetParam(ctx->main_fn, param_start_instance), "");
320 }
321
322 /* Bitcast <4 x float> to <2 x double>, extract the component, and convert
323 * to float. */
324 static LLVMValueRef extract_double_to_float(struct si_shader_context *ctx,
325 LLVMValueRef vec4,
326 unsigned double_index)
327 {
328 LLVMBuilderRef builder = ctx->gallivm.builder;
329 LLVMTypeRef f64 = LLVMDoubleTypeInContext(ctx->gallivm.context);
330 LLVMValueRef dvec2 = LLVMBuildBitCast(builder, vec4,
331 LLVMVectorType(f64, 2), "");
332 LLVMValueRef index = LLVMConstInt(ctx->i32, double_index, 0);
333 LLVMValueRef value = LLVMBuildExtractElement(builder, dvec2, index, "");
334 return LLVMBuildFPTrunc(builder, value, ctx->f32, "");
335 }
336
337 static void declare_input_vs(
338 struct si_shader_context *ctx,
339 unsigned input_index,
340 const struct tgsi_full_declaration *decl,
341 LLVMValueRef out[4])
342 {
343 struct gallivm_state *gallivm = &ctx->gallivm;
344
345 unsigned chan;
346 unsigned fix_fetch;
347 unsigned num_fetches;
348 unsigned fetch_stride;
349
350 LLVMValueRef t_list_ptr;
351 LLVMValueRef t_offset;
352 LLVMValueRef t_list;
353 LLVMValueRef vertex_index;
354 LLVMValueRef input[3];
355
356 /* Load the T list */
357 t_list_ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_VERTEX_BUFFERS);
358
359 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
360
361 t_list = ac_build_indexed_load_const(&ctx->ac, t_list_ptr, t_offset);
362
363 vertex_index = LLVMGetParam(ctx->main_fn,
364 ctx->param_vertex_index0 +
365 input_index);
366
367 fix_fetch = ctx->shader->key.mono.vs.fix_fetch[input_index];
368
369 /* Do multiple loads for special formats. */
370 switch (fix_fetch) {
371 case SI_FIX_FETCH_RGB_64_FLOAT:
372 num_fetches = 3; /* 3 2-dword loads */
373 fetch_stride = 8;
374 break;
375 case SI_FIX_FETCH_RGBA_64_FLOAT:
376 num_fetches = 2; /* 2 4-dword loads */
377 fetch_stride = 16;
378 break;
379 case SI_FIX_FETCH_RGB_8:
380 case SI_FIX_FETCH_RGB_8_INT:
381 num_fetches = 3;
382 fetch_stride = 1;
383 break;
384 case SI_FIX_FETCH_RGB_16:
385 case SI_FIX_FETCH_RGB_16_INT:
386 num_fetches = 3;
387 fetch_stride = 2;
388 break;
389 default:
390 num_fetches = 1;
391 fetch_stride = 0;
392 }
393
394 for (unsigned i = 0; i < num_fetches; i++) {
395 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
396
397 input[i] = ac_build_buffer_load_format(&ctx->ac, t_list,
398 vertex_index, voffset,
399 true);
400 }
401
402 /* Break up the vec4 into individual components */
403 for (chan = 0; chan < 4; chan++) {
404 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
405 out[chan] = LLVMBuildExtractElement(gallivm->builder,
406 input[0], llvm_chan, "");
407 }
408
409 switch (fix_fetch) {
410 case SI_FIX_FETCH_A2_SNORM:
411 case SI_FIX_FETCH_A2_SSCALED:
412 case SI_FIX_FETCH_A2_SINT: {
413 /* The hardware returns an unsigned value; convert it to a
414 * signed one.
415 */
416 LLVMValueRef tmp = out[3];
417 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
418
419 /* First, recover the sign-extended signed integer value. */
420 if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
421 tmp = LLVMBuildFPToUI(gallivm->builder, tmp, ctx->i32, "");
422 else
423 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->i32, "");
424
425 /* For the integer-like cases, do a natural sign extension.
426 *
427 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
428 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
429 * exponent.
430 */
431 tmp = LLVMBuildShl(gallivm->builder, tmp,
432 fix_fetch == SI_FIX_FETCH_A2_SNORM ?
433 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
434 tmp = LLVMBuildAShr(gallivm->builder, tmp, c30, "");
435
436 /* Convert back to the right type. */
437 if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
438 LLVMValueRef clamp;
439 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
440 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
441 clamp = LLVMBuildFCmp(gallivm->builder, LLVMRealULT, tmp, neg_one, "");
442 tmp = LLVMBuildSelect(gallivm->builder, clamp, neg_one, tmp, "");
443 } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
444 tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, "");
445 }
446
447 out[3] = tmp;
448 break;
449 }
450 case SI_FIX_FETCH_RGBA_32_UNORM:
451 case SI_FIX_FETCH_RGBX_32_UNORM:
452 for (chan = 0; chan < 4; chan++) {
453 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
454 ctx->i32, "");
455 out[chan] = LLVMBuildUIToFP(gallivm->builder,
456 out[chan], ctx->f32, "");
457 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
458 LLVMConstReal(ctx->f32, 1.0 / UINT_MAX), "");
459 }
460 /* RGBX UINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
461 if (fix_fetch == SI_FIX_FETCH_RGBX_32_UNORM)
462 out[3] = LLVMConstReal(ctx->f32, 1);
463 break;
464 case SI_FIX_FETCH_RGBA_32_SNORM:
465 case SI_FIX_FETCH_RGBX_32_SNORM:
466 case SI_FIX_FETCH_RGBA_32_FIXED:
467 case SI_FIX_FETCH_RGBX_32_FIXED: {
468 double scale;
469 if (fix_fetch >= SI_FIX_FETCH_RGBA_32_FIXED)
470 scale = 1.0 / 0x10000;
471 else
472 scale = 1.0 / INT_MAX;
473
474 for (chan = 0; chan < 4; chan++) {
475 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
476 ctx->i32, "");
477 out[chan] = LLVMBuildSIToFP(gallivm->builder,
478 out[chan], ctx->f32, "");
479 out[chan] = LLVMBuildFMul(gallivm->builder, out[chan],
480 LLVMConstReal(ctx->f32, scale), "");
481 }
482 /* RGBX SINT returns 1 in alpha, which would be rounded to 0 by normalizing. */
483 if (fix_fetch == SI_FIX_FETCH_RGBX_32_SNORM ||
484 fix_fetch == SI_FIX_FETCH_RGBX_32_FIXED)
485 out[3] = LLVMConstReal(ctx->f32, 1);
486 break;
487 }
488 case SI_FIX_FETCH_RGBA_32_USCALED:
489 for (chan = 0; chan < 4; chan++) {
490 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
491 ctx->i32, "");
492 out[chan] = LLVMBuildUIToFP(gallivm->builder,
493 out[chan], ctx->f32, "");
494 }
495 break;
496 case SI_FIX_FETCH_RGBA_32_SSCALED:
497 for (chan = 0; chan < 4; chan++) {
498 out[chan] = LLVMBuildBitCast(gallivm->builder, out[chan],
499 ctx->i32, "");
500 out[chan] = LLVMBuildSIToFP(gallivm->builder,
501 out[chan], ctx->f32, "");
502 }
503 break;
504 case SI_FIX_FETCH_RG_64_FLOAT:
505 for (chan = 0; chan < 2; chan++)
506 out[chan] = extract_double_to_float(ctx, input[0], chan);
507
508 out[2] = LLVMConstReal(ctx->f32, 0);
509 out[3] = LLVMConstReal(ctx->f32, 1);
510 break;
511 case SI_FIX_FETCH_RGB_64_FLOAT:
512 for (chan = 0; chan < 3; chan++)
513 out[chan] = extract_double_to_float(ctx, input[chan], 0);
514
515 out[3] = LLVMConstReal(ctx->f32, 1);
516 break;
517 case SI_FIX_FETCH_RGBA_64_FLOAT:
518 for (chan = 0; chan < 4; chan++) {
519 out[chan] = extract_double_to_float(ctx, input[chan / 2],
520 chan % 2);
521 }
522 break;
523 case SI_FIX_FETCH_RGB_8:
524 case SI_FIX_FETCH_RGB_8_INT:
525 case SI_FIX_FETCH_RGB_16:
526 case SI_FIX_FETCH_RGB_16_INT:
527 for (chan = 0; chan < 3; chan++) {
528 out[chan] = LLVMBuildExtractElement(gallivm->builder,
529 input[chan],
530 ctx->i32_0, "");
531 }
532 if (fix_fetch == SI_FIX_FETCH_RGB_8 ||
533 fix_fetch == SI_FIX_FETCH_RGB_16) {
534 out[3] = LLVMConstReal(ctx->f32, 1);
535 } else {
536 out[3] = LLVMBuildBitCast(gallivm->builder, ctx->i32_1,
537 ctx->f32, "");
538 }
539 break;
540 }
541 }
542
543 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
544 unsigned swizzle)
545 {
546 struct si_shader_context *ctx = si_shader_context(bld_base);
547
548 if (swizzle > 0)
549 return ctx->i32_0;
550
551 switch (ctx->type) {
552 case PIPE_SHADER_VERTEX:
553 return LLVMGetParam(ctx->main_fn,
554 ctx->param_vs_prim_id);
555 case PIPE_SHADER_TESS_CTRL:
556 return LLVMGetParam(ctx->main_fn,
557 SI_PARAM_PATCH_ID);
558 case PIPE_SHADER_TESS_EVAL:
559 return LLVMGetParam(ctx->main_fn,
560 ctx->param_tes_patch_id);
561 case PIPE_SHADER_GEOMETRY:
562 return LLVMGetParam(ctx->main_fn,
563 SI_PARAM_PRIMITIVE_ID);
564 default:
565 assert(0);
566 return ctx->i32_0;
567 }
568 }
569
570 /**
571 * Return the value of tgsi_ind_register for indexing.
572 * This is the indirect index with the constant offset added to it.
573 */
574 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
575 const struct tgsi_ind_register *ind,
576 int rel_index)
577 {
578 struct gallivm_state *gallivm = &ctx->gallivm;
579 LLVMValueRef result;
580
581 result = ctx->addrs[ind->Index][ind->Swizzle];
582 result = LLVMBuildLoad(gallivm->builder, result, "");
583 result = LLVMBuildAdd(gallivm->builder, result,
584 LLVMConstInt(ctx->i32, rel_index, 0), "");
585 return result;
586 }
587
588 /**
589 * Like get_indirect_index, but restricts the return value to a (possibly
590 * undefined) value inside [0..num).
591 */
592 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
593 const struct tgsi_ind_register *ind,
594 int rel_index, unsigned num)
595 {
596 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
597
598 /* LLVM 3.8: If indirect resource indexing is used:
599 * - SI & CIK hang
600 * - VI crashes
601 */
602 if (HAVE_LLVM == 0x0308)
603 return LLVMGetUndef(ctx->i32);
604
605 return si_llvm_bound_index(ctx, result, num);
606 }
607
608
609 /**
610 * Calculate a dword address given an input or output register and a stride.
611 */
612 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
613 const struct tgsi_full_dst_register *dst,
614 const struct tgsi_full_src_register *src,
615 LLVMValueRef vertex_dw_stride,
616 LLVMValueRef base_addr)
617 {
618 struct gallivm_state *gallivm = &ctx->gallivm;
619 struct tgsi_shader_info *info = &ctx->shader->selector->info;
620 ubyte *name, *index, *array_first;
621 int first, param;
622 struct tgsi_full_dst_register reg;
623
624 /* Set the register description. The address computation is the same
625 * for sources and destinations. */
626 if (src) {
627 reg.Register.File = src->Register.File;
628 reg.Register.Index = src->Register.Index;
629 reg.Register.Indirect = src->Register.Indirect;
630 reg.Register.Dimension = src->Register.Dimension;
631 reg.Indirect = src->Indirect;
632 reg.Dimension = src->Dimension;
633 reg.DimIndirect = src->DimIndirect;
634 } else
635 reg = *dst;
636
637 /* If the register is 2-dimensional (e.g. an array of vertices
638 * in a primitive), calculate the base address of the vertex. */
639 if (reg.Register.Dimension) {
640 LLVMValueRef index;
641
642 if (reg.Dimension.Indirect)
643 index = get_indirect_index(ctx, &reg.DimIndirect,
644 reg.Dimension.Index);
645 else
646 index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
647
648 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
649 LLVMBuildMul(gallivm->builder, index,
650 vertex_dw_stride, ""), "");
651 }
652
653 /* Get information about the register. */
654 if (reg.Register.File == TGSI_FILE_INPUT) {
655 name = info->input_semantic_name;
656 index = info->input_semantic_index;
657 array_first = info->input_array_first;
658 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
659 name = info->output_semantic_name;
660 index = info->output_semantic_index;
661 array_first = info->output_array_first;
662 } else {
663 assert(0);
664 return NULL;
665 }
666
667 if (reg.Register.Indirect) {
668 /* Add the relative address of the element. */
669 LLVMValueRef ind_index;
670
671 if (reg.Indirect.ArrayID)
672 first = array_first[reg.Indirect.ArrayID];
673 else
674 first = reg.Register.Index;
675
676 ind_index = get_indirect_index(ctx, &reg.Indirect,
677 reg.Register.Index - first);
678
679 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
680 LLVMBuildMul(gallivm->builder, ind_index,
681 LLVMConstInt(ctx->i32, 4, 0), ""), "");
682
683 param = si_shader_io_get_unique_index(name[first], index[first]);
684 } else {
685 param = si_shader_io_get_unique_index(name[reg.Register.Index],
686 index[reg.Register.Index]);
687 }
688
689 /* Add the base address of the element. */
690 return LLVMBuildAdd(gallivm->builder, base_addr,
691 LLVMConstInt(ctx->i32, param * 4, 0), "");
692 }
693
694 /* The offchip buffer layout for TCS->TES is
695 *
696 * - attribute 0 of patch 0 vertex 0
697 * - attribute 0 of patch 0 vertex 1
698 * - attribute 0 of patch 0 vertex 2
699 * ...
700 * - attribute 0 of patch 1 vertex 0
701 * - attribute 0 of patch 1 vertex 1
702 * ...
703 * - attribute 1 of patch 0 vertex 0
704 * - attribute 1 of patch 0 vertex 1
705 * ...
706 * - per patch attribute 0 of patch 0
707 * - per patch attribute 0 of patch 1
708 * ...
709 *
710 * Note that every attribute has 4 components.
711 */
712 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
713 LLVMValueRef rel_patch_id,
714 LLVMValueRef vertex_index,
715 LLVMValueRef param_index)
716 {
717 struct gallivm_state *gallivm = &ctx->gallivm;
718 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
719 LLVMValueRef param_stride, constant16;
720
721 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
722 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
723 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
724 num_patches, "");
725
726 constant16 = LLVMConstInt(ctx->i32, 16, 0);
727 if (vertex_index) {
728 base_addr = LLVMBuildMul(gallivm->builder, rel_patch_id,
729 vertices_per_patch, "");
730
731 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
732 vertex_index, "");
733
734 param_stride = total_vertices;
735 } else {
736 base_addr = rel_patch_id;
737 param_stride = num_patches;
738 }
739
740 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
741 LLVMBuildMul(gallivm->builder, param_index,
742 param_stride, ""), "");
743
744 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
745
746 if (!vertex_index) {
747 LLVMValueRef patch_data_offset =
748 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
749
750 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
751 patch_data_offset, "");
752 }
753 return base_addr;
754 }
755
756 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
757 struct si_shader_context *ctx,
758 const struct tgsi_full_dst_register *dst,
759 const struct tgsi_full_src_register *src)
760 {
761 struct gallivm_state *gallivm = &ctx->gallivm;
762 struct tgsi_shader_info *info = &ctx->shader->selector->info;
763 ubyte *name, *index, *array_first;
764 struct tgsi_full_src_register reg;
765 LLVMValueRef vertex_index = NULL;
766 LLVMValueRef param_index = NULL;
767 unsigned param_index_base, param_base;
768
769 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
770
771 if (reg.Register.Dimension) {
772
773 if (reg.Dimension.Indirect)
774 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
775 reg.Dimension.Index);
776 else
777 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
778 }
779
780 /* Get information about the register. */
781 if (reg.Register.File == TGSI_FILE_INPUT) {
782 name = info->input_semantic_name;
783 index = info->input_semantic_index;
784 array_first = info->input_array_first;
785 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
786 name = info->output_semantic_name;
787 index = info->output_semantic_index;
788 array_first = info->output_array_first;
789 } else {
790 assert(0);
791 return NULL;
792 }
793
794 if (reg.Register.Indirect) {
795 if (reg.Indirect.ArrayID)
796 param_base = array_first[reg.Indirect.ArrayID];
797 else
798 param_base = reg.Register.Index;
799
800 param_index = get_indirect_index(ctx, &reg.Indirect,
801 reg.Register.Index - param_base);
802
803 } else {
804 param_base = reg.Register.Index;
805 param_index = ctx->i32_0;
806 }
807
808 param_index_base = si_shader_io_get_unique_index(name[param_base],
809 index[param_base]);
810
811 param_index = LLVMBuildAdd(gallivm->builder, param_index,
812 LLVMConstInt(ctx->i32, param_index_base, 0),
813 "");
814
815 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
816 vertex_index, param_index);
817 }
818
819 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
820 enum tgsi_opcode_type type, unsigned swizzle,
821 LLVMValueRef buffer, LLVMValueRef offset,
822 LLVMValueRef base, bool readonly_memory)
823 {
824 struct si_shader_context *ctx = si_shader_context(bld_base);
825 struct gallivm_state *gallivm = &ctx->gallivm;
826 LLVMValueRef value, value2;
827 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
828 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
829
830 if (swizzle == ~0) {
831 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
832 0, 1, 0, readonly_memory);
833
834 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
835 }
836
837 if (!tgsi_type_is_64bit(type)) {
838 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
839 0, 1, 0, readonly_memory);
840
841 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
842 return LLVMBuildExtractElement(gallivm->builder, value,
843 LLVMConstInt(ctx->i32, swizzle, 0), "");
844 }
845
846 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
847 swizzle * 4, 1, 0, readonly_memory);
848
849 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
850 swizzle * 4 + 4, 1, 0, readonly_memory);
851
852 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
853 }
854
855 /**
856 * Load from LDS.
857 *
858 * \param type output value type
859 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
860 * \param dw_addr address in dwords
861 */
862 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
863 enum tgsi_opcode_type type, unsigned swizzle,
864 LLVMValueRef dw_addr)
865 {
866 struct si_shader_context *ctx = si_shader_context(bld_base);
867 struct gallivm_state *gallivm = &ctx->gallivm;
868 LLVMValueRef value;
869
870 if (swizzle == ~0) {
871 LLVMValueRef values[TGSI_NUM_CHANNELS];
872
873 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
874 values[chan] = lds_load(bld_base, type, chan, dw_addr);
875
876 return lp_build_gather_values(gallivm, values,
877 TGSI_NUM_CHANNELS);
878 }
879
880 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
881 LLVMConstInt(ctx->i32, swizzle, 0));
882
883 value = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
884 if (tgsi_type_is_64bit(type)) {
885 LLVMValueRef value2;
886 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
887 ctx->i32_1);
888 value2 = ac_build_indexed_load(&ctx->ac, ctx->lds, dw_addr, false);
889 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
890 }
891
892 return LLVMBuildBitCast(gallivm->builder, value,
893 tgsi2llvmtype(bld_base, type), "");
894 }
895
896 /**
897 * Store to LDS.
898 *
899 * \param swizzle offset (typically 0..3)
900 * \param dw_addr address in dwords
901 * \param value value to store
902 */
903 static void lds_store(struct lp_build_tgsi_context *bld_base,
904 unsigned swizzle, LLVMValueRef dw_addr,
905 LLVMValueRef value)
906 {
907 struct si_shader_context *ctx = si_shader_context(bld_base);
908 struct gallivm_state *gallivm = &ctx->gallivm;
909
910 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
911 LLVMConstInt(ctx->i32, swizzle, 0));
912
913 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
914 ac_build_indexed_store(&ctx->ac, ctx->lds,
915 dw_addr, value);
916 }
917
918 static LLVMValueRef fetch_input_tcs(
919 struct lp_build_tgsi_context *bld_base,
920 const struct tgsi_full_src_register *reg,
921 enum tgsi_opcode_type type, unsigned swizzle)
922 {
923 struct si_shader_context *ctx = si_shader_context(bld_base);
924 LLVMValueRef dw_addr, stride;
925
926 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
927 dw_addr = get_tcs_in_current_patch_offset(ctx);
928 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
929
930 return lds_load(bld_base, type, swizzle, dw_addr);
931 }
932
933 static LLVMValueRef fetch_output_tcs(
934 struct lp_build_tgsi_context *bld_base,
935 const struct tgsi_full_src_register *reg,
936 enum tgsi_opcode_type type, unsigned swizzle)
937 {
938 struct si_shader_context *ctx = si_shader_context(bld_base);
939 LLVMValueRef dw_addr, stride;
940
941 if (reg->Register.Dimension) {
942 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
943 dw_addr = get_tcs_out_current_patch_offset(ctx);
944 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
945 } else {
946 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
947 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
948 }
949
950 return lds_load(bld_base, type, swizzle, dw_addr);
951 }
952
953 static LLVMValueRef fetch_input_tes(
954 struct lp_build_tgsi_context *bld_base,
955 const struct tgsi_full_src_register *reg,
956 enum tgsi_opcode_type type, unsigned swizzle)
957 {
958 struct si_shader_context *ctx = si_shader_context(bld_base);
959 LLVMValueRef rw_buffers, buffer, base, addr;
960
961 rw_buffers = LLVMGetParam(ctx->main_fn,
962 SI_PARAM_RW_BUFFERS);
963 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
964 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
965
966 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
967 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
968
969 return buffer_load(bld_base, type, swizzle, buffer, base, addr, true);
970 }
971
972 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
973 const struct tgsi_full_instruction *inst,
974 const struct tgsi_opcode_info *info,
975 LLVMValueRef dst[4])
976 {
977 struct si_shader_context *ctx = si_shader_context(bld_base);
978 struct gallivm_state *gallivm = &ctx->gallivm;
979 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
980 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
981 unsigned chan_index;
982 LLVMValueRef dw_addr, stride;
983 LLVMValueRef rw_buffers, buffer, base, buf_addr;
984 LLVMValueRef values[4];
985 bool skip_lds_store;
986 bool is_tess_factor = false;
987
988 /* Only handle per-patch and per-vertex outputs here.
989 * Vectors will be lowered to scalars and this function will be called again.
990 */
991 if (reg->Register.File != TGSI_FILE_OUTPUT ||
992 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
993 si_llvm_emit_store(bld_base, inst, info, dst);
994 return;
995 }
996
997 if (reg->Register.Dimension) {
998 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
999 dw_addr = get_tcs_out_current_patch_offset(ctx);
1000 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1001 skip_lds_store = !sh_info->reads_pervertex_outputs;
1002 } else {
1003 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1004 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1005 skip_lds_store = !sh_info->reads_perpatch_outputs;
1006
1007 if (!reg->Register.Indirect) {
1008 int name = sh_info->output_semantic_name[reg->Register.Index];
1009
1010 /* Always write tess factors into LDS for the TCS epilog. */
1011 if (name == TGSI_SEMANTIC_TESSINNER ||
1012 name == TGSI_SEMANTIC_TESSOUTER) {
1013 skip_lds_store = false;
1014 is_tess_factor = true;
1015 }
1016 }
1017 }
1018
1019 rw_buffers = LLVMGetParam(ctx->main_fn,
1020 SI_PARAM_RW_BUFFERS);
1021 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
1022 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
1023
1024 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1025 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1026
1027
1028 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1029 LLVMValueRef value = dst[chan_index];
1030
1031 if (inst->Instruction.Saturate)
1032 value = ac_build_clamp(&ctx->ac, value);
1033
1034 /* Skip LDS stores if there is no LDS read of this output. */
1035 if (!skip_lds_store)
1036 lds_store(bld_base, chan_index, dw_addr, value);
1037
1038 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1039 values[chan_index] = value;
1040
1041 if (inst->Dst[0].Register.WriteMask != 0xF && !is_tess_factor) {
1042 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1043 buf_addr, base,
1044 4 * chan_index, 1, 0, true, false);
1045 }
1046 }
1047
1048 if (inst->Dst[0].Register.WriteMask == 0xF && !is_tess_factor) {
1049 LLVMValueRef value = lp_build_gather_values(gallivm,
1050 values, 4);
1051 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1052 base, 0, 1, 0, true, false);
1053 }
1054 }
1055
1056 static LLVMValueRef fetch_input_gs(
1057 struct lp_build_tgsi_context *bld_base,
1058 const struct tgsi_full_src_register *reg,
1059 enum tgsi_opcode_type type,
1060 unsigned swizzle)
1061 {
1062 struct si_shader_context *ctx = si_shader_context(bld_base);
1063 struct si_shader *shader = ctx->shader;
1064 struct lp_build_context *uint = &ctx->bld_base.uint_bld;
1065 struct gallivm_state *gallivm = &ctx->gallivm;
1066 LLVMValueRef vtx_offset, soffset;
1067 unsigned vtx_offset_param;
1068 struct tgsi_shader_info *info = &shader->selector->info;
1069 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1070 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1071 unsigned param;
1072 LLVMValueRef value;
1073
1074 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1075 return get_primitive_id(bld_base, swizzle);
1076
1077 if (!reg->Register.Dimension)
1078 return NULL;
1079
1080 if (swizzle == ~0) {
1081 LLVMValueRef values[TGSI_NUM_CHANNELS];
1082 unsigned chan;
1083 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1084 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1085 }
1086 return lp_build_gather_values(gallivm, values,
1087 TGSI_NUM_CHANNELS);
1088 }
1089
1090 /* Get the vertex offset parameter */
1091 vtx_offset_param = reg->Dimension.Index;
1092 if (vtx_offset_param < 2) {
1093 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1094 } else {
1095 assert(vtx_offset_param < 6);
1096 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1097 }
1098 vtx_offset = lp_build_mul_imm(uint,
1099 LLVMGetParam(ctx->main_fn,
1100 vtx_offset_param),
1101 4);
1102
1103 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1104 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1105
1106 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1107 vtx_offset, soffset, 0, 1, 0, true);
1108 if (tgsi_type_is_64bit(type)) {
1109 LLVMValueRef value2;
1110 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1111
1112 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1113 ctx->i32_0, vtx_offset, soffset,
1114 0, 1, 0, true);
1115 return si_llvm_emit_fetch_64bit(bld_base, type,
1116 value, value2);
1117 }
1118 return LLVMBuildBitCast(gallivm->builder,
1119 value,
1120 tgsi2llvmtype(bld_base, type), "");
1121 }
1122
1123 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1124 {
1125 switch (interpolate) {
1126 case TGSI_INTERPOLATE_CONSTANT:
1127 return 0;
1128
1129 case TGSI_INTERPOLATE_LINEAR:
1130 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1131 return SI_PARAM_LINEAR_SAMPLE;
1132 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1133 return SI_PARAM_LINEAR_CENTROID;
1134 else
1135 return SI_PARAM_LINEAR_CENTER;
1136 break;
1137 case TGSI_INTERPOLATE_COLOR:
1138 case TGSI_INTERPOLATE_PERSPECTIVE:
1139 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1140 return SI_PARAM_PERSP_SAMPLE;
1141 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1142 return SI_PARAM_PERSP_CENTROID;
1143 else
1144 return SI_PARAM_PERSP_CENTER;
1145 break;
1146 default:
1147 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1148 return -1;
1149 }
1150 }
1151
1152 /**
1153 * Interpolate a fragment shader input.
1154 *
1155 * @param ctx context
1156 * @param input_index index of the input in hardware
1157 * @param semantic_name TGSI_SEMANTIC_*
1158 * @param semantic_index semantic index
1159 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1160 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1161 * @param interp_param interpolation weights (i,j)
1162 * @param prim_mask SI_PARAM_PRIM_MASK
1163 * @param face SI_PARAM_FRONT_FACE
1164 * @param result the return value (4 components)
1165 */
1166 static void interp_fs_input(struct si_shader_context *ctx,
1167 unsigned input_index,
1168 unsigned semantic_name,
1169 unsigned semantic_index,
1170 unsigned num_interp_inputs,
1171 unsigned colors_read_mask,
1172 LLVMValueRef interp_param,
1173 LLVMValueRef prim_mask,
1174 LLVMValueRef face,
1175 LLVMValueRef result[4])
1176 {
1177 struct gallivm_state *gallivm = &ctx->gallivm;
1178 LLVMValueRef attr_number;
1179 LLVMValueRef i, j;
1180
1181 unsigned chan;
1182
1183 /* fs.constant returns the param from the middle vertex, so it's not
1184 * really useful for flat shading. It's meant to be used for custom
1185 * interpolation (but the intrinsic can't fetch from the other two
1186 * vertices).
1187 *
1188 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1189 * to do the right thing. The only reason we use fs.constant is that
1190 * fs.interp cannot be used on integers, because they can be equal
1191 * to NaN.
1192 *
1193 * When interp is false we will use fs.constant or for newer llvm,
1194 * amdgcn.interp.mov.
1195 */
1196 bool interp = interp_param != NULL;
1197
1198 attr_number = LLVMConstInt(ctx->i32, input_index, 0);
1199
1200 if (interp) {
1201 interp_param = LLVMBuildBitCast(gallivm->builder, interp_param,
1202 LLVMVectorType(ctx->f32, 2), "");
1203
1204 i = LLVMBuildExtractElement(gallivm->builder, interp_param,
1205 ctx->i32_0, "");
1206 j = LLVMBuildExtractElement(gallivm->builder, interp_param,
1207 ctx->i32_1, "");
1208 }
1209
1210 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1211 ctx->shader->key.part.ps.prolog.color_two_side) {
1212 LLVMValueRef is_face_positive;
1213 LLVMValueRef back_attr_number;
1214
1215 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1216 * otherwise it's at offset "num_inputs".
1217 */
1218 unsigned back_attr_offset = num_interp_inputs;
1219 if (semantic_index == 1 && colors_read_mask & 0xf)
1220 back_attr_offset += 1;
1221
1222 back_attr_number = LLVMConstInt(ctx->i32, back_attr_offset, 0);
1223
1224 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1225 face, ctx->i32_0, "");
1226
1227 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1228 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
1229 LLVMValueRef front, back;
1230
1231 if (interp) {
1232 front = ac_build_fs_interp(&ctx->ac, llvm_chan,
1233 attr_number, prim_mask,
1234 i, j);
1235 back = ac_build_fs_interp(&ctx->ac, llvm_chan,
1236 back_attr_number, prim_mask,
1237 i, j);
1238 } else {
1239 front = ac_build_fs_interp_mov(&ctx->ac,
1240 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1241 llvm_chan, attr_number, prim_mask);
1242 back = ac_build_fs_interp_mov(&ctx->ac,
1243 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1244 llvm_chan, back_attr_number, prim_mask);
1245 }
1246
1247 result[chan] = LLVMBuildSelect(gallivm->builder,
1248 is_face_positive,
1249 front,
1250 back,
1251 "");
1252 }
1253 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1254 if (interp) {
1255 result[0] = ac_build_fs_interp(&ctx->ac, ctx->i32_0,
1256 attr_number, prim_mask, i, j);
1257 } else {
1258 result[0] = ac_build_fs_interp_mov(&ctx->ac, ctx->i32_0,
1259 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1260 attr_number, prim_mask);
1261 }
1262 result[1] =
1263 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1264 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1265 } else {
1266 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1267 LLVMValueRef llvm_chan = LLVMConstInt(ctx->i32, chan, 0);
1268
1269 if (interp) {
1270 result[chan] = ac_build_fs_interp(&ctx->ac,
1271 llvm_chan, attr_number, prim_mask, i, j);
1272 } else {
1273 result[chan] = ac_build_fs_interp_mov(&ctx->ac,
1274 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1275 llvm_chan, attr_number, prim_mask);
1276 }
1277 }
1278 }
1279 }
1280
1281 static void declare_input_fs(
1282 struct si_shader_context *ctx,
1283 unsigned input_index,
1284 const struct tgsi_full_declaration *decl,
1285 LLVMValueRef out[4])
1286 {
1287 struct lp_build_context *base = &ctx->bld_base.base;
1288 struct si_shader *shader = ctx->shader;
1289 LLVMValueRef main_fn = ctx->main_fn;
1290 LLVMValueRef interp_param = NULL;
1291 int interp_param_idx;
1292
1293 /* Get colors from input VGPRs (set by the prolog). */
1294 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1295 unsigned i = decl->Semantic.Index;
1296 unsigned colors_read = shader->selector->info.colors_read;
1297 unsigned mask = colors_read >> (i * 4);
1298 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1299 (i ? util_bitcount(colors_read & 0xf) : 0);
1300
1301 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1302 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1303 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1304 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1305 return;
1306 }
1307
1308 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1309 decl->Interp.Location);
1310 if (interp_param_idx == -1)
1311 return;
1312 else if (interp_param_idx) {
1313 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1314 }
1315
1316 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1317 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1318 ctx->shader->key.part.ps.prolog.flatshade_colors)
1319 interp_param = NULL; /* load the constant color */
1320
1321 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1322 decl->Semantic.Index, shader->selector->info.num_inputs,
1323 shader->selector->info.colors_read, interp_param,
1324 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1325 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1326 &out[0]);
1327 }
1328
1329 static LLVMValueRef get_sample_id(struct si_shader_context *ctx)
1330 {
1331 return unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1332 }
1333
1334
1335 /**
1336 * Load a dword from a constant buffer.
1337 */
1338 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1339 LLVMValueRef resource,
1340 LLVMValueRef offset)
1341 {
1342 LLVMBuilderRef builder = ctx->gallivm.builder;
1343 LLVMValueRef args[2] = {resource, offset};
1344
1345 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1346 LP_FUNC_ATTR_READNONE |
1347 LP_FUNC_ATTR_LEGACY);
1348 }
1349
1350 static LLVMValueRef load_sample_position(struct si_shader_context *ctx, LLVMValueRef sample_id)
1351 {
1352 struct lp_build_context *uint_bld = &ctx->bld_base.uint_bld;
1353 struct gallivm_state *gallivm = &ctx->gallivm;
1354 LLVMBuilderRef builder = gallivm->builder;
1355 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1356 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1357 LLVMValueRef resource = ac_build_indexed_load_const(&ctx->ac, desc, buf_index);
1358
1359 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1360 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1361 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1362
1363 LLVMValueRef pos[4] = {
1364 buffer_load_const(ctx, resource, offset0),
1365 buffer_load_const(ctx, resource, offset1),
1366 LLVMConstReal(ctx->f32, 0),
1367 LLVMConstReal(ctx->f32, 0)
1368 };
1369
1370 return lp_build_gather_values(gallivm, pos, 4);
1371 }
1372
1373 static void declare_system_value(struct si_shader_context *ctx,
1374 unsigned index,
1375 const struct tgsi_full_declaration *decl)
1376 {
1377 struct lp_build_context *bld = &ctx->bld_base.base;
1378 struct gallivm_state *gallivm = &ctx->gallivm;
1379 LLVMValueRef value = 0;
1380
1381 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
1382
1383 switch (decl->Semantic.Name) {
1384 case TGSI_SEMANTIC_INSTANCEID:
1385 value = LLVMGetParam(ctx->main_fn,
1386 ctx->param_instance_id);
1387 break;
1388
1389 case TGSI_SEMANTIC_VERTEXID:
1390 value = LLVMBuildAdd(gallivm->builder,
1391 LLVMGetParam(ctx->main_fn,
1392 ctx->param_vertex_id),
1393 LLVMGetParam(ctx->main_fn,
1394 SI_PARAM_BASE_VERTEX), "");
1395 break;
1396
1397 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1398 /* Unused. Clarify the meaning in indexed vs. non-indexed
1399 * draws if this is ever used again. */
1400 assert(false);
1401 break;
1402
1403 case TGSI_SEMANTIC_BASEVERTEX:
1404 value = LLVMGetParam(ctx->main_fn,
1405 SI_PARAM_BASE_VERTEX);
1406 break;
1407
1408 case TGSI_SEMANTIC_BASEINSTANCE:
1409 value = LLVMGetParam(ctx->main_fn,
1410 SI_PARAM_START_INSTANCE);
1411 break;
1412
1413 case TGSI_SEMANTIC_DRAWID:
1414 value = LLVMGetParam(ctx->main_fn,
1415 SI_PARAM_DRAWID);
1416 break;
1417
1418 case TGSI_SEMANTIC_INVOCATIONID:
1419 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1420 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1421 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1422 value = LLVMGetParam(ctx->main_fn,
1423 SI_PARAM_GS_INSTANCE_ID);
1424 else
1425 assert(!"INVOCATIONID not implemented");
1426 break;
1427
1428 case TGSI_SEMANTIC_POSITION:
1429 {
1430 LLVMValueRef pos[4] = {
1431 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1432 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1433 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
1434 lp_build_emit_llvm_unary(&ctx->bld_base, TGSI_OPCODE_RCP,
1435 LLVMGetParam(ctx->main_fn,
1436 SI_PARAM_POS_W_FLOAT)),
1437 };
1438 value = lp_build_gather_values(gallivm, pos, 4);
1439 break;
1440 }
1441
1442 case TGSI_SEMANTIC_FACE:
1443 value = LLVMGetParam(ctx->main_fn, SI_PARAM_FRONT_FACE);
1444 break;
1445
1446 case TGSI_SEMANTIC_SAMPLEID:
1447 value = get_sample_id(ctx);
1448 break;
1449
1450 case TGSI_SEMANTIC_SAMPLEPOS: {
1451 LLVMValueRef pos[4] = {
1452 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
1453 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
1454 LLVMConstReal(ctx->f32, 0),
1455 LLVMConstReal(ctx->f32, 0)
1456 };
1457 pos[0] = lp_build_emit_llvm_unary(&ctx->bld_base,
1458 TGSI_OPCODE_FRC, pos[0]);
1459 pos[1] = lp_build_emit_llvm_unary(&ctx->bld_base,
1460 TGSI_OPCODE_FRC, pos[1]);
1461 value = lp_build_gather_values(gallivm, pos, 4);
1462 break;
1463 }
1464
1465 case TGSI_SEMANTIC_SAMPLEMASK:
1466 /* This can only occur with the OpenGL Core profile, which
1467 * doesn't support smoothing.
1468 */
1469 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1470 break;
1471
1472 case TGSI_SEMANTIC_TESSCOORD:
1473 {
1474 LLVMValueRef coord[4] = {
1475 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1476 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1477 bld->zero,
1478 bld->zero
1479 };
1480
1481 /* For triangles, the vector should be (u, v, 1-u-v). */
1482 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1483 PIPE_PRIM_TRIANGLES)
1484 coord[2] = lp_build_sub(bld, bld->one,
1485 lp_build_add(bld, coord[0], coord[1]));
1486
1487 value = lp_build_gather_values(gallivm, coord, 4);
1488 break;
1489 }
1490
1491 case TGSI_SEMANTIC_VERTICESIN:
1492 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1493 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1494 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1495 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1496 else
1497 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1498 break;
1499
1500 case TGSI_SEMANTIC_TESSINNER:
1501 case TGSI_SEMANTIC_TESSOUTER:
1502 {
1503 LLVMValueRef rw_buffers, buffer, base, addr;
1504 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1505
1506 rw_buffers = LLVMGetParam(ctx->main_fn,
1507 SI_PARAM_RW_BUFFERS);
1508 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
1509 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
1510
1511 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
1512 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1513 LLVMConstInt(ctx->i32, param, 0));
1514
1515 value = buffer_load(&ctx->bld_base, TGSI_TYPE_FLOAT,
1516 ~0, buffer, base, addr, true);
1517
1518 break;
1519 }
1520
1521 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1522 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1523 {
1524 LLVMValueRef buf, slot, val[4];
1525 int i, offset;
1526
1527 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1528 buf = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
1529 buf = ac_build_indexed_load_const(&ctx->ac, buf, slot);
1530 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1531
1532 for (i = 0; i < 4; i++)
1533 val[i] = buffer_load_const(ctx, buf,
1534 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1535 value = lp_build_gather_values(gallivm, val, 4);
1536 break;
1537 }
1538
1539 case TGSI_SEMANTIC_PRIMID:
1540 value = get_primitive_id(&ctx->bld_base, 0);
1541 break;
1542
1543 case TGSI_SEMANTIC_GRID_SIZE:
1544 value = LLVMGetParam(ctx->main_fn, SI_PARAM_GRID_SIZE);
1545 break;
1546
1547 case TGSI_SEMANTIC_BLOCK_SIZE:
1548 {
1549 LLVMValueRef values[3];
1550 unsigned i;
1551 unsigned *properties = ctx->shader->selector->info.properties;
1552
1553 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1554 unsigned sizes[3] = {
1555 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1556 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1557 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1558 };
1559
1560 for (i = 0; i < 3; ++i)
1561 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1562
1563 value = lp_build_gather_values(gallivm, values, 3);
1564 } else {
1565 value = LLVMGetParam(ctx->main_fn, SI_PARAM_BLOCK_SIZE);
1566 }
1567 break;
1568 }
1569
1570 case TGSI_SEMANTIC_BLOCK_ID:
1571 value = LLVMGetParam(ctx->main_fn, SI_PARAM_BLOCK_ID);
1572 break;
1573
1574 case TGSI_SEMANTIC_THREAD_ID:
1575 value = LLVMGetParam(ctx->main_fn, SI_PARAM_THREAD_ID);
1576 break;
1577
1578 case TGSI_SEMANTIC_HELPER_INVOCATION:
1579 if (HAVE_LLVM >= 0x0309) {
1580 value = lp_build_intrinsic(gallivm->builder,
1581 "llvm.amdgcn.ps.live",
1582 ctx->i1, NULL, 0,
1583 LP_FUNC_ATTR_READNONE);
1584 value = LLVMBuildNot(gallivm->builder, value, "");
1585 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1586 } else {
1587 assert(!"TGSI_SEMANTIC_HELPER_INVOCATION unsupported");
1588 return;
1589 }
1590 break;
1591
1592 case TGSI_SEMANTIC_SUBGROUP_SIZE:
1593 value = LLVMConstInt(ctx->i32, 64, 0);
1594 break;
1595
1596 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
1597 value = ac_get_thread_id(&ctx->ac);
1598 break;
1599
1600 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
1601 {
1602 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1603 id = LLVMBuildZExt(gallivm->builder, id, ctx->i64, "");
1604 value = LLVMBuildShl(gallivm->builder, LLVMConstInt(ctx->i64, 1, 0), id, "");
1605 value = LLVMBuildBitCast(gallivm->builder, value, ctx->v2i32, "");
1606 break;
1607 }
1608
1609 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
1610 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
1611 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
1612 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
1613 {
1614 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
1615 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
1616 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
1617 /* All bits set except LSB */
1618 value = LLVMConstInt(ctx->i64, -2, 0);
1619 } else {
1620 /* All bits set */
1621 value = LLVMConstInt(ctx->i64, -1, 0);
1622 }
1623 id = LLVMBuildZExt(gallivm->builder, id, ctx->i64, "");
1624 value = LLVMBuildShl(gallivm->builder, value, id, "");
1625 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
1626 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
1627 value = LLVMBuildNot(gallivm->builder, value, "");
1628 value = LLVMBuildBitCast(gallivm->builder, value, ctx->v2i32, "");
1629 break;
1630 }
1631
1632 default:
1633 assert(!"unknown system value");
1634 return;
1635 }
1636
1637 ctx->system_values[index] = value;
1638 }
1639
1640 static void declare_compute_memory(struct si_shader_context *ctx,
1641 const struct tgsi_full_declaration *decl)
1642 {
1643 struct si_shader_selector *sel = ctx->shader->selector;
1644 struct gallivm_state *gallivm = &ctx->gallivm;
1645
1646 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1647 LLVMValueRef var;
1648
1649 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1650 assert(decl->Range.First == decl->Range.Last);
1651 assert(!ctx->shared_memory);
1652
1653 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1654 LLVMArrayType(ctx->i8, sel->local_size),
1655 "compute_lds",
1656 LOCAL_ADDR_SPACE);
1657 LLVMSetAlignment(var, 4);
1658
1659 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1660 }
1661
1662 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1663 {
1664 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
1665 SI_PARAM_CONST_BUFFERS);
1666
1667 return ac_build_indexed_load_const(&ctx->ac, list_ptr,
1668 LLVMConstInt(ctx->i32, i, 0));
1669 }
1670
1671 static LLVMValueRef fetch_constant(
1672 struct lp_build_tgsi_context *bld_base,
1673 const struct tgsi_full_src_register *reg,
1674 enum tgsi_opcode_type type,
1675 unsigned swizzle)
1676 {
1677 struct si_shader_context *ctx = si_shader_context(bld_base);
1678 struct lp_build_context *base = &bld_base->base;
1679 const struct tgsi_ind_register *ireg = &reg->Indirect;
1680 unsigned buf, idx;
1681
1682 LLVMValueRef addr, bufp;
1683 LLVMValueRef result;
1684
1685 if (swizzle == LP_CHAN_ALL) {
1686 unsigned chan;
1687 LLVMValueRef values[4];
1688 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1689 values[chan] = fetch_constant(bld_base, reg, type, chan);
1690
1691 return lp_build_gather_values(&ctx->gallivm, values, 4);
1692 }
1693
1694 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1695 idx = reg->Register.Index * 4 + swizzle;
1696
1697 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1698 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_CONST_BUFFERS);
1699 LLVMValueRef index;
1700 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1701 reg->Dimension.Index,
1702 SI_NUM_CONST_BUFFERS);
1703 bufp = ac_build_indexed_load_const(&ctx->ac, ptr, index);
1704 } else
1705 bufp = load_const_buffer_desc(ctx, buf);
1706
1707 if (reg->Register.Indirect) {
1708 addr = ctx->addrs[ireg->Index][ireg->Swizzle];
1709 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1710 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1711 addr = lp_build_add(&bld_base->uint_bld, addr,
1712 LLVMConstInt(ctx->i32, idx * 4, 0));
1713 } else {
1714 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
1715 }
1716
1717 result = buffer_load_const(ctx, bufp, addr);
1718
1719 if (!tgsi_type_is_64bit(type))
1720 result = bitcast(bld_base, type, result);
1721 else {
1722 LLVMValueRef addr2, result2;
1723
1724 addr2 = lp_build_add(&bld_base->uint_bld, addr,
1725 LLVMConstInt(ctx->i32, 4, 0));
1726 result2 = buffer_load_const(ctx, bufp, addr2);
1727
1728 result = si_llvm_emit_fetch_64bit(bld_base, type,
1729 result, result2);
1730 }
1731 return result;
1732 }
1733
1734 /* Upper 16 bits must be zero. */
1735 static LLVMValueRef si_llvm_pack_two_int16(struct si_shader_context *ctx,
1736 LLVMValueRef val[2])
1737 {
1738 return LLVMBuildOr(ctx->gallivm.builder, val[0],
1739 LLVMBuildShl(ctx->gallivm.builder, val[1],
1740 LLVMConstInt(ctx->i32, 16, 0),
1741 ""), "");
1742 }
1743
1744 /* Upper 16 bits are ignored and will be dropped. */
1745 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct si_shader_context *ctx,
1746 LLVMValueRef val[2])
1747 {
1748 LLVMValueRef v[2] = {
1749 LLVMBuildAnd(ctx->gallivm.builder, val[0],
1750 LLVMConstInt(ctx->i32, 0xffff, 0), ""),
1751 val[1],
1752 };
1753 return si_llvm_pack_two_int16(ctx, v);
1754 }
1755
1756 /* Initialize arguments for the shader export intrinsic */
1757 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1758 LLVMValueRef *values,
1759 unsigned target,
1760 struct ac_export_args *args)
1761 {
1762 struct si_shader_context *ctx = si_shader_context(bld_base);
1763 struct lp_build_context *base = &bld_base->base;
1764 LLVMBuilderRef builder = ctx->gallivm.builder;
1765 LLVMValueRef val[4];
1766 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1767 unsigned chan;
1768 bool is_int8, is_int10;
1769
1770 /* Default is 0xf. Adjusted below depending on the format. */
1771 args->enabled_channels = 0xf; /* writemask */
1772
1773 /* Specify whether the EXEC mask represents the valid mask */
1774 args->valid_mask = 0;
1775
1776 /* Specify whether this is the last export */
1777 args->done = 0;
1778
1779 /* Specify the target we are exporting */
1780 args->target = target;
1781
1782 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1783 const struct si_shader_key *key = &ctx->shader->key;
1784 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
1785 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1786
1787 assert(cbuf >= 0 && cbuf < 8);
1788 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1789 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
1790 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
1791 }
1792
1793 args->compr = false;
1794 args->out[0] = base->undef;
1795 args->out[1] = base->undef;
1796 args->out[2] = base->undef;
1797 args->out[3] = base->undef;
1798
1799 switch (spi_shader_col_format) {
1800 case V_028714_SPI_SHADER_ZERO:
1801 args->enabled_channels = 0; /* writemask */
1802 args->target = V_008DFC_SQ_EXP_NULL;
1803 break;
1804
1805 case V_028714_SPI_SHADER_32_R:
1806 args->enabled_channels = 1; /* writemask */
1807 args->out[0] = values[0];
1808 break;
1809
1810 case V_028714_SPI_SHADER_32_GR:
1811 args->enabled_channels = 0x3; /* writemask */
1812 args->out[0] = values[0];
1813 args->out[1] = values[1];
1814 break;
1815
1816 case V_028714_SPI_SHADER_32_AR:
1817 args->enabled_channels = 0x9; /* writemask */
1818 args->out[0] = values[0];
1819 args->out[3] = values[3];
1820 break;
1821
1822 case V_028714_SPI_SHADER_FP16_ABGR:
1823 args->compr = 1; /* COMPR flag */
1824
1825 for (chan = 0; chan < 2; chan++) {
1826 LLVMValueRef pack_args[2] = {
1827 values[2 * chan],
1828 values[2 * chan + 1]
1829 };
1830 LLVMValueRef packed;
1831
1832 packed = ac_build_cvt_pkrtz_f16(&ctx->ac, pack_args);
1833 args->out[chan] =
1834 LLVMBuildBitCast(ctx->gallivm.builder,
1835 packed, ctx->f32, "");
1836 }
1837 break;
1838
1839 case V_028714_SPI_SHADER_UNORM16_ABGR:
1840 for (chan = 0; chan < 4; chan++) {
1841 val[chan] = ac_build_clamp(&ctx->ac, values[chan]);
1842 val[chan] = LLVMBuildFMul(builder, val[chan],
1843 LLVMConstReal(ctx->f32, 65535), "");
1844 val[chan] = LLVMBuildFAdd(builder, val[chan],
1845 LLVMConstReal(ctx->f32, 0.5), "");
1846 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1847 ctx->i32, "");
1848 }
1849
1850 args->compr = 1; /* COMPR flag */
1851 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1852 si_llvm_pack_two_int16(ctx, val));
1853 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1854 si_llvm_pack_two_int16(ctx, val+2));
1855 break;
1856
1857 case V_028714_SPI_SHADER_SNORM16_ABGR:
1858 for (chan = 0; chan < 4; chan++) {
1859 /* Clamp between [-1, 1]. */
1860 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1861 values[chan],
1862 LLVMConstReal(ctx->f32, 1));
1863 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1864 val[chan],
1865 LLVMConstReal(ctx->f32, -1));
1866 /* Convert to a signed integer in [-32767, 32767]. */
1867 val[chan] = LLVMBuildFMul(builder, val[chan],
1868 LLVMConstReal(ctx->f32, 32767), "");
1869 /* If positive, add 0.5, else add -0.5. */
1870 val[chan] = LLVMBuildFAdd(builder, val[chan],
1871 LLVMBuildSelect(builder,
1872 LLVMBuildFCmp(builder, LLVMRealOGE,
1873 val[chan], base->zero, ""),
1874 LLVMConstReal(ctx->f32, 0.5),
1875 LLVMConstReal(ctx->f32, -0.5), ""), "");
1876 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
1877 }
1878
1879 args->compr = 1; /* COMPR flag */
1880 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1881 si_llvm_pack_two_int32_as_int16(ctx, val));
1882 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1883 si_llvm_pack_two_int32_as_int16(ctx, val+2));
1884 break;
1885
1886 case V_028714_SPI_SHADER_UINT16_ABGR: {
1887 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
1888 is_int8 ? 255 : is_int10 ? 1023 : 65535, 0);
1889 LLVMValueRef max_alpha =
1890 !is_int10 ? max_rgb : LLVMConstInt(ctx->i32, 3, 0);
1891
1892 /* Clamp. */
1893 for (chan = 0; chan < 4; chan++) {
1894 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1895 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1896 val[chan],
1897 chan == 3 ? max_alpha : max_rgb);
1898 }
1899
1900 args->compr = 1; /* COMPR flag */
1901 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1902 si_llvm_pack_two_int16(ctx, val));
1903 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1904 si_llvm_pack_two_int16(ctx, val+2));
1905 break;
1906 }
1907
1908 case V_028714_SPI_SHADER_SINT16_ABGR: {
1909 LLVMValueRef max_rgb = LLVMConstInt(ctx->i32,
1910 is_int8 ? 127 : is_int10 ? 511 : 32767, 0);
1911 LLVMValueRef min_rgb = LLVMConstInt(ctx->i32,
1912 is_int8 ? -128 : is_int10 ? -512 : -32768, 0);
1913 LLVMValueRef max_alpha =
1914 !is_int10 ? max_rgb : ctx->i32_1;
1915 LLVMValueRef min_alpha =
1916 !is_int10 ? min_rgb : LLVMConstInt(ctx->i32, -2, 0);
1917
1918 /* Clamp. */
1919 for (chan = 0; chan < 4; chan++) {
1920 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1921 val[chan] = lp_build_emit_llvm_binary(bld_base,
1922 TGSI_OPCODE_IMIN,
1923 val[chan], chan == 3 ? max_alpha : max_rgb);
1924 val[chan] = lp_build_emit_llvm_binary(bld_base,
1925 TGSI_OPCODE_IMAX,
1926 val[chan], chan == 3 ? min_alpha : min_rgb);
1927 }
1928
1929 args->compr = 1; /* COMPR flag */
1930 args->out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1931 si_llvm_pack_two_int32_as_int16(ctx, val));
1932 args->out[1] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1933 si_llvm_pack_two_int32_as_int16(ctx, val+2));
1934 break;
1935 }
1936
1937 case V_028714_SPI_SHADER_32_ABGR:
1938 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1939 break;
1940 }
1941 }
1942
1943 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1944 LLVMValueRef alpha)
1945 {
1946 struct si_shader_context *ctx = si_shader_context(bld_base);
1947
1948 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
1949 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
1950 SI_PARAM_ALPHA_REF);
1951
1952 LLVMValueRef alpha_pass =
1953 lp_build_cmp(&bld_base->base,
1954 ctx->shader->key.part.ps.epilog.alpha_func,
1955 alpha, alpha_ref);
1956 LLVMValueRef arg =
1957 lp_build_select(&bld_base->base,
1958 alpha_pass,
1959 LLVMConstReal(ctx->f32, 1.0f),
1960 LLVMConstReal(ctx->f32, -1.0f));
1961
1962 ac_build_kill(&ctx->ac, arg);
1963 } else {
1964 ac_build_kill(&ctx->ac, NULL);
1965 }
1966 }
1967
1968 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1969 LLVMValueRef alpha,
1970 unsigned samplemask_param)
1971 {
1972 struct si_shader_context *ctx = si_shader_context(bld_base);
1973 struct gallivm_state *gallivm = &ctx->gallivm;
1974 LLVMValueRef coverage;
1975
1976 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1977 coverage = LLVMGetParam(ctx->main_fn,
1978 samplemask_param);
1979 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1980
1981 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1982 ctx->i32,
1983 &coverage, 1, LP_FUNC_ATTR_READNONE);
1984
1985 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1986 ctx->f32, "");
1987
1988 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1989 LLVMConstReal(ctx->f32,
1990 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1991
1992 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1993 }
1994
1995 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
1996 struct ac_export_args *pos, LLVMValueRef *out_elts)
1997 {
1998 struct si_shader_context *ctx = si_shader_context(bld_base);
1999 struct lp_build_context *base = &bld_base->base;
2000 unsigned reg_index;
2001 unsigned chan;
2002 unsigned const_chan;
2003 LLVMValueRef base_elt;
2004 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2005 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2006 SI_VS_CONST_CLIP_PLANES, 0);
2007 LLVMValueRef const_resource = ac_build_indexed_load_const(&ctx->ac, ptr, constbuf_index);
2008
2009 for (reg_index = 0; reg_index < 2; reg_index ++) {
2010 struct ac_export_args *args = &pos[2 + reg_index];
2011
2012 args->out[0] =
2013 args->out[1] =
2014 args->out[2] =
2015 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2016
2017 /* Compute dot products of position and user clip plane vectors */
2018 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2019 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2020 LLVMValueRef addr =
2021 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2022 const_chan) * 4, 0);
2023 base_elt = buffer_load_const(ctx, const_resource,
2024 addr);
2025 args->out[chan] =
2026 lp_build_add(base, args->out[chan],
2027 lp_build_mul(base, base_elt,
2028 out_elts[const_chan]));
2029 }
2030 }
2031
2032 args->enabled_channels = 0xf;
2033 args->valid_mask = 0;
2034 args->done = 0;
2035 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2036 args->compr = 0;
2037 }
2038 }
2039
2040 static void si_dump_streamout(struct pipe_stream_output_info *so)
2041 {
2042 unsigned i;
2043
2044 if (so->num_outputs)
2045 fprintf(stderr, "STREAMOUT\n");
2046
2047 for (i = 0; i < so->num_outputs; i++) {
2048 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2049 so->output[i].start_component;
2050 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2051 i, so->output[i].output_buffer,
2052 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2053 so->output[i].register_index,
2054 mask & 1 ? "x" : "",
2055 mask & 2 ? "y" : "",
2056 mask & 4 ? "z" : "",
2057 mask & 8 ? "w" : "");
2058 }
2059 }
2060
2061 static void emit_streamout_output(struct si_shader_context *ctx,
2062 LLVMValueRef const *so_buffers,
2063 LLVMValueRef const *so_write_offsets,
2064 struct pipe_stream_output *stream_out,
2065 struct si_shader_output_values *shader_out)
2066 {
2067 struct gallivm_state *gallivm = &ctx->gallivm;
2068 LLVMBuilderRef builder = gallivm->builder;
2069 unsigned buf_idx = stream_out->output_buffer;
2070 unsigned start = stream_out->start_component;
2071 unsigned num_comps = stream_out->num_components;
2072 LLVMValueRef out[4];
2073
2074 assert(num_comps && num_comps <= 4);
2075 if (!num_comps || num_comps > 4)
2076 return;
2077
2078 /* Load the output as int. */
2079 for (int j = 0; j < num_comps; j++) {
2080 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2081
2082 out[j] = LLVMBuildBitCast(builder,
2083 shader_out->values[start + j],
2084 ctx->i32, "");
2085 }
2086
2087 /* Pack the output. */
2088 LLVMValueRef vdata = NULL;
2089
2090 switch (num_comps) {
2091 case 1: /* as i32 */
2092 vdata = out[0];
2093 break;
2094 case 2: /* as v2i32 */
2095 case 3: /* as v4i32 (aligned to 4) */
2096 case 4: /* as v4i32 */
2097 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2098 for (int j = 0; j < num_comps; j++) {
2099 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2100 LLVMConstInt(ctx->i32, j, 0), "");
2101 }
2102 break;
2103 }
2104
2105 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2106 vdata, num_comps,
2107 so_write_offsets[buf_idx],
2108 ctx->i32_0,
2109 stream_out->dst_offset * 4, 1, 1, true, false);
2110 }
2111
2112 /**
2113 * Write streamout data to buffers for vertex stream @p stream (different
2114 * vertex streams can occur for GS copy shaders).
2115 */
2116 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2117 struct si_shader_output_values *outputs,
2118 unsigned noutput, unsigned stream)
2119 {
2120 struct si_shader_selector *sel = ctx->shader->selector;
2121 struct pipe_stream_output_info *so = &sel->so;
2122 struct gallivm_state *gallivm = &ctx->gallivm;
2123 LLVMBuilderRef builder = gallivm->builder;
2124 int i;
2125 struct lp_build_if_state if_ctx;
2126
2127 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2128 LLVMValueRef so_vtx_count =
2129 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2130
2131 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2132
2133 /* can_emit = tid < so_vtx_count; */
2134 LLVMValueRef can_emit =
2135 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2136
2137 /* Emit the streamout code conditionally. This actually avoids
2138 * out-of-bounds buffer access. The hw tells us via the SGPR
2139 * (so_vtx_count) which threads are allowed to emit streamout data. */
2140 lp_build_if(&if_ctx, gallivm, can_emit);
2141 {
2142 /* The buffer offset is computed as follows:
2143 * ByteOffset = streamout_offset[buffer_id]*4 +
2144 * (streamout_write_index + thread_id)*stride[buffer_id] +
2145 * attrib_offset
2146 */
2147
2148 LLVMValueRef so_write_index =
2149 LLVMGetParam(ctx->main_fn,
2150 ctx->param_streamout_write_index);
2151
2152 /* Compute (streamout_write_index + thread_id). */
2153 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2154
2155 /* Load the descriptor and compute the write offset for each
2156 * enabled buffer. */
2157 LLVMValueRef so_write_offset[4] = {};
2158 LLVMValueRef so_buffers[4];
2159 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2160 SI_PARAM_RW_BUFFERS);
2161
2162 for (i = 0; i < 4; i++) {
2163 if (!so->stride[i])
2164 continue;
2165
2166 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2167 SI_VS_STREAMOUT_BUF0 + i, 0);
2168
2169 so_buffers[i] = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
2170
2171 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2172 ctx->param_streamout_offset[i]);
2173 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2174
2175 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2176 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2177 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2178 }
2179
2180 /* Write streamout data. */
2181 for (i = 0; i < so->num_outputs; i++) {
2182 unsigned reg = so->output[i].register_index;
2183
2184 if (reg >= noutput)
2185 continue;
2186
2187 if (stream != so->output[i].stream)
2188 continue;
2189
2190 emit_streamout_output(ctx, so_buffers, so_write_offset,
2191 &so->output[i], &outputs[reg]);
2192 }
2193 }
2194 lp_build_endif(&if_ctx);
2195 }
2196
2197
2198 /* Generate export instructions for hardware VS shader stage */
2199 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2200 struct si_shader_output_values *outputs,
2201 unsigned noutput)
2202 {
2203 struct si_shader_context *ctx = si_shader_context(bld_base);
2204 struct si_shader *shader = ctx->shader;
2205 struct lp_build_context *base = &bld_base->base;
2206 struct ac_export_args args, pos_args[4] = {};
2207 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2208 unsigned semantic_name, semantic_index;
2209 unsigned target;
2210 unsigned param_count = 0;
2211 unsigned pos_idx;
2212 int i;
2213
2214 for (i = 0; i < noutput; i++) {
2215 semantic_name = outputs[i].semantic_name;
2216 semantic_index = outputs[i].semantic_index;
2217 bool export_param = true;
2218
2219 switch (semantic_name) {
2220 case TGSI_SEMANTIC_POSITION: /* ignore these */
2221 case TGSI_SEMANTIC_PSIZE:
2222 case TGSI_SEMANTIC_CLIPVERTEX:
2223 case TGSI_SEMANTIC_EDGEFLAG:
2224 break;
2225 case TGSI_SEMANTIC_GENERIC:
2226 case TGSI_SEMANTIC_CLIPDIST:
2227 if (shader->key.opt.hw_vs.kill_outputs &
2228 (1ull << si_shader_io_get_unique_index(semantic_name, semantic_index)))
2229 export_param = false;
2230 break;
2231 default:
2232 if (shader->key.opt.hw_vs.kill_outputs2 &
2233 (1u << si_shader_io_get_unique_index2(semantic_name, semantic_index)))
2234 export_param = false;
2235 break;
2236 }
2237
2238 if (outputs[i].vertex_stream[0] != 0 &&
2239 outputs[i].vertex_stream[1] != 0 &&
2240 outputs[i].vertex_stream[2] != 0 &&
2241 outputs[i].vertex_stream[3] != 0)
2242 export_param = false;
2243
2244 handle_semantic:
2245 /* Select the correct target */
2246 switch(semantic_name) {
2247 case TGSI_SEMANTIC_PSIZE:
2248 psize_value = outputs[i].values[0];
2249 continue;
2250 case TGSI_SEMANTIC_EDGEFLAG:
2251 edgeflag_value = outputs[i].values[0];
2252 continue;
2253 case TGSI_SEMANTIC_LAYER:
2254 layer_value = outputs[i].values[0];
2255 semantic_name = TGSI_SEMANTIC_GENERIC;
2256 goto handle_semantic;
2257 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2258 viewport_index_value = outputs[i].values[0];
2259 semantic_name = TGSI_SEMANTIC_GENERIC;
2260 goto handle_semantic;
2261 case TGSI_SEMANTIC_POSITION:
2262 target = V_008DFC_SQ_EXP_POS;
2263 break;
2264 case TGSI_SEMANTIC_CLIPDIST:
2265 if (shader->key.opt.hw_vs.clip_disable) {
2266 semantic_name = TGSI_SEMANTIC_GENERIC;
2267 goto handle_semantic;
2268 }
2269 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2270 break;
2271 case TGSI_SEMANTIC_CLIPVERTEX:
2272 if (shader->key.opt.hw_vs.clip_disable)
2273 continue;
2274 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2275 continue;
2276 case TGSI_SEMANTIC_COLOR:
2277 case TGSI_SEMANTIC_BCOLOR:
2278 case TGSI_SEMANTIC_PRIMID:
2279 case TGSI_SEMANTIC_FOG:
2280 case TGSI_SEMANTIC_TEXCOORD:
2281 case TGSI_SEMANTIC_GENERIC:
2282 if (!export_param)
2283 continue;
2284 target = V_008DFC_SQ_EXP_PARAM + param_count;
2285 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2286 shader->info.vs_output_param_offset[i] = param_count;
2287 param_count++;
2288 break;
2289 default:
2290 target = 0;
2291 fprintf(stderr,
2292 "Warning: SI unhandled vs output type:%d\n",
2293 semantic_name);
2294 }
2295
2296 si_llvm_init_export_args(bld_base, outputs[i].values, target, &args);
2297
2298 if (target >= V_008DFC_SQ_EXP_POS &&
2299 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2300 memcpy(&pos_args[target - V_008DFC_SQ_EXP_POS],
2301 &args, sizeof(args));
2302 } else {
2303 ac_build_export(&ctx->ac, &args);
2304 }
2305
2306 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2307 semantic_name = TGSI_SEMANTIC_GENERIC;
2308 goto handle_semantic;
2309 }
2310 }
2311
2312 shader->info.nr_param_exports = param_count;
2313
2314 /* We need to add the position output manually if it's missing. */
2315 if (!pos_args[0].out[0]) {
2316 pos_args[0].enabled_channels = 0xf; /* writemask */
2317 pos_args[0].valid_mask = 0; /* EXEC mask */
2318 pos_args[0].done = 0; /* last export? */
2319 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2320 pos_args[0].compr = 0; /* COMPR flag */
2321 pos_args[0].out[0] = base->zero; /* X */
2322 pos_args[0].out[1] = base->zero; /* Y */
2323 pos_args[0].out[2] = base->zero; /* Z */
2324 pos_args[0].out[3] = base->one; /* W */
2325 }
2326
2327 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2328 if (shader->selector->info.writes_psize ||
2329 shader->selector->info.writes_edgeflag ||
2330 shader->selector->info.writes_viewport_index ||
2331 shader->selector->info.writes_layer) {
2332 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2333 (shader->selector->info.writes_edgeflag << 1) |
2334 (shader->selector->info.writes_layer << 2) |
2335 (shader->selector->info.writes_viewport_index << 3);
2336 pos_args[1].valid_mask = 0; /* EXEC mask */
2337 pos_args[1].done = 0; /* last export? */
2338 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2339 pos_args[1].compr = 0; /* COMPR flag */
2340 pos_args[1].out[0] = base->zero; /* X */
2341 pos_args[1].out[1] = base->zero; /* Y */
2342 pos_args[1].out[2] = base->zero; /* Z */
2343 pos_args[1].out[3] = base->zero; /* W */
2344
2345 if (shader->selector->info.writes_psize)
2346 pos_args[1].out[0] = psize_value;
2347
2348 if (shader->selector->info.writes_edgeflag) {
2349 /* The output is a float, but the hw expects an integer
2350 * with the first bit containing the edge flag. */
2351 edgeflag_value = LLVMBuildFPToUI(ctx->gallivm.builder,
2352 edgeflag_value,
2353 ctx->i32, "");
2354 edgeflag_value = lp_build_min(&bld_base->int_bld,
2355 edgeflag_value,
2356 ctx->i32_1);
2357
2358 /* The LLVM intrinsic expects a float. */
2359 pos_args[1].out[1] = LLVMBuildBitCast(ctx->gallivm.builder,
2360 edgeflag_value,
2361 ctx->f32, "");
2362 }
2363
2364 if (shader->selector->info.writes_layer)
2365 pos_args[1].out[2] = layer_value;
2366
2367 if (shader->selector->info.writes_viewport_index)
2368 pos_args[1].out[3] = viewport_index_value;
2369 }
2370
2371 for (i = 0; i < 4; i++)
2372 if (pos_args[i].out[0])
2373 shader->info.nr_pos_exports++;
2374
2375 pos_idx = 0;
2376 for (i = 0; i < 4; i++) {
2377 if (!pos_args[i].out[0])
2378 continue;
2379
2380 /* Specify the target we are exporting */
2381 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2382
2383 if (pos_idx == shader->info.nr_pos_exports)
2384 /* Specify that this is the last export */
2385 pos_args[i].done = 1;
2386
2387 ac_build_export(&ctx->ac, &pos_args[i]);
2388 }
2389 }
2390
2391 /**
2392 * Forward all outputs from the vertex shader to the TES. This is only used
2393 * for the fixed function TCS.
2394 */
2395 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2396 {
2397 struct si_shader_context *ctx = si_shader_context(bld_base);
2398 struct gallivm_state *gallivm = &ctx->gallivm;
2399 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2400 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2401 uint64_t inputs;
2402
2403 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2404
2405 rw_buffers = LLVMGetParam(ctx->main_fn, SI_PARAM_RW_BUFFERS);
2406 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2407 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
2408
2409 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2410
2411 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2412 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2413 lds_vertex_stride, "");
2414 lds_base = get_tcs_in_current_patch_offset(ctx);
2415 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2416
2417 inputs = ctx->shader->key.mono.tcs.inputs_to_copy;
2418 while (inputs) {
2419 unsigned i = u_bit_scan64(&inputs);
2420
2421 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2422 LLVMConstInt(ctx->i32, 4 * i, 0),
2423 "");
2424
2425 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2426 get_rel_patch_id(ctx),
2427 invocation_id,
2428 LLVMConstInt(ctx->i32, i, 0));
2429
2430 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2431 lds_ptr);
2432
2433 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
2434 buffer_offset, 0, 1, 0, true, false);
2435 }
2436 }
2437
2438 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2439 LLVMValueRef rel_patch_id,
2440 LLVMValueRef invocation_id,
2441 LLVMValueRef tcs_out_current_patch_data_offset)
2442 {
2443 struct si_shader_context *ctx = si_shader_context(bld_base);
2444 struct gallivm_state *gallivm = &ctx->gallivm;
2445 struct si_shader *shader = ctx->shader;
2446 unsigned tess_inner_index, tess_outer_index;
2447 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2448 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base, inner[4], outer[4];
2449 unsigned stride, outer_comps, inner_comps, i;
2450 struct lp_build_if_state if_ctx, inner_if_ctx;
2451
2452 si_llvm_emit_barrier(NULL, bld_base, NULL);
2453
2454 /* Do this only for invocation 0, because the tess levels are per-patch,
2455 * not per-vertex.
2456 *
2457 * This can't jump, because invocation 0 executes this. It should
2458 * at least mask out the loads and stores for other invocations.
2459 */
2460 lp_build_if(&if_ctx, gallivm,
2461 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2462 invocation_id, ctx->i32_0, ""));
2463
2464 /* Determine the layout of one tess factor element in the buffer. */
2465 switch (shader->key.part.tcs.epilog.prim_mode) {
2466 case PIPE_PRIM_LINES:
2467 stride = 2; /* 2 dwords, 1 vec2 store */
2468 outer_comps = 2;
2469 inner_comps = 0;
2470 break;
2471 case PIPE_PRIM_TRIANGLES:
2472 stride = 4; /* 4 dwords, 1 vec4 store */
2473 outer_comps = 3;
2474 inner_comps = 1;
2475 break;
2476 case PIPE_PRIM_QUADS:
2477 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2478 outer_comps = 4;
2479 inner_comps = 2;
2480 break;
2481 default:
2482 assert(0);
2483 return;
2484 }
2485
2486 /* Load tess_inner and tess_outer from LDS.
2487 * Any invocation can write them, so we can't get them from a temporary.
2488 */
2489 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2490 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2491
2492 lds_base = tcs_out_current_patch_data_offset;
2493 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2494 LLVMConstInt(ctx->i32,
2495 tess_inner_index * 4, 0), "");
2496 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2497 LLVMConstInt(ctx->i32,
2498 tess_outer_index * 4, 0), "");
2499
2500 for (i = 0; i < 4; i++) {
2501 inner[i] = LLVMGetUndef(ctx->i32);
2502 outer[i] = LLVMGetUndef(ctx->i32);
2503 }
2504
2505 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
2506 /* For isolines, the hardware expects tess factors in the
2507 * reverse order from what GLSL / TGSI specify.
2508 */
2509 outer[0] = out[1] = lds_load(bld_base, TGSI_TYPE_SIGNED, 0, lds_outer);
2510 outer[1] = out[0] = lds_load(bld_base, TGSI_TYPE_SIGNED, 1, lds_outer);
2511 } else {
2512 for (i = 0; i < outer_comps; i++) {
2513 outer[i] = out[i] =
2514 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2515 }
2516 for (i = 0; i < inner_comps; i++) {
2517 inner[i] = out[outer_comps+i] =
2518 lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2519 }
2520 }
2521
2522 /* Convert the outputs to vectors for stores. */
2523 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2524 vec1 = NULL;
2525
2526 if (stride > 4)
2527 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2528
2529 /* Get the buffer. */
2530 rw_buffers = LLVMGetParam(ctx->main_fn,
2531 SI_PARAM_RW_BUFFERS);
2532 buffer = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2533 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_FACTOR, 0));
2534
2535 /* Get the offset. */
2536 tf_base = LLVMGetParam(ctx->main_fn,
2537 SI_PARAM_TESS_FACTOR_OFFSET);
2538 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2539 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
2540
2541 lp_build_if(&inner_if_ctx, gallivm,
2542 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2543 rel_patch_id, ctx->i32_0, ""));
2544
2545 /* Store the dynamic HS control word. */
2546 ac_build_buffer_store_dword(&ctx->ac, buffer,
2547 LLVMConstInt(ctx->i32, 0x80000000, 0),
2548 1, ctx->i32_0, tf_base,
2549 0, 1, 0, true, false);
2550
2551 lp_build_endif(&inner_if_ctx);
2552
2553 /* Store the tessellation factors. */
2554 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
2555 MIN2(stride, 4), byteoffset, tf_base,
2556 4, 1, 0, true, false);
2557 if (vec1)
2558 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
2559 stride - 4, byteoffset, tf_base,
2560 20, 1, 0, true, false);
2561
2562 /* Store the tess factors into the offchip buffer if TES reads them. */
2563 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
2564 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
2565 LLVMValueRef tf_inner_offset;
2566 unsigned param_outer, param_inner;
2567
2568 buf = ac_build_indexed_load_const(&ctx->ac, rw_buffers,
2569 LLVMConstInt(ctx->i32, SI_HS_RING_TESS_OFFCHIP, 0));
2570 base = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2571
2572 param_outer = si_shader_io_get_unique_index(
2573 TGSI_SEMANTIC_TESSOUTER, 0);
2574 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2575 LLVMConstInt(ctx->i32, param_outer, 0));
2576
2577 outer_vec = lp_build_gather_values(gallivm, outer,
2578 util_next_power_of_two(outer_comps));
2579
2580 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
2581 outer_comps, tf_outer_offset,
2582 base, 0, 1, 0, true, false);
2583 if (inner_comps) {
2584 param_inner = si_shader_io_get_unique_index(
2585 TGSI_SEMANTIC_TESSINNER, 0);
2586 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
2587 LLVMConstInt(ctx->i32, param_inner, 0));
2588
2589 inner_vec = inner_comps == 1 ? inner[0] :
2590 lp_build_gather_values(gallivm, inner, inner_comps);
2591 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
2592 inner_comps, tf_inner_offset,
2593 base, 0, 1, 0, true, false);
2594 }
2595 }
2596
2597 lp_build_endif(&if_ctx);
2598 }
2599
2600 /* This only writes the tessellation factor levels. */
2601 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2602 {
2603 struct si_shader_context *ctx = si_shader_context(bld_base);
2604 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2605 LLVMValueRef offchip_soffset, offchip_layout;
2606
2607 si_copy_tcs_inputs(bld_base);
2608
2609 rel_patch_id = get_rel_patch_id(ctx);
2610 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2611 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2612
2613 /* Return epilog parameters from this function. */
2614 LLVMBuilderRef builder = ctx->gallivm.builder;
2615 LLVMValueRef ret = ctx->return_value;
2616 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2617 unsigned vgpr;
2618
2619 /* RW_BUFFERS pointer */
2620 rw_buffers = LLVMGetParam(ctx->main_fn,
2621 SI_PARAM_RW_BUFFERS);
2622 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2623 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2624 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2625 ctx->i32_0, "");
2626 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2627 ctx->i32_1, "");
2628 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2629 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2630
2631 /* Tess offchip and factor buffer soffset are after user SGPRs. */
2632 offchip_layout = LLVMGetParam(ctx->main_fn,
2633 SI_PARAM_TCS_OFFCHIP_LAYOUT);
2634 offchip_soffset = LLVMGetParam(ctx->main_fn, ctx->param_oc_lds);
2635 tf_soffset = LLVMGetParam(ctx->main_fn,
2636 SI_PARAM_TESS_FACTOR_OFFSET);
2637 ret = LLVMBuildInsertValue(builder, ret, offchip_layout,
2638 SI_SGPR_TCS_OFFCHIP_LAYOUT, "");
2639 ret = LLVMBuildInsertValue(builder, ret, offchip_soffset,
2640 SI_TCS_NUM_USER_SGPR, "");
2641 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2642 SI_TCS_NUM_USER_SGPR + 1, "");
2643
2644 /* VGPRs */
2645 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2646 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2647 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2648
2649 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2650 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2651 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2652 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2653 ctx->return_value = ret;
2654 }
2655
2656 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2657 {
2658 struct si_shader_context *ctx = si_shader_context(bld_base);
2659 struct si_shader *shader = ctx->shader;
2660 struct tgsi_shader_info *info = &shader->selector->info;
2661 struct gallivm_state *gallivm = &ctx->gallivm;
2662 unsigned i, chan;
2663 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
2664 ctx->param_rel_auto_id);
2665 LLVMValueRef vertex_dw_stride =
2666 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2667 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2668 vertex_dw_stride, "");
2669
2670 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2671 * its inputs from it. */
2672 for (i = 0; i < info->num_outputs; i++) {
2673 LLVMValueRef *out_ptr = ctx->outputs[i];
2674 unsigned name = info->output_semantic_name[i];
2675 unsigned index = info->output_semantic_index[i];
2676 int param = si_shader_io_get_unique_index(name, index);
2677 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2678 LLVMConstInt(ctx->i32, param * 4, 0), "");
2679
2680 for (chan = 0; chan < 4; chan++) {
2681 lds_store(bld_base, chan, dw_addr,
2682 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2683 }
2684 }
2685 }
2686
2687 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2688 {
2689 struct si_shader_context *ctx = si_shader_context(bld_base);
2690 struct gallivm_state *gallivm = &ctx->gallivm;
2691 struct si_shader *es = ctx->shader;
2692 struct tgsi_shader_info *info = &es->selector->info;
2693 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
2694 ctx->param_es2gs_offset);
2695 unsigned chan;
2696 int i;
2697
2698 for (i = 0; i < info->num_outputs; i++) {
2699 LLVMValueRef *out_ptr = ctx->outputs[i];
2700 int param_index;
2701
2702 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2703 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2704 continue;
2705
2706 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2707 info->output_semantic_index[i]);
2708
2709 for (chan = 0; chan < 4; chan++) {
2710 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2711 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2712
2713 ac_build_buffer_store_dword(&ctx->ac,
2714 ctx->esgs_ring,
2715 out_val, 1, NULL, soffset,
2716 (4 * param_index + chan) * 4,
2717 1, 1, true, true);
2718 }
2719 }
2720 }
2721
2722 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2723 {
2724 struct si_shader_context *ctx = si_shader_context(bld_base);
2725
2726 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
2727 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
2728 }
2729
2730 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2731 {
2732 struct si_shader_context *ctx = si_shader_context(bld_base);
2733 struct gallivm_state *gallivm = &ctx->gallivm;
2734 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2735 struct si_shader_output_values *outputs = NULL;
2736 int i,j;
2737
2738 assert(!ctx->shader->is_gs_copy_shader);
2739
2740 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2741
2742 /* Vertex color clamping.
2743 *
2744 * This uses a state constant loaded in a user data SGPR and
2745 * an IF statement is added that clamps all colors if the constant
2746 * is true.
2747 */
2748 if (ctx->type == PIPE_SHADER_VERTEX) {
2749 struct lp_build_if_state if_ctx;
2750 LLVMValueRef cond = NULL;
2751 LLVMValueRef addr, val;
2752
2753 for (i = 0; i < info->num_outputs; i++) {
2754 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2755 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2756 continue;
2757
2758 /* We've found a color. */
2759 if (!cond) {
2760 /* The state is in the first bit of the user SGPR. */
2761 cond = LLVMGetParam(ctx->main_fn,
2762 SI_PARAM_VS_STATE_BITS);
2763 cond = LLVMBuildTrunc(gallivm->builder, cond,
2764 ctx->i1, "");
2765 lp_build_if(&if_ctx, gallivm, cond);
2766 }
2767
2768 for (j = 0; j < 4; j++) {
2769 addr = ctx->outputs[i][j];
2770 val = LLVMBuildLoad(gallivm->builder, addr, "");
2771 val = ac_build_clamp(&ctx->ac, val);
2772 LLVMBuildStore(gallivm->builder, val, addr);
2773 }
2774 }
2775
2776 if (cond)
2777 lp_build_endif(&if_ctx);
2778 }
2779
2780 for (i = 0; i < info->num_outputs; i++) {
2781 outputs[i].semantic_name = info->output_semantic_name[i];
2782 outputs[i].semantic_index = info->output_semantic_index[i];
2783
2784 for (j = 0; j < 4; j++) {
2785 outputs[i].values[j] =
2786 LLVMBuildLoad(gallivm->builder,
2787 ctx->outputs[i][j],
2788 "");
2789 outputs[i].vertex_stream[j] =
2790 (info->output_streams[i] >> (2 * j)) & 3;
2791 }
2792
2793 }
2794
2795 /* Return the primitive ID from the LLVM function. */
2796 ctx->return_value =
2797 LLVMBuildInsertValue(gallivm->builder,
2798 ctx->return_value,
2799 bitcast(bld_base, TGSI_TYPE_FLOAT,
2800 get_primitive_id(bld_base, 0)),
2801 VS_EPILOG_PRIMID_LOC, "");
2802
2803 if (ctx->shader->selector->so.num_outputs)
2804 si_llvm_emit_streamout(ctx, outputs, i, 0);
2805 si_llvm_export_vs(bld_base, outputs, i);
2806 FREE(outputs);
2807 }
2808
2809 struct si_ps_exports {
2810 unsigned num;
2811 struct ac_export_args args[10];
2812 };
2813
2814 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2815 bool writes_samplemask)
2816 {
2817 if (writes_z) {
2818 /* Z needs 32 bits. */
2819 if (writes_samplemask)
2820 return V_028710_SPI_SHADER_32_ABGR;
2821 else if (writes_stencil)
2822 return V_028710_SPI_SHADER_32_GR;
2823 else
2824 return V_028710_SPI_SHADER_32_R;
2825 } else if (writes_stencil || writes_samplemask) {
2826 /* Both stencil and sample mask need only 16 bits. */
2827 return V_028710_SPI_SHADER_UINT16_ABGR;
2828 } else {
2829 return V_028710_SPI_SHADER_ZERO;
2830 }
2831 }
2832
2833 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2834 LLVMValueRef depth, LLVMValueRef stencil,
2835 LLVMValueRef samplemask, struct si_ps_exports *exp)
2836 {
2837 struct si_shader_context *ctx = si_shader_context(bld_base);
2838 struct lp_build_context *base = &bld_base->base;
2839 struct ac_export_args args;
2840 unsigned mask = 0;
2841 unsigned format = si_get_spi_shader_z_format(depth != NULL,
2842 stencil != NULL,
2843 samplemask != NULL);
2844
2845 assert(depth || stencil || samplemask);
2846
2847 args.valid_mask = 1; /* whether the EXEC mask is valid */
2848 args.done = 1; /* DONE bit */
2849
2850 /* Specify the target we are exporting */
2851 args.target = V_008DFC_SQ_EXP_MRTZ;
2852
2853 args.compr = 0; /* COMP flag */
2854 args.out[0] = base->undef; /* R, depth */
2855 args.out[1] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2856 args.out[2] = base->undef; /* B, sample mask */
2857 args.out[3] = base->undef; /* A, alpha to mask */
2858
2859 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
2860 assert(!depth);
2861 args.compr = 1; /* COMPR flag */
2862
2863 if (stencil) {
2864 /* Stencil should be in X[23:16]. */
2865 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
2866 stencil = LLVMBuildShl(ctx->gallivm.builder, stencil,
2867 LLVMConstInt(ctx->i32, 16, 0), "");
2868 args.out[0] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
2869 mask |= 0x3;
2870 }
2871 if (samplemask) {
2872 /* SampleMask should be in Y[15:0]. */
2873 args.out[1] = samplemask;
2874 mask |= 0xc;
2875 }
2876 } else {
2877 if (depth) {
2878 args.out[0] = depth;
2879 mask |= 0x1;
2880 }
2881 if (stencil) {
2882 args.out[1] = stencil;
2883 mask |= 0x2;
2884 }
2885 if (samplemask) {
2886 args.out[2] = samplemask;
2887 mask |= 0x4;
2888 }
2889 }
2890
2891 /* SI (except OLAND and HAINAN) has a bug that it only looks
2892 * at the X writemask component. */
2893 if (ctx->screen->b.chip_class == SI &&
2894 ctx->screen->b.family != CHIP_OLAND &&
2895 ctx->screen->b.family != CHIP_HAINAN)
2896 mask |= 0x1;
2897
2898 /* Specify which components to enable */
2899 args.enabled_channels = mask;
2900
2901 memcpy(&exp->args[exp->num++], &args, sizeof(args));
2902 }
2903
2904 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2905 LLVMValueRef *color, unsigned index,
2906 unsigned samplemask_param,
2907 bool is_last, struct si_ps_exports *exp)
2908 {
2909 struct si_shader_context *ctx = si_shader_context(bld_base);
2910 struct lp_build_context *base = &bld_base->base;
2911 int i;
2912
2913 /* Clamp color */
2914 if (ctx->shader->key.part.ps.epilog.clamp_color)
2915 for (i = 0; i < 4; i++)
2916 color[i] = ac_build_clamp(&ctx->ac, color[i]);
2917
2918 /* Alpha to one */
2919 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
2920 color[3] = base->one;
2921
2922 /* Alpha test */
2923 if (index == 0 &&
2924 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
2925 si_alpha_test(bld_base, color[3]);
2926
2927 /* Line & polygon smoothing */
2928 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
2929 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
2930 samplemask_param);
2931
2932 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2933 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
2934 struct ac_export_args args[8];
2935 int c, last = -1;
2936
2937 /* Get the export arguments, also find out what the last one is. */
2938 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2939 si_llvm_init_export_args(bld_base, color,
2940 V_008DFC_SQ_EXP_MRT + c, &args[c]);
2941 if (args[c].enabled_channels)
2942 last = c;
2943 }
2944
2945 /* Emit all exports. */
2946 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
2947 if (is_last && last == c) {
2948 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
2949 args[c].done = 1; /* DONE bit */
2950 } else if (!args[c].enabled_channels)
2951 continue; /* unnecessary NULL export */
2952
2953 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
2954 }
2955 } else {
2956 struct ac_export_args args;
2957
2958 /* Export */
2959 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2960 &args);
2961 if (is_last) {
2962 args.valid_mask = 1; /* whether the EXEC mask is valid */
2963 args.done = 1; /* DONE bit */
2964 } else if (!args.enabled_channels)
2965 return; /* unnecessary NULL export */
2966
2967 memcpy(&exp->args[exp->num++], &args, sizeof(args));
2968 }
2969 }
2970
2971 static void si_emit_ps_exports(struct si_shader_context *ctx,
2972 struct si_ps_exports *exp)
2973 {
2974 for (unsigned i = 0; i < exp->num; i++)
2975 ac_build_export(&ctx->ac, &exp->args[i]);
2976 }
2977
2978 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2979 {
2980 struct si_shader_context *ctx = si_shader_context(bld_base);
2981 struct lp_build_context *base = &bld_base->base;
2982 struct ac_export_args args;
2983
2984 args.enabled_channels = 0x0; /* enabled channels */
2985 args.valid_mask = 1; /* whether the EXEC mask is valid */
2986 args.done = 1; /* DONE bit */
2987 args.target = V_008DFC_SQ_EXP_NULL;
2988 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
2989 args.out[0] = base->undef; /* R */
2990 args.out[1] = base->undef; /* G */
2991 args.out[2] = base->undef; /* B */
2992 args.out[3] = base->undef; /* A */
2993
2994 ac_build_export(&ctx->ac, &args);
2995 }
2996
2997 /**
2998 * Return PS outputs in this order:
2999 *
3000 * v[0:3] = color0.xyzw
3001 * v[4:7] = color1.xyzw
3002 * ...
3003 * vN+0 = Depth
3004 * vN+1 = Stencil
3005 * vN+2 = SampleMask
3006 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3007 *
3008 * The alpha-ref SGPR is returned via its original location.
3009 */
3010 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3011 {
3012 struct si_shader_context *ctx = si_shader_context(bld_base);
3013 struct si_shader *shader = ctx->shader;
3014 struct tgsi_shader_info *info = &shader->selector->info;
3015 LLVMBuilderRef builder = ctx->gallivm.builder;
3016 unsigned i, j, first_vgpr, vgpr;
3017
3018 LLVMValueRef color[8][4] = {};
3019 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3020 LLVMValueRef ret;
3021
3022 /* Read the output values. */
3023 for (i = 0; i < info->num_outputs; i++) {
3024 unsigned semantic_name = info->output_semantic_name[i];
3025 unsigned semantic_index = info->output_semantic_index[i];
3026
3027 switch (semantic_name) {
3028 case TGSI_SEMANTIC_COLOR:
3029 assert(semantic_index < 8);
3030 for (j = 0; j < 4; j++) {
3031 LLVMValueRef ptr = ctx->outputs[i][j];
3032 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3033 color[semantic_index][j] = result;
3034 }
3035 break;
3036 case TGSI_SEMANTIC_POSITION:
3037 depth = LLVMBuildLoad(builder,
3038 ctx->outputs[i][2], "");
3039 break;
3040 case TGSI_SEMANTIC_STENCIL:
3041 stencil = LLVMBuildLoad(builder,
3042 ctx->outputs[i][1], "");
3043 break;
3044 case TGSI_SEMANTIC_SAMPLEMASK:
3045 samplemask = LLVMBuildLoad(builder,
3046 ctx->outputs[i][0], "");
3047 break;
3048 default:
3049 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3050 semantic_name);
3051 }
3052 }
3053
3054 /* Fill the return structure. */
3055 ret = ctx->return_value;
3056
3057 /* Set SGPRs. */
3058 ret = LLVMBuildInsertValue(builder, ret,
3059 bitcast(bld_base, TGSI_TYPE_SIGNED,
3060 LLVMGetParam(ctx->main_fn,
3061 SI_PARAM_ALPHA_REF)),
3062 SI_SGPR_ALPHA_REF, "");
3063
3064 /* Set VGPRs */
3065 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3066 for (i = 0; i < ARRAY_SIZE(color); i++) {
3067 if (!color[i][0])
3068 continue;
3069
3070 for (j = 0; j < 4; j++)
3071 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3072 }
3073 if (depth)
3074 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3075 if (stencil)
3076 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3077 if (samplemask)
3078 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3079
3080 /* Add the input sample mask for smoothing at the end. */
3081 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3082 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3083 ret = LLVMBuildInsertValue(builder, ret,
3084 LLVMGetParam(ctx->main_fn,
3085 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3086
3087 ctx->return_value = ret;
3088 }
3089
3090 /**
3091 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3092 * buffer in number of elements and return it as an i32.
3093 */
3094 static LLVMValueRef get_buffer_size(
3095 struct lp_build_tgsi_context *bld_base,
3096 LLVMValueRef descriptor)
3097 {
3098 struct si_shader_context *ctx = si_shader_context(bld_base);
3099 struct gallivm_state *gallivm = &ctx->gallivm;
3100 LLVMBuilderRef builder = gallivm->builder;
3101 LLVMValueRef size =
3102 LLVMBuildExtractElement(builder, descriptor,
3103 LLVMConstInt(ctx->i32, 2, 0), "");
3104
3105 if (ctx->screen->b.chip_class == VI) {
3106 /* On VI, the descriptor contains the size in bytes,
3107 * but TXQ must return the size in elements.
3108 * The stride is always non-zero for resources using TXQ.
3109 */
3110 LLVMValueRef stride =
3111 LLVMBuildExtractElement(builder, descriptor,
3112 ctx->i32_1, "");
3113 stride = LLVMBuildLShr(builder, stride,
3114 LLVMConstInt(ctx->i32, 16, 0), "");
3115 stride = LLVMBuildAnd(builder, stride,
3116 LLVMConstInt(ctx->i32, 0x3FFF, 0), "");
3117
3118 size = LLVMBuildUDiv(builder, size, stride, "");
3119 }
3120
3121 return size;
3122 }
3123
3124 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3125 struct lp_build_tgsi_context *bld_base,
3126 struct lp_build_emit_data *emit_data);
3127
3128 /* Prevent optimizations (at least of memory accesses) across the current
3129 * point in the program by emitting empty inline assembly that is marked as
3130 * having side effects.
3131 *
3132 * Optionally, a value can be passed through the inline assembly to prevent
3133 * LLVM from hoisting calls to ReadNone functions.
3134 */
3135 static void emit_optimization_barrier(struct si_shader_context *ctx,
3136 LLVMValueRef *pvgpr)
3137 {
3138 static int counter = 0;
3139
3140 LLVMBuilderRef builder = ctx->gallivm.builder;
3141 char code[16];
3142
3143 snprintf(code, sizeof(code), "; %d", p_atomic_inc_return(&counter));
3144
3145 if (!pvgpr) {
3146 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3147 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, code, "", true, false);
3148 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3149 } else {
3150 LLVMTypeRef ftype = LLVMFunctionType(ctx->i32, &ctx->i32, 1, false);
3151 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, code, "=v,0", true, false);
3152 LLVMValueRef vgpr = *pvgpr;
3153 LLVMTypeRef vgpr_type = LLVMTypeOf(vgpr);
3154 unsigned vgpr_size = llvm_get_type_size(vgpr_type);
3155 LLVMValueRef vgpr0;
3156
3157 assert(vgpr_size % 4 == 0);
3158
3159 vgpr = LLVMBuildBitCast(builder, vgpr, LLVMVectorType(ctx->i32, vgpr_size / 4), "");
3160 vgpr0 = LLVMBuildExtractElement(builder, vgpr, ctx->i32_0, "");
3161 vgpr0 = LLVMBuildCall(builder, inlineasm, &vgpr0, 1, "");
3162 vgpr = LLVMBuildInsertElement(builder, vgpr, vgpr0, ctx->i32_0, "");
3163 vgpr = LLVMBuildBitCast(builder, vgpr, vgpr_type, "");
3164
3165 *pvgpr = vgpr;
3166 }
3167 }
3168
3169 /* Combine these with & instead of |. */
3170 #define NOOP_WAITCNT 0xf7f
3171 #define LGKM_CNT 0x07f
3172 #define VM_CNT 0xf70
3173
3174 static void emit_waitcnt(struct si_shader_context *ctx, unsigned simm16)
3175 {
3176 struct gallivm_state *gallivm = &ctx->gallivm;
3177 LLVMBuilderRef builder = gallivm->builder;
3178 LLVMValueRef args[1] = {
3179 LLVMConstInt(ctx->i32, simm16, 0)
3180 };
3181 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3182 ctx->voidt, args, 1, 0);
3183 }
3184
3185 static void membar_emit(
3186 const struct lp_build_tgsi_action *action,
3187 struct lp_build_tgsi_context *bld_base,
3188 struct lp_build_emit_data *emit_data)
3189 {
3190 struct si_shader_context *ctx = si_shader_context(bld_base);
3191 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3192 unsigned flags = LLVMConstIntGetZExtValue(src0);
3193 unsigned waitcnt = NOOP_WAITCNT;
3194
3195 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3196 waitcnt &= VM_CNT & LGKM_CNT;
3197
3198 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3199 TGSI_MEMBAR_SHADER_BUFFER |
3200 TGSI_MEMBAR_SHADER_IMAGE))
3201 waitcnt &= VM_CNT;
3202
3203 if (flags & TGSI_MEMBAR_SHARED)
3204 waitcnt &= LGKM_CNT;
3205
3206 if (waitcnt != NOOP_WAITCNT)
3207 emit_waitcnt(ctx, waitcnt);
3208 }
3209
3210 static void clock_emit(
3211 const struct lp_build_tgsi_action *action,
3212 struct lp_build_tgsi_context *bld_base,
3213 struct lp_build_emit_data *emit_data)
3214 {
3215 struct si_shader_context *ctx = si_shader_context(bld_base);
3216 struct gallivm_state *gallivm = &ctx->gallivm;
3217 LLVMValueRef tmp;
3218
3219 tmp = lp_build_intrinsic(gallivm->builder, "llvm.readcyclecounter",
3220 ctx->i64, NULL, 0, 0);
3221 tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->v2i32, "");
3222
3223 emit_data->output[0] =
3224 LLVMBuildExtractElement(gallivm->builder, tmp, ctx->i32_0, "");
3225 emit_data->output[1] =
3226 LLVMBuildExtractElement(gallivm->builder, tmp, ctx->i32_1, "");
3227 }
3228
3229 static LLVMValueRef
3230 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3231 const struct tgsi_full_src_register *reg)
3232 {
3233 LLVMValueRef index;
3234 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3235 SI_PARAM_SHADER_BUFFERS);
3236
3237 if (!reg->Register.Indirect)
3238 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
3239 else
3240 index = get_bounded_indirect_index(ctx, &reg->Indirect,
3241 reg->Register.Index,
3242 SI_NUM_SHADER_BUFFERS);
3243
3244 return ac_build_indexed_load_const(&ctx->ac, rsrc_ptr, index);
3245 }
3246
3247 static bool tgsi_is_array_sampler(unsigned target)
3248 {
3249 return target == TGSI_TEXTURE_1D_ARRAY ||
3250 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3251 target == TGSI_TEXTURE_2D_ARRAY ||
3252 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3253 target == TGSI_TEXTURE_CUBE_ARRAY ||
3254 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3255 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3256 }
3257
3258 static bool tgsi_is_array_image(unsigned target)
3259 {
3260 return target == TGSI_TEXTURE_3D ||
3261 target == TGSI_TEXTURE_CUBE ||
3262 target == TGSI_TEXTURE_1D_ARRAY ||
3263 target == TGSI_TEXTURE_2D_ARRAY ||
3264 target == TGSI_TEXTURE_CUBE_ARRAY ||
3265 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3266 }
3267
3268 /**
3269 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3270 *
3271 * At least on Tonga, executing image stores on images with DCC enabled and
3272 * non-trivial can eventually lead to lockups. This can occur when an
3273 * application binds an image as read-only but then uses a shader that writes
3274 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3275 * program termination) in this case, but it doesn't cost much to be a bit
3276 * nicer: disabling DCC in the shader still leads to undefined results but
3277 * avoids the lockup.
3278 */
3279 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3280 LLVMValueRef rsrc)
3281 {
3282 if (ctx->screen->b.chip_class <= CIK) {
3283 return rsrc;
3284 } else {
3285 LLVMBuilderRef builder = ctx->gallivm.builder;
3286 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3287 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3288 LLVMValueRef tmp;
3289
3290 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3291 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3292 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3293 }
3294 }
3295
3296 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3297 {
3298 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3299 CONST_ADDR_SPACE);
3300 }
3301
3302 static LLVMValueRef load_image_desc(struct si_shader_context *ctx,
3303 LLVMValueRef list, LLVMValueRef index,
3304 unsigned target)
3305 {
3306 LLVMBuilderRef builder = ctx->gallivm.builder;
3307
3308 if (target == TGSI_TEXTURE_BUFFER) {
3309 index = LLVMBuildMul(builder, index,
3310 LLVMConstInt(ctx->i32, 2, 0), "");
3311 index = LLVMBuildAdd(builder, index,
3312 ctx->i32_1, "");
3313 list = LLVMBuildPointerCast(builder, list,
3314 const_array(ctx->v4i32, 0), "");
3315 }
3316
3317 return ac_build_indexed_load_const(&ctx->ac, list, index);
3318 }
3319
3320 /**
3321 * Load the resource descriptor for \p image.
3322 */
3323 static void
3324 image_fetch_rsrc(
3325 struct lp_build_tgsi_context *bld_base,
3326 const struct tgsi_full_src_register *image,
3327 bool is_store, unsigned target,
3328 LLVMValueRef *rsrc)
3329 {
3330 struct si_shader_context *ctx = si_shader_context(bld_base);
3331 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
3332 SI_PARAM_IMAGES);
3333 LLVMValueRef index;
3334 bool dcc_off = is_store;
3335
3336 assert(image->Register.File == TGSI_FILE_IMAGE);
3337
3338 if (!image->Register.Indirect) {
3339 const struct tgsi_shader_info *info = bld_base->info;
3340 unsigned images_writemask = info->images_store |
3341 info->images_atomic;
3342
3343 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
3344
3345 if (images_writemask & (1 << image->Register.Index))
3346 dcc_off = true;
3347 } else {
3348 /* From the GL_ARB_shader_image_load_store extension spec:
3349 *
3350 * If a shader performs an image load, store, or atomic
3351 * operation using an image variable declared as an array,
3352 * and if the index used to select an individual element is
3353 * negative or greater than or equal to the size of the
3354 * array, the results of the operation are undefined but may
3355 * not lead to termination.
3356 */
3357 index = get_bounded_indirect_index(ctx, &image->Indirect,
3358 image->Register.Index,
3359 SI_NUM_IMAGES);
3360 }
3361
3362 *rsrc = load_image_desc(ctx, rsrc_ptr, index, target);
3363 if (dcc_off && target != TGSI_TEXTURE_BUFFER)
3364 *rsrc = force_dcc_off(ctx, *rsrc);
3365 }
3366
3367 static LLVMValueRef image_fetch_coords(
3368 struct lp_build_tgsi_context *bld_base,
3369 const struct tgsi_full_instruction *inst,
3370 unsigned src)
3371 {
3372 struct si_shader_context *ctx = si_shader_context(bld_base);
3373 struct gallivm_state *gallivm = &ctx->gallivm;
3374 LLVMBuilderRef builder = gallivm->builder;
3375 unsigned target = inst->Memory.Texture;
3376 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3377 LLVMValueRef coords[4];
3378 LLVMValueRef tmp;
3379 int chan;
3380
3381 for (chan = 0; chan < num_coords; ++chan) {
3382 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3383 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
3384 coords[chan] = tmp;
3385 }
3386
3387 /* 1D textures are allocated and used as 2D on GFX9. */
3388 if (ctx->screen->b.chip_class >= GFX9) {
3389 if (target == TGSI_TEXTURE_1D) {
3390 coords[1] = ctx->i32_0;
3391 num_coords++;
3392 } else if (target == TGSI_TEXTURE_1D_ARRAY) {
3393 coords[2] = coords[1];
3394 coords[1] = ctx->i32_0;
3395 }
3396 }
3397
3398 if (num_coords == 1)
3399 return coords[0];
3400
3401 if (num_coords == 3) {
3402 /* LLVM has difficulties lowering 3-element vectors. */
3403 coords[3] = bld_base->uint_bld.undef;
3404 num_coords = 4;
3405 }
3406
3407 return lp_build_gather_values(gallivm, coords, num_coords);
3408 }
3409
3410 /**
3411 * Append the extra mode bits that are used by image load and store.
3412 */
3413 static void image_append_args(
3414 struct si_shader_context *ctx,
3415 struct lp_build_emit_data * emit_data,
3416 unsigned target,
3417 bool atomic,
3418 bool force_glc)
3419 {
3420 const struct tgsi_full_instruction *inst = emit_data->inst;
3421 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3422 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3423 LLVMValueRef r128 = i1false;
3424 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
3425 LLVMValueRef glc =
3426 force_glc ||
3427 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3428 i1true : i1false;
3429 LLVMValueRef slc = i1false;
3430 LLVMValueRef lwe = i1false;
3431
3432 if (atomic || (HAVE_LLVM <= 0x0309)) {
3433 emit_data->args[emit_data->arg_count++] = r128;
3434 emit_data->args[emit_data->arg_count++] = da;
3435 if (!atomic) {
3436 emit_data->args[emit_data->arg_count++] = glc;
3437 }
3438 emit_data->args[emit_data->arg_count++] = slc;
3439 return;
3440 }
3441
3442 /* HAVE_LLVM >= 0x0400 */
3443 emit_data->args[emit_data->arg_count++] = glc;
3444 emit_data->args[emit_data->arg_count++] = slc;
3445 emit_data->args[emit_data->arg_count++] = lwe;
3446 emit_data->args[emit_data->arg_count++] = da;
3447 }
3448
3449 /**
3450 * Append the resource and indexing arguments for buffer intrinsics.
3451 *
3452 * \param rsrc the v4i32 buffer resource
3453 * \param index index into the buffer (stride-based)
3454 * \param offset byte offset into the buffer
3455 */
3456 static void buffer_append_args(
3457 struct si_shader_context *ctx,
3458 struct lp_build_emit_data *emit_data,
3459 LLVMValueRef rsrc,
3460 LLVMValueRef index,
3461 LLVMValueRef offset,
3462 bool atomic,
3463 bool force_glc)
3464 {
3465 const struct tgsi_full_instruction *inst = emit_data->inst;
3466 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3467 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3468
3469 emit_data->args[emit_data->arg_count++] = rsrc;
3470 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3471 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3472 if (!atomic) {
3473 emit_data->args[emit_data->arg_count++] =
3474 force_glc ||
3475 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3476 i1true : i1false; /* glc */
3477 }
3478 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3479 }
3480
3481 static void load_fetch_args(
3482 struct lp_build_tgsi_context * bld_base,
3483 struct lp_build_emit_data * emit_data)
3484 {
3485 struct si_shader_context *ctx = si_shader_context(bld_base);
3486 struct gallivm_state *gallivm = &ctx->gallivm;
3487 const struct tgsi_full_instruction * inst = emit_data->inst;
3488 unsigned target = inst->Memory.Texture;
3489 LLVMValueRef rsrc;
3490
3491 emit_data->dst_type = ctx->v4f32;
3492
3493 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3494 LLVMBuilderRef builder = gallivm->builder;
3495 LLVMValueRef offset;
3496 LLVMValueRef tmp;
3497
3498 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3499
3500 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3501 offset = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
3502
3503 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
3504 offset, false, false);
3505 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3506 LLVMValueRef coords;
3507
3508 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
3509 coords = image_fetch_coords(bld_base, inst, 1);
3510
3511 if (target == TGSI_TEXTURE_BUFFER) {
3512 buffer_append_args(ctx, emit_data, rsrc, coords,
3513 ctx->i32_0, false, false);
3514 } else {
3515 emit_data->args[0] = coords;
3516 emit_data->args[1] = rsrc;
3517 emit_data->args[2] = LLVMConstInt(ctx->i32, 15, 0); /* dmask */
3518 emit_data->arg_count = 3;
3519
3520 image_append_args(ctx, emit_data, target, false, false);
3521 }
3522 }
3523 }
3524
3525 static unsigned get_load_intr_attribs(bool readonly_memory)
3526 {
3527 /* READNONE means writes can't affect it, while READONLY means that
3528 * writes can affect it. */
3529 return readonly_memory && HAVE_LLVM >= 0x0400 ?
3530 LP_FUNC_ATTR_READNONE :
3531 LP_FUNC_ATTR_READONLY;
3532 }
3533
3534 static unsigned get_store_intr_attribs(bool writeonly_memory)
3535 {
3536 return writeonly_memory && HAVE_LLVM >= 0x0400 ?
3537 LP_FUNC_ATTR_INACCESSIBLE_MEM_ONLY :
3538 LP_FUNC_ATTR_WRITEONLY;
3539 }
3540
3541 static void load_emit_buffer(struct si_shader_context *ctx,
3542 struct lp_build_emit_data *emit_data,
3543 bool readonly_memory)
3544 {
3545 const struct tgsi_full_instruction *inst = emit_data->inst;
3546 struct gallivm_state *gallivm = &ctx->gallivm;
3547 LLVMBuilderRef builder = gallivm->builder;
3548 uint writemask = inst->Dst[0].Register.WriteMask;
3549 uint count = util_last_bit(writemask);
3550 const char *intrinsic_name;
3551 LLVMTypeRef dst_type;
3552
3553 switch (count) {
3554 case 1:
3555 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3556 dst_type = ctx->f32;
3557 break;
3558 case 2:
3559 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3560 dst_type = LLVMVectorType(ctx->f32, 2);
3561 break;
3562 default: // 3 & 4
3563 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3564 dst_type = ctx->v4f32;
3565 count = 4;
3566 }
3567
3568 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3569 builder, intrinsic_name, dst_type,
3570 emit_data->args, emit_data->arg_count,
3571 get_load_intr_attribs(readonly_memory));
3572 }
3573
3574 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3575 const struct tgsi_full_instruction *inst,
3576 LLVMTypeRef type, int arg)
3577 {
3578 struct gallivm_state *gallivm = &ctx->gallivm;
3579 LLVMBuilderRef builder = gallivm->builder;
3580 LLVMValueRef offset, ptr;
3581 int addr_space;
3582
3583 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
3584 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3585
3586 ptr = ctx->shared_memory;
3587 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3588 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3589 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3590
3591 return ptr;
3592 }
3593
3594 static void load_emit_memory(
3595 struct si_shader_context *ctx,
3596 struct lp_build_emit_data *emit_data)
3597 {
3598 const struct tgsi_full_instruction *inst = emit_data->inst;
3599 struct gallivm_state *gallivm = &ctx->gallivm;
3600 LLVMBuilderRef builder = gallivm->builder;
3601 unsigned writemask = inst->Dst[0].Register.WriteMask;
3602 LLVMValueRef channels[4], ptr, derived_ptr, index;
3603 int chan;
3604
3605 ptr = get_memory_ptr(ctx, inst, ctx->f32, 1);
3606
3607 for (chan = 0; chan < 4; ++chan) {
3608 if (!(writemask & (1 << chan))) {
3609 channels[chan] = LLVMGetUndef(ctx->f32);
3610 continue;
3611 }
3612
3613 index = LLVMConstInt(ctx->i32, chan, 0);
3614 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3615 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3616 }
3617 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3618 }
3619
3620 /**
3621 * Return true if the memory accessed by a LOAD or STORE instruction is
3622 * read-only or write-only, respectively.
3623 *
3624 * \param shader_buffers_reverse_access_mask
3625 * For LOAD, set this to (store | atomic) slot usage in the shader.
3626 * For STORE, set this to (load | atomic) slot usage in the shader.
3627 * \param images_reverse_access_mask Same as above, but for images.
3628 */
3629 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
3630 const struct tgsi_shader_info *info,
3631 unsigned shader_buffers_reverse_access_mask,
3632 unsigned images_reverse_access_mask)
3633 {
3634 /* RESTRICT means NOALIAS.
3635 * If there are no writes, we can assume the accessed memory is read-only.
3636 * If there are no reads, we can assume the accessed memory is write-only.
3637 */
3638 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT) {
3639 unsigned reverse_access_mask;
3640
3641 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3642 reverse_access_mask = shader_buffers_reverse_access_mask;
3643 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3644 reverse_access_mask = info->images_buffers &
3645 images_reverse_access_mask;
3646 } else {
3647 reverse_access_mask = ~info->images_buffers &
3648 images_reverse_access_mask;
3649 }
3650
3651 if (inst->Src[0].Register.Indirect) {
3652 if (!reverse_access_mask)
3653 return true;
3654 } else {
3655 if (!(reverse_access_mask &
3656 (1u << inst->Src[0].Register.Index)))
3657 return true;
3658 }
3659 }
3660
3661 /* If there are no buffer writes (for both shader buffers & image
3662 * buffers), it implies that buffer memory is read-only.
3663 * If there are no buffer reads (for both shader buffers & image
3664 * buffers), it implies that buffer memory is write-only.
3665 *
3666 * Same for the case when there are no writes/reads for non-buffer
3667 * images.
3668 */
3669 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
3670 (inst->Src[0].Register.File == TGSI_FILE_IMAGE &&
3671 inst->Memory.Texture == TGSI_TEXTURE_BUFFER)) {
3672 if (!shader_buffers_reverse_access_mask &&
3673 !(info->images_buffers & images_reverse_access_mask))
3674 return true;
3675 } else {
3676 if (!(~info->images_buffers & images_reverse_access_mask))
3677 return true;
3678 }
3679 return false;
3680 }
3681
3682 static void load_emit(
3683 const struct lp_build_tgsi_action *action,
3684 struct lp_build_tgsi_context *bld_base,
3685 struct lp_build_emit_data *emit_data)
3686 {
3687 struct si_shader_context *ctx = si_shader_context(bld_base);
3688 struct gallivm_state *gallivm = &ctx->gallivm;
3689 LLVMBuilderRef builder = gallivm->builder;
3690 const struct tgsi_full_instruction * inst = emit_data->inst;
3691 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
3692 char intrinsic_name[64];
3693 bool readonly_memory = false;
3694
3695 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3696 load_emit_memory(ctx, emit_data);
3697 return;
3698 }
3699
3700 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3701 emit_waitcnt(ctx, VM_CNT);
3702
3703 readonly_memory = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
3704 is_oneway_access_only(inst, info,
3705 info->shader_buffers_store |
3706 info->shader_buffers_atomic,
3707 info->images_store |
3708 info->images_atomic);
3709
3710 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3711 load_emit_buffer(ctx, emit_data, readonly_memory);
3712 return;
3713 }
3714
3715 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3716 emit_data->output[emit_data->chan] =
3717 lp_build_intrinsic(
3718 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3719 emit_data->args, emit_data->arg_count,
3720 get_load_intr_attribs(readonly_memory));
3721 } else {
3722 ac_get_image_intr_name("llvm.amdgcn.image.load",
3723 emit_data->dst_type, /* vdata */
3724 LLVMTypeOf(emit_data->args[0]), /* coords */
3725 LLVMTypeOf(emit_data->args[1]), /* rsrc */
3726 intrinsic_name, sizeof(intrinsic_name));
3727
3728 emit_data->output[emit_data->chan] =
3729 lp_build_intrinsic(
3730 builder, intrinsic_name, emit_data->dst_type,
3731 emit_data->args, emit_data->arg_count,
3732 get_load_intr_attribs(readonly_memory));
3733 }
3734 }
3735
3736 static void store_fetch_args(
3737 struct lp_build_tgsi_context * bld_base,
3738 struct lp_build_emit_data * emit_data)
3739 {
3740 struct si_shader_context *ctx = si_shader_context(bld_base);
3741 struct gallivm_state *gallivm = &ctx->gallivm;
3742 LLVMBuilderRef builder = gallivm->builder;
3743 const struct tgsi_full_instruction * inst = emit_data->inst;
3744 struct tgsi_full_src_register memory;
3745 LLVMValueRef chans[4];
3746 LLVMValueRef data;
3747 LLVMValueRef rsrc;
3748 unsigned chan;
3749
3750 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3751
3752 for (chan = 0; chan < 4; ++chan) {
3753 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3754 }
3755 data = lp_build_gather_values(gallivm, chans, 4);
3756
3757 emit_data->args[emit_data->arg_count++] = data;
3758
3759 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3760
3761 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3762 LLVMValueRef offset;
3763 LLVMValueRef tmp;
3764
3765 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3766
3767 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3768 offset = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
3769
3770 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
3771 offset, false, false);
3772 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3773 unsigned target = inst->Memory.Texture;
3774 LLVMValueRef coords;
3775
3776 /* 8bit/16bit TC L1 write corruption bug on SI.
3777 * All store opcodes not aligned to a dword are affected.
3778 *
3779 * The only way to get unaligned stores in radeonsi is through
3780 * shader images.
3781 */
3782 bool force_glc = ctx->screen->b.chip_class == SI;
3783
3784 coords = image_fetch_coords(bld_base, inst, 0);
3785
3786 if (target == TGSI_TEXTURE_BUFFER) {
3787 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
3788 buffer_append_args(ctx, emit_data, rsrc, coords,
3789 ctx->i32_0, false, force_glc);
3790 } else {
3791 emit_data->args[1] = coords;
3792 image_fetch_rsrc(bld_base, &memory, true, target,
3793 &emit_data->args[2]);
3794 emit_data->args[3] = LLVMConstInt(ctx->i32, 15, 0); /* dmask */
3795 emit_data->arg_count = 4;
3796
3797 image_append_args(ctx, emit_data, target, false, force_glc);
3798 }
3799 }
3800 }
3801
3802 static void store_emit_buffer(
3803 struct si_shader_context *ctx,
3804 struct lp_build_emit_data *emit_data,
3805 bool writeonly_memory)
3806 {
3807 const struct tgsi_full_instruction *inst = emit_data->inst;
3808 struct gallivm_state *gallivm = &ctx->gallivm;
3809 LLVMBuilderRef builder = gallivm->builder;
3810 LLVMValueRef base_data = emit_data->args[0];
3811 LLVMValueRef base_offset = emit_data->args[3];
3812 unsigned writemask = inst->Dst[0].Register.WriteMask;
3813
3814 while (writemask) {
3815 int start, count;
3816 const char *intrinsic_name;
3817 LLVMValueRef data;
3818 LLVMValueRef offset;
3819 LLVMValueRef tmp;
3820
3821 u_bit_scan_consecutive_range(&writemask, &start, &count);
3822
3823 /* Due to an LLVM limitation, split 3-element writes
3824 * into a 2-element and a 1-element write. */
3825 if (count == 3) {
3826 writemask |= 1 << (start + 2);
3827 count = 2;
3828 }
3829
3830 if (count == 4) {
3831 data = base_data;
3832 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3833 } else if (count == 2) {
3834 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3835
3836 tmp = LLVMBuildExtractElement(
3837 builder, base_data,
3838 LLVMConstInt(ctx->i32, start, 0), "");
3839 data = LLVMBuildInsertElement(
3840 builder, LLVMGetUndef(v2f32), tmp,
3841 ctx->i32_0, "");
3842
3843 tmp = LLVMBuildExtractElement(
3844 builder, base_data,
3845 LLVMConstInt(ctx->i32, start + 1, 0), "");
3846 data = LLVMBuildInsertElement(
3847 builder, data, tmp, ctx->i32_1, "");
3848
3849 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3850 } else {
3851 assert(count == 1);
3852 data = LLVMBuildExtractElement(
3853 builder, base_data,
3854 LLVMConstInt(ctx->i32, start, 0), "");
3855 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3856 }
3857
3858 offset = base_offset;
3859 if (start != 0) {
3860 offset = LLVMBuildAdd(
3861 builder, offset,
3862 LLVMConstInt(ctx->i32, start * 4, 0), "");
3863 }
3864
3865 emit_data->args[0] = data;
3866 emit_data->args[3] = offset;
3867
3868 lp_build_intrinsic(
3869 builder, intrinsic_name, emit_data->dst_type,
3870 emit_data->args, emit_data->arg_count,
3871 get_store_intr_attribs(writeonly_memory));
3872 }
3873 }
3874
3875 static void store_emit_memory(
3876 struct si_shader_context *ctx,
3877 struct lp_build_emit_data *emit_data)
3878 {
3879 const struct tgsi_full_instruction *inst = emit_data->inst;
3880 struct gallivm_state *gallivm = &ctx->gallivm;
3881 LLVMBuilderRef builder = gallivm->builder;
3882 unsigned writemask = inst->Dst[0].Register.WriteMask;
3883 LLVMValueRef ptr, derived_ptr, data, index;
3884 int chan;
3885
3886 ptr = get_memory_ptr(ctx, inst, ctx->f32, 0);
3887
3888 for (chan = 0; chan < 4; ++chan) {
3889 if (!(writemask & (1 << chan))) {
3890 continue;
3891 }
3892 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
3893 index = LLVMConstInt(ctx->i32, chan, 0);
3894 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3895 LLVMBuildStore(builder, data, derived_ptr);
3896 }
3897 }
3898
3899 static void store_emit(
3900 const struct lp_build_tgsi_action *action,
3901 struct lp_build_tgsi_context *bld_base,
3902 struct lp_build_emit_data *emit_data)
3903 {
3904 struct si_shader_context *ctx = si_shader_context(bld_base);
3905 struct gallivm_state *gallivm = &ctx->gallivm;
3906 LLVMBuilderRef builder = gallivm->builder;
3907 const struct tgsi_full_instruction * inst = emit_data->inst;
3908 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
3909 unsigned target = inst->Memory.Texture;
3910 char intrinsic_name[64];
3911 bool writeonly_memory = false;
3912
3913 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
3914 store_emit_memory(ctx, emit_data);
3915 return;
3916 }
3917
3918 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3919 emit_waitcnt(ctx, VM_CNT);
3920
3921 writeonly_memory = is_oneway_access_only(inst, info,
3922 info->shader_buffers_load |
3923 info->shader_buffers_atomic,
3924 info->images_load |
3925 info->images_atomic);
3926
3927 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3928 store_emit_buffer(ctx, emit_data, writeonly_memory);
3929 return;
3930 }
3931
3932 if (target == TGSI_TEXTURE_BUFFER) {
3933 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3934 builder, "llvm.amdgcn.buffer.store.format.v4f32",
3935 emit_data->dst_type, emit_data->args,
3936 emit_data->arg_count,
3937 get_store_intr_attribs(writeonly_memory));
3938 } else {
3939 ac_get_image_intr_name("llvm.amdgcn.image.store",
3940 LLVMTypeOf(emit_data->args[0]), /* vdata */
3941 LLVMTypeOf(emit_data->args[1]), /* coords */
3942 LLVMTypeOf(emit_data->args[2]), /* rsrc */
3943 intrinsic_name, sizeof(intrinsic_name));
3944
3945 emit_data->output[emit_data->chan] =
3946 lp_build_intrinsic(
3947 builder, intrinsic_name, emit_data->dst_type,
3948 emit_data->args, emit_data->arg_count,
3949 get_store_intr_attribs(writeonly_memory));
3950 }
3951 }
3952
3953 static void atomic_fetch_args(
3954 struct lp_build_tgsi_context * bld_base,
3955 struct lp_build_emit_data * emit_data)
3956 {
3957 struct si_shader_context *ctx = si_shader_context(bld_base);
3958 struct gallivm_state *gallivm = &ctx->gallivm;
3959 LLVMBuilderRef builder = gallivm->builder;
3960 const struct tgsi_full_instruction * inst = emit_data->inst;
3961 LLVMValueRef data1, data2;
3962 LLVMValueRef rsrc;
3963 LLVMValueRef tmp;
3964
3965 emit_data->dst_type = ctx->f32;
3966
3967 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
3968 data1 = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
3969
3970 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
3971 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
3972 data2 = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
3973 }
3974
3975 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
3976 * of arguments, which is reversed relative to TGSI (and GLSL)
3977 */
3978 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
3979 emit_data->args[emit_data->arg_count++] = data2;
3980 emit_data->args[emit_data->arg_count++] = data1;
3981
3982 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3983 LLVMValueRef offset;
3984
3985 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3986
3987 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3988 offset = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
3989
3990 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
3991 offset, true, false);
3992 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3993 unsigned target = inst->Memory.Texture;
3994 LLVMValueRef coords;
3995
3996 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
3997 coords = image_fetch_coords(bld_base, inst, 1);
3998
3999 if (target == TGSI_TEXTURE_BUFFER) {
4000 buffer_append_args(ctx, emit_data, rsrc, coords,
4001 ctx->i32_0, true, false);
4002 } else {
4003 emit_data->args[emit_data->arg_count++] = coords;
4004 emit_data->args[emit_data->arg_count++] = rsrc;
4005
4006 image_append_args(ctx, emit_data, target, true, false);
4007 }
4008 }
4009 }
4010
4011 static void atomic_emit_memory(struct si_shader_context *ctx,
4012 struct lp_build_emit_data *emit_data) {
4013 struct gallivm_state *gallivm = &ctx->gallivm;
4014 LLVMBuilderRef builder = gallivm->builder;
4015 const struct tgsi_full_instruction * inst = emit_data->inst;
4016 LLVMValueRef ptr, result, arg;
4017
4018 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
4019
4020 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
4021 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
4022
4023 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4024 LLVMValueRef new_data;
4025 new_data = lp_build_emit_fetch(&ctx->bld_base,
4026 inst, 3, 0);
4027
4028 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
4029
4030 #if HAVE_LLVM >= 0x309
4031 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
4032 LLVMAtomicOrderingSequentiallyConsistent,
4033 LLVMAtomicOrderingSequentiallyConsistent,
4034 false);
4035 #endif
4036
4037 result = LLVMBuildExtractValue(builder, result, 0, "");
4038 } else {
4039 LLVMAtomicRMWBinOp op;
4040
4041 switch(inst->Instruction.Opcode) {
4042 case TGSI_OPCODE_ATOMUADD:
4043 op = LLVMAtomicRMWBinOpAdd;
4044 break;
4045 case TGSI_OPCODE_ATOMXCHG:
4046 op = LLVMAtomicRMWBinOpXchg;
4047 break;
4048 case TGSI_OPCODE_ATOMAND:
4049 op = LLVMAtomicRMWBinOpAnd;
4050 break;
4051 case TGSI_OPCODE_ATOMOR:
4052 op = LLVMAtomicRMWBinOpOr;
4053 break;
4054 case TGSI_OPCODE_ATOMXOR:
4055 op = LLVMAtomicRMWBinOpXor;
4056 break;
4057 case TGSI_OPCODE_ATOMUMIN:
4058 op = LLVMAtomicRMWBinOpUMin;
4059 break;
4060 case TGSI_OPCODE_ATOMUMAX:
4061 op = LLVMAtomicRMWBinOpUMax;
4062 break;
4063 case TGSI_OPCODE_ATOMIMIN:
4064 op = LLVMAtomicRMWBinOpMin;
4065 break;
4066 case TGSI_OPCODE_ATOMIMAX:
4067 op = LLVMAtomicRMWBinOpMax;
4068 break;
4069 default:
4070 unreachable("unknown atomic opcode");
4071 }
4072
4073 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
4074 LLVMAtomicOrderingSequentiallyConsistent,
4075 false);
4076 }
4077 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
4078 }
4079
4080 static void atomic_emit(
4081 const struct lp_build_tgsi_action *action,
4082 struct lp_build_tgsi_context *bld_base,
4083 struct lp_build_emit_data *emit_data)
4084 {
4085 struct si_shader_context *ctx = si_shader_context(bld_base);
4086 struct gallivm_state *gallivm = &ctx->gallivm;
4087 LLVMBuilderRef builder = gallivm->builder;
4088 const struct tgsi_full_instruction * inst = emit_data->inst;
4089 char intrinsic_name[40];
4090 LLVMValueRef tmp;
4091
4092 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
4093 atomic_emit_memory(ctx, emit_data);
4094 return;
4095 }
4096
4097 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
4098 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4099 snprintf(intrinsic_name, sizeof(intrinsic_name),
4100 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
4101 } else {
4102 LLVMValueRef coords;
4103 char coords_type[8];
4104
4105 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4106 coords = emit_data->args[2];
4107 else
4108 coords = emit_data->args[1];
4109
4110 ac_build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
4111 snprintf(intrinsic_name, sizeof(intrinsic_name),
4112 "llvm.amdgcn.image.atomic.%s.%s",
4113 action->intr_name, coords_type);
4114 }
4115
4116 tmp = lp_build_intrinsic(
4117 builder, intrinsic_name, ctx->i32,
4118 emit_data->args, emit_data->arg_count, 0);
4119 emit_data->output[emit_data->chan] =
4120 LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4121 }
4122
4123 static void set_tex_fetch_args(struct si_shader_context *ctx,
4124 struct lp_build_emit_data *emit_data,
4125 unsigned target,
4126 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4127 LLVMValueRef *param, unsigned count,
4128 unsigned dmask)
4129 {
4130 struct gallivm_state *gallivm = &ctx->gallivm;
4131 struct ac_image_args args = {};
4132
4133 /* Pad to power of two vector */
4134 while (count < util_next_power_of_two(count))
4135 param[count++] = LLVMGetUndef(ctx->i32);
4136
4137 if (count > 1)
4138 args.addr = lp_build_gather_values(gallivm, param, count);
4139 else
4140 args.addr = param[0];
4141
4142 args.resource = res_ptr;
4143 args.sampler = samp_ptr;
4144 args.dmask = dmask;
4145 args.unorm = target == TGSI_TEXTURE_RECT ||
4146 target == TGSI_TEXTURE_SHADOWRECT;
4147 args.da = tgsi_is_array_sampler(target);
4148
4149 /* Ugly, but we seem to have no other choice right now. */
4150 STATIC_ASSERT(sizeof(args) <= sizeof(emit_data->args));
4151 memcpy(emit_data->args, &args, sizeof(args));
4152 }
4153
4154 static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
4155 unsigned target, LLVMValueRef out)
4156 {
4157 LLVMBuilderRef builder = ctx->gallivm.builder;
4158
4159 /* 1D textures are allocated and used as 2D on GFX9. */
4160 if (ctx->screen->b.chip_class >= GFX9 &&
4161 (target == TGSI_TEXTURE_1D_ARRAY ||
4162 target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
4163 LLVMValueRef layers =
4164 LLVMBuildExtractElement(builder, out,
4165 LLVMConstInt(ctx->i32, 2, 0), "");
4166 out = LLVMBuildInsertElement(builder, out, layers,
4167 ctx->i32_1, "");
4168 }
4169
4170 /* Divide the number of layers by 6 to get the number of cubes. */
4171 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4172 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4173 LLVMValueRef imm2 = LLVMConstInt(ctx->i32, 2, 0);
4174
4175 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4176 z = LLVMBuildSDiv(builder, z, LLVMConstInt(ctx->i32, 6, 0), "");
4177
4178 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4179 }
4180 return out;
4181 }
4182
4183 static void resq_fetch_args(
4184 struct lp_build_tgsi_context * bld_base,
4185 struct lp_build_emit_data * emit_data)
4186 {
4187 struct si_shader_context *ctx = si_shader_context(bld_base);
4188 const struct tgsi_full_instruction *inst = emit_data->inst;
4189 const struct tgsi_full_src_register *reg = &inst->Src[0];
4190
4191 emit_data->dst_type = ctx->v4i32;
4192
4193 if (reg->Register.File == TGSI_FILE_BUFFER) {
4194 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4195 emit_data->arg_count = 1;
4196 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4197 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4198 &emit_data->args[0]);
4199 emit_data->arg_count = 1;
4200 } else {
4201 LLVMValueRef res_ptr;
4202 unsigned image_target;
4203
4204 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
4205 image_target = TGSI_TEXTURE_2D_ARRAY;
4206 else
4207 image_target = inst->Memory.Texture;
4208
4209 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
4210 &res_ptr);
4211 set_tex_fetch_args(ctx, emit_data, image_target,
4212 res_ptr, NULL, &ctx->i32_0, 1,
4213 0xf);
4214 }
4215 }
4216
4217 static void resq_emit(
4218 const struct lp_build_tgsi_action *action,
4219 struct lp_build_tgsi_context *bld_base,
4220 struct lp_build_emit_data *emit_data)
4221 {
4222 struct si_shader_context *ctx = si_shader_context(bld_base);
4223 struct gallivm_state *gallivm = &ctx->gallivm;
4224 LLVMBuilderRef builder = gallivm->builder;
4225 const struct tgsi_full_instruction *inst = emit_data->inst;
4226 LLVMValueRef out;
4227
4228 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4229 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4230 LLVMConstInt(ctx->i32, 2, 0), "");
4231 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4232 out = get_buffer_size(bld_base, emit_data->args[0]);
4233 } else {
4234 struct ac_image_args args;
4235
4236 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4237 args.opcode = ac_image_get_resinfo;
4238 out = ac_build_image_opcode(&ctx->ac, &args);
4239
4240 out = fix_resinfo(ctx, inst->Memory.Texture, out);
4241 }
4242
4243 emit_data->output[emit_data->chan] = out;
4244 }
4245
4246 static const struct lp_build_tgsi_action tex_action;
4247
4248 enum desc_type {
4249 DESC_IMAGE,
4250 DESC_BUFFER,
4251 DESC_FMASK,
4252 DESC_SAMPLER,
4253 };
4254
4255 /**
4256 * Load an image view, fmask view. or sampler state descriptor.
4257 */
4258 static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx,
4259 LLVMValueRef list, LLVMValueRef index,
4260 enum desc_type type)
4261 {
4262 struct gallivm_state *gallivm = &ctx->gallivm;
4263 LLVMBuilderRef builder = gallivm->builder;
4264
4265 switch (type) {
4266 case DESC_IMAGE:
4267 /* The image is at [0:7]. */
4268 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4269 break;
4270 case DESC_BUFFER:
4271 /* The buffer is in [4:7]. */
4272 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4273 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
4274 list = LLVMBuildPointerCast(builder, list,
4275 const_array(ctx->v4i32, 0), "");
4276 break;
4277 case DESC_FMASK:
4278 /* The FMASK is at [8:15]. */
4279 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4280 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
4281 break;
4282 case DESC_SAMPLER:
4283 /* The sampler state is at [12:15]. */
4284 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4285 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4286 list = LLVMBuildPointerCast(builder, list,
4287 const_array(ctx->v4i32, 0), "");
4288 break;
4289 }
4290
4291 return ac_build_indexed_load_const(&ctx->ac, list, index);
4292 }
4293
4294 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4295 *
4296 * SI-CI:
4297 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4298 * filtering manually. The driver sets img7 to a mask clearing
4299 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4300 * s_and_b32 samp0, samp0, img7
4301 *
4302 * VI:
4303 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4304 */
4305 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4306 LLVMValueRef res, LLVMValueRef samp)
4307 {
4308 LLVMBuilderRef builder = ctx->gallivm.builder;
4309 LLVMValueRef img7, samp0;
4310
4311 if (ctx->screen->b.chip_class >= VI)
4312 return samp;
4313
4314 img7 = LLVMBuildExtractElement(builder, res,
4315 LLVMConstInt(ctx->i32, 7, 0), "");
4316 samp0 = LLVMBuildExtractElement(builder, samp,
4317 ctx->i32_0, "");
4318 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4319 return LLVMBuildInsertElement(builder, samp, samp0,
4320 ctx->i32_0, "");
4321 }
4322
4323 static void tex_fetch_ptrs(
4324 struct lp_build_tgsi_context *bld_base,
4325 struct lp_build_emit_data *emit_data,
4326 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4327 {
4328 struct si_shader_context *ctx = si_shader_context(bld_base);
4329 LLVMValueRef list = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLERS);
4330 const struct tgsi_full_instruction *inst = emit_data->inst;
4331 const struct tgsi_full_src_register *reg;
4332 unsigned target = inst->Texture.Texture;
4333 unsigned sampler_src;
4334 LLVMValueRef index;
4335
4336 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4337 reg = &emit_data->inst->Src[sampler_src];
4338
4339 if (reg->Register.Indirect) {
4340 index = get_bounded_indirect_index(ctx,
4341 &reg->Indirect,
4342 reg->Register.Index,
4343 SI_NUM_SAMPLERS);
4344 } else {
4345 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
4346 }
4347
4348 if (target == TGSI_TEXTURE_BUFFER)
4349 *res_ptr = load_sampler_desc(ctx, list, index, DESC_BUFFER);
4350 else
4351 *res_ptr = load_sampler_desc(ctx, list, index, DESC_IMAGE);
4352
4353 if (samp_ptr)
4354 *samp_ptr = NULL;
4355 if (fmask_ptr)
4356 *fmask_ptr = NULL;
4357
4358 if (target == TGSI_TEXTURE_2D_MSAA ||
4359 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4360 if (fmask_ptr)
4361 *fmask_ptr = load_sampler_desc(ctx, list, index,
4362 DESC_FMASK);
4363 } else if (target != TGSI_TEXTURE_BUFFER) {
4364 if (samp_ptr) {
4365 *samp_ptr = load_sampler_desc(ctx, list, index,
4366 DESC_SAMPLER);
4367 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4368 }
4369 }
4370 }
4371
4372 static void txq_fetch_args(
4373 struct lp_build_tgsi_context *bld_base,
4374 struct lp_build_emit_data *emit_data)
4375 {
4376 struct si_shader_context *ctx = si_shader_context(bld_base);
4377 const struct tgsi_full_instruction *inst = emit_data->inst;
4378 unsigned target = inst->Texture.Texture;
4379 LLVMValueRef res_ptr;
4380 LLVMValueRef address;
4381
4382 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4383
4384 if (target == TGSI_TEXTURE_BUFFER) {
4385 /* Read the size from the buffer descriptor directly. */
4386 emit_data->args[0] = get_buffer_size(bld_base, res_ptr);
4387 return;
4388 }
4389
4390 /* Textures - set the mip level. */
4391 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4392
4393 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
4394 NULL, &address, 1, 0xf);
4395 }
4396
4397 static void txq_emit(const struct lp_build_tgsi_action *action,
4398 struct lp_build_tgsi_context *bld_base,
4399 struct lp_build_emit_data *emit_data)
4400 {
4401 struct si_shader_context *ctx = si_shader_context(bld_base);
4402 struct ac_image_args args;
4403 unsigned target = emit_data->inst->Texture.Texture;
4404
4405 if (target == TGSI_TEXTURE_BUFFER) {
4406 /* Just return the buffer size. */
4407 emit_data->output[emit_data->chan] = emit_data->args[0];
4408 return;
4409 }
4410
4411 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4412
4413 args.opcode = ac_image_get_resinfo;
4414 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
4415
4416 emit_data->output[emit_data->chan] = fix_resinfo(ctx, target, result);
4417 }
4418
4419 static void tex_fetch_args(
4420 struct lp_build_tgsi_context *bld_base,
4421 struct lp_build_emit_data *emit_data)
4422 {
4423 struct si_shader_context *ctx = si_shader_context(bld_base);
4424 struct gallivm_state *gallivm = &ctx->gallivm;
4425 const struct tgsi_full_instruction *inst = emit_data->inst;
4426 unsigned opcode = inst->Instruction.Opcode;
4427 unsigned target = inst->Texture.Texture;
4428 LLVMValueRef coords[5], derivs[6];
4429 LLVMValueRef address[16];
4430 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4431 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4432 unsigned count = 0;
4433 unsigned chan;
4434 unsigned num_deriv_channels = 0;
4435 bool has_offset = inst->Texture.NumOffsets > 0;
4436 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4437 unsigned dmask = 0xf;
4438
4439 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4440
4441 if (target == TGSI_TEXTURE_BUFFER) {
4442 emit_data->dst_type = ctx->v4f32;
4443 emit_data->args[0] = LLVMBuildBitCast(gallivm->builder, res_ptr,
4444 ctx->v16i8, "");
4445 emit_data->args[1] = ctx->i32_0;
4446 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4447 emit_data->arg_count = 3;
4448 return;
4449 }
4450
4451 /* Fetch and project texture coordinates */
4452 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4453 for (chan = 0; chan < 3; chan++ ) {
4454 coords[chan] = lp_build_emit_fetch(bld_base,
4455 emit_data->inst, 0,
4456 chan);
4457 if (opcode == TGSI_OPCODE_TXP)
4458 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4459 TGSI_OPCODE_DIV,
4460 coords[chan],
4461 coords[3]);
4462 }
4463
4464 if (opcode == TGSI_OPCODE_TXP)
4465 coords[3] = bld_base->base.one;
4466
4467 /* Pack offsets. */
4468 if (has_offset &&
4469 opcode != TGSI_OPCODE_TXF &&
4470 opcode != TGSI_OPCODE_TXF_LZ) {
4471 /* The offsets are six-bit signed integers packed like this:
4472 * X=[5:0], Y=[13:8], and Z=[21:16].
4473 */
4474 LLVMValueRef offset[3], pack;
4475
4476 assert(inst->Texture.NumOffsets == 1);
4477
4478 for (chan = 0; chan < 3; chan++) {
4479 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4480 emit_data->inst, 0, chan);
4481 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4482 LLVMConstInt(ctx->i32, 0x3f, 0), "");
4483 if (chan)
4484 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4485 LLVMConstInt(ctx->i32, chan*8, 0), "");
4486 }
4487
4488 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4489 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4490 address[count++] = pack;
4491 }
4492
4493 /* Pack LOD bias value */
4494 if (opcode == TGSI_OPCODE_TXB)
4495 address[count++] = coords[3];
4496 if (opcode == TGSI_OPCODE_TXB2)
4497 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4498
4499 /* Pack depth comparison value */
4500 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4501 LLVMValueRef z;
4502
4503 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4504 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4505 } else {
4506 assert(ref_pos >= 0);
4507 z = coords[ref_pos];
4508 }
4509
4510 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4511 * so the depth comparison value isn't clamped for Z16 and
4512 * Z24 anymore. Do it manually here.
4513 *
4514 * It's unnecessary if the original texture format was
4515 * Z32_FLOAT, but we don't know that here.
4516 */
4517 if (ctx->screen->b.chip_class == VI)
4518 z = ac_build_clamp(&ctx->ac, z);
4519
4520 address[count++] = z;
4521 }
4522
4523 /* Pack user derivatives */
4524 if (opcode == TGSI_OPCODE_TXD) {
4525 int param, num_src_deriv_channels, num_dst_deriv_channels;
4526
4527 switch (target) {
4528 case TGSI_TEXTURE_3D:
4529 num_src_deriv_channels = 3;
4530 num_dst_deriv_channels = 3;
4531 num_deriv_channels = 3;
4532 break;
4533 case TGSI_TEXTURE_2D:
4534 case TGSI_TEXTURE_SHADOW2D:
4535 case TGSI_TEXTURE_RECT:
4536 case TGSI_TEXTURE_SHADOWRECT:
4537 case TGSI_TEXTURE_2D_ARRAY:
4538 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4539 num_src_deriv_channels = 2;
4540 num_dst_deriv_channels = 2;
4541 num_deriv_channels = 2;
4542 break;
4543 case TGSI_TEXTURE_CUBE:
4544 case TGSI_TEXTURE_SHADOWCUBE:
4545 case TGSI_TEXTURE_CUBE_ARRAY:
4546 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4547 /* Cube derivatives will be converted to 2D. */
4548 num_src_deriv_channels = 3;
4549 num_dst_deriv_channels = 3;
4550 num_deriv_channels = 2;
4551 break;
4552 case TGSI_TEXTURE_1D:
4553 case TGSI_TEXTURE_SHADOW1D:
4554 case TGSI_TEXTURE_1D_ARRAY:
4555 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4556 num_src_deriv_channels = 1;
4557
4558 /* 1D textures are allocated and used as 2D on GFX9. */
4559 if (ctx->screen->b.chip_class >= GFX9) {
4560 num_dst_deriv_channels = 2;
4561 num_deriv_channels = 2;
4562 } else {
4563 num_dst_deriv_channels = 1;
4564 num_deriv_channels = 1;
4565 }
4566 break;
4567 default:
4568 unreachable("invalid target");
4569 }
4570
4571 for (param = 0; param < 2; param++) {
4572 for (chan = 0; chan < num_src_deriv_channels; chan++)
4573 derivs[param * num_dst_deriv_channels + chan] =
4574 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4575
4576 /* Fill in the rest with zeros. */
4577 for (chan = num_src_deriv_channels;
4578 chan < num_dst_deriv_channels; chan++)
4579 derivs[param * num_dst_deriv_channels + chan] =
4580 bld_base->base.zero;
4581 }
4582 }
4583
4584 if (target == TGSI_TEXTURE_CUBE ||
4585 target == TGSI_TEXTURE_CUBE_ARRAY ||
4586 target == TGSI_TEXTURE_SHADOWCUBE ||
4587 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4588 ac_prepare_cube_coords(&ctx->ac,
4589 opcode == TGSI_OPCODE_TXD,
4590 target == TGSI_TEXTURE_CUBE_ARRAY ||
4591 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
4592 coords, derivs);
4593
4594 if (opcode == TGSI_OPCODE_TXD)
4595 for (int i = 0; i < num_deriv_channels * 2; i++)
4596 address[count++] = derivs[i];
4597
4598 /* Pack texture coordinates */
4599 address[count++] = coords[0];
4600 if (num_coords > 1)
4601 address[count++] = coords[1];
4602 if (num_coords > 2)
4603 address[count++] = coords[2];
4604
4605 /* 1D textures are allocated and used as 2D on GFX9. */
4606 if (ctx->screen->b.chip_class >= GFX9) {
4607 LLVMValueRef filler;
4608
4609 /* Use 0.5, so that we don't sample the border color. */
4610 if (opcode == TGSI_OPCODE_TXF)
4611 filler = ctx->i32_0;
4612 else
4613 filler = LLVMConstReal(ctx->f32, 0.5);
4614
4615 if (target == TGSI_TEXTURE_1D ||
4616 target == TGSI_TEXTURE_SHADOW1D) {
4617 address[count++] = filler;
4618 } else if (target == TGSI_TEXTURE_1D_ARRAY ||
4619 target == TGSI_TEXTURE_SHADOW1D_ARRAY) {
4620 address[count] = address[count - 1];
4621 address[count - 1] = filler;
4622 count++;
4623 }
4624 }
4625
4626 /* Pack LOD or sample index */
4627 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4628 address[count++] = coords[3];
4629 else if (opcode == TGSI_OPCODE_TXL2)
4630 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4631
4632 if (count > 16) {
4633 assert(!"Cannot handle more than 16 texture address parameters");
4634 count = 16;
4635 }
4636
4637 for (chan = 0; chan < count; chan++ ) {
4638 address[chan] = LLVMBuildBitCast(gallivm->builder,
4639 address[chan], ctx->i32, "");
4640 }
4641
4642 /* Adjust the sample index according to FMASK.
4643 *
4644 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4645 * which is the identity mapping. Each nibble says which physical sample
4646 * should be fetched to get that sample.
4647 *
4648 * For example, 0x11111100 means there are only 2 samples stored and
4649 * the second sample covers 3/4 of the pixel. When reading samples 0
4650 * and 1, return physical sample 0 (determined by the first two 0s
4651 * in FMASK), otherwise return physical sample 1.
4652 *
4653 * The sample index should be adjusted as follows:
4654 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4655 */
4656 if (target == TGSI_TEXTURE_2D_MSAA ||
4657 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4658 struct lp_build_emit_data txf_emit_data = *emit_data;
4659 LLVMValueRef txf_address[4];
4660 /* We only need .xy for non-arrays, and .xyz for arrays. */
4661 unsigned txf_count = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4662 struct tgsi_full_instruction inst = {};
4663
4664 memcpy(txf_address, address, sizeof(txf_address));
4665
4666 /* Read FMASK using TXF_LZ. */
4667 inst.Instruction.Opcode = TGSI_OPCODE_TXF_LZ;
4668 inst.Texture.Texture = target;
4669 txf_emit_data.inst = &inst;
4670 txf_emit_data.chan = 0;
4671 set_tex_fetch_args(ctx, &txf_emit_data,
4672 target, fmask_ptr, NULL,
4673 txf_address, txf_count, 0xf);
4674 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4675
4676 /* Initialize some constants. */
4677 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4678 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4679
4680 /* Apply the formula. */
4681 LLVMValueRef fmask =
4682 LLVMBuildExtractElement(gallivm->builder,
4683 txf_emit_data.output[0],
4684 ctx->i32_0, "");
4685
4686 unsigned sample_chan = txf_count; /* the sample index is last */
4687
4688 LLVMValueRef sample_index4 =
4689 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4690
4691 LLVMValueRef shifted_fmask =
4692 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4693
4694 LLVMValueRef final_sample =
4695 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4696
4697 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4698 * resource descriptor is 0 (invalid),
4699 */
4700 LLVMValueRef fmask_desc =
4701 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4702 ctx->v8i32, "");
4703
4704 LLVMValueRef fmask_word1 =
4705 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4706 ctx->i32_1, "");
4707
4708 LLVMValueRef word1_is_nonzero =
4709 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4710 fmask_word1, ctx->i32_0, "");
4711
4712 /* Replace the MSAA sample index. */
4713 address[sample_chan] =
4714 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4715 final_sample, address[sample_chan], "");
4716 }
4717
4718 if (opcode == TGSI_OPCODE_TXF ||
4719 opcode == TGSI_OPCODE_TXF_LZ) {
4720 /* add tex offsets */
4721 if (inst->Texture.NumOffsets) {
4722 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4723 const struct tgsi_texture_offset *off = inst->TexOffsets;
4724
4725 assert(inst->Texture.NumOffsets == 1);
4726
4727 switch (target) {
4728 case TGSI_TEXTURE_3D:
4729 address[2] = lp_build_add(uint_bld, address[2],
4730 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ]);
4731 /* fall through */
4732 case TGSI_TEXTURE_2D:
4733 case TGSI_TEXTURE_SHADOW2D:
4734 case TGSI_TEXTURE_RECT:
4735 case TGSI_TEXTURE_SHADOWRECT:
4736 case TGSI_TEXTURE_2D_ARRAY:
4737 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4738 address[1] =
4739 lp_build_add(uint_bld, address[1],
4740 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY]);
4741 /* fall through */
4742 case TGSI_TEXTURE_1D:
4743 case TGSI_TEXTURE_SHADOW1D:
4744 case TGSI_TEXTURE_1D_ARRAY:
4745 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4746 address[0] =
4747 lp_build_add(uint_bld, address[0],
4748 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX]);
4749 break;
4750 /* texture offsets do not apply to other texture targets */
4751 }
4752 }
4753 }
4754
4755 if (opcode == TGSI_OPCODE_TG4) {
4756 unsigned gather_comp = 0;
4757
4758 /* DMASK was repurposed for GATHER4. 4 components are always
4759 * returned and DMASK works like a swizzle - it selects
4760 * the component to fetch. The only valid DMASK values are
4761 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4762 * (red,red,red,red) etc.) The ISA document doesn't mention
4763 * this.
4764 */
4765
4766 /* Get the component index from src1.x for Gather4. */
4767 if (!tgsi_is_shadow_target(target)) {
4768 LLVMValueRef comp_imm;
4769 struct tgsi_src_register src1 = inst->Src[1].Register;
4770
4771 assert(src1.File == TGSI_FILE_IMMEDIATE);
4772
4773 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
4774 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4775 gather_comp = CLAMP(gather_comp, 0, 3);
4776 }
4777
4778 dmask = 1 << gather_comp;
4779 }
4780
4781 set_tex_fetch_args(ctx, emit_data, target, res_ptr,
4782 samp_ptr, address, count, dmask);
4783 }
4784
4785 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4786 * incorrectly forces nearest filtering if the texture format is integer.
4787 * The only effect it has on Gather4, which always returns 4 texels for
4788 * bilinear filtering, is that the final coordinates are off by 0.5 of
4789 * the texel size.
4790 *
4791 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4792 * or (0.5 / size) from the normalized coordinates.
4793 */
4794 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4795 struct ac_image_args *args,
4796 unsigned target)
4797 {
4798 LLVMBuilderRef builder = ctx->gallivm.builder;
4799 LLVMValueRef coord = args->addr;
4800 LLVMValueRef half_texel[2];
4801 /* Texture coordinates start after:
4802 * {offset, bias, z-compare, derivatives}
4803 * Only the offset and z-compare can occur here.
4804 */
4805 unsigned coord_vgpr_index = (int)args->offset + (int)args->compare;
4806 int c;
4807
4808 if (target == TGSI_TEXTURE_RECT ||
4809 target == TGSI_TEXTURE_SHADOWRECT) {
4810 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4811 } else {
4812 struct tgsi_full_instruction txq_inst = {};
4813 struct lp_build_emit_data txq_emit_data = {};
4814
4815 /* Query the texture size. */
4816 txq_inst.Texture.Texture = target;
4817 txq_emit_data.inst = &txq_inst;
4818 txq_emit_data.dst_type = ctx->v4i32;
4819 set_tex_fetch_args(ctx, &txq_emit_data, target,
4820 args->resource, NULL, &ctx->i32_0,
4821 1, 0xf);
4822 txq_emit(NULL, &ctx->bld_base, &txq_emit_data);
4823
4824 /* Compute -0.5 / size. */
4825 for (c = 0; c < 2; c++) {
4826 half_texel[c] =
4827 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4828 LLVMConstInt(ctx->i32, c, 0), "");
4829 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4830 half_texel[c] =
4831 lp_build_emit_llvm_unary(&ctx->bld_base,
4832 TGSI_OPCODE_RCP, half_texel[c]);
4833 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4834 LLVMConstReal(ctx->f32, -0.5), "");
4835 }
4836 }
4837
4838 for (c = 0; c < 2; c++) {
4839 LLVMValueRef tmp;
4840 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4841
4842 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4843 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4844 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4845 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4846 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4847 }
4848
4849 args->addr = coord;
4850 }
4851
4852 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4853 struct lp_build_tgsi_context *bld_base,
4854 struct lp_build_emit_data *emit_data)
4855 {
4856 struct si_shader_context *ctx = si_shader_context(bld_base);
4857 const struct tgsi_full_instruction *inst = emit_data->inst;
4858 struct ac_image_args args;
4859 unsigned opcode = inst->Instruction.Opcode;
4860 unsigned target = inst->Texture.Texture;
4861
4862 if (target == TGSI_TEXTURE_BUFFER) {
4863 emit_data->output[emit_data->chan] =
4864 ac_build_buffer_load_format(&ctx->ac,
4865 emit_data->args[0],
4866 emit_data->args[2],
4867 emit_data->args[1],
4868 true);
4869 return;
4870 }
4871
4872 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
4873
4874 args.opcode = ac_image_sample;
4875 args.compare = tgsi_is_shadow_target(target);
4876 args.offset = inst->Texture.NumOffsets > 0;
4877
4878 switch (opcode) {
4879 case TGSI_OPCODE_TXF:
4880 case TGSI_OPCODE_TXF_LZ:
4881 args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
4882 target == TGSI_TEXTURE_2D_MSAA ||
4883 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4884 ac_image_load : ac_image_load_mip;
4885 args.compare = false;
4886 args.offset = false;
4887 break;
4888 case TGSI_OPCODE_LODQ:
4889 args.opcode = ac_image_get_lod;
4890 args.compare = false;
4891 args.offset = false;
4892 break;
4893 case TGSI_OPCODE_TEX:
4894 case TGSI_OPCODE_TEX2:
4895 case TGSI_OPCODE_TXP:
4896 if (ctx->type != PIPE_SHADER_FRAGMENT)
4897 args.level_zero = true;
4898 break;
4899 case TGSI_OPCODE_TEX_LZ:
4900 args.level_zero = true;
4901 break;
4902 case TGSI_OPCODE_TXB:
4903 case TGSI_OPCODE_TXB2:
4904 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4905 args.bias = true;
4906 break;
4907 case TGSI_OPCODE_TXL:
4908 case TGSI_OPCODE_TXL2:
4909 args.lod = true;
4910 break;
4911 case TGSI_OPCODE_TXD:
4912 args.deriv = true;
4913 break;
4914 case TGSI_OPCODE_TG4:
4915 args.opcode = ac_image_gather4;
4916 args.level_zero = true;
4917 break;
4918 default:
4919 assert(0);
4920 return;
4921 }
4922
4923 /* The hardware needs special lowering for Gather4 with integer formats. */
4924 if (ctx->screen->b.chip_class <= VI &&
4925 opcode == TGSI_OPCODE_TG4) {
4926 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4927 /* This will also work with non-constant indexing because of how
4928 * glsl_to_tgsi works and we intent to preserve that behavior.
4929 */
4930 const unsigned src_idx = 2;
4931 unsigned sampler = inst->Src[src_idx].Register.Index;
4932
4933 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
4934
4935 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
4936 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT)
4937 si_lower_gather4_integer(ctx, &args, target);
4938 }
4939
4940 emit_data->output[emit_data->chan] =
4941 ac_build_image_opcode(&ctx->ac, &args);
4942 }
4943
4944 static void si_llvm_emit_txqs(
4945 const struct lp_build_tgsi_action *action,
4946 struct lp_build_tgsi_context *bld_base,
4947 struct lp_build_emit_data *emit_data)
4948 {
4949 struct si_shader_context *ctx = si_shader_context(bld_base);
4950 struct gallivm_state *gallivm = &ctx->gallivm;
4951 LLVMBuilderRef builder = gallivm->builder;
4952 LLVMValueRef res, samples;
4953 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4954
4955 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4956
4957
4958 /* Read the samples from the descriptor directly. */
4959 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4960 samples = LLVMBuildExtractElement(
4961 builder, res,
4962 LLVMConstInt(ctx->i32, 3, 0), "");
4963 samples = LLVMBuildLShr(builder, samples,
4964 LLVMConstInt(ctx->i32, 16, 0), "");
4965 samples = LLVMBuildAnd(builder, samples,
4966 LLVMConstInt(ctx->i32, 0xf, 0), "");
4967 samples = LLVMBuildShl(builder, ctx->i32_1,
4968 samples, "");
4969
4970 emit_data->output[emit_data->chan] = samples;
4971 }
4972
4973 static void si_llvm_emit_ddxy(
4974 const struct lp_build_tgsi_action *action,
4975 struct lp_build_tgsi_context *bld_base,
4976 struct lp_build_emit_data *emit_data)
4977 {
4978 struct si_shader_context *ctx = si_shader_context(bld_base);
4979 struct gallivm_state *gallivm = &ctx->gallivm;
4980 unsigned opcode = emit_data->info->opcode;
4981 LLVMValueRef val;
4982 int idx;
4983 unsigned mask;
4984
4985 if (opcode == TGSI_OPCODE_DDX_FINE)
4986 mask = AC_TID_MASK_LEFT;
4987 else if (opcode == TGSI_OPCODE_DDY_FINE)
4988 mask = AC_TID_MASK_TOP;
4989 else
4990 mask = AC_TID_MASK_TOP_LEFT;
4991
4992 /* for DDX we want to next X pixel, DDY next Y pixel. */
4993 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
4994
4995 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
4996 val = ac_build_ddxy(&ctx->ac, ctx->screen->has_ds_bpermute,
4997 mask, idx, ctx->lds, val);
4998 emit_data->output[emit_data->chan] = val;
4999 }
5000
5001 /*
5002 * this takes an I,J coordinate pair,
5003 * and works out the X and Y derivatives.
5004 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
5005 */
5006 static LLVMValueRef si_llvm_emit_ddxy_interp(
5007 struct lp_build_tgsi_context *bld_base,
5008 LLVMValueRef interp_ij)
5009 {
5010 struct si_shader_context *ctx = si_shader_context(bld_base);
5011 struct gallivm_state *gallivm = &ctx->gallivm;
5012 LLVMValueRef result[4], a;
5013 unsigned i;
5014
5015 for (i = 0; i < 2; i++) {
5016 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
5017 LLVMConstInt(ctx->i32, i, 0), "");
5018 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
5019 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
5020 }
5021
5022 return lp_build_gather_values(gallivm, result, 4);
5023 }
5024
5025 static void interp_fetch_args(
5026 struct lp_build_tgsi_context *bld_base,
5027 struct lp_build_emit_data *emit_data)
5028 {
5029 struct si_shader_context *ctx = si_shader_context(bld_base);
5030 struct gallivm_state *gallivm = &ctx->gallivm;
5031 const struct tgsi_full_instruction *inst = emit_data->inst;
5032
5033 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
5034 /* offset is in second src, first two channels */
5035 emit_data->args[0] = lp_build_emit_fetch(bld_base,
5036 emit_data->inst, 1,
5037 TGSI_CHAN_X);
5038 emit_data->args[1] = lp_build_emit_fetch(bld_base,
5039 emit_data->inst, 1,
5040 TGSI_CHAN_Y);
5041 emit_data->arg_count = 2;
5042 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5043 LLVMValueRef sample_position;
5044 LLVMValueRef sample_id;
5045 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
5046
5047 /* fetch sample ID, then fetch its sample position,
5048 * and place into first two channels.
5049 */
5050 sample_id = lp_build_emit_fetch(bld_base,
5051 emit_data->inst, 1, TGSI_CHAN_X);
5052 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
5053 ctx->i32, "");
5054 sample_position = load_sample_position(ctx, sample_id);
5055
5056 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
5057 sample_position,
5058 ctx->i32_0, "");
5059
5060 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
5061 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
5062 sample_position,
5063 ctx->i32_1, "");
5064 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
5065 emit_data->arg_count = 2;
5066 }
5067 }
5068
5069 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
5070 struct lp_build_tgsi_context *bld_base,
5071 struct lp_build_emit_data *emit_data)
5072 {
5073 struct si_shader_context *ctx = si_shader_context(bld_base);
5074 struct si_shader *shader = ctx->shader;
5075 struct gallivm_state *gallivm = &ctx->gallivm;
5076 LLVMValueRef interp_param;
5077 const struct tgsi_full_instruction *inst = emit_data->inst;
5078 int input_index = inst->Src[0].Register.Index;
5079 int chan;
5080 int i;
5081 LLVMValueRef attr_number;
5082 LLVMValueRef params = LLVMGetParam(ctx->main_fn, SI_PARAM_PRIM_MASK);
5083 int interp_param_idx;
5084 unsigned interp = shader->selector->info.input_interpolate[input_index];
5085 unsigned location;
5086
5087 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5088
5089 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5090 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5091 location = TGSI_INTERPOLATE_LOC_CENTER;
5092 else
5093 location = TGSI_INTERPOLATE_LOC_CENTROID;
5094
5095 interp_param_idx = lookup_interp_param_index(interp, location);
5096 if (interp_param_idx == -1)
5097 return;
5098 else if (interp_param_idx)
5099 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
5100 else
5101 interp_param = NULL;
5102
5103 attr_number = LLVMConstInt(ctx->i32, input_index, 0);
5104
5105 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5106 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5107 LLVMValueRef ij_out[2];
5108 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5109
5110 /*
5111 * take the I then J parameters, and the DDX/Y for it, and
5112 * calculate the IJ inputs for the interpolator.
5113 * temp1 = ddx * offset/sample.x + I;
5114 * interp_param.I = ddy * offset/sample.y + temp1;
5115 * temp1 = ddx * offset/sample.x + J;
5116 * interp_param.J = ddy * offset/sample.y + temp1;
5117 */
5118 for (i = 0; i < 2; i++) {
5119 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
5120 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
5121 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5122 ddxy_out, ix_ll, "");
5123 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5124 ddxy_out, iy_ll, "");
5125 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5126 interp_param, ix_ll, "");
5127 LLVMValueRef temp1, temp2;
5128
5129 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5130 ctx->f32, "");
5131
5132 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5133
5134 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5135
5136 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5137
5138 ij_out[i] = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5139 }
5140 interp_param = lp_build_gather_values(gallivm, ij_out, 2);
5141 }
5142
5143 for (chan = 0; chan < 4; chan++) {
5144 LLVMValueRef llvm_chan;
5145 unsigned schan;
5146
5147 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5148 llvm_chan = LLVMConstInt(ctx->i32, schan, 0);
5149
5150 if (interp_param) {
5151 interp_param = LLVMBuildBitCast(gallivm->builder,
5152 interp_param, LLVMVectorType(ctx->f32, 2), "");
5153 LLVMValueRef i = LLVMBuildExtractElement(
5154 gallivm->builder, interp_param, ctx->i32_0, "");
5155 LLVMValueRef j = LLVMBuildExtractElement(
5156 gallivm->builder, interp_param, ctx->i32_1, "");
5157 emit_data->output[chan] = ac_build_fs_interp(&ctx->ac,
5158 llvm_chan, attr_number, params,
5159 i, j);
5160 } else {
5161 emit_data->output[chan] = ac_build_fs_interp_mov(&ctx->ac,
5162 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
5163 llvm_chan, attr_number, params);
5164 }
5165 }
5166 }
5167
5168 static LLVMValueRef si_emit_ballot(struct si_shader_context *ctx,
5169 LLVMValueRef value)
5170 {
5171 struct gallivm_state *gallivm = &ctx->gallivm;
5172 LLVMValueRef args[3] = {
5173 value,
5174 ctx->i32_0,
5175 LLVMConstInt(ctx->i32, LLVMIntNE, 0)
5176 };
5177
5178 /* We currently have no other way to prevent LLVM from lifting the icmp
5179 * calls to a dominating basic block.
5180 */
5181 emit_optimization_barrier(ctx, &args[0]);
5182
5183 if (LLVMTypeOf(args[0]) != ctx->i32)
5184 args[0] = LLVMBuildBitCast(gallivm->builder, args[0], ctx->i32, "");
5185
5186 return lp_build_intrinsic(gallivm->builder,
5187 "llvm.amdgcn.icmp.i32",
5188 ctx->i64, args, 3,
5189 LP_FUNC_ATTR_NOUNWIND |
5190 LP_FUNC_ATTR_READNONE |
5191 LP_FUNC_ATTR_CONVERGENT);
5192 }
5193
5194 static void vote_all_emit(
5195 const struct lp_build_tgsi_action *action,
5196 struct lp_build_tgsi_context *bld_base,
5197 struct lp_build_emit_data *emit_data)
5198 {
5199 struct si_shader_context *ctx = si_shader_context(bld_base);
5200 struct gallivm_state *gallivm = &ctx->gallivm;
5201 LLVMValueRef active_set, vote_set;
5202 LLVMValueRef tmp;
5203
5204 active_set = si_emit_ballot(ctx, ctx->i32_1);
5205 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
5206
5207 tmp = LLVMBuildICmp(gallivm->builder, LLVMIntEQ, vote_set, active_set, "");
5208 emit_data->output[emit_data->chan] =
5209 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
5210 }
5211
5212 static void vote_any_emit(
5213 const struct lp_build_tgsi_action *action,
5214 struct lp_build_tgsi_context *bld_base,
5215 struct lp_build_emit_data *emit_data)
5216 {
5217 struct si_shader_context *ctx = si_shader_context(bld_base);
5218 struct gallivm_state *gallivm = &ctx->gallivm;
5219 LLVMValueRef vote_set;
5220 LLVMValueRef tmp;
5221
5222 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
5223
5224 tmp = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
5225 vote_set, LLVMConstInt(ctx->i64, 0, 0), "");
5226 emit_data->output[emit_data->chan] =
5227 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
5228 }
5229
5230 static void vote_eq_emit(
5231 const struct lp_build_tgsi_action *action,
5232 struct lp_build_tgsi_context *bld_base,
5233 struct lp_build_emit_data *emit_data)
5234 {
5235 struct si_shader_context *ctx = si_shader_context(bld_base);
5236 struct gallivm_state *gallivm = &ctx->gallivm;
5237 LLVMValueRef active_set, vote_set;
5238 LLVMValueRef all, none, tmp;
5239
5240 active_set = si_emit_ballot(ctx, ctx->i32_1);
5241 vote_set = si_emit_ballot(ctx, emit_data->args[0]);
5242
5243 all = LLVMBuildICmp(gallivm->builder, LLVMIntEQ, vote_set, active_set, "");
5244 none = LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
5245 vote_set, LLVMConstInt(ctx->i64, 0, 0), "");
5246 tmp = LLVMBuildOr(gallivm->builder, all, none, "");
5247 emit_data->output[emit_data->chan] =
5248 LLVMBuildSExt(gallivm->builder, tmp, ctx->i32, "");
5249 }
5250
5251 static void ballot_emit(
5252 const struct lp_build_tgsi_action *action,
5253 struct lp_build_tgsi_context *bld_base,
5254 struct lp_build_emit_data *emit_data)
5255 {
5256 struct si_shader_context *ctx = si_shader_context(bld_base);
5257 LLVMBuilderRef builder = ctx->gallivm.builder;
5258 LLVMValueRef tmp;
5259
5260 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
5261 tmp = si_emit_ballot(ctx, tmp);
5262 tmp = LLVMBuildBitCast(builder, tmp, ctx->v2i32, "");
5263
5264 emit_data->output[0] = LLVMBuildExtractElement(builder, tmp, ctx->i32_0, "");
5265 emit_data->output[1] = LLVMBuildExtractElement(builder, tmp, ctx->i32_1, "");
5266 }
5267
5268 static void read_invoc_fetch_args(
5269 struct lp_build_tgsi_context *bld_base,
5270 struct lp_build_emit_data *emit_data)
5271 {
5272 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
5273 0, emit_data->src_chan);
5274
5275 /* Always read the source invocation (= lane) from the X channel. */
5276 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
5277 1, TGSI_CHAN_X);
5278 emit_data->arg_count = 2;
5279 }
5280
5281 static void read_lane_emit(
5282 const struct lp_build_tgsi_action *action,
5283 struct lp_build_tgsi_context *bld_base,
5284 struct lp_build_emit_data *emit_data)
5285 {
5286 struct si_shader_context *ctx = si_shader_context(bld_base);
5287 LLVMBuilderRef builder = ctx->gallivm.builder;
5288
5289 /* We currently have no other way to prevent LLVM from lifting the icmp
5290 * calls to a dominating basic block.
5291 */
5292 emit_optimization_barrier(ctx, &emit_data->args[0]);
5293
5294 for (unsigned i = 0; i < emit_data->arg_count; ++i) {
5295 emit_data->args[i] = LLVMBuildBitCast(builder, emit_data->args[i],
5296 ctx->i32, "");
5297 }
5298
5299 emit_data->output[emit_data->chan] =
5300 ac_build_intrinsic(&ctx->ac, action->intr_name,
5301 ctx->i32, emit_data->args, emit_data->arg_count,
5302 AC_FUNC_ATTR_READNONE |
5303 AC_FUNC_ATTR_CONVERGENT);
5304 }
5305
5306 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5307 struct lp_build_emit_data *emit_data)
5308 {
5309 struct si_shader_context *ctx = si_shader_context(bld_base);
5310 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5311 LLVMValueRef imm;
5312 unsigned stream;
5313
5314 assert(src0.File == TGSI_FILE_IMMEDIATE);
5315
5316 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
5317 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
5318 return stream;
5319 }
5320
5321 /* Emit one vertex from the geometry shader */
5322 static void si_llvm_emit_vertex(
5323 const struct lp_build_tgsi_action *action,
5324 struct lp_build_tgsi_context *bld_base,
5325 struct lp_build_emit_data *emit_data)
5326 {
5327 struct si_shader_context *ctx = si_shader_context(bld_base);
5328 struct lp_build_context *uint = &bld_base->uint_bld;
5329 struct si_shader *shader = ctx->shader;
5330 struct tgsi_shader_info *info = &shader->selector->info;
5331 struct gallivm_state *gallivm = &ctx->gallivm;
5332 struct lp_build_if_state if_state;
5333 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
5334 SI_PARAM_GS2VS_OFFSET);
5335 LLVMValueRef gs_next_vertex;
5336 LLVMValueRef can_emit, kill;
5337 unsigned chan, offset;
5338 int i;
5339 unsigned stream;
5340
5341 stream = si_llvm_get_stream(bld_base, emit_data);
5342
5343 /* Write vertex attribute values to GSVS ring */
5344 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5345 ctx->gs_next_vertex[stream],
5346 "");
5347
5348 /* If this thread has already emitted the declared maximum number of
5349 * vertices, skip the write: excessive vertex emissions are not
5350 * supposed to have any effect.
5351 *
5352 * If the shader has no writes to memory, kill it instead. This skips
5353 * further memory loads and may allow LLVM to skip to the end
5354 * altogether.
5355 */
5356 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULT, gs_next_vertex,
5357 LLVMConstInt(ctx->i32,
5358 shader->selector->gs_max_out_vertices, 0), "");
5359
5360 bool use_kill = !info->writes_memory;
5361 if (use_kill) {
5362 kill = lp_build_select(&bld_base->base, can_emit,
5363 LLVMConstReal(ctx->f32, 1.0f),
5364 LLVMConstReal(ctx->f32, -1.0f));
5365
5366 ac_build_kill(&ctx->ac, kill);
5367 } else {
5368 lp_build_if(&if_state, gallivm, can_emit);
5369 }
5370
5371 offset = 0;
5372 for (i = 0; i < info->num_outputs; i++) {
5373 LLVMValueRef *out_ptr = ctx->outputs[i];
5374
5375 for (chan = 0; chan < 4; chan++) {
5376 if (!(info->output_usagemask[i] & (1 << chan)) ||
5377 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
5378 continue;
5379
5380 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5381 LLVMValueRef voffset =
5382 LLVMConstInt(ctx->i32, offset *
5383 shader->selector->gs_max_out_vertices, 0);
5384 offset++;
5385
5386 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5387 voffset = lp_build_mul_imm(uint, voffset, 4);
5388
5389 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5390
5391 ac_build_buffer_store_dword(&ctx->ac,
5392 ctx->gsvs_ring[stream],
5393 out_val, 1,
5394 voffset, soffset, 0,
5395 1, 1, true, true);
5396 }
5397 }
5398
5399 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5400 ctx->i32_1);
5401
5402 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5403
5404 /* Signal vertex emission */
5405 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
5406 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
5407 if (!use_kill)
5408 lp_build_endif(&if_state);
5409 }
5410
5411 /* Cut one primitive from the geometry shader */
5412 static void si_llvm_emit_primitive(
5413 const struct lp_build_tgsi_action *action,
5414 struct lp_build_tgsi_context *bld_base,
5415 struct lp_build_emit_data *emit_data)
5416 {
5417 struct si_shader_context *ctx = si_shader_context(bld_base);
5418 unsigned stream;
5419
5420 /* Signal primitive cut */
5421 stream = si_llvm_get_stream(bld_base, emit_data);
5422 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
5423 LLVMGetParam(ctx->main_fn, SI_PARAM_GS_WAVE_ID));
5424 }
5425
5426 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5427 struct lp_build_tgsi_context *bld_base,
5428 struct lp_build_emit_data *emit_data)
5429 {
5430 struct si_shader_context *ctx = si_shader_context(bld_base);
5431 struct gallivm_state *gallivm = &ctx->gallivm;
5432
5433 /* SI only (thanks to a hw bug workaround):
5434 * The real barrier instruction isn’t needed, because an entire patch
5435 * always fits into a single wave.
5436 */
5437 if (HAVE_LLVM >= 0x0309 &&
5438 ctx->screen->b.chip_class == SI &&
5439 ctx->type == PIPE_SHADER_TESS_CTRL) {
5440 emit_waitcnt(ctx, LGKM_CNT & VM_CNT);
5441 return;
5442 }
5443
5444 lp_build_intrinsic(gallivm->builder,
5445 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5446 : "llvm.AMDGPU.barrier.local",
5447 ctx->voidt, NULL, 0, LP_FUNC_ATTR_CONVERGENT);
5448 }
5449
5450 static const struct lp_build_tgsi_action tex_action = {
5451 .fetch_args = tex_fetch_args,
5452 .emit = build_tex_intrinsic,
5453 };
5454
5455 static const struct lp_build_tgsi_action interp_action = {
5456 .fetch_args = interp_fetch_args,
5457 .emit = build_interp_intrinsic,
5458 };
5459
5460 static void si_create_function(struct si_shader_context *ctx,
5461 const char *name,
5462 LLVMTypeRef *returns, unsigned num_returns,
5463 LLVMTypeRef *params, unsigned num_params,
5464 int last_sgpr)
5465 {
5466 int i;
5467
5468 si_llvm_create_func(ctx, name, returns, num_returns,
5469 params, num_params);
5470 si_llvm_shader_type(ctx->main_fn, ctx->type);
5471 ctx->return_value = LLVMGetUndef(ctx->return_type);
5472
5473 for (i = 0; i <= last_sgpr; ++i) {
5474 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
5475
5476 /* The combination of:
5477 * - ByVal
5478 * - dereferenceable
5479 * - invariant.load
5480 * allows the optimization passes to move loads and reduces
5481 * SGPR spilling significantly.
5482 */
5483 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5484 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_BYVAL);
5485 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_NOALIAS);
5486 ac_add_attr_dereferenceable(P, UINT64_MAX);
5487 } else
5488 lp_add_function_attr(ctx->main_fn, i + 1, LP_FUNC_ATTR_INREG);
5489 }
5490
5491 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5492 "no-signed-zeros-fp-math",
5493 "true");
5494
5495 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5496 /* These were copied from some LLVM test. */
5497 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5498 "less-precise-fpmad",
5499 "true");
5500 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5501 "no-infs-fp-math",
5502 "true");
5503 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5504 "no-nans-fp-math",
5505 "true");
5506 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
5507 "unsafe-fp-math",
5508 "true");
5509 }
5510 }
5511
5512 static void declare_streamout_params(struct si_shader_context *ctx,
5513 struct pipe_stream_output_info *so,
5514 LLVMTypeRef *params, LLVMTypeRef i32,
5515 unsigned *num_params)
5516 {
5517 int i;
5518
5519 /* Streamout SGPRs. */
5520 if (so->num_outputs) {
5521 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5522 params[ctx->param_streamout_config = (*num_params)++] = i32;
5523 else
5524 ctx->param_streamout_config = *num_params - 1;
5525
5526 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5527 }
5528 /* A streamout buffer offset is loaded if the stride is non-zero. */
5529 for (i = 0; i < 4; i++) {
5530 if (!so->stride[i])
5531 continue;
5532
5533 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5534 }
5535 }
5536
5537 static unsigned llvm_get_type_size(LLVMTypeRef type)
5538 {
5539 LLVMTypeKind kind = LLVMGetTypeKind(type);
5540
5541 switch (kind) {
5542 case LLVMIntegerTypeKind:
5543 return LLVMGetIntTypeWidth(type) / 8;
5544 case LLVMFloatTypeKind:
5545 return 4;
5546 case LLVMPointerTypeKind:
5547 return 8;
5548 case LLVMVectorTypeKind:
5549 return LLVMGetVectorSize(type) *
5550 llvm_get_type_size(LLVMGetElementType(type));
5551 case LLVMArrayTypeKind:
5552 return LLVMGetArrayLength(type) *
5553 llvm_get_type_size(LLVMGetElementType(type));
5554 default:
5555 assert(0);
5556 return 0;
5557 }
5558 }
5559
5560 static void declare_tess_lds(struct si_shader_context *ctx)
5561 {
5562 struct gallivm_state *gallivm = &ctx->gallivm;
5563
5564 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5565 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, ctx->i32_0,
5566 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5567 "tess_lds");
5568 }
5569
5570 static unsigned si_get_max_workgroup_size(struct si_shader *shader)
5571 {
5572 const unsigned *properties = shader->selector->info.properties;
5573 unsigned max_work_group_size =
5574 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5575 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5576 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5577
5578 if (!max_work_group_size) {
5579 /* This is a variable group size compute shader,
5580 * compile it for the maximum possible group size.
5581 */
5582 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
5583 }
5584 return max_work_group_size;
5585 }
5586
5587 static void create_function(struct si_shader_context *ctx)
5588 {
5589 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
5590 struct gallivm_state *gallivm = &ctx->gallivm;
5591 struct si_shader *shader = ctx->shader;
5592 LLVMTypeRef params[SI_NUM_PARAMS + SI_MAX_ATTRIBS], v3i32;
5593 LLVMTypeRef returns[16+32*4];
5594 unsigned i, last_sgpr, num_params, num_return_sgprs;
5595 unsigned num_returns = 0;
5596 unsigned num_prolog_vgprs = 0;
5597
5598 v3i32 = LLVMVectorType(ctx->i32, 3);
5599
5600 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5601 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5602 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5603 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5604 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5605
5606 switch (ctx->type) {
5607 case PIPE_SHADER_VERTEX:
5608 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_MAX_ATTRIBS);
5609 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5610 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5611 params[SI_PARAM_DRAWID] = ctx->i32;
5612 num_params = SI_PARAM_DRAWID+1;
5613
5614 if (shader->key.as_es) {
5615 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5616 } else if (shader->key.as_ls) {
5617 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5618 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5619 } else {
5620 if (shader->is_gs_copy_shader) {
5621 num_params = SI_PARAM_RW_BUFFERS+1;
5622 } else {
5623 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5624 num_params = SI_PARAM_VS_STATE_BITS+1;
5625 }
5626
5627 /* The locations of the other parameters are assigned dynamically. */
5628 declare_streamout_params(ctx, &shader->selector->so,
5629 params, ctx->i32, &num_params);
5630 }
5631
5632 last_sgpr = num_params-1;
5633
5634 /* VGPRs */
5635 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5636 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5637 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5638 params[ctx->param_instance_id = num_params++] = ctx->i32;
5639
5640 if (!shader->is_gs_copy_shader) {
5641 /* Vertex load indices. */
5642 ctx->param_vertex_index0 = num_params;
5643
5644 for (i = 0; i < shader->selector->info.num_inputs; i++)
5645 params[num_params++] = ctx->i32;
5646
5647 num_prolog_vgprs += shader->selector->info.num_inputs;
5648
5649 /* PrimitiveID output. */
5650 if (!shader->key.as_es && !shader->key.as_ls)
5651 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5652 returns[num_returns++] = ctx->f32;
5653 }
5654 break;
5655
5656 case PIPE_SHADER_TESS_CTRL:
5657 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5658 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5659 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5660 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5661 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5662 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5663 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5664
5665 /* VGPRs */
5666 params[SI_PARAM_PATCH_ID] = ctx->i32;
5667 params[SI_PARAM_REL_IDS] = ctx->i32;
5668 num_params = SI_PARAM_REL_IDS+1;
5669
5670 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5671 * placed after the user SGPRs.
5672 */
5673 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5674 returns[num_returns++] = ctx->i32; /* SGPRs */
5675
5676 for (i = 0; i < 3; i++)
5677 returns[num_returns++] = ctx->f32; /* VGPRs */
5678 break;
5679
5680 case PIPE_SHADER_TESS_EVAL:
5681 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5682 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5683
5684 if (shader->key.as_es) {
5685 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5686 params[num_params++] = ctx->i32;
5687 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5688 } else {
5689 params[num_params++] = ctx->i32;
5690 declare_streamout_params(ctx, &shader->selector->so,
5691 params, ctx->i32, &num_params);
5692 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5693 }
5694 last_sgpr = num_params - 1;
5695
5696 /* VGPRs */
5697 params[ctx->param_tes_u = num_params++] = ctx->f32;
5698 params[ctx->param_tes_v = num_params++] = ctx->f32;
5699 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5700 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5701
5702 /* PrimitiveID output. */
5703 if (!shader->key.as_es)
5704 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5705 returns[num_returns++] = ctx->f32;
5706 break;
5707
5708 case PIPE_SHADER_GEOMETRY:
5709 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5710 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5711 last_sgpr = SI_PARAM_GS_WAVE_ID;
5712
5713 /* VGPRs */
5714 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5715 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5716 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5717 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5718 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5719 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5720 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5721 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5722 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5723 break;
5724
5725 case PIPE_SHADER_FRAGMENT:
5726 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5727 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5728 last_sgpr = SI_PARAM_PRIM_MASK;
5729 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5730 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5731 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5732 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5733 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5734 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5735 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5736 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5737 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5738 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5739 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5740 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5741 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5742 shader->info.face_vgpr_index = 20;
5743 params[SI_PARAM_ANCILLARY] = ctx->i32;
5744 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5745 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5746 num_params = SI_PARAM_POS_FIXED_PT+1;
5747
5748 /* Color inputs from the prolog. */
5749 if (shader->selector->info.colors_read) {
5750 unsigned num_color_elements =
5751 util_bitcount(shader->selector->info.colors_read);
5752
5753 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5754 for (i = 0; i < num_color_elements; i++)
5755 params[num_params++] = ctx->f32;
5756
5757 num_prolog_vgprs += num_color_elements;
5758 }
5759
5760 /* Outputs for the epilog. */
5761 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5762 num_returns =
5763 num_return_sgprs +
5764 util_bitcount(shader->selector->info.colors_written) * 4 +
5765 shader->selector->info.writes_z +
5766 shader->selector->info.writes_stencil +
5767 shader->selector->info.writes_samplemask +
5768 1 /* SampleMaskIn */;
5769
5770 num_returns = MAX2(num_returns,
5771 num_return_sgprs +
5772 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5773
5774 for (i = 0; i < num_return_sgprs; i++)
5775 returns[i] = ctx->i32;
5776 for (; i < num_returns; i++)
5777 returns[i] = ctx->f32;
5778 break;
5779
5780 case PIPE_SHADER_COMPUTE:
5781 params[SI_PARAM_GRID_SIZE] = v3i32;
5782 params[SI_PARAM_BLOCK_SIZE] = v3i32;
5783 params[SI_PARAM_BLOCK_ID] = v3i32;
5784 last_sgpr = SI_PARAM_BLOCK_ID;
5785
5786 params[SI_PARAM_THREAD_ID] = v3i32;
5787 num_params = SI_PARAM_THREAD_ID + 1;
5788 break;
5789 default:
5790 assert(0 && "unimplemented shader");
5791 return;
5792 }
5793
5794 assert(num_params <= ARRAY_SIZE(params));
5795
5796 si_create_function(ctx, "main", returns, num_returns, params,
5797 num_params, last_sgpr);
5798
5799 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5800 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5801 ctx->separate_prolog) {
5802 si_llvm_add_attribute(ctx->main_fn,
5803 "InitialPSInputAddr",
5804 S_0286D0_PERSP_SAMPLE_ENA(1) |
5805 S_0286D0_PERSP_CENTER_ENA(1) |
5806 S_0286D0_PERSP_CENTROID_ENA(1) |
5807 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5808 S_0286D0_LINEAR_CENTER_ENA(1) |
5809 S_0286D0_LINEAR_CENTROID_ENA(1) |
5810 S_0286D0_FRONT_FACE_ENA(1) |
5811 S_0286D0_POS_FIXED_PT_ENA(1));
5812 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5813 si_llvm_add_attribute(ctx->main_fn,
5814 "amdgpu-max-work-group-size",
5815 si_get_max_workgroup_size(shader));
5816 }
5817
5818 shader->info.num_input_sgprs = 0;
5819 shader->info.num_input_vgprs = 0;
5820
5821 for (i = 0; i <= last_sgpr; ++i)
5822 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5823
5824 for (; i < num_params; ++i)
5825 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5826
5827 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5828 shader->info.num_input_vgprs -= num_prolog_vgprs;
5829
5830 if (!ctx->screen->has_ds_bpermute &&
5831 bld_base->info &&
5832 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5833 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5834 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5835 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5836 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5837 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5838 ctx->lds =
5839 LLVMAddGlobalInAddressSpace(gallivm->module,
5840 LLVMArrayType(ctx->i32, 64),
5841 "ddxy_lds",
5842 LOCAL_ADDR_SPACE);
5843
5844 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.as_ls) ||
5845 ctx->type == PIPE_SHADER_TESS_CTRL)
5846 declare_tess_lds(ctx);
5847 }
5848
5849 /**
5850 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5851 * for later use.
5852 */
5853 static void preload_ring_buffers(struct si_shader_context *ctx)
5854 {
5855 struct gallivm_state *gallivm = &ctx->gallivm;
5856 LLVMBuilderRef builder = gallivm->builder;
5857
5858 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5859 SI_PARAM_RW_BUFFERS);
5860
5861 if ((ctx->type == PIPE_SHADER_VERTEX &&
5862 ctx->shader->key.as_es) ||
5863 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5864 ctx->shader->key.as_es) ||
5865 ctx->type == PIPE_SHADER_GEOMETRY) {
5866 unsigned ring =
5867 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5868 : SI_ES_RING_ESGS;
5869 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
5870
5871 ctx->esgs_ring =
5872 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5873 }
5874
5875 if (ctx->shader->is_gs_copy_shader) {
5876 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5877
5878 ctx->gsvs_ring[0] =
5879 ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5880 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5881 const struct si_shader_selector *sel = ctx->shader->selector;
5882 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5883 LLVMValueRef base_ring;
5884
5885 base_ring = ac_build_indexed_load_const(&ctx->ac, buf_ptr, offset);
5886
5887 /* The conceptual layout of the GSVS ring is
5888 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5889 * but the real memory layout is swizzled across
5890 * threads:
5891 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5892 * t16v0c0 ..
5893 * Override the buffer descriptor accordingly.
5894 */
5895 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5896 uint64_t stream_offset = 0;
5897
5898 for (unsigned stream = 0; stream < 4; ++stream) {
5899 unsigned num_components;
5900 unsigned stride;
5901 unsigned num_records;
5902 LLVMValueRef ring, tmp;
5903
5904 num_components = sel->info.num_stream_output_components[stream];
5905 if (!num_components)
5906 continue;
5907
5908 stride = 4 * num_components * sel->gs_max_out_vertices;
5909
5910 /* Limit on the stride field for <= CIK. */
5911 assert(stride < (1 << 14));
5912
5913 num_records = 64;
5914
5915 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5916 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5917 tmp = LLVMBuildAdd(builder, tmp,
5918 LLVMConstInt(ctx->i64,
5919 stream_offset, 0), "");
5920 stream_offset += stride * 64;
5921
5922 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5923 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5924 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5925 tmp = LLVMBuildOr(builder, tmp,
5926 LLVMConstInt(ctx->i32,
5927 S_008F04_STRIDE(stride) |
5928 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5929 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5930 ring = LLVMBuildInsertElement(builder, ring,
5931 LLVMConstInt(ctx->i32, num_records, 0),
5932 LLVMConstInt(ctx->i32, 2, 0), "");
5933 ring = LLVMBuildInsertElement(builder, ring,
5934 LLVMConstInt(ctx->i32,
5935 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5936 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5937 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5938 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5939 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5940 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5941 S_008F0C_ELEMENT_SIZE(1) | /* element_size = 4 (bytes) */
5942 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5943 S_008F0C_ADD_TID_ENABLE(1),
5944 0),
5945 LLVMConstInt(ctx->i32, 3, 0), "");
5946 ring = LLVMBuildBitCast(builder, ring, ctx->v16i8, "");
5947
5948 ctx->gsvs_ring[stream] = ring;
5949 }
5950 }
5951 }
5952
5953 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5954 LLVMValueRef param_rw_buffers,
5955 unsigned param_pos_fixed_pt)
5956 {
5957 struct gallivm_state *gallivm = &ctx->gallivm;
5958 LLVMBuilderRef builder = gallivm->builder;
5959 LLVMValueRef slot, desc, offset, row, bit, address[2];
5960
5961 /* Use the fixed-point gl_FragCoord input.
5962 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5963 * per coordinate to get the repeating effect.
5964 */
5965 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5966 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5967
5968 /* Load the buffer descriptor. */
5969 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5970 desc = ac_build_indexed_load_const(&ctx->ac, param_rw_buffers, slot);
5971
5972 /* The stipple pattern is 32x32, each row has 32 bits. */
5973 offset = LLVMBuildMul(builder, address[1],
5974 LLVMConstInt(ctx->i32, 4, 0), "");
5975 row = buffer_load_const(ctx, desc, offset);
5976 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
5977 bit = LLVMBuildLShr(builder, row, address[0], "");
5978 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5979
5980 /* The intrinsic kills the thread if arg < 0. */
5981 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5982 LLVMConstReal(ctx->f32, -1), "");
5983 ac_build_kill(&ctx->ac, bit);
5984 }
5985
5986 void si_shader_binary_read_config(struct ac_shader_binary *binary,
5987 struct si_shader_config *conf,
5988 unsigned symbol_offset)
5989 {
5990 unsigned i;
5991 const unsigned char *config =
5992 ac_shader_binary_config_start(binary, symbol_offset);
5993 bool really_needs_scratch = false;
5994
5995 /* LLVM adds SGPR spills to the scratch size.
5996 * Find out if we really need the scratch buffer.
5997 */
5998 for (i = 0; i < binary->reloc_count; i++) {
5999 const struct ac_shader_reloc *reloc = &binary->relocs[i];
6000
6001 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
6002 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
6003 really_needs_scratch = true;
6004 break;
6005 }
6006 }
6007
6008 /* XXX: We may be able to emit some of these values directly rather than
6009 * extracting fields to be emitted later.
6010 */
6011
6012 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
6013 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
6014 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
6015 switch (reg) {
6016 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
6017 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
6018 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
6019 case R_00B848_COMPUTE_PGM_RSRC1:
6020 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
6021 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
6022 conf->float_mode = G_00B028_FLOAT_MODE(value);
6023 conf->rsrc1 = value;
6024 break;
6025 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
6026 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
6027 break;
6028 case R_00B84C_COMPUTE_PGM_RSRC2:
6029 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
6030 conf->rsrc2 = value;
6031 break;
6032 case R_0286CC_SPI_PS_INPUT_ENA:
6033 conf->spi_ps_input_ena = value;
6034 break;
6035 case R_0286D0_SPI_PS_INPUT_ADDR:
6036 conf->spi_ps_input_addr = value;
6037 break;
6038 case R_0286E8_SPI_TMPRING_SIZE:
6039 case R_00B860_COMPUTE_TMPRING_SIZE:
6040 /* WAVESIZE is in units of 256 dwords. */
6041 if (really_needs_scratch)
6042 conf->scratch_bytes_per_wave =
6043 G_00B860_WAVESIZE(value) * 256 * 4;
6044 break;
6045 case 0x4: /* SPILLED_SGPRS */
6046 conf->spilled_sgprs = value;
6047 break;
6048 case 0x8: /* SPILLED_VGPRS */
6049 conf->spilled_vgprs = value;
6050 break;
6051 default:
6052 {
6053 static bool printed;
6054
6055 if (!printed) {
6056 fprintf(stderr, "Warning: LLVM emitted unknown "
6057 "config register: 0x%x\n", reg);
6058 printed = true;
6059 }
6060 }
6061 break;
6062 }
6063 }
6064
6065 if (!conf->spi_ps_input_addr)
6066 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
6067 }
6068
6069 void si_shader_apply_scratch_relocs(struct si_context *sctx,
6070 struct si_shader *shader,
6071 struct si_shader_config *config,
6072 uint64_t scratch_va)
6073 {
6074 unsigned i;
6075 uint32_t scratch_rsrc_dword0 = scratch_va;
6076 uint32_t scratch_rsrc_dword1 =
6077 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
6078
6079 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
6080 * correctly.
6081 */
6082 if (HAVE_LLVM >= 0x0309)
6083 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
6084 else
6085 scratch_rsrc_dword1 |=
6086 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
6087
6088 for (i = 0 ; i < shader->binary.reloc_count; i++) {
6089 const struct ac_shader_reloc *reloc =
6090 &shader->binary.relocs[i];
6091 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
6092 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
6093 &scratch_rsrc_dword0, 4);
6094 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
6095 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
6096 &scratch_rsrc_dword1, 4);
6097 }
6098 }
6099 }
6100
6101 static unsigned si_get_shader_binary_size(struct si_shader *shader)
6102 {
6103 unsigned size = shader->binary.code_size;
6104
6105 if (shader->prolog)
6106 size += shader->prolog->binary.code_size;
6107 if (shader->epilog)
6108 size += shader->epilog->binary.code_size;
6109 return size;
6110 }
6111
6112 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
6113 {
6114 const struct ac_shader_binary *prolog =
6115 shader->prolog ? &shader->prolog->binary : NULL;
6116 const struct ac_shader_binary *epilog =
6117 shader->epilog ? &shader->epilog->binary : NULL;
6118 const struct ac_shader_binary *mainb = &shader->binary;
6119 unsigned bo_size = si_get_shader_binary_size(shader) +
6120 (!epilog ? mainb->rodata_size : 0);
6121 unsigned char *ptr;
6122
6123 assert(!prolog || !prolog->rodata_size);
6124 assert((!prolog && !epilog) || !mainb->rodata_size);
6125 assert(!epilog || !epilog->rodata_size);
6126
6127 /* GFX9 can fetch at most 128 bytes past the end of the shader.
6128 * Prevent VM faults.
6129 */
6130 if (sscreen->b.chip_class >= GFX9)
6131 bo_size += 128;
6132
6133 r600_resource_reference(&shader->bo, NULL);
6134 shader->bo = (struct r600_resource*)
6135 pipe_buffer_create(&sscreen->b.b, 0,
6136 PIPE_USAGE_IMMUTABLE,
6137 align(bo_size, SI_CPDMA_ALIGNMENT));
6138 if (!shader->bo)
6139 return -ENOMEM;
6140
6141 /* Upload. */
6142 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
6143 PIPE_TRANSFER_READ_WRITE);
6144
6145 if (prolog) {
6146 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
6147 ptr += prolog->code_size;
6148 }
6149
6150 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
6151 ptr += mainb->code_size;
6152
6153 if (epilog)
6154 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
6155 else if (mainb->rodata_size > 0)
6156 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
6157
6158 sscreen->b.ws->buffer_unmap(shader->bo->buf);
6159 return 0;
6160 }
6161
6162 static void si_shader_dump_disassembly(const struct ac_shader_binary *binary,
6163 struct pipe_debug_callback *debug,
6164 const char *name, FILE *file)
6165 {
6166 char *line, *p;
6167 unsigned i, count;
6168
6169 if (binary->disasm_string) {
6170 fprintf(file, "Shader %s disassembly:\n", name);
6171 fprintf(file, "%s", binary->disasm_string);
6172
6173 if (debug && debug->debug_message) {
6174 /* Very long debug messages are cut off, so send the
6175 * disassembly one line at a time. This causes more
6176 * overhead, but on the plus side it simplifies
6177 * parsing of resulting logs.
6178 */
6179 pipe_debug_message(debug, SHADER_INFO,
6180 "Shader Disassembly Begin");
6181
6182 line = binary->disasm_string;
6183 while (*line) {
6184 p = util_strchrnul(line, '\n');
6185 count = p - line;
6186
6187 if (count) {
6188 pipe_debug_message(debug, SHADER_INFO,
6189 "%.*s", count, line);
6190 }
6191
6192 if (!*p)
6193 break;
6194 line = p + 1;
6195 }
6196
6197 pipe_debug_message(debug, SHADER_INFO,
6198 "Shader Disassembly End");
6199 }
6200 } else {
6201 fprintf(file, "Shader %s binary:\n", name);
6202 for (i = 0; i < binary->code_size; i += 4) {
6203 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
6204 binary->code[i + 3], binary->code[i + 2],
6205 binary->code[i + 1], binary->code[i]);
6206 }
6207 }
6208 }
6209
6210 static void si_shader_dump_stats(struct si_screen *sscreen,
6211 struct si_shader *shader,
6212 struct pipe_debug_callback *debug,
6213 unsigned processor,
6214 FILE *file,
6215 bool check_debug_option)
6216 {
6217 struct si_shader_config *conf = &shader->config;
6218 unsigned num_inputs = shader->selector ? shader->selector->info.num_inputs : 0;
6219 unsigned code_size = si_get_shader_binary_size(shader);
6220 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
6221 unsigned lds_per_wave = 0;
6222 unsigned max_simd_waves = 10;
6223
6224 /* Compute LDS usage for PS. */
6225 switch (processor) {
6226 case PIPE_SHADER_FRAGMENT:
6227 /* The minimum usage per wave is (num_inputs * 48). The maximum
6228 * usage is (num_inputs * 48 * 16).
6229 * We can get anything in between and it varies between waves.
6230 *
6231 * The 48 bytes per input for a single primitive is equal to
6232 * 4 bytes/component * 4 components/input * 3 points.
6233 *
6234 * Other stages don't know the size at compile time or don't
6235 * allocate LDS per wave, but instead they do it per thread group.
6236 */
6237 lds_per_wave = conf->lds_size * lds_increment +
6238 align(num_inputs * 48, lds_increment);
6239 break;
6240 case PIPE_SHADER_COMPUTE:
6241 if (shader->selector) {
6242 unsigned max_workgroup_size =
6243 si_get_max_workgroup_size(shader);
6244 lds_per_wave = (conf->lds_size * lds_increment) /
6245 DIV_ROUND_UP(max_workgroup_size, 64);
6246 }
6247 break;
6248 }
6249
6250 /* Compute the per-SIMD wave counts. */
6251 if (conf->num_sgprs) {
6252 if (sscreen->b.chip_class >= VI)
6253 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
6254 else
6255 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
6256 }
6257
6258 if (conf->num_vgprs)
6259 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
6260
6261 /* LDS is 64KB per CU (4 SIMDs), which is 16KB per SIMD (usage above
6262 * 16KB makes some SIMDs unoccupied). */
6263 if (lds_per_wave)
6264 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6265
6266 if (!check_debug_option ||
6267 r600_can_dump_shader(&sscreen->b, processor)) {
6268 if (processor == PIPE_SHADER_FRAGMENT) {
6269 fprintf(file, "*** SHADER CONFIG ***\n"
6270 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6271 "SPI_PS_INPUT_ENA = 0x%04x\n",
6272 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6273 }
6274
6275 fprintf(file, "*** SHADER STATS ***\n"
6276 "SGPRS: %d\n"
6277 "VGPRS: %d\n"
6278 "Spilled SGPRs: %d\n"
6279 "Spilled VGPRs: %d\n"
6280 "Private memory VGPRs: %d\n"
6281 "Code Size: %d bytes\n"
6282 "LDS: %d blocks\n"
6283 "Scratch: %d bytes per wave\n"
6284 "Max Waves: %d\n"
6285 "********************\n\n\n",
6286 conf->num_sgprs, conf->num_vgprs,
6287 conf->spilled_sgprs, conf->spilled_vgprs,
6288 conf->private_mem_vgprs, code_size,
6289 conf->lds_size, conf->scratch_bytes_per_wave,
6290 max_simd_waves);
6291 }
6292
6293 pipe_debug_message(debug, SHADER_INFO,
6294 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6295 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6296 "Spilled VGPRs: %d PrivMem VGPRs: %d",
6297 conf->num_sgprs, conf->num_vgprs, code_size,
6298 conf->lds_size, conf->scratch_bytes_per_wave,
6299 max_simd_waves, conf->spilled_sgprs,
6300 conf->spilled_vgprs, conf->private_mem_vgprs);
6301 }
6302
6303 const char *si_get_shader_name(struct si_shader *shader, unsigned processor)
6304 {
6305 switch (processor) {
6306 case PIPE_SHADER_VERTEX:
6307 if (shader->key.as_es)
6308 return "Vertex Shader as ES";
6309 else if (shader->key.as_ls)
6310 return "Vertex Shader as LS";
6311 else
6312 return "Vertex Shader as VS";
6313 case PIPE_SHADER_TESS_CTRL:
6314 return "Tessellation Control Shader";
6315 case PIPE_SHADER_TESS_EVAL:
6316 if (shader->key.as_es)
6317 return "Tessellation Evaluation Shader as ES";
6318 else
6319 return "Tessellation Evaluation Shader as VS";
6320 case PIPE_SHADER_GEOMETRY:
6321 if (shader->is_gs_copy_shader)
6322 return "GS Copy Shader as VS";
6323 else
6324 return "Geometry Shader";
6325 case PIPE_SHADER_FRAGMENT:
6326 return "Pixel Shader";
6327 case PIPE_SHADER_COMPUTE:
6328 return "Compute Shader";
6329 default:
6330 return "Unknown Shader";
6331 }
6332 }
6333
6334 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6335 struct pipe_debug_callback *debug, unsigned processor,
6336 FILE *file, bool check_debug_option)
6337 {
6338 if (!check_debug_option ||
6339 r600_can_dump_shader(&sscreen->b, processor))
6340 si_dump_shader_key(processor, &shader->key, file);
6341
6342 if (!check_debug_option && shader->binary.llvm_ir_string) {
6343 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6344 si_get_shader_name(shader, processor));
6345 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6346 }
6347
6348 if (!check_debug_option ||
6349 (r600_can_dump_shader(&sscreen->b, processor) &&
6350 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6351 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6352
6353 if (shader->prolog)
6354 si_shader_dump_disassembly(&shader->prolog->binary,
6355 debug, "prolog", file);
6356
6357 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6358
6359 if (shader->epilog)
6360 si_shader_dump_disassembly(&shader->epilog->binary,
6361 debug, "epilog", file);
6362 fprintf(file, "\n");
6363 }
6364
6365 si_shader_dump_stats(sscreen, shader, debug, processor, file,
6366 check_debug_option);
6367 }
6368
6369 int si_compile_llvm(struct si_screen *sscreen,
6370 struct ac_shader_binary *binary,
6371 struct si_shader_config *conf,
6372 LLVMTargetMachineRef tm,
6373 LLVMModuleRef mod,
6374 struct pipe_debug_callback *debug,
6375 unsigned processor,
6376 const char *name)
6377 {
6378 int r = 0;
6379 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6380
6381 if (r600_can_dump_shader(&sscreen->b, processor)) {
6382 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6383
6384 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6385 fprintf(stderr, "%s LLVM IR:\n\n", name);
6386 ac_dump_module(mod);
6387 fprintf(stderr, "\n");
6388 }
6389 }
6390
6391 if (sscreen->record_llvm_ir) {
6392 char *ir = LLVMPrintModuleToString(mod);
6393 binary->llvm_ir_string = strdup(ir);
6394 LLVMDisposeMessage(ir);
6395 }
6396
6397 if (!si_replace_shader(count, binary)) {
6398 r = si_llvm_compile(mod, binary, tm, debug);
6399 if (r)
6400 return r;
6401 }
6402
6403 si_shader_binary_read_config(binary, conf, 0);
6404
6405 /* Enable 64-bit and 16-bit denormals, because there is no performance
6406 * cost.
6407 *
6408 * If denormals are enabled, all floating-point output modifiers are
6409 * ignored.
6410 *
6411 * Don't enable denormals for 32-bit floats, because:
6412 * - Floating-point output modifiers would be ignored by the hw.
6413 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6414 * have to stop using those.
6415 * - SI & CI would be very slow.
6416 */
6417 conf->float_mode |= V_00B028_FP_64_DENORMS;
6418
6419 FREE(binary->config);
6420 FREE(binary->global_symbol_offsets);
6421 binary->config = NULL;
6422 binary->global_symbol_offsets = NULL;
6423
6424 /* Some shaders can't have rodata because their binaries can be
6425 * concatenated.
6426 */
6427 if (binary->rodata_size &&
6428 (processor == PIPE_SHADER_VERTEX ||
6429 processor == PIPE_SHADER_TESS_CTRL ||
6430 processor == PIPE_SHADER_TESS_EVAL ||
6431 processor == PIPE_SHADER_FRAGMENT)) {
6432 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6433 return -EINVAL;
6434 }
6435
6436 return r;
6437 }
6438
6439 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6440 {
6441 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6442 LLVMBuildRetVoid(ctx->gallivm.builder);
6443 else
6444 LLVMBuildRet(ctx->gallivm.builder, ret);
6445 }
6446
6447 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6448 struct si_shader *
6449 si_generate_gs_copy_shader(struct si_screen *sscreen,
6450 LLVMTargetMachineRef tm,
6451 struct si_shader_selector *gs_selector,
6452 struct pipe_debug_callback *debug)
6453 {
6454 struct si_shader_context ctx;
6455 struct si_shader *shader;
6456 struct gallivm_state *gallivm = &ctx.gallivm;
6457 LLVMBuilderRef builder;
6458 struct lp_build_tgsi_context *bld_base = &ctx.bld_base;
6459 struct lp_build_context *uint = &bld_base->uint_bld;
6460 struct si_shader_output_values *outputs;
6461 struct tgsi_shader_info *gsinfo = &gs_selector->info;
6462 int i, r;
6463
6464 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6465
6466 if (!outputs)
6467 return NULL;
6468
6469 shader = CALLOC_STRUCT(si_shader);
6470 if (!shader) {
6471 FREE(outputs);
6472 return NULL;
6473 }
6474
6475
6476 shader->selector = gs_selector;
6477 shader->is_gs_copy_shader = true;
6478
6479 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6480 ctx.type = PIPE_SHADER_VERTEX;
6481
6482 builder = gallivm->builder;
6483
6484 create_function(&ctx);
6485 preload_ring_buffers(&ctx);
6486
6487 LLVMValueRef voffset =
6488 lp_build_mul_imm(uint, LLVMGetParam(ctx.main_fn,
6489 ctx.param_vertex_id), 4);
6490
6491 /* Fetch the vertex stream ID.*/
6492 LLVMValueRef stream_id;
6493
6494 if (gs_selector->so.num_outputs)
6495 stream_id = unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
6496 else
6497 stream_id = ctx.i32_0;
6498
6499 /* Fill in output information. */
6500 for (i = 0; i < gsinfo->num_outputs; ++i) {
6501 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
6502 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
6503
6504 for (int chan = 0; chan < 4; chan++) {
6505 outputs[i].vertex_stream[chan] =
6506 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
6507 }
6508 }
6509
6510 LLVMBasicBlockRef end_bb;
6511 LLVMValueRef switch_inst;
6512
6513 end_bb = LLVMAppendBasicBlockInContext(gallivm->context, ctx.main_fn, "end");
6514 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
6515
6516 for (int stream = 0; stream < 4; stream++) {
6517 LLVMBasicBlockRef bb;
6518 unsigned offset;
6519
6520 if (!gsinfo->num_stream_output_components[stream])
6521 continue;
6522
6523 if (stream > 0 && !gs_selector->so.num_outputs)
6524 continue;
6525
6526 bb = LLVMInsertBasicBlockInContext(gallivm->context, end_bb, "out");
6527 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
6528 LLVMPositionBuilderAtEnd(builder, bb);
6529
6530 /* Fetch vertex data from GSVS ring */
6531 offset = 0;
6532 for (i = 0; i < gsinfo->num_outputs; ++i) {
6533 for (unsigned chan = 0; chan < 4; chan++) {
6534 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
6535 outputs[i].vertex_stream[chan] != stream) {
6536 outputs[i].values[chan] = ctx.bld_base.base.undef;
6537 continue;
6538 }
6539
6540 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
6541 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
6542 offset++;
6543
6544 outputs[i].values[chan] =
6545 ac_build_buffer_load(&ctx.ac,
6546 ctx.gsvs_ring[0], 1,
6547 ctx.i32_0, voffset,
6548 soffset, 0, 1, 1, true);
6549 }
6550 }
6551
6552 /* Streamout and exports. */
6553 if (gs_selector->so.num_outputs) {
6554 si_llvm_emit_streamout(&ctx, outputs,
6555 gsinfo->num_outputs,
6556 stream);
6557 }
6558
6559 if (stream == 0)
6560 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6561
6562 LLVMBuildBr(builder, end_bb);
6563 }
6564
6565 LLVMPositionBuilderAtEnd(builder, end_bb);
6566
6567 LLVMBuildRetVoid(gallivm->builder);
6568
6569 /* Dump LLVM IR before any optimization passes */
6570 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6571 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6572 ac_dump_module(ctx.gallivm.module);
6573
6574 si_llvm_finalize_module(&ctx,
6575 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_GEOMETRY));
6576
6577 r = si_compile_llvm(sscreen, &ctx.shader->binary,
6578 &ctx.shader->config, ctx.tm,
6579 ctx.gallivm.module,
6580 debug, PIPE_SHADER_GEOMETRY,
6581 "GS Copy Shader");
6582 if (!r) {
6583 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6584 fprintf(stderr, "GS Copy Shader:\n");
6585 si_shader_dump(sscreen, ctx.shader, debug,
6586 PIPE_SHADER_GEOMETRY, stderr, true);
6587 r = si_shader_binary_upload(sscreen, ctx.shader);
6588 }
6589
6590 si_llvm_dispose(&ctx);
6591
6592 FREE(outputs);
6593
6594 if (r != 0) {
6595 FREE(shader);
6596 shader = NULL;
6597 }
6598 return shader;
6599 }
6600
6601 static void si_dump_shader_key(unsigned shader, struct si_shader_key *key,
6602 FILE *f)
6603 {
6604 int i;
6605
6606 fprintf(f, "SHADER KEY\n");
6607
6608 switch (shader) {
6609 case PIPE_SHADER_VERTEX:
6610 fprintf(f, " part.vs.prolog.instance_divisors = {");
6611 for (i = 0; i < ARRAY_SIZE(key->part.vs.prolog.instance_divisors); i++)
6612 fprintf(f, !i ? "%u" : ", %u",
6613 key->part.vs.prolog.instance_divisors[i]);
6614 fprintf(f, "}\n");
6615 fprintf(f, " part.vs.epilog.export_prim_id = %u\n", key->part.vs.epilog.export_prim_id);
6616 fprintf(f, " as_es = %u\n", key->as_es);
6617 fprintf(f, " as_ls = %u\n", key->as_ls);
6618
6619 fprintf(f, " mono.vs.fix_fetch = {");
6620 for (i = 0; i < SI_MAX_ATTRIBS; i++)
6621 fprintf(f, !i ? "%u" : ", %u", key->mono.vs.fix_fetch[i]);
6622 fprintf(f, "}\n");
6623 break;
6624
6625 case PIPE_SHADER_TESS_CTRL:
6626 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
6627 fprintf(f, " mono.tcs.inputs_to_copy = 0x%"PRIx64"\n", key->mono.tcs.inputs_to_copy);
6628 break;
6629
6630 case PIPE_SHADER_TESS_EVAL:
6631 fprintf(f, " part.tes.epilog.export_prim_id = %u\n", key->part.tes.epilog.export_prim_id);
6632 fprintf(f, " as_es = %u\n", key->as_es);
6633 break;
6634
6635 case PIPE_SHADER_GEOMETRY:
6636 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
6637 break;
6638
6639 case PIPE_SHADER_COMPUTE:
6640 break;
6641
6642 case PIPE_SHADER_FRAGMENT:
6643 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
6644 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
6645 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
6646 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
6647 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
6648 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
6649 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
6650 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
6651 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
6652 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
6653 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
6654 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
6655 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
6656 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
6657 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
6658 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
6659 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
6660 break;
6661
6662 default:
6663 assert(0);
6664 }
6665
6666 if ((shader == PIPE_SHADER_GEOMETRY ||
6667 shader == PIPE_SHADER_TESS_EVAL ||
6668 shader == PIPE_SHADER_VERTEX) &&
6669 !key->as_es && !key->as_ls) {
6670 fprintf(f, " opt.hw_vs.kill_outputs = 0x%"PRIx64"\n", key->opt.hw_vs.kill_outputs);
6671 fprintf(f, " opt.hw_vs.kill_outputs2 = 0x%x\n", key->opt.hw_vs.kill_outputs2);
6672 fprintf(f, " opt.hw_vs.clip_disable = %u\n", key->opt.hw_vs.clip_disable);
6673 }
6674 }
6675
6676 static void si_init_shader_ctx(struct si_shader_context *ctx,
6677 struct si_screen *sscreen,
6678 struct si_shader *shader,
6679 LLVMTargetMachineRef tm)
6680 {
6681 struct lp_build_tgsi_context *bld_base;
6682 struct lp_build_tgsi_action tmpl = {};
6683
6684 si_llvm_context_init(ctx, sscreen, shader, tm,
6685 (shader && shader->selector) ? &shader->selector->info : NULL,
6686 (shader && shader->selector) ? shader->selector->tokens : NULL);
6687
6688 bld_base = &ctx->bld_base;
6689 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6690
6691 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6692 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6693 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6694
6695 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6696 bld_base->op_actions[TGSI_OPCODE_TEX_LZ] = tex_action;
6697 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6698 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6699 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6700 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6701 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6702 bld_base->op_actions[TGSI_OPCODE_TXF_LZ] = tex_action;
6703 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6704 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6705 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6706 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6707 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6708 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6709 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6710 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6711
6712 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6713 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6714 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6715 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6716 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6717 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6718
6719 tmpl.fetch_args = atomic_fetch_args;
6720 tmpl.emit = atomic_emit;
6721 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6722 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6723 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6724 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6725 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6726 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6727 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6728 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6729 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6730 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6731 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6732 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6733 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6734 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6735 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6736 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6737 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6738 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6739 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6740 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6741
6742 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6743
6744 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
6745
6746 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6747 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6748 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6749 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6750
6751 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
6752 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
6753 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
6754 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
6755 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
6756 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
6757 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
6758 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].fetch_args = read_invoc_fetch_args;
6759 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
6760
6761 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6762 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6763 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6764 }
6765
6766 #define EXP_TARGET (HAVE_LLVM >= 0x0500 ? 0 : 3)
6767 #define EXP_OUT0 (HAVE_LLVM >= 0x0500 ? 2 : 5)
6768
6769 /* Return true if the PARAM export has been eliminated. */
6770 static bool si_eliminate_const_output(struct si_shader_context *ctx,
6771 LLVMValueRef inst, unsigned offset)
6772 {
6773 struct si_shader *shader = ctx->shader;
6774 unsigned num_outputs = shader->selector->info.num_outputs;
6775 unsigned i, default_val; /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL */
6776 bool is_zero[4] = {}, is_one[4] = {};
6777
6778 for (i = 0; i < 4; i++) {
6779 LLVMBool loses_info;
6780 LLVMValueRef p = LLVMGetOperand(inst, EXP_OUT0 + i);
6781
6782 /* It's a constant expression. Undef outputs are eliminated too. */
6783 if (LLVMIsUndef(p)) {
6784 is_zero[i] = true;
6785 is_one[i] = true;
6786 } else if (LLVMIsAConstantFP(p)) {
6787 double a = LLVMConstRealGetDouble(p, &loses_info);
6788
6789 if (a == 0)
6790 is_zero[i] = true;
6791 else if (a == 1)
6792 is_one[i] = true;
6793 else
6794 return false; /* other constant */
6795 } else
6796 return false;
6797 }
6798
6799 /* Only certain combinations of 0 and 1 can be eliminated. */
6800 if (is_zero[0] && is_zero[1] && is_zero[2])
6801 default_val = is_zero[3] ? 0 : 1;
6802 else if (is_one[0] && is_one[1] && is_one[2])
6803 default_val = is_zero[3] ? 2 : 3;
6804 else
6805 return false;
6806
6807 /* The PARAM export can be represented as DEFAULT_VAL. Kill it. */
6808 LLVMInstructionEraseFromParent(inst);
6809
6810 /* Change OFFSET to DEFAULT_VAL. */
6811 for (i = 0; i < num_outputs; i++) {
6812 if (shader->info.vs_output_param_offset[i] == offset) {
6813 shader->info.vs_output_param_offset[i] =
6814 EXP_PARAM_DEFAULT_VAL_0000 + default_val;
6815 break;
6816 }
6817 }
6818 return true;
6819 }
6820
6821 struct si_vs_exports {
6822 unsigned num;
6823 unsigned offset[SI_MAX_VS_OUTPUTS];
6824 LLVMValueRef inst[SI_MAX_VS_OUTPUTS];
6825 };
6826
6827 static void si_eliminate_const_vs_outputs(struct si_shader_context *ctx)
6828 {
6829 struct si_shader *shader = ctx->shader;
6830 struct tgsi_shader_info *info = &shader->selector->info;
6831 LLVMBasicBlockRef bb;
6832 struct si_vs_exports exports;
6833 bool removed_any = false;
6834
6835 exports.num = 0;
6836
6837 if (ctx->type == PIPE_SHADER_FRAGMENT ||
6838 ctx->type == PIPE_SHADER_COMPUTE ||
6839 shader->key.as_es ||
6840 shader->key.as_ls)
6841 return;
6842
6843 /* Process all LLVM instructions. */
6844 bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6845 while (bb) {
6846 LLVMValueRef inst = LLVMGetFirstInstruction(bb);
6847
6848 while (inst) {
6849 LLVMValueRef cur = inst;
6850 inst = LLVMGetNextInstruction(inst);
6851
6852 if (LLVMGetInstructionOpcode(cur) != LLVMCall)
6853 continue;
6854
6855 LLVMValueRef callee = lp_get_called_value(cur);
6856
6857 if (!lp_is_function(callee))
6858 continue;
6859
6860 const char *name = LLVMGetValueName(callee);
6861 unsigned num_args = LLVMCountParams(callee);
6862
6863 /* Check if this is an export instruction. */
6864 if ((num_args != 9 && num_args != 8) ||
6865 (strcmp(name, "llvm.SI.export") &&
6866 strcmp(name, "llvm.amdgcn.exp.f32")))
6867 continue;
6868
6869 LLVMValueRef arg = LLVMGetOperand(cur, EXP_TARGET);
6870 unsigned target = LLVMConstIntGetZExtValue(arg);
6871
6872 if (target < V_008DFC_SQ_EXP_PARAM)
6873 continue;
6874
6875 target -= V_008DFC_SQ_EXP_PARAM;
6876
6877 /* Eliminate constant value PARAM exports. */
6878 if (si_eliminate_const_output(ctx, cur, target)) {
6879 removed_any = true;
6880 } else {
6881 exports.offset[exports.num] = target;
6882 exports.inst[exports.num] = cur;
6883 exports.num++;
6884 }
6885 }
6886 bb = LLVMGetNextBasicBlock(bb);
6887 }
6888
6889 /* Remove holes in export memory due to removed PARAM exports.
6890 * This is done by renumbering all PARAM exports.
6891 */
6892 if (removed_any) {
6893 ubyte current_offset[SI_MAX_VS_OUTPUTS];
6894 unsigned new_count = 0;
6895 unsigned out, i;
6896
6897 /* Make a copy of the offsets. We need the old version while
6898 * we are modifying some of them. */
6899 assert(sizeof(current_offset) ==
6900 sizeof(shader->info.vs_output_param_offset));
6901 memcpy(current_offset, shader->info.vs_output_param_offset,
6902 sizeof(current_offset));
6903
6904 for (i = 0; i < exports.num; i++) {
6905 unsigned offset = exports.offset[i];
6906
6907 for (out = 0; out < info->num_outputs; out++) {
6908 if (current_offset[out] != offset)
6909 continue;
6910
6911 LLVMSetOperand(exports.inst[i], EXP_TARGET,
6912 LLVMConstInt(ctx->i32,
6913 V_008DFC_SQ_EXP_PARAM + new_count, 0));
6914 shader->info.vs_output_param_offset[out] = new_count;
6915 new_count++;
6916 break;
6917 }
6918 }
6919 shader->info.nr_param_exports = new_count;
6920 }
6921 }
6922
6923 static void si_count_scratch_private_memory(struct si_shader_context *ctx)
6924 {
6925 ctx->shader->config.private_mem_vgprs = 0;
6926
6927 /* Process all LLVM instructions. */
6928 LLVMBasicBlockRef bb = LLVMGetFirstBasicBlock(ctx->main_fn);
6929 while (bb) {
6930 LLVMValueRef next = LLVMGetFirstInstruction(bb);
6931
6932 while (next) {
6933 LLVMValueRef inst = next;
6934 next = LLVMGetNextInstruction(next);
6935
6936 if (LLVMGetInstructionOpcode(inst) != LLVMAlloca)
6937 continue;
6938
6939 LLVMTypeRef type = LLVMGetElementType(LLVMTypeOf(inst));
6940 /* No idea why LLVM aligns allocas to 4 elements. */
6941 unsigned alignment = LLVMGetAlignment(inst);
6942 unsigned dw_size = align(llvm_get_type_size(type) / 4, alignment);
6943 ctx->shader->config.private_mem_vgprs += dw_size;
6944 }
6945 bb = LLVMGetNextBasicBlock(bb);
6946 }
6947 }
6948
6949 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6950 struct si_shader *shader)
6951 {
6952 struct si_shader_selector *sel = shader->selector;
6953 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6954
6955 switch (ctx->type) {
6956 case PIPE_SHADER_VERTEX:
6957 ctx->load_input = declare_input_vs;
6958 if (shader->key.as_ls)
6959 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6960 else if (shader->key.as_es)
6961 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6962 else
6963 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6964 break;
6965 case PIPE_SHADER_TESS_CTRL:
6966 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6967 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6968 bld_base->emit_store = store_output_tcs;
6969 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6970 break;
6971 case PIPE_SHADER_TESS_EVAL:
6972 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6973 if (shader->key.as_es)
6974 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6975 else
6976 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6977 break;
6978 case PIPE_SHADER_GEOMETRY:
6979 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6980 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6981 break;
6982 case PIPE_SHADER_FRAGMENT:
6983 ctx->load_input = declare_input_fs;
6984 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6985 break;
6986 case PIPE_SHADER_COMPUTE:
6987 ctx->declare_memory_region = declare_compute_memory;
6988 break;
6989 default:
6990 assert(!"Unsupported shader type");
6991 return false;
6992 }
6993
6994 create_function(ctx);
6995 preload_ring_buffers(ctx);
6996
6997 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6998 int i;
6999 for (i = 0; i < 4; i++) {
7000 ctx->gs_next_vertex[i] =
7001 lp_build_alloca(&ctx->gallivm,
7002 ctx->i32, "");
7003 }
7004 }
7005
7006 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
7007 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
7008 return false;
7009 }
7010
7011 si_llvm_build_ret(ctx, ctx->return_value);
7012 return true;
7013 }
7014
7015 /**
7016 * Compute the VS prolog key, which contains all the information needed to
7017 * build the VS prolog function, and set shader->info bits where needed.
7018 */
7019 static void si_get_vs_prolog_key(struct si_shader *shader,
7020 union si_shader_part_key *key)
7021 {
7022 struct tgsi_shader_info *info = &shader->selector->info;
7023
7024 memset(key, 0, sizeof(*key));
7025 key->vs_prolog.states = shader->key.part.vs.prolog;
7026 key->vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7027 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
7028
7029 /* Set the instanceID flag. */
7030 for (unsigned i = 0; i < info->num_inputs; i++)
7031 if (key->vs_prolog.states.instance_divisors[i])
7032 shader->info.uses_instanceid = true;
7033 }
7034
7035 /**
7036 * Compute the VS epilog key, which contains all the information needed to
7037 * build the VS epilog function, and set the PrimitiveID output offset.
7038 */
7039 static void si_get_vs_epilog_key(struct si_shader *shader,
7040 struct si_vs_epilog_bits *states,
7041 union si_shader_part_key *key)
7042 {
7043 memset(key, 0, sizeof(*key));
7044 key->vs_epilog.states = *states;
7045
7046 /* Set up the PrimitiveID output. */
7047 if (shader->key.part.vs.epilog.export_prim_id) {
7048 unsigned index = shader->selector->info.num_outputs;
7049 unsigned offset = shader->info.nr_param_exports++;
7050
7051 key->vs_epilog.prim_id_param_offset = offset;
7052 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
7053 shader->info.vs_output_param_offset[index] = offset;
7054 }
7055 }
7056
7057 /**
7058 * Compute the PS prolog key, which contains all the information needed to
7059 * build the PS prolog function, and set related bits in shader->config.
7060 */
7061 static void si_get_ps_prolog_key(struct si_shader *shader,
7062 union si_shader_part_key *key,
7063 bool separate_prolog)
7064 {
7065 struct tgsi_shader_info *info = &shader->selector->info;
7066
7067 memset(key, 0, sizeof(*key));
7068 key->ps_prolog.states = shader->key.part.ps.prolog;
7069 key->ps_prolog.colors_read = info->colors_read;
7070 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7071 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
7072 key->ps_prolog.wqm = info->uses_derivatives &&
7073 (key->ps_prolog.colors_read ||
7074 key->ps_prolog.states.force_persp_sample_interp ||
7075 key->ps_prolog.states.force_linear_sample_interp ||
7076 key->ps_prolog.states.force_persp_center_interp ||
7077 key->ps_prolog.states.force_linear_center_interp ||
7078 key->ps_prolog.states.bc_optimize_for_persp ||
7079 key->ps_prolog.states.bc_optimize_for_linear);
7080
7081 if (info->colors_read) {
7082 unsigned *color = shader->selector->color_attr_index;
7083
7084 if (shader->key.part.ps.prolog.color_two_side) {
7085 /* BCOLORs are stored after the last input. */
7086 key->ps_prolog.num_interp_inputs = info->num_inputs;
7087 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
7088 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
7089 }
7090
7091 for (unsigned i = 0; i < 2; i++) {
7092 unsigned interp = info->input_interpolate[color[i]];
7093 unsigned location = info->input_interpolate_loc[color[i]];
7094
7095 if (!(info->colors_read & (0xf << i*4)))
7096 continue;
7097
7098 key->ps_prolog.color_attr_index[i] = color[i];
7099
7100 if (shader->key.part.ps.prolog.flatshade_colors &&
7101 interp == TGSI_INTERPOLATE_COLOR)
7102 interp = TGSI_INTERPOLATE_CONSTANT;
7103
7104 switch (interp) {
7105 case TGSI_INTERPOLATE_CONSTANT:
7106 key->ps_prolog.color_interp_vgpr_index[i] = -1;
7107 break;
7108 case TGSI_INTERPOLATE_PERSPECTIVE:
7109 case TGSI_INTERPOLATE_COLOR:
7110 /* Force the interpolation location for colors here. */
7111 if (shader->key.part.ps.prolog.force_persp_sample_interp)
7112 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7113 if (shader->key.part.ps.prolog.force_persp_center_interp)
7114 location = TGSI_INTERPOLATE_LOC_CENTER;
7115
7116 switch (location) {
7117 case TGSI_INTERPOLATE_LOC_SAMPLE:
7118 key->ps_prolog.color_interp_vgpr_index[i] = 0;
7119 shader->config.spi_ps_input_ena |=
7120 S_0286CC_PERSP_SAMPLE_ENA(1);
7121 break;
7122 case TGSI_INTERPOLATE_LOC_CENTER:
7123 key->ps_prolog.color_interp_vgpr_index[i] = 2;
7124 shader->config.spi_ps_input_ena |=
7125 S_0286CC_PERSP_CENTER_ENA(1);
7126 break;
7127 case TGSI_INTERPOLATE_LOC_CENTROID:
7128 key->ps_prolog.color_interp_vgpr_index[i] = 4;
7129 shader->config.spi_ps_input_ena |=
7130 S_0286CC_PERSP_CENTROID_ENA(1);
7131 break;
7132 default:
7133 assert(0);
7134 }
7135 break;
7136 case TGSI_INTERPOLATE_LINEAR:
7137 /* Force the interpolation location for colors here. */
7138 if (shader->key.part.ps.prolog.force_linear_sample_interp)
7139 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7140 if (shader->key.part.ps.prolog.force_linear_center_interp)
7141 location = TGSI_INTERPOLATE_LOC_CENTER;
7142
7143 /* The VGPR assignment for non-monolithic shaders
7144 * works because InitialPSInputAddr is set on the
7145 * main shader and PERSP_PULL_MODEL is never used.
7146 */
7147 switch (location) {
7148 case TGSI_INTERPOLATE_LOC_SAMPLE:
7149 key->ps_prolog.color_interp_vgpr_index[i] =
7150 separate_prolog ? 6 : 9;
7151 shader->config.spi_ps_input_ena |=
7152 S_0286CC_LINEAR_SAMPLE_ENA(1);
7153 break;
7154 case TGSI_INTERPOLATE_LOC_CENTER:
7155 key->ps_prolog.color_interp_vgpr_index[i] =
7156 separate_prolog ? 8 : 11;
7157 shader->config.spi_ps_input_ena |=
7158 S_0286CC_LINEAR_CENTER_ENA(1);
7159 break;
7160 case TGSI_INTERPOLATE_LOC_CENTROID:
7161 key->ps_prolog.color_interp_vgpr_index[i] =
7162 separate_prolog ? 10 : 13;
7163 shader->config.spi_ps_input_ena |=
7164 S_0286CC_LINEAR_CENTROID_ENA(1);
7165 break;
7166 default:
7167 assert(0);
7168 }
7169 break;
7170 default:
7171 assert(0);
7172 }
7173 }
7174 }
7175 }
7176
7177 /**
7178 * Check whether a PS prolog is required based on the key.
7179 */
7180 static bool si_need_ps_prolog(const union si_shader_part_key *key)
7181 {
7182 return key->ps_prolog.colors_read ||
7183 key->ps_prolog.states.force_persp_sample_interp ||
7184 key->ps_prolog.states.force_linear_sample_interp ||
7185 key->ps_prolog.states.force_persp_center_interp ||
7186 key->ps_prolog.states.force_linear_center_interp ||
7187 key->ps_prolog.states.bc_optimize_for_persp ||
7188 key->ps_prolog.states.bc_optimize_for_linear ||
7189 key->ps_prolog.states.poly_stipple;
7190 }
7191
7192 /**
7193 * Compute the PS epilog key, which contains all the information needed to
7194 * build the PS epilog function.
7195 */
7196 static void si_get_ps_epilog_key(struct si_shader *shader,
7197 union si_shader_part_key *key)
7198 {
7199 struct tgsi_shader_info *info = &shader->selector->info;
7200 memset(key, 0, sizeof(*key));
7201 key->ps_epilog.colors_written = info->colors_written;
7202 key->ps_epilog.writes_z = info->writes_z;
7203 key->ps_epilog.writes_stencil = info->writes_stencil;
7204 key->ps_epilog.writes_samplemask = info->writes_samplemask;
7205 key->ps_epilog.states = shader->key.part.ps.epilog;
7206 }
7207
7208 /**
7209 * Build the GS prolog function. Rotate the input vertices for triangle strips
7210 * with adjacency.
7211 */
7212 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
7213 union si_shader_part_key *key)
7214 {
7215 const unsigned num_sgprs = SI_GS_NUM_USER_SGPR + 2;
7216 const unsigned num_vgprs = 8;
7217 struct gallivm_state *gallivm = &ctx->gallivm;
7218 LLVMBuilderRef builder = gallivm->builder;
7219 LLVMTypeRef params[32];
7220 LLVMTypeRef returns[32];
7221 LLVMValueRef func, ret;
7222
7223 for (unsigned i = 0; i < num_sgprs; ++i) {
7224 params[i] = ctx->i32;
7225 returns[i] = ctx->i32;
7226 }
7227
7228 for (unsigned i = 0; i < num_vgprs; ++i) {
7229 params[num_sgprs + i] = ctx->i32;
7230 returns[num_sgprs + i] = ctx->f32;
7231 }
7232
7233 /* Create the function. */
7234 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
7235 params, num_sgprs + num_vgprs, num_sgprs - 1);
7236 func = ctx->main_fn;
7237
7238 /* Copy inputs to outputs. This should be no-op, as the registers match,
7239 * but it will prevent the compiler from overwriting them unintentionally.
7240 */
7241 ret = ctx->return_value;
7242 for (unsigned i = 0; i < num_sgprs; i++) {
7243 LLVMValueRef p = LLVMGetParam(func, i);
7244 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
7245 }
7246 for (unsigned i = 0; i < num_vgprs; i++) {
7247 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
7248 p = LLVMBuildBitCast(builder, p, ctx->f32, "");
7249 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
7250 }
7251
7252 if (key->gs_prolog.states.tri_strip_adj_fix) {
7253 /* Remap the input vertices for every other primitive. */
7254 const unsigned vtx_params[6] = {
7255 num_sgprs,
7256 num_sgprs + 1,
7257 num_sgprs + 3,
7258 num_sgprs + 4,
7259 num_sgprs + 5,
7260 num_sgprs + 6
7261 };
7262 LLVMValueRef prim_id, rotate;
7263
7264 prim_id = LLVMGetParam(func, num_sgprs + 2);
7265 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
7266
7267 for (unsigned i = 0; i < 6; ++i) {
7268 LLVMValueRef base, rotated, actual;
7269 base = LLVMGetParam(func, vtx_params[i]);
7270 rotated = LLVMGetParam(func, vtx_params[(i + 4) % 6]);
7271 actual = LLVMBuildSelect(builder, rotate, rotated, base, "");
7272 actual = LLVMBuildBitCast(builder, actual, ctx->f32, "");
7273 ret = LLVMBuildInsertValue(builder, ret, actual, vtx_params[i], "");
7274 }
7275 }
7276
7277 LLVMBuildRet(builder, ret);
7278 }
7279
7280 /**
7281 * Given a list of shader part functions, build a wrapper function that
7282 * runs them in sequence to form a monolithic shader.
7283 */
7284 static void si_build_wrapper_function(struct si_shader_context *ctx,
7285 LLVMValueRef *parts,
7286 unsigned num_parts,
7287 unsigned main_part)
7288 {
7289 struct gallivm_state *gallivm = &ctx->gallivm;
7290 LLVMBuilderRef builder = ctx->gallivm.builder;
7291 /* PS epilog has one arg per color component */
7292 LLVMTypeRef param_types[48];
7293 LLVMValueRef out[48];
7294 LLVMTypeRef function_type;
7295 unsigned num_params;
7296 unsigned num_out;
7297 MAYBE_UNUSED unsigned num_out_sgpr; /* used in debug checks */
7298 unsigned num_sgprs, num_vgprs;
7299 unsigned last_sgpr_param;
7300 unsigned gprs;
7301
7302 for (unsigned i = 0; i < num_parts; ++i) {
7303 lp_add_function_attr(parts[i], -1, LP_FUNC_ATTR_ALWAYSINLINE);
7304 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
7305 }
7306
7307 /* The parameters of the wrapper function correspond to those of the
7308 * first part in terms of SGPRs and VGPRs, but we use the types of the
7309 * main part to get the right types. This is relevant for the
7310 * dereferenceable attribute on descriptor table pointers.
7311 */
7312 num_sgprs = 0;
7313 num_vgprs = 0;
7314
7315 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
7316 num_params = LLVMCountParamTypes(function_type);
7317
7318 for (unsigned i = 0; i < num_params; ++i) {
7319 LLVMValueRef param = LLVMGetParam(parts[0], i);
7320
7321 if (ac_is_sgpr_param(param)) {
7322 assert(num_vgprs == 0);
7323 num_sgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7324 } else {
7325 num_vgprs += llvm_get_type_size(LLVMTypeOf(param)) / 4;
7326 }
7327 }
7328 assert(num_vgprs + num_sgprs <= ARRAY_SIZE(param_types));
7329
7330 num_params = 0;
7331 last_sgpr_param = 0;
7332 gprs = 0;
7333 while (gprs < num_sgprs + num_vgprs) {
7334 LLVMValueRef param = LLVMGetParam(parts[main_part], num_params);
7335 unsigned size;
7336
7337 param_types[num_params] = LLVMTypeOf(param);
7338 if (gprs < num_sgprs)
7339 last_sgpr_param = num_params;
7340 size = llvm_get_type_size(param_types[num_params]) / 4;
7341 num_params++;
7342
7343 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
7344 assert(gprs + size <= num_sgprs + num_vgprs &&
7345 (gprs >= num_sgprs || gprs + size <= num_sgprs));
7346
7347 gprs += size;
7348 }
7349
7350 si_create_function(ctx, "wrapper", NULL, 0, param_types, num_params, last_sgpr_param);
7351
7352 /* Record the arguments of the function as if they were an output of
7353 * a previous part.
7354 */
7355 num_out = 0;
7356 num_out_sgpr = 0;
7357
7358 for (unsigned i = 0; i < num_params; ++i) {
7359 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
7360 LLVMTypeRef param_type = LLVMTypeOf(param);
7361 LLVMTypeRef out_type = i <= last_sgpr_param ? ctx->i32 : ctx->f32;
7362 unsigned size = llvm_get_type_size(param_type) / 4;
7363
7364 if (size == 1) {
7365 if (param_type != out_type)
7366 param = LLVMBuildBitCast(builder, param, out_type, "");
7367 out[num_out++] = param;
7368 } else {
7369 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
7370
7371 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7372 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
7373 param_type = ctx->i64;
7374 }
7375
7376 if (param_type != vector_type)
7377 param = LLVMBuildBitCast(builder, param, vector_type, "");
7378
7379 for (unsigned j = 0; j < size; ++j)
7380 out[num_out++] = LLVMBuildExtractElement(
7381 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
7382 }
7383
7384 if (i <= last_sgpr_param)
7385 num_out_sgpr = num_out;
7386 }
7387
7388 /* Now chain the parts. */
7389 for (unsigned part = 0; part < num_parts; ++part) {
7390 LLVMValueRef in[48];
7391 LLVMValueRef ret;
7392 LLVMTypeRef ret_type;
7393 unsigned out_idx = 0;
7394
7395 num_params = LLVMCountParams(parts[part]);
7396 assert(num_params <= ARRAY_SIZE(param_types));
7397
7398 /* Derive arguments for the next part from outputs of the
7399 * previous one.
7400 */
7401 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
7402 LLVMValueRef param;
7403 LLVMTypeRef param_type;
7404 bool is_sgpr;
7405 unsigned param_size;
7406 LLVMValueRef arg = NULL;
7407
7408 param = LLVMGetParam(parts[part], param_idx);
7409 param_type = LLVMTypeOf(param);
7410 param_size = llvm_get_type_size(param_type) / 4;
7411 is_sgpr = ac_is_sgpr_param(param);
7412
7413 if (is_sgpr) {
7414 #if HAVE_LLVM < 0x0400
7415 LLVMRemoveAttribute(param, LLVMByValAttribute);
7416 #else
7417 unsigned kind_id = LLVMGetEnumAttributeKindForName("byval", 5);
7418 LLVMRemoveEnumAttributeAtIndex(parts[part], param_idx + 1, kind_id);
7419 #endif
7420 lp_add_function_attr(parts[part], param_idx + 1, LP_FUNC_ATTR_INREG);
7421 }
7422
7423 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
7424 assert(is_sgpr || out_idx >= num_out_sgpr);
7425
7426 if (param_size == 1)
7427 arg = out[out_idx];
7428 else
7429 arg = lp_build_gather_values(gallivm, &out[out_idx], param_size);
7430
7431 if (LLVMTypeOf(arg) != param_type) {
7432 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
7433 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
7434 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
7435 } else {
7436 arg = LLVMBuildBitCast(builder, arg, param_type, "");
7437 }
7438 }
7439
7440 in[param_idx] = arg;
7441 out_idx += param_size;
7442 }
7443
7444 ret = LLVMBuildCall(builder, parts[part], in, num_params, "");
7445 ret_type = LLVMTypeOf(ret);
7446
7447 /* Extract the returned GPRs. */
7448 num_out = 0;
7449 num_out_sgpr = 0;
7450
7451 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
7452 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
7453
7454 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
7455
7456 for (unsigned i = 0; i < ret_size; ++i) {
7457 LLVMValueRef val =
7458 LLVMBuildExtractValue(builder, ret, i, "");
7459
7460 out[num_out++] = val;
7461
7462 if (LLVMTypeOf(val) == ctx->i32) {
7463 assert(num_out_sgpr + 1 == num_out);
7464 num_out_sgpr = num_out;
7465 }
7466 }
7467 }
7468 }
7469
7470 LLVMBuildRetVoid(builder);
7471 }
7472
7473 int si_compile_tgsi_shader(struct si_screen *sscreen,
7474 LLVMTargetMachineRef tm,
7475 struct si_shader *shader,
7476 bool is_monolithic,
7477 struct pipe_debug_callback *debug)
7478 {
7479 struct si_shader_selector *sel = shader->selector;
7480 struct si_shader_context ctx;
7481 LLVMModuleRef mod;
7482 int r = -1;
7483
7484 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
7485 * conversion fails. */
7486 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
7487 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
7488 tgsi_dump(sel->tokens, 0);
7489 si_dump_streamout(&sel->so);
7490 }
7491
7492 si_init_shader_ctx(&ctx, sscreen, shader, tm);
7493 ctx.separate_prolog = !is_monolithic;
7494
7495 memset(shader->info.vs_output_param_offset, EXP_PARAM_UNDEFINED,
7496 sizeof(shader->info.vs_output_param_offset));
7497
7498 shader->info.uses_instanceid = sel->info.uses_instanceid;
7499
7500 ctx.load_system_value = declare_system_value;
7501
7502 if (!si_compile_tgsi_main(&ctx, shader)) {
7503 si_llvm_dispose(&ctx);
7504 return -1;
7505 }
7506
7507 if (is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
7508 LLVMValueRef parts[3];
7509 bool need_prolog;
7510 bool need_epilog;
7511
7512 need_prolog = sel->info.num_inputs;
7513 need_epilog = !shader->key.as_es && !shader->key.as_ls;
7514
7515 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7516
7517 if (need_prolog) {
7518 union si_shader_part_key prolog_key;
7519 si_get_vs_prolog_key(shader, &prolog_key);
7520 si_build_vs_prolog_function(&ctx, &prolog_key);
7521 parts[0] = ctx.main_fn;
7522 }
7523
7524 if (need_epilog) {
7525 union si_shader_part_key epilog_key;
7526 si_get_vs_epilog_key(shader, &shader->key.part.vs.epilog, &epilog_key);
7527 si_build_vs_epilog_function(&ctx, &epilog_key);
7528 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7529 }
7530
7531 si_build_wrapper_function(&ctx, parts, 1 + need_prolog + need_epilog,
7532 need_prolog ? 1 : 0);
7533 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
7534 LLVMValueRef parts[2];
7535 union si_shader_part_key epilog_key;
7536
7537 parts[0] = ctx.main_fn;
7538
7539 memset(&epilog_key, 0, sizeof(epilog_key));
7540 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7541 si_build_tcs_epilog_function(&ctx, &epilog_key);
7542 parts[1] = ctx.main_fn;
7543
7544 si_build_wrapper_function(&ctx, parts, 2, 0);
7545 } else if (is_monolithic && ctx.type == PIPE_SHADER_TESS_EVAL &&
7546 !shader->key.as_es) {
7547 LLVMValueRef parts[2];
7548 union si_shader_part_key epilog_key;
7549
7550 parts[0] = ctx.main_fn;
7551
7552 si_get_vs_epilog_key(shader, &shader->key.part.tes.epilog, &epilog_key);
7553 si_build_vs_epilog_function(&ctx, &epilog_key);
7554 parts[1] = ctx.main_fn;
7555
7556 si_build_wrapper_function(&ctx, parts, 2, 0);
7557 } else if (is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
7558 LLVMValueRef parts[2];
7559 union si_shader_part_key prolog_key;
7560
7561 parts[1] = ctx.main_fn;
7562
7563 memset(&prolog_key, 0, sizeof(prolog_key));
7564 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7565 si_build_gs_prolog_function(&ctx, &prolog_key);
7566 parts[0] = ctx.main_fn;
7567
7568 si_build_wrapper_function(&ctx, parts, 2, 1);
7569 } else if (is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
7570 LLVMValueRef parts[3];
7571 union si_shader_part_key prolog_key;
7572 union si_shader_part_key epilog_key;
7573 bool need_prolog;
7574
7575 si_get_ps_prolog_key(shader, &prolog_key, false);
7576 need_prolog = si_need_ps_prolog(&prolog_key);
7577
7578 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7579
7580 if (need_prolog) {
7581 si_build_ps_prolog_function(&ctx, &prolog_key);
7582 parts[0] = ctx.main_fn;
7583 }
7584
7585 si_get_ps_epilog_key(shader, &epilog_key);
7586 si_build_ps_epilog_function(&ctx, &epilog_key);
7587 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7588
7589 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2, need_prolog ? 1 : 0);
7590 }
7591
7592 mod = ctx.gallivm.module;
7593
7594 /* Dump LLVM IR before any optimization passes */
7595 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
7596 r600_can_dump_shader(&sscreen->b, ctx.type))
7597 ac_dump_module(mod);
7598
7599 si_llvm_finalize_module(&ctx,
7600 r600_extra_shader_checks(&sscreen->b, ctx.type));
7601
7602 /* Post-optimization transformations and analysis. */
7603 si_eliminate_const_vs_outputs(&ctx);
7604
7605 if ((debug && debug->debug_message) ||
7606 r600_can_dump_shader(&sscreen->b, ctx.type))
7607 si_count_scratch_private_memory(&ctx);
7608
7609 /* Compile to bytecode. */
7610 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
7611 mod, debug, ctx.type, "TGSI shader");
7612 si_llvm_dispose(&ctx);
7613 if (r) {
7614 fprintf(stderr, "LLVM failed to compile shader\n");
7615 return r;
7616 }
7617
7618 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
7619 * LLVM 3.9svn has this bug.
7620 */
7621 if (sel->type == PIPE_SHADER_COMPUTE) {
7622 unsigned wave_size = 64;
7623 unsigned max_vgprs = 256;
7624 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
7625 unsigned max_sgprs_per_wave = 128;
7626 unsigned max_block_threads = si_get_max_workgroup_size(shader);
7627 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
7628 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
7629
7630 max_vgprs = max_vgprs / min_waves_per_simd;
7631 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
7632
7633 if (shader->config.num_sgprs > max_sgprs ||
7634 shader->config.num_vgprs > max_vgprs) {
7635 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7636 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7637 shader->config.num_sgprs, shader->config.num_vgprs,
7638 max_sgprs, max_vgprs);
7639
7640 /* Just terminate the process, because dependent
7641 * shaders can hang due to bad input data, but use
7642 * the env var to allow shader-db to work.
7643 */
7644 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7645 abort();
7646 }
7647 }
7648
7649 /* Add the scratch offset to input SGPRs. */
7650 if (shader->config.scratch_bytes_per_wave)
7651 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7652
7653 /* Calculate the number of fragment input VGPRs. */
7654 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7655 shader->info.num_input_vgprs = 0;
7656 shader->info.face_vgpr_index = -1;
7657
7658 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7659 shader->info.num_input_vgprs += 2;
7660 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
7661 shader->info.num_input_vgprs += 2;
7662 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
7663 shader->info.num_input_vgprs += 2;
7664 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
7665 shader->info.num_input_vgprs += 3;
7666 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
7667 shader->info.num_input_vgprs += 2;
7668 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
7669 shader->info.num_input_vgprs += 2;
7670 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
7671 shader->info.num_input_vgprs += 2;
7672 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
7673 shader->info.num_input_vgprs += 1;
7674 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
7675 shader->info.num_input_vgprs += 1;
7676 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
7677 shader->info.num_input_vgprs += 1;
7678 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
7679 shader->info.num_input_vgprs += 1;
7680 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
7681 shader->info.num_input_vgprs += 1;
7682 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
7683 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
7684 shader->info.num_input_vgprs += 1;
7685 }
7686 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
7687 shader->info.num_input_vgprs += 1;
7688 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
7689 shader->info.num_input_vgprs += 1;
7690 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
7691 shader->info.num_input_vgprs += 1;
7692 }
7693
7694 return 0;
7695 }
7696
7697 /**
7698 * Create, compile and return a shader part (prolog or epilog).
7699 *
7700 * \param sscreen screen
7701 * \param list list of shader parts of the same category
7702 * \param type shader type
7703 * \param key shader part key
7704 * \param prolog whether the part being requested is a prolog
7705 * \param tm LLVM target machine
7706 * \param debug debug callback
7707 * \param build the callback responsible for building the main function
7708 * \return non-NULL on success
7709 */
7710 static struct si_shader_part *
7711 si_get_shader_part(struct si_screen *sscreen,
7712 struct si_shader_part **list,
7713 enum pipe_shader_type type,
7714 bool prolog,
7715 union si_shader_part_key *key,
7716 LLVMTargetMachineRef tm,
7717 struct pipe_debug_callback *debug,
7718 void (*build)(struct si_shader_context *,
7719 union si_shader_part_key *),
7720 const char *name)
7721 {
7722 struct si_shader_part *result;
7723
7724 mtx_lock(&sscreen->shader_parts_mutex);
7725
7726 /* Find existing. */
7727 for (result = *list; result; result = result->next) {
7728 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7729 mtx_unlock(&sscreen->shader_parts_mutex);
7730 return result;
7731 }
7732 }
7733
7734 /* Compile a new one. */
7735 result = CALLOC_STRUCT(si_shader_part);
7736 result->key = *key;
7737
7738 struct si_shader shader = {};
7739 struct si_shader_context ctx;
7740 struct gallivm_state *gallivm = &ctx.gallivm;
7741
7742 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7743 ctx.type = type;
7744
7745 switch (type) {
7746 case PIPE_SHADER_VERTEX:
7747 break;
7748 case PIPE_SHADER_TESS_CTRL:
7749 assert(!prolog);
7750 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7751 break;
7752 case PIPE_SHADER_GEOMETRY:
7753 assert(prolog);
7754 break;
7755 case PIPE_SHADER_FRAGMENT:
7756 if (prolog)
7757 shader.key.part.ps.prolog = key->ps_prolog.states;
7758 else
7759 shader.key.part.ps.epilog = key->ps_epilog.states;
7760 break;
7761 default:
7762 unreachable("bad shader part");
7763 }
7764
7765 build(&ctx, key);
7766
7767 /* Compile. */
7768 si_llvm_finalize_module(&ctx,
7769 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
7770
7771 if (si_compile_llvm(sscreen, &result->binary, &result->config, tm,
7772 gallivm->module, debug, ctx.type, name)) {
7773 FREE(result);
7774 result = NULL;
7775 goto out;
7776 }
7777
7778 result->next = *list;
7779 *list = result;
7780
7781 out:
7782 si_llvm_dispose(&ctx);
7783 mtx_unlock(&sscreen->shader_parts_mutex);
7784 return result;
7785 }
7786
7787 /**
7788 * Build the vertex shader prolog function.
7789 *
7790 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7791 * All inputs are returned unmodified. The vertex load indices are
7792 * stored after them, which will be used by the API VS for fetching inputs.
7793 *
7794 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7795 * input_v0,
7796 * input_v1,
7797 * input_v2,
7798 * input_v3,
7799 * (VertexID + BaseVertex),
7800 * (InstanceID + StartInstance),
7801 * (InstanceID / 2 + StartInstance)
7802 */
7803 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7804 union si_shader_part_key *key)
7805 {
7806 struct gallivm_state *gallivm = &ctx->gallivm;
7807 LLVMTypeRef *params, *returns;
7808 LLVMValueRef ret, func;
7809 int last_sgpr, num_params, num_returns, i;
7810
7811 ctx->param_vertex_id = key->vs_prolog.num_input_sgprs;
7812 ctx->param_instance_id = key->vs_prolog.num_input_sgprs + 3;
7813
7814 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7815 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
7816 sizeof(LLVMTypeRef));
7817 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
7818 key->vs_prolog.last_input + 1) *
7819 sizeof(LLVMTypeRef));
7820 num_params = 0;
7821 num_returns = 0;
7822
7823 /* Declare input and output SGPRs. */
7824 num_params = 0;
7825 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7826 params[num_params++] = ctx->i32;
7827 returns[num_returns++] = ctx->i32;
7828 }
7829 last_sgpr = num_params - 1;
7830
7831 /* 4 preloaded VGPRs (outputs must be floats) */
7832 for (i = 0; i < 4; i++) {
7833 params[num_params++] = ctx->i32;
7834 returns[num_returns++] = ctx->f32;
7835 }
7836
7837 /* Vertex load indices. */
7838 for (i = 0; i <= key->vs_prolog.last_input; i++)
7839 returns[num_returns++] = ctx->f32;
7840
7841 /* Create the function. */
7842 si_create_function(ctx, "vs_prolog", returns, num_returns, params,
7843 num_params, last_sgpr);
7844 func = ctx->main_fn;
7845
7846 /* Copy inputs to outputs. This should be no-op, as the registers match,
7847 * but it will prevent the compiler from overwriting them unintentionally.
7848 */
7849 ret = ctx->return_value;
7850 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7851 LLVMValueRef p = LLVMGetParam(func, i);
7852 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7853 }
7854 for (i = num_params - 4; i < num_params; i++) {
7855 LLVMValueRef p = LLVMGetParam(func, i);
7856 p = LLVMBuildBitCast(gallivm->builder, p, ctx->f32, "");
7857 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7858 }
7859
7860 /* Compute vertex load indices from instance divisors. */
7861 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7862 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
7863 LLVMValueRef index;
7864
7865 if (divisor) {
7866 /* InstanceID / Divisor + StartInstance */
7867 index = get_instance_index_for_fetch(ctx,
7868 SI_SGPR_START_INSTANCE,
7869 divisor);
7870 } else {
7871 /* VertexID + BaseVertex */
7872 index = LLVMBuildAdd(gallivm->builder,
7873 LLVMGetParam(func, ctx->param_vertex_id),
7874 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
7875 }
7876
7877 index = LLVMBuildBitCast(gallivm->builder, index, ctx->f32, "");
7878 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
7879 num_params++, "");
7880 }
7881
7882 si_llvm_build_ret(ctx, ret);
7883 }
7884
7885 /**
7886 * Build the vertex shader epilog function. This is also used by the tessellation
7887 * evaluation shader compiled as VS.
7888 *
7889 * The input is PrimitiveID.
7890 *
7891 * If PrimitiveID is required by the pixel shader, export it.
7892 * Otherwise, do nothing.
7893 */
7894 static void si_build_vs_epilog_function(struct si_shader_context *ctx,
7895 union si_shader_part_key *key)
7896 {
7897 struct gallivm_state *gallivm = &ctx->gallivm;
7898 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7899 LLVMTypeRef params[5];
7900 int num_params, i;
7901
7902 /* Declare input VGPRs. */
7903 num_params = key->vs_epilog.states.export_prim_id ?
7904 (VS_EPILOG_PRIMID_LOC + 1) : 0;
7905 assert(num_params <= ARRAY_SIZE(params));
7906
7907 for (i = 0; i < num_params; i++)
7908 params[i] = ctx->f32;
7909
7910 /* Create the function. */
7911 si_create_function(ctx, "vs_epilog", NULL, 0, params, num_params, -1);
7912
7913 /* Emit exports. */
7914 if (key->vs_epilog.states.export_prim_id) {
7915 struct lp_build_context *base = &bld_base->base;
7916 struct ac_export_args args;
7917
7918 args.enabled_channels = 0x1; /* enabled channels */
7919 args.valid_mask = 0; /* whether the EXEC mask is valid */
7920 args.done = 0; /* DONE bit */
7921 args.target = V_008DFC_SQ_EXP_PARAM +
7922 key->vs_epilog.prim_id_param_offset;
7923 args.compr = 0; /* COMPR flag (0 = 32-bit export) */
7924 args.out[0] = LLVMGetParam(ctx->main_fn,
7925 VS_EPILOG_PRIMID_LOC); /* X */
7926 args.out[1] = base->undef; /* Y */
7927 args.out[2] = base->undef; /* Z */
7928 args.out[3] = base->undef; /* W */
7929
7930 ac_build_export(&ctx->ac, &args);
7931 }
7932
7933 LLVMBuildRetVoid(gallivm->builder);
7934 }
7935
7936 /**
7937 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7938 */
7939 static bool si_get_vs_epilog(struct si_screen *sscreen,
7940 LLVMTargetMachineRef tm,
7941 struct si_shader *shader,
7942 struct pipe_debug_callback *debug,
7943 struct si_vs_epilog_bits *states)
7944 {
7945 union si_shader_part_key epilog_key;
7946
7947 si_get_vs_epilog_key(shader, states, &epilog_key);
7948
7949 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7950 PIPE_SHADER_VERTEX, true,
7951 &epilog_key, tm, debug,
7952 si_build_vs_epilog_function,
7953 "Vertex Shader Epilog");
7954 return shader->epilog != NULL;
7955 }
7956
7957 /**
7958 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7959 */
7960 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7961 LLVMTargetMachineRef tm,
7962 struct si_shader *shader,
7963 struct pipe_debug_callback *debug)
7964 {
7965 struct tgsi_shader_info *info = &shader->selector->info;
7966 union si_shader_part_key prolog_key;
7967
7968 /* Get the prolog. */
7969 si_get_vs_prolog_key(shader, &prolog_key);
7970
7971 /* The prolog is a no-op if there are no inputs. */
7972 if (info->num_inputs) {
7973 shader->prolog =
7974 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7975 PIPE_SHADER_VERTEX, true,
7976 &prolog_key, tm, debug,
7977 si_build_vs_prolog_function,
7978 "Vertex Shader Prolog");
7979 if (!shader->prolog)
7980 return false;
7981 }
7982
7983 /* Get the epilog. */
7984 if (!shader->key.as_es && !shader->key.as_ls &&
7985 !si_get_vs_epilog(sscreen, tm, shader, debug,
7986 &shader->key.part.vs.epilog))
7987 return false;
7988
7989 return true;
7990 }
7991
7992 /**
7993 * Select and compile (or reuse) TES parts (epilog).
7994 */
7995 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7996 LLVMTargetMachineRef tm,
7997 struct si_shader *shader,
7998 struct pipe_debug_callback *debug)
7999 {
8000 if (shader->key.as_es)
8001 return true;
8002
8003 /* TES compiled as VS. */
8004 return si_get_vs_epilog(sscreen, tm, shader, debug,
8005 &shader->key.part.tes.epilog);
8006 }
8007
8008 /**
8009 * Compile the TCS epilog function. This writes tesselation factors to memory
8010 * based on the output primitive type of the tesselator (determined by TES).
8011 */
8012 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
8013 union si_shader_part_key *key)
8014 {
8015 struct gallivm_state *gallivm = &ctx->gallivm;
8016 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
8017 LLVMTypeRef params[16];
8018 LLVMValueRef func;
8019 int last_sgpr, num_params;
8020
8021 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
8022 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
8023 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
8024 params[SI_PARAM_SAMPLERS] = ctx->i64;
8025 params[SI_PARAM_IMAGES] = ctx->i64;
8026 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
8027 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
8028 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
8029 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
8030 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
8031 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
8032 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
8033 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
8034 num_params = last_sgpr + 1;
8035
8036 params[num_params++] = ctx->i32; /* patch index within the wave (REL_PATCH_ID) */
8037 params[num_params++] = ctx->i32; /* invocation ID within the patch */
8038 params[num_params++] = ctx->i32; /* LDS offset where tess factors should be loaded from */
8039
8040 /* Create the function. */
8041 si_create_function(ctx, "tcs_epilog", NULL, 0, params, num_params, last_sgpr);
8042 declare_tess_lds(ctx);
8043 func = ctx->main_fn;
8044
8045 si_write_tess_factors(bld_base,
8046 LLVMGetParam(func, last_sgpr + 1),
8047 LLVMGetParam(func, last_sgpr + 2),
8048 LLVMGetParam(func, last_sgpr + 3));
8049
8050 LLVMBuildRetVoid(gallivm->builder);
8051 }
8052
8053 /**
8054 * Select and compile (or reuse) TCS parts (epilog).
8055 */
8056 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
8057 LLVMTargetMachineRef tm,
8058 struct si_shader *shader,
8059 struct pipe_debug_callback *debug)
8060 {
8061 union si_shader_part_key epilog_key;
8062
8063 /* Get the epilog. */
8064 memset(&epilog_key, 0, sizeof(epilog_key));
8065 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
8066
8067 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
8068 PIPE_SHADER_TESS_CTRL, false,
8069 &epilog_key, tm, debug,
8070 si_build_tcs_epilog_function,
8071 "Tessellation Control Shader Epilog");
8072 return shader->epilog != NULL;
8073 }
8074
8075 /**
8076 * Select and compile (or reuse) GS parts (prolog).
8077 */
8078 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
8079 LLVMTargetMachineRef tm,
8080 struct si_shader *shader,
8081 struct pipe_debug_callback *debug)
8082 {
8083 union si_shader_part_key prolog_key;
8084
8085 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
8086 return true;
8087
8088 memset(&prolog_key, 0, sizeof(prolog_key));
8089 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
8090
8091 shader->prolog = si_get_shader_part(sscreen, &sscreen->gs_prologs,
8092 PIPE_SHADER_GEOMETRY, true,
8093 &prolog_key, tm, debug,
8094 si_build_gs_prolog_function,
8095 "Geometry Shader Prolog");
8096 return shader->prolog != NULL;
8097 }
8098
8099 /**
8100 * Build the pixel shader prolog function. This handles:
8101 * - two-side color selection and interpolation
8102 * - overriding interpolation parameters for the API PS
8103 * - polygon stippling
8104 *
8105 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
8106 * overriden by other states. (e.g. per-sample interpolation)
8107 * Interpolated colors are stored after the preloaded VGPRs.
8108 */
8109 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
8110 union si_shader_part_key *key)
8111 {
8112 struct gallivm_state *gallivm = &ctx->gallivm;
8113 LLVMTypeRef *params;
8114 LLVMValueRef ret, func;
8115 int last_sgpr, num_params, num_returns, i, num_color_channels;
8116
8117 assert(si_need_ps_prolog(key));
8118
8119 /* Number of inputs + 8 color elements. */
8120 params = alloca((key->ps_prolog.num_input_sgprs +
8121 key->ps_prolog.num_input_vgprs + 8) *
8122 sizeof(LLVMTypeRef));
8123
8124 /* Declare inputs. */
8125 num_params = 0;
8126 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
8127 params[num_params++] = ctx->i32;
8128 last_sgpr = num_params - 1;
8129
8130 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
8131 params[num_params++] = ctx->f32;
8132
8133 /* Declare outputs (same as inputs + add colors if needed) */
8134 num_returns = num_params;
8135 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
8136 for (i = 0; i < num_color_channels; i++)
8137 params[num_returns++] = ctx->f32;
8138
8139 /* Create the function. */
8140 si_create_function(ctx, "ps_prolog", params, num_returns, params,
8141 num_params, last_sgpr);
8142 func = ctx->main_fn;
8143
8144 /* Copy inputs to outputs. This should be no-op, as the registers match,
8145 * but it will prevent the compiler from overwriting them unintentionally.
8146 */
8147 ret = ctx->return_value;
8148 for (i = 0; i < num_params; i++) {
8149 LLVMValueRef p = LLVMGetParam(func, i);
8150 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
8151 }
8152
8153 /* Polygon stippling. */
8154 if (key->ps_prolog.states.poly_stipple) {
8155 /* POS_FIXED_PT is always last. */
8156 unsigned pos = key->ps_prolog.num_input_sgprs +
8157 key->ps_prolog.num_input_vgprs - 1;
8158 LLVMValueRef ptr[2], list;
8159
8160 /* Get the pointer to rw buffers. */
8161 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
8162 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
8163 list = lp_build_gather_values(gallivm, ptr, 2);
8164 list = LLVMBuildBitCast(gallivm->builder, list, ctx->i64, "");
8165 list = LLVMBuildIntToPtr(gallivm->builder, list,
8166 const_array(ctx->v16i8, SI_NUM_RW_BUFFERS), "");
8167
8168 si_llvm_emit_polygon_stipple(ctx, list, pos);
8169 }
8170
8171 if (key->ps_prolog.states.bc_optimize_for_persp ||
8172 key->ps_prolog.states.bc_optimize_for_linear) {
8173 unsigned i, base = key->ps_prolog.num_input_sgprs;
8174 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
8175
8176 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
8177 * The hw doesn't compute CENTROID if the whole wave only
8178 * contains fully-covered quads.
8179 *
8180 * PRIM_MASK is after user SGPRs.
8181 */
8182 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
8183 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
8184 LLVMConstInt(ctx->i32, 31, 0), "");
8185 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
8186 ctx->i1, "");
8187
8188 if (key->ps_prolog.states.bc_optimize_for_persp) {
8189 /* Read PERSP_CENTER. */
8190 for (i = 0; i < 2; i++)
8191 center[i] = LLVMGetParam(func, base + 2 + i);
8192 /* Read PERSP_CENTROID. */
8193 for (i = 0; i < 2; i++)
8194 centroid[i] = LLVMGetParam(func, base + 4 + i);
8195 /* Select PERSP_CENTROID. */
8196 for (i = 0; i < 2; i++) {
8197 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
8198 center[i], centroid[i], "");
8199 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8200 tmp, base + 4 + i, "");
8201 }
8202 }
8203 if (key->ps_prolog.states.bc_optimize_for_linear) {
8204 /* Read LINEAR_CENTER. */
8205 for (i = 0; i < 2; i++)
8206 center[i] = LLVMGetParam(func, base + 8 + i);
8207 /* Read LINEAR_CENTROID. */
8208 for (i = 0; i < 2; i++)
8209 centroid[i] = LLVMGetParam(func, base + 10 + i);
8210 /* Select LINEAR_CENTROID. */
8211 for (i = 0; i < 2; i++) {
8212 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
8213 center[i], centroid[i], "");
8214 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8215 tmp, base + 10 + i, "");
8216 }
8217 }
8218 }
8219
8220 /* Force per-sample interpolation. */
8221 if (key->ps_prolog.states.force_persp_sample_interp) {
8222 unsigned i, base = key->ps_prolog.num_input_sgprs;
8223 LLVMValueRef persp_sample[2];
8224
8225 /* Read PERSP_SAMPLE. */
8226 for (i = 0; i < 2; i++)
8227 persp_sample[i] = LLVMGetParam(func, base + i);
8228 /* Overwrite PERSP_CENTER. */
8229 for (i = 0; i < 2; i++)
8230 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8231 persp_sample[i], base + 2 + i, "");
8232 /* Overwrite PERSP_CENTROID. */
8233 for (i = 0; i < 2; i++)
8234 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8235 persp_sample[i], base + 4 + i, "");
8236 }
8237 if (key->ps_prolog.states.force_linear_sample_interp) {
8238 unsigned i, base = key->ps_prolog.num_input_sgprs;
8239 LLVMValueRef linear_sample[2];
8240
8241 /* Read LINEAR_SAMPLE. */
8242 for (i = 0; i < 2; i++)
8243 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
8244 /* Overwrite LINEAR_CENTER. */
8245 for (i = 0; i < 2; i++)
8246 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8247 linear_sample[i], base + 8 + i, "");
8248 /* Overwrite LINEAR_CENTROID. */
8249 for (i = 0; i < 2; i++)
8250 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8251 linear_sample[i], base + 10 + i, "");
8252 }
8253
8254 /* Force center interpolation. */
8255 if (key->ps_prolog.states.force_persp_center_interp) {
8256 unsigned i, base = key->ps_prolog.num_input_sgprs;
8257 LLVMValueRef persp_center[2];
8258
8259 /* Read PERSP_CENTER. */
8260 for (i = 0; i < 2; i++)
8261 persp_center[i] = LLVMGetParam(func, base + 2 + i);
8262 /* Overwrite PERSP_SAMPLE. */
8263 for (i = 0; i < 2; i++)
8264 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8265 persp_center[i], base + i, "");
8266 /* Overwrite PERSP_CENTROID. */
8267 for (i = 0; i < 2; i++)
8268 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8269 persp_center[i], base + 4 + i, "");
8270 }
8271 if (key->ps_prolog.states.force_linear_center_interp) {
8272 unsigned i, base = key->ps_prolog.num_input_sgprs;
8273 LLVMValueRef linear_center[2];
8274
8275 /* Read LINEAR_CENTER. */
8276 for (i = 0; i < 2; i++)
8277 linear_center[i] = LLVMGetParam(func, base + 8 + i);
8278 /* Overwrite LINEAR_SAMPLE. */
8279 for (i = 0; i < 2; i++)
8280 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8281 linear_center[i], base + 6 + i, "");
8282 /* Overwrite LINEAR_CENTROID. */
8283 for (i = 0; i < 2; i++)
8284 ret = LLVMBuildInsertValue(gallivm->builder, ret,
8285 linear_center[i], base + 10 + i, "");
8286 }
8287
8288 /* Interpolate colors. */
8289 for (i = 0; i < 2; i++) {
8290 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
8291 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
8292 key->ps_prolog.face_vgpr_index;
8293 LLVMValueRef interp[2], color[4];
8294 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
8295
8296 if (!writemask)
8297 continue;
8298
8299 /* If the interpolation qualifier is not CONSTANT (-1). */
8300 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
8301 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
8302 key->ps_prolog.color_interp_vgpr_index[i];
8303
8304 /* Get the (i,j) updated by bc_optimize handling. */
8305 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
8306 interp_vgpr, "");
8307 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
8308 interp_vgpr + 1, "");
8309 interp_ij = lp_build_gather_values(gallivm, interp, 2);
8310 }
8311
8312 /* Use the absolute location of the input. */
8313 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
8314
8315 if (key->ps_prolog.states.color_two_side) {
8316 face = LLVMGetParam(func, face_vgpr);
8317 face = LLVMBuildBitCast(gallivm->builder, face, ctx->i32, "");
8318 }
8319
8320 interp_fs_input(ctx,
8321 key->ps_prolog.color_attr_index[i],
8322 TGSI_SEMANTIC_COLOR, i,
8323 key->ps_prolog.num_interp_inputs,
8324 key->ps_prolog.colors_read, interp_ij,
8325 prim_mask, face, color);
8326
8327 while (writemask) {
8328 unsigned chan = u_bit_scan(&writemask);
8329 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
8330 num_params++, "");
8331 }
8332 }
8333
8334 /* Tell LLVM to insert WQM instruction sequence when needed. */
8335 if (key->ps_prolog.wqm) {
8336 LLVMAddTargetDependentFunctionAttr(func,
8337 "amdgpu-ps-wqm-outputs", "");
8338 }
8339
8340 si_llvm_build_ret(ctx, ret);
8341 }
8342
8343 /**
8344 * Build the pixel shader epilog function. This handles everything that must be
8345 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
8346 */
8347 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
8348 union si_shader_part_key *key)
8349 {
8350 struct gallivm_state *gallivm = &ctx->gallivm;
8351 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
8352 LLVMTypeRef params[16+8*4+3];
8353 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
8354 int last_sgpr, num_params, i;
8355 struct si_ps_exports exp = {};
8356
8357 /* Declare input SGPRs. */
8358 params[SI_PARAM_RW_BUFFERS] = ctx->i64;
8359 params[SI_PARAM_CONST_BUFFERS] = ctx->i64;
8360 params[SI_PARAM_SAMPLERS] = ctx->i64;
8361 params[SI_PARAM_IMAGES] = ctx->i64;
8362 params[SI_PARAM_SHADER_BUFFERS] = ctx->i64;
8363 params[SI_PARAM_ALPHA_REF] = ctx->f32;
8364 last_sgpr = SI_PARAM_ALPHA_REF;
8365
8366 /* Declare input VGPRs. */
8367 num_params = (last_sgpr + 1) +
8368 util_bitcount(key->ps_epilog.colors_written) * 4 +
8369 key->ps_epilog.writes_z +
8370 key->ps_epilog.writes_stencil +
8371 key->ps_epilog.writes_samplemask;
8372
8373 num_params = MAX2(num_params,
8374 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
8375
8376 assert(num_params <= ARRAY_SIZE(params));
8377
8378 for (i = last_sgpr + 1; i < num_params; i++)
8379 params[i] = ctx->f32;
8380
8381 /* Create the function. */
8382 si_create_function(ctx, "ps_epilog", NULL, 0, params, num_params, last_sgpr);
8383 /* Disable elimination of unused inputs. */
8384 si_llvm_add_attribute(ctx->main_fn,
8385 "InitialPSInputAddr", 0xffffff);
8386
8387 /* Process colors. */
8388 unsigned vgpr = last_sgpr + 1;
8389 unsigned colors_written = key->ps_epilog.colors_written;
8390 int last_color_export = -1;
8391
8392 /* Find the last color export. */
8393 if (!key->ps_epilog.writes_z &&
8394 !key->ps_epilog.writes_stencil &&
8395 !key->ps_epilog.writes_samplemask) {
8396 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
8397
8398 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
8399 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
8400 /* Just set this if any of the colorbuffers are enabled. */
8401 if (spi_format &
8402 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
8403 last_color_export = 0;
8404 } else {
8405 for (i = 0; i < 8; i++)
8406 if (colors_written & (1 << i) &&
8407 (spi_format >> (i * 4)) & 0xf)
8408 last_color_export = i;
8409 }
8410 }
8411
8412 while (colors_written) {
8413 LLVMValueRef color[4];
8414 int mrt = u_bit_scan(&colors_written);
8415
8416 for (i = 0; i < 4; i++)
8417 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
8418
8419 si_export_mrt_color(bld_base, color, mrt,
8420 num_params - 1,
8421 mrt == last_color_export, &exp);
8422 }
8423
8424 /* Process depth, stencil, samplemask. */
8425 if (key->ps_epilog.writes_z)
8426 depth = LLVMGetParam(ctx->main_fn, vgpr++);
8427 if (key->ps_epilog.writes_stencil)
8428 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
8429 if (key->ps_epilog.writes_samplemask)
8430 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
8431
8432 if (depth || stencil || samplemask)
8433 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
8434 else if (last_color_export == -1)
8435 si_export_null(bld_base);
8436
8437 if (exp.num)
8438 si_emit_ps_exports(ctx, &exp);
8439
8440 /* Compile. */
8441 LLVMBuildRetVoid(gallivm->builder);
8442 }
8443
8444 /**
8445 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
8446 */
8447 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
8448 LLVMTargetMachineRef tm,
8449 struct si_shader *shader,
8450 struct pipe_debug_callback *debug)
8451 {
8452 union si_shader_part_key prolog_key;
8453 union si_shader_part_key epilog_key;
8454
8455 /* Get the prolog. */
8456 si_get_ps_prolog_key(shader, &prolog_key, true);
8457
8458 /* The prolog is a no-op if these aren't set. */
8459 if (si_need_ps_prolog(&prolog_key)) {
8460 shader->prolog =
8461 si_get_shader_part(sscreen, &sscreen->ps_prologs,
8462 PIPE_SHADER_FRAGMENT, true,
8463 &prolog_key, tm, debug,
8464 si_build_ps_prolog_function,
8465 "Fragment Shader Prolog");
8466 if (!shader->prolog)
8467 return false;
8468 }
8469
8470 /* Get the epilog. */
8471 si_get_ps_epilog_key(shader, &epilog_key);
8472
8473 shader->epilog =
8474 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
8475 PIPE_SHADER_FRAGMENT, false,
8476 &epilog_key, tm, debug,
8477 si_build_ps_epilog_function,
8478 "Fragment Shader Epilog");
8479 if (!shader->epilog)
8480 return false;
8481
8482 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
8483 if (shader->key.part.ps.prolog.poly_stipple) {
8484 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
8485 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
8486 }
8487
8488 /* Set up the enable bits for per-sample shading if needed. */
8489 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
8490 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8491 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8492 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
8493 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8494 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
8495 }
8496 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
8497 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8498 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8499 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
8500 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8501 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
8502 }
8503 if (shader->key.part.ps.prolog.force_persp_center_interp &&
8504 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8505 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8506 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
8507 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8508 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8509 }
8510 if (shader->key.part.ps.prolog.force_linear_center_interp &&
8511 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8512 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8513 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
8514 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8515 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8516 }
8517
8518 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
8519 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
8520 !(shader->config.spi_ps_input_ena & 0xf)) {
8521 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8522 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
8523 }
8524
8525 /* At least one pair of interpolation weights must be enabled. */
8526 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
8527 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8528 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
8529 }
8530
8531 /* The sample mask input is always enabled, because the API shader always
8532 * passes it through to the epilog. Disable it here if it's unused.
8533 */
8534 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
8535 !shader->selector->info.reads_samplemask)
8536 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
8537
8538 return true;
8539 }
8540
8541 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
8542 unsigned *lds_size)
8543 {
8544 /* SPI barrier management bug:
8545 * Make sure we have at least 4k of LDS in use to avoid the bug.
8546 * It applies to workgroup sizes of more than one wavefront.
8547 */
8548 if (sscreen->b.family == CHIP_BONAIRE ||
8549 sscreen->b.family == CHIP_KABINI ||
8550 sscreen->b.family == CHIP_MULLINS)
8551 *lds_size = MAX2(*lds_size, 8);
8552 }
8553
8554 static void si_fix_resource_usage(struct si_screen *sscreen,
8555 struct si_shader *shader)
8556 {
8557 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8558
8559 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8560
8561 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8562 si_get_max_workgroup_size(shader) > 64) {
8563 si_multiwave_lds_size_workaround(sscreen,
8564 &shader->config.lds_size);
8565 }
8566 }
8567
8568 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
8569 struct si_shader *shader,
8570 struct pipe_debug_callback *debug)
8571 {
8572 struct si_shader_selector *sel = shader->selector;
8573 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
8574 int r;
8575
8576 /* LS, ES, VS are compiled on demand if the main part hasn't been
8577 * compiled for that stage.
8578 *
8579 * Vertex shaders are compiled on demand when a vertex fetch
8580 * workaround must be applied.
8581 */
8582 if (shader->is_monolithic) {
8583 /* Monolithic shader (compiled as a whole, has many variants,
8584 * may take a long time to compile).
8585 */
8586 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
8587 if (r)
8588 return r;
8589 } else {
8590 /* The shader consists of 2-3 parts:
8591 *
8592 * - the middle part is the user shader, it has 1 variant only
8593 * and it was compiled during the creation of the shader
8594 * selector
8595 * - the prolog part is inserted at the beginning
8596 * - the epilog part is inserted at the end
8597 *
8598 * The prolog and epilog have many (but simple) variants.
8599 */
8600
8601 /* Copy the compiled TGSI shader data over. */
8602 shader->is_binary_shared = true;
8603 shader->binary = mainp->binary;
8604 shader->config = mainp->config;
8605 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8606 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8607 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8608 memcpy(shader->info.vs_output_param_offset,
8609 mainp->info.vs_output_param_offset,
8610 sizeof(mainp->info.vs_output_param_offset));
8611 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8612 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8613 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8614
8615 /* Select prologs and/or epilogs. */
8616 switch (sel->type) {
8617 case PIPE_SHADER_VERTEX:
8618 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
8619 return -1;
8620 break;
8621 case PIPE_SHADER_TESS_CTRL:
8622 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
8623 return -1;
8624 break;
8625 case PIPE_SHADER_TESS_EVAL:
8626 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
8627 return -1;
8628 break;
8629 case PIPE_SHADER_GEOMETRY:
8630 if (!si_shader_select_gs_parts(sscreen, tm, shader, debug))
8631 return -1;
8632 break;
8633 case PIPE_SHADER_FRAGMENT:
8634 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
8635 return -1;
8636
8637 /* Make sure we have at least as many VGPRs as there
8638 * are allocated inputs.
8639 */
8640 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8641 shader->info.num_input_vgprs);
8642 break;
8643 }
8644
8645 /* Update SGPR and VGPR counts. */
8646 if (shader->prolog) {
8647 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8648 shader->prolog->config.num_sgprs);
8649 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8650 shader->prolog->config.num_vgprs);
8651 }
8652 if (shader->epilog) {
8653 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8654 shader->epilog->config.num_sgprs);
8655 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8656 shader->epilog->config.num_vgprs);
8657 }
8658 }
8659
8660 si_fix_resource_usage(sscreen, shader);
8661 si_shader_dump(sscreen, shader, debug, sel->info.processor,
8662 stderr, true);
8663
8664 /* Upload. */
8665 r = si_shader_binary_upload(sscreen, shader);
8666 if (r) {
8667 fprintf(stderr, "LLVM failed to upload shader\n");
8668 return r;
8669 }
8670
8671 return 0;
8672 }
8673
8674 void si_shader_destroy(struct si_shader *shader)
8675 {
8676 if (shader->scratch_bo)
8677 r600_resource_reference(&shader->scratch_bo, NULL);
8678
8679 r600_resource_reference(&shader->bo, NULL);
8680
8681 if (!shader->is_binary_shared)
8682 radeon_shader_binary_clean(&shader->binary);
8683
8684 free(shader->shader_log);
8685 }