ac/nir, radv, radeonsi: Switch to using ac_shader_args

[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c

/*
 * Copyright 2012 Advanced Micro Devices, Inc.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * on the rights to use, copy, modify, merge, publish, distribute, sub
 * license, and/or sell copies of the Software, and to permit persons to whom
 * the Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
 * USE OR OTHER DEALINGS IN THE SOFTWARE.
 */

#include <llvm/Config/llvm-config.h>

#include "util/u_memory.h"
#include "util/u_string.h"
#include "tgsi/tgsi_build.h"
#include "tgsi/tgsi_strings.h"
#include "tgsi/tgsi_util.h"
#include "tgsi/tgsi_dump.h"
#include "tgsi/tgsi_from_mesa.h"

#include "ac_binary.h"
#include "ac_exp_param.h"
#include "ac_shader_util.h"
#include "ac_rtld.h"
#include "ac_llvm_util.h"
#include "si_shader_internal.h"
#include "si_pipe.h"
#include "sid.h"

#include "compiler/nir/nir.h"
#include "compiler/nir/nir_serialize.h"

static const char scratch_rsrc_dword0_symbol[] =
        "SCRATCH_RSRC_DWORD0";

static const char scratch_rsrc_dword1_symbol[] =
        "SCRATCH_RSRC_DWORD1";

static void si_init_shader_ctx(struct si_shader_context *ctx,
                               struct si_screen *sscreen,
                               struct ac_llvm_compiler *compiler,
                               unsigned wave_size,
                               bool nir);

static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
                                 struct lp_build_tgsi_context *bld_base,
                                 struct lp_build_emit_data *emit_data);

static void si_dump_shader_key(const struct si_shader *shader, FILE *f);

static void si_build_vs_prolog_function(struct si_shader_context *ctx,
                                        union si_shader_part_key *key);
static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
                                         union si_shader_part_key *key);
static void si_build_ps_prolog_function(struct si_shader_context *ctx,
                                        union si_shader_part_key *key);
static void si_build_ps_epilog_function(struct si_shader_context *ctx,
                                        union si_shader_part_key *key);
static void si_fix_resource_usage(struct si_screen *sscreen,
                                  struct si_shader *shader);

/* Ideally pass the sample mask input to the PS epilog as v14, which
 * is its usual location, so that the shader doesn't have to add v_mov.
 */
#define PS_EPILOG_SAMPLEMASK_MIN_LOC 14

static bool llvm_type_is_64bit(struct si_shader_context *ctx,
                               LLVMTypeRef type)
{
        if (type == ctx->ac.i64 || type == ctx->ac.f64)
                return true;

        return false;
}

/** Whether the shader runs as a combination of multiple API shaders */
static bool is_multi_part_shader(struct si_shader_context *ctx)
{
        if (ctx->screen->info.chip_class <= GFX8)
                return false;

        return ctx->shader->key.as_ls ||
               ctx->shader->key.as_es ||
               ctx->type == PIPE_SHADER_TESS_CTRL ||
               ctx->type == PIPE_SHADER_GEOMETRY;
}

/** Whether the shader runs on a merged HW stage (LSHS or ESGS) */
static bool is_merged_shader(struct si_shader_context *ctx)
{
        return ctx->shader->key.as_ngg || is_multi_part_shader(ctx);
}

/**
 * Returns a unique index for a per-patch semantic name and index. The index
 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
 * can be calculated.
 */
unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
{
        switch (semantic_name) {
        case TGSI_SEMANTIC_TESSOUTER:
                return 0;
        case TGSI_SEMANTIC_TESSINNER:
                return 1;
        case TGSI_SEMANTIC_PATCH:
                assert(index < 30);
                return 2 + index;

        default:
                assert(!"invalid semantic name");
                return 0;
        }
}

/**
 * Returns a unique index for a semantic name and index. The index must be
 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
 * calculated.
 */
unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index,
                                       unsigned is_varying)
{
        switch (semantic_name) {
        case TGSI_SEMANTIC_POSITION:
                return 0;
        case TGSI_SEMANTIC_GENERIC:
                /* Since some shader stages use the the highest used IO index
                 * to determine the size to allocate for inputs/outputs
                 * (in LDS, tess and GS rings). GENERIC should be placed right
                 * after POSITION to make that size as small as possible.
                 */
                if (index < SI_MAX_IO_GENERIC)
                        return 1 + index;

                assert(!"invalid generic index");
                return 0;
        case TGSI_SEMANTIC_FOG:
                return SI_MAX_IO_GENERIC + 1;
        case TGSI_SEMANTIC_COLOR:
                assert(index < 2);
                return SI_MAX_IO_GENERIC + 2 + index;
        case TGSI_SEMANTIC_BCOLOR:
                assert(index < 2);
                /* If it's a varying, COLOR and BCOLOR alias. */
                if (is_varying)
                        return SI_MAX_IO_GENERIC + 2 + index;
                else
                        return SI_MAX_IO_GENERIC + 4 + index;
        case TGSI_SEMANTIC_TEXCOORD:
                assert(index < 8);
                return SI_MAX_IO_GENERIC + 6 + index;

        /* These are rarely used between LS and HS or ES and GS. */
        case TGSI_SEMANTIC_CLIPDIST:
                assert(index < 2);
                return SI_MAX_IO_GENERIC + 6 + 8 + index;
        case TGSI_SEMANTIC_CLIPVERTEX:
                return SI_MAX_IO_GENERIC + 6 + 8 + 2;
        case TGSI_SEMANTIC_PSIZE:
                return SI_MAX_IO_GENERIC + 6 + 8 + 3;

        /* These can't be written by LS, HS, and ES. */
        case TGSI_SEMANTIC_LAYER:
                return SI_MAX_IO_GENERIC + 6 + 8 + 4;
        case TGSI_SEMANTIC_VIEWPORT_INDEX:
                return SI_MAX_IO_GENERIC + 6 + 8 + 5;
        case TGSI_SEMANTIC_PRIMID:
                STATIC_ASSERT(SI_MAX_IO_GENERIC + 6 + 8 + 6 <= 63);
                return SI_MAX_IO_GENERIC + 6 + 8 + 6;
        default:
                fprintf(stderr, "invalid semantic name = %u\n", semantic_name);
                assert(!"invalid semantic name");
                return 0;
        }
}

/**
 * Get the value of a shader input parameter and extract a bitfield.
 */
static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
                                      LLVMValueRef value, unsigned rshift,
                                      unsigned bitwidth)
{
        if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
                value = ac_to_integer(&ctx->ac, value);

        if (rshift)
                value = LLVMBuildLShr(ctx->ac.builder, value,
                                      LLVMConstInt(ctx->i32, rshift, 0), "");

        if (rshift + bitwidth < 32) {
                unsigned mask = (1 << bitwidth) - 1;
                value = LLVMBuildAnd(ctx->ac.builder, value,
                                     LLVMConstInt(ctx->i32, mask, 0), "");
        }

        return value;
}

LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
                             struct ac_arg param, unsigned rshift,
                             unsigned bitwidth)
{
        LLVMValueRef value = ac_get_arg(&ctx->ac, param);

        return unpack_llvm_param(ctx, value, rshift, bitwidth);
}

static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
{
        switch (ctx->type) {
        case PIPE_SHADER_TESS_CTRL:
                return si_unpack_param(ctx, ctx->args.tcs_rel_ids, 0, 8);

        case PIPE_SHADER_TESS_EVAL:
                return ac_get_arg(&ctx->ac, ctx->tes_rel_patch_id);

        default:
                assert(0);
                return NULL;
        }
}

/* Tessellation shaders pass outputs to the next shader using LDS.
 *
 * LS outputs = TCS inputs
 * TCS outputs = TES inputs
 *
 * The LDS layout is:
 * - TCS inputs for patch 0
 * - TCS inputs for patch 1
 * - TCS inputs for patch 2             = get_tcs_in_current_patch_offset (if RelPatchID==2)
 * - ...
 * - TCS outputs for patch 0            = get_tcs_out_patch0_offset
 * - Per-patch TCS outputs for patch 0  = get_tcs_out_patch0_patch_data_offset
 * - TCS outputs for patch 1
 * - Per-patch TCS outputs for patch 1
 * - TCS outputs for patch 2            = get_tcs_out_current_patch_offset (if RelPatchID==2)
 * - Per-patch TCS outputs for patch 2  = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
 * - ...
 *
 * All three shaders VS(LS), TCS, TES share the same LDS space.
 */

static LLVMValueRef
get_tcs_in_patch_stride(struct si_shader_context *ctx)
{
        return si_unpack_param(ctx, ctx->vs_state_bits, 8, 13);
}

static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
{
        assert(ctx->type == PIPE_SHADER_TESS_CTRL);

        if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
                return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;

        return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
}

static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
{
        unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);

        return LLVMConstInt(ctx->i32, stride, 0);
}

static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
{
        if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
                return si_unpack_param(ctx, ctx->tcs_out_lds_layout, 0, 13);

        const struct tgsi_shader_info *info = &ctx->shader->selector->info;
        unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
        unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
        unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
        unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
                                   num_patch_outputs * 4;
        return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
}

static LLVMValueRef
get_tcs_out_patch0_offset(struct si_shader_context *ctx)
{
        return LLVMBuildMul(ctx->ac.builder,
                            si_unpack_param(ctx, ctx->tcs_out_lds_offsets, 0, 16),
                            LLVMConstInt(ctx->i32, 4, 0), "");
}

static LLVMValueRef
get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
{
        return LLVMBuildMul(ctx->ac.builder,
                            si_unpack_param(ctx, ctx->tcs_out_lds_offsets, 16, 16),
                            LLVMConstInt(ctx->i32, 4, 0), "");
}

static LLVMValueRef
get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
{
        LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
        LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);

        return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
}

static LLVMValueRef
get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
{
        LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
        LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
        LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);

        return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_offset);
}

static LLVMValueRef
get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
{
        LLVMValueRef patch0_patch_data_offset =
                get_tcs_out_patch0_patch_data_offset(ctx);
        LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
        LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);

        return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);
}

static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
{
        unsigned tcs_out_vertices =
                ctx->shader->selector ?
                ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;

        /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
        if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
                return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);

        return si_unpack_param(ctx, ctx->tcs_offchip_layout, 6, 6);
}

static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
{
        unsigned stride;

        switch (ctx->type) {
        case PIPE_SHADER_VERTEX:
                stride = ctx->shader->selector->lshs_vertex_stride / 4;
                return LLVMConstInt(ctx->i32, stride, 0);

        case PIPE_SHADER_TESS_CTRL:
                if (ctx->screen->info.chip_class >= GFX9 &&
                    ctx->shader->is_monolithic) {
                        stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4;
                        return LLVMConstInt(ctx->i32, stride, 0);
                }
                return si_unpack_param(ctx, ctx->vs_state_bits, 24, 8);

        default:
                assert(0);
                return NULL;
        }
}

static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
                                 LLVMValueRef i32, unsigned index)
{
        assert(index <= 1);

        if (index == 1)
                return LLVMBuildAShr(ctx->ac.builder, i32,
                                     LLVMConstInt(ctx->i32, 16, 0), "");

        return LLVMBuildSExt(ctx->ac.builder,
                             LLVMBuildTrunc(ctx->ac.builder, i32,
                                            ctx->ac.i16, ""),
                             ctx->i32, "");
}

void si_llvm_load_input_vs(
        struct si_shader_context *ctx,
        unsigned input_index,
        LLVMValueRef out[4])
{
        const struct tgsi_shader_info *info = &ctx->shader->selector->info;
        unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];

        if (vs_blit_property) {
                LLVMValueRef vertex_id = ctx->abi.vertex_id;
                LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
                                                    LLVMIntULE, vertex_id,
                                                    ctx->i32_1, "");
                /* Use LLVMIntNE, because we have 3 vertices and only
                 * the middle one should use y2.
                 */
                LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
                                                    LLVMIntNE, vertex_id,
                                                    ctx->i32_1, "");

                unsigned param_vs_blit_inputs = ctx->vs_blit_inputs.arg_index;
                if (input_index == 0) {
                        /* Position: */
                        LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
                                                         param_vs_blit_inputs);
                        LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
                                                         param_vs_blit_inputs + 1);

                        LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
                        LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
                        LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
                        LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);

                        LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
                                                         x1, x2, "");
                        LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
                                                         y1, y2, "");

                        out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
                        out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
                        out[2] = LLVMGetParam(ctx->main_fn,
                                              param_vs_blit_inputs + 2);
                        out[3] = ctx->ac.f32_1;
                        return;
                }

                /* Color or texture coordinates: */
                assert(input_index == 1);

                if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
                        for (int i = 0; i < 4; i++) {
                                out[i] = LLVMGetParam(ctx->main_fn,
                                                      param_vs_blit_inputs + 3 + i);
                        }
                } else {
                        assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
                        LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
                                                       param_vs_blit_inputs + 3);
                        LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
                                                       param_vs_blit_inputs + 4);
                        LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
                                                       param_vs_blit_inputs + 5);
                        LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
                                                       param_vs_blit_inputs + 6);

                        out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
                                                 x1, x2, "");
                        out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
                                                 y1, y2, "");
                        out[2] = LLVMGetParam(ctx->main_fn,
                                              param_vs_blit_inputs + 7);
                        out[3] = LLVMGetParam(ctx->main_fn,
                                              param_vs_blit_inputs + 8);
                }
                return;
        }

        union si_vs_fix_fetch fix_fetch;
        LLVMValueRef t_list_ptr;
        LLVMValueRef t_offset;
        LLVMValueRef t_list;
        LLVMValueRef vertex_index;
        LLVMValueRef tmp;

        /* Load the T list */
        t_list_ptr = ac_get_arg(&ctx->ac, ctx->vertex_buffers);

        t_offset = LLVMConstInt(ctx->i32, input_index, 0);

        t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);

        vertex_index = LLVMGetParam(ctx->main_fn,
                                    ctx->vertex_index0.arg_index +
                                    input_index);

        /* Use the open-coded implementation for all loads of doubles and
         * of dword-sized data that needs fixups. We need to insert conversion
         * code anyway, and the amd/common code does it for us.
         *
         * Note: On LLVM <= 8, we can only open-code formats with
         * channel size >= 4 bytes.
         */
        bool opencode = ctx->shader->key.mono.vs_fetch_opencode & (1 << input_index);
        fix_fetch.bits = ctx->shader->key.mono.vs_fix_fetch[input_index].bits;
        if (opencode ||
            (fix_fetch.u.log_size == 3 && fix_fetch.u.format == AC_FETCH_FORMAT_FLOAT) ||
            (fix_fetch.u.log_size == 2)) {
                tmp = ac_build_opencoded_load_format(
                                &ctx->ac, fix_fetch.u.log_size, fix_fetch.u.num_channels_m1 + 1,
                                fix_fetch.u.format, fix_fetch.u.reverse, !opencode,
                                t_list, vertex_index, ctx->ac.i32_0, ctx->ac.i32_0, 0, true);
                for (unsigned i = 0; i < 4; ++i)
                        out[i] = LLVMBuildExtractElement(ctx->ac.builder, tmp, LLVMConstInt(ctx->i32, i, false), "");
                return;
        }

        /* Do multiple loads for special formats. */
        unsigned required_channels = util_last_bit(info->input_usage_mask[input_index]);
        LLVMValueRef fetches[4];
        unsigned num_fetches;
        unsigned fetch_stride;
        unsigned channels_per_fetch;

        if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2) {
                num_fetches = MIN2(required_channels, 3);
                fetch_stride = 1 << fix_fetch.u.log_size;
                channels_per_fetch = 1;
        } else {
                num_fetches = 1;
                fetch_stride = 0;
                channels_per_fetch = required_channels;
        }

        for (unsigned i = 0; i < num_fetches; ++i) {
                LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
                fetches[i] = ac_build_buffer_load_format(&ctx->ac, t_list, vertex_index, voffset,
                                                         channels_per_fetch, 0, true);
        }

        if (num_fetches == 1 && channels_per_fetch > 1) {
                LLVMValueRef fetch = fetches[0];
                for (unsigned i = 0; i < channels_per_fetch; ++i) {
                        tmp = LLVMConstInt(ctx->i32, i, false);
                        fetches[i] = LLVMBuildExtractElement(
                                ctx->ac.builder, fetch, tmp, "");
                }
                num_fetches = channels_per_fetch;
                channels_per_fetch = 1;
        }

        for (unsigned i = num_fetches; i < 4; ++i)
                fetches[i] = LLVMGetUndef(ctx->f32);

        if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2 &&
            required_channels == 4) {
                if (fix_fetch.u.format == AC_FETCH_FORMAT_UINT || fix_fetch.u.format == AC_FETCH_FORMAT_SINT)
                        fetches[3] = ctx->ac.i32_1;
                else
                        fetches[3] = ctx->ac.f32_1;
        } else if (fix_fetch.u.log_size == 3 &&
                   (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ||
                    fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED ||
                    fix_fetch.u.format == AC_FETCH_FORMAT_SINT) &&
                   required_channels == 4) {
                /* For 2_10_10_10, the hardware returns an unsigned value;
                 * convert it to a signed one.
                 */
                LLVMValueRef tmp = fetches[3];
                LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);

                /* First, recover the sign-extended signed integer value. */
                if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED)
                        tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
                else
                        tmp = ac_to_integer(&ctx->ac, tmp);

                /* For the integer-like cases, do a natural sign extension.
                 *
                 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
                 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
                 * exponent.
                 */
                tmp = LLVMBuildShl(ctx->ac.builder, tmp,
                                   fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ?
                                   LLVMConstInt(ctx->i32, 7, 0) : c30, "");
                tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");

                /* Convert back to the right type. */
                if (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM) {
                        LLVMValueRef clamp;
                        LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
                        tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
                        clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
                        tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
                } else if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED) {
                        tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
                }

                fetches[3] = tmp;
        }

        for (unsigned i = 0; i < 4; ++i)
                out[i] = ac_to_float(&ctx->ac, fetches[i]);
}

static void declare_input_vs(
        struct si_shader_context *ctx,
        unsigned input_index,
        const struct tgsi_full_declaration *decl,
        LLVMValueRef out[4])
{
        si_llvm_load_input_vs(ctx, input_index, out);
}

LLVMValueRef si_get_primitive_id(struct si_shader_context *ctx,
                                 unsigned swizzle)
{
        if (swizzle > 0)
                return ctx->i32_0;

        switch (ctx->type) {
        case PIPE_SHADER_VERTEX:
                return ac_get_arg(&ctx->ac, ctx->vs_prim_id);
        case PIPE_SHADER_TESS_CTRL:
                return ac_get_arg(&ctx->ac, ctx->args.tcs_patch_id);
        case PIPE_SHADER_TESS_EVAL:
                return ac_get_arg(&ctx->ac, ctx->args.tes_patch_id);
        case PIPE_SHADER_GEOMETRY:
                return ac_get_arg(&ctx->ac, ctx->args.gs_prim_id);
        default:
                assert(0);
                return ctx->i32_0;
        }
}

/**
 * Return the value of tgsi_ind_register for indexing.
 * This is the indirect index with the constant offset added to it.
 */
LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
                                   const struct tgsi_ind_register *ind,
                                   unsigned addr_mul,
                                   int rel_index)
{
        LLVMValueRef result;

        if (ind->File == TGSI_FILE_ADDRESS) {
                result = ctx->addrs[ind->Index][ind->Swizzle];
                result = LLVMBuildLoad(ctx->ac.builder, result, "");
        } else {
                struct tgsi_full_src_register src = {};

                src.Register.File = ind->File;
                src.Register.Index = ind->Index;

                /* Set the second index to 0 for constants. */
                if (ind->File == TGSI_FILE_CONSTANT)
                        src.Register.Dimension = 1;

                result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
                                                                   TGSI_TYPE_SIGNED,
                                                                   ind->Swizzle);
                result = ac_to_integer(&ctx->ac, result);
        }

        return ac_build_imad(&ctx->ac, result, LLVMConstInt(ctx->i32, addr_mul, 0),
                             LLVMConstInt(ctx->i32, rel_index, 0));
}

/**
 * Like si_get_indirect_index, but restricts the return value to a (possibly
 * undefined) value inside [0..num).
 */
LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
                                           const struct tgsi_ind_register *ind,
                                           int rel_index, unsigned num)
{
        LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);

        return si_llvm_bound_index(ctx, result, num);
}

static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
                                                        LLVMValueRef vertex_dw_stride,
                                                        LLVMValueRef base_addr,
                                                        LLVMValueRef vertex_index,
                                                        LLVMValueRef param_index,
                                                        unsigned input_index,
                                                        ubyte *name,
                                                        ubyte *index,
                                                        bool is_patch)
{
        if (vertex_dw_stride) {
                base_addr = ac_build_imad(&ctx->ac, vertex_index,
                                          vertex_dw_stride, base_addr);
        }

        if (param_index) {
                base_addr = ac_build_imad(&ctx->ac, param_index,
                                          LLVMConstInt(ctx->i32, 4, 0), base_addr);
        }

        int param = is_patch ?
                si_shader_io_get_unique_index_patch(name[input_index],
                                                    index[input_index]) :
                si_shader_io_get_unique_index(name[input_index],
                                              index[input_index], false);

        /* Add the base address of the element. */
        return LLVMBuildAdd(ctx->ac.builder, base_addr,
                            LLVMConstInt(ctx->i32, param * 4, 0), "");
}

/**
 * Calculate a dword address given an input or output register and a stride.
 */
static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
                                   const struct tgsi_full_dst_register *dst,
                                   const struct tgsi_full_src_register *src,
                                   LLVMValueRef vertex_dw_stride,
                                   LLVMValueRef base_addr)
{
        struct tgsi_shader_info *info = &ctx->shader->selector->info;
        ubyte *name, *index, *array_first;
        int input_index;
        struct tgsi_full_dst_register reg;
        LLVMValueRef vertex_index = NULL;
        LLVMValueRef ind_index = NULL;

        /* Set the register description. The address computation is the same
         * for sources and destinations. */
        if (src) {
                reg.Register.File = src->Register.File;
                reg.Register.Index = src->Register.Index;
                reg.Register.Indirect = src->Register.Indirect;
                reg.Register.Dimension = src->Register.Dimension;
                reg.Indirect = src->Indirect;
                reg.Dimension = src->Dimension;
                reg.DimIndirect = src->DimIndirect;
        } else
                reg = *dst;

        /* If the register is 2-dimensional (e.g. an array of vertices
         * in a primitive), calculate the base address of the vertex. */
        if (reg.Register.Dimension) {
                if (reg.Dimension.Indirect)
                        vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
                                                      1, reg.Dimension.Index);
                else
                        vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
        }

        /* Get information about the register. */
        if (reg.Register.File == TGSI_FILE_INPUT) {
                name = info->input_semantic_name;
                index = info->input_semantic_index;
                array_first = info->input_array_first;
        } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
                name = info->output_semantic_name;
                index = info->output_semantic_index;
                array_first = info->output_array_first;
        } else {
                assert(0);
                return NULL;
        }

        if (reg.Register.Indirect) {
                /* Add the relative address of the element. */
                if (reg.Indirect.ArrayID)
                        input_index = array_first[reg.Indirect.ArrayID];
                else
                        input_index = reg.Register.Index;

                ind_index = si_get_indirect_index(ctx, &reg.Indirect,
                                                  1, reg.Register.Index - input_index);
        } else {
                input_index = reg.Register.Index;
        }

        return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
                                                   base_addr, vertex_index,
                                                   ind_index, input_index,
                                                   name, index,
                                                   !reg.Register.Dimension);
}

/* The offchip buffer layout for TCS->TES is
 *
 * - attribute 0 of patch 0 vertex 0
 * - attribute 0 of patch 0 vertex 1
 * - attribute 0 of patch 0 vertex 2
 *   ...
 * - attribute 0 of patch 1 vertex 0
 * - attribute 0 of patch 1 vertex 1
 *   ...
 * - attribute 1 of patch 0 vertex 0
 * - attribute 1 of patch 0 vertex 1
 *   ...
 * - per patch attribute 0 of patch 0
 * - per patch attribute 0 of patch 1
 *   ...
 *
 * Note that every attribute has 4 components.
 */
static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
                                               LLVMValueRef rel_patch_id,
                                               LLVMValueRef vertex_index,
                                               LLVMValueRef param_index)
{
        LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
        LLVMValueRef param_stride, constant16;

        vertices_per_patch = get_num_tcs_out_vertices(ctx);
        num_patches = si_unpack_param(ctx, ctx->tcs_offchip_layout, 0, 6);
        total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
                                      num_patches, "");

        constant16 = LLVMConstInt(ctx->i32, 16, 0);
        if (vertex_index) {
                base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
                                          vertices_per_patch, vertex_index);
                param_stride = total_vertices;
        } else {
                base_addr = rel_patch_id;
                param_stride = num_patches;
        }

        base_addr = ac_build_imad(&ctx->ac, param_index, param_stride, base_addr);
        base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");

        if (!vertex_index) {
                LLVMValueRef patch_data_offset =
                           si_unpack_param(ctx, ctx->tcs_offchip_layout, 12, 20);

                base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
                                         patch_data_offset, "");
        }
        return base_addr;
}

/* This is a generic helper that can be shared by the NIR and TGSI backends */
static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
                                        struct si_shader_context *ctx,
                                        LLVMValueRef vertex_index,
                                        LLVMValueRef param_index,
                                        unsigned param_base,
                                        ubyte *name,
                                        ubyte *index,
                                        bool is_patch)
{
        unsigned param_index_base;

        param_index_base = is_patch ?
                si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
                si_shader_io_get_unique_index(name[param_base], index[param_base], false);

        if (param_index) {
                param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
                                           LLVMConstInt(ctx->i32, param_index_base, 0),
                                           "");
        } else {
                param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
        }

        return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
                                          vertex_index, param_index);
}

static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
                                       struct si_shader_context *ctx,
                                       const struct tgsi_full_dst_register *dst,
                                       const struct tgsi_full_src_register *src)
{
        struct tgsi_shader_info *info = &ctx->shader->selector->info;
        ubyte *name, *index, *array_first;
        struct tgsi_full_src_register reg;
        LLVMValueRef vertex_index = NULL;
        LLVMValueRef param_index = NULL;
        unsigned param_base;

        reg = src ? *src : tgsi_full_src_register_from_dst(dst);

        if (reg.Register.Dimension) {

                if (reg.Dimension.Indirect)
                        vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
                                                             1, reg.Dimension.Index);
                else
                        vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
        }

        /* Get information about the register. */
        if (reg.Register.File == TGSI_FILE_INPUT) {
                name = info->input_semantic_name;
                index = info->input_semantic_index;
                array_first = info->input_array_first;
        } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
                name = info->output_semantic_name;
                index = info->output_semantic_index;
                array_first = info->output_array_first;
        } else {
                assert(0);
                return NULL;
        }

        if (reg.Register.Indirect) {
                if (reg.Indirect.ArrayID)
                        param_base = array_first[reg.Indirect.ArrayID];
                else
                        param_base = reg.Register.Index;

                param_index = si_get_indirect_index(ctx, &reg.Indirect,
                                                    1, reg.Register.Index - param_base);

        } else {
                param_base = reg.Register.Index;
        }

        return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
                                                               param_index, param_base,
                                                               name, index, !reg.Register.Dimension);
}

static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
                                LLVMTypeRef type, unsigned swizzle,
                                LLVMValueRef buffer, LLVMValueRef offset,
                                LLVMValueRef base, bool can_speculate)
{
        struct si_shader_context *ctx = si_shader_context(bld_base);
        LLVMValueRef value, value2;
        LLVMTypeRef vec_type = LLVMVectorType(type, 4);

        if (swizzle == ~0) {
                value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
                                             0, ac_glc, can_speculate, false);

                return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
        }

        if (!llvm_type_is_64bit(ctx, type)) {
                value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
                                             0, ac_glc, can_speculate, false);

                value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
                return LLVMBuildExtractElement(ctx->ac.builder, value,
                                    LLVMConstInt(ctx->i32, swizzle, 0), "");
        }

        value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
                                  swizzle * 4, ac_glc, can_speculate, false);

        value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
                                   swizzle * 4 + 4, ac_glc, can_speculate, false);

        return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
}

/**
 * Load from LSHS LDS storage.
 *
 * \param type          output value type
 * \param swizzle       offset (typically 0..3); it can be ~0, which loads a vec4
 * \param dw_addr       address in dwords
 */
static LLVMValueRef lshs_lds_load(struct lp_build_tgsi_context *bld_base,
                             LLVMTypeRef type, unsigned swizzle,
                             LLVMValueRef dw_addr)
{
        struct si_shader_context *ctx = si_shader_context(bld_base);
        LLVMValueRef value;

        if (swizzle == ~0) {
                LLVMValueRef values[TGSI_NUM_CHANNELS];

                for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
                        values[chan] = lshs_lds_load(bld_base, type, chan, dw_addr);

                return ac_build_gather_values(&ctx->ac, values,
                                              TGSI_NUM_CHANNELS);
        }

        /* Split 64-bit loads. */
        if (llvm_type_is_64bit(ctx, type)) {
                LLVMValueRef lo, hi;

                lo = lshs_lds_load(bld_base, ctx->i32, swizzle, dw_addr);
                hi = lshs_lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
                return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
        }

        dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
                               LLVMConstInt(ctx->i32, swizzle, 0), "");

        value = ac_lds_load(&ctx->ac, dw_addr);

        return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
}

/**
 * Store to LSHS LDS storage.
 *
 * \param swizzle       offset (typically 0..3)
 * \param dw_addr       address in dwords
 * \param value         value to store
 */
static void lshs_lds_store(struct si_shader_context *ctx,
                      unsigned dw_offset_imm, LLVMValueRef dw_addr,
                      LLVMValueRef value)
{
        dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
                               LLVMConstInt(ctx->i32, dw_offset_imm, 0), "");

        ac_lds_store(&ctx->ac, dw_addr, value);
}

enum si_tess_ring {
        TCS_FACTOR_RING,
        TESS_OFFCHIP_RING_TCS,
        TESS_OFFCHIP_RING_TES,
};

static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
                                             enum si_tess_ring ring)
{
        LLVMBuilderRef builder = ctx->ac.builder;
        LLVMValueRef addr = ac_get_arg(&ctx->ac,
                                       ring == TESS_OFFCHIP_RING_TES ?
                                       ctx->tes_offchip_addr :
                                       ctx->tcs_out_lds_layout);

        /* TCS only receives high 13 bits of the address. */
        if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
                addr = LLVMBuildAnd(builder, addr,
                                    LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
        }

        if (ring == TCS_FACTOR_RING) {
                unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
                addr = LLVMBuildAdd(builder, addr,
                                    LLVMConstInt(ctx->i32, tf_offset, 0), "");
        }

        uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
                         S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
                         S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);

        if (ctx->screen->info.chip_class >= GFX10)
                rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
                         S_008F0C_OOB_SELECT(3) |
                         S_008F0C_RESOURCE_LEVEL(1);
        else
                rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);

        LLVMValueRef desc[4];
        desc[0] = addr;
        desc[1] = LLVMConstInt(ctx->i32,
                               S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
        desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
        desc[3] = LLVMConstInt(ctx->i32, rsrc3, false);

        return ac_build_gather_values(&ctx->ac, desc, 4);
}

static LLVMValueRef fetch_input_tcs(
        struct lp_build_tgsi_context *bld_base,
        const struct tgsi_full_src_register *reg,
        enum tgsi_opcode_type type, unsigned swizzle_in)
{
        struct si_shader_context *ctx = si_shader_context(bld_base);
        LLVMValueRef dw_addr, stride;
        unsigned swizzle = swizzle_in & 0xffff;
        stride = get_tcs_in_vertex_dw_stride(ctx);
        dw_addr = get_tcs_in_current_patch_offset(ctx);
        dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);

        return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
}

static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
                                             LLVMTypeRef type,
                                             LLVMValueRef vertex_index,
                                             LLVMValueRef param_index,
                                             unsigned const_index,
                                             unsigned location,
                                             unsigned driver_location,
                                             unsigned component,
                                             unsigned num_components,
                                             bool is_patch,
                                             bool is_compact,
                                             bool load_input)
{
        struct si_shader_context *ctx = si_shader_context_from_abi(abi);
        struct tgsi_shader_info *info = &ctx->shader->selector->info;
        struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
        LLVMValueRef dw_addr, stride;

        driver_location = driver_location / 4;

        if (load_input) {
                stride = get_tcs_in_vertex_dw_stride(ctx);
                dw_addr = get_tcs_in_current_patch_offset(ctx);
        } else {
                if (is_patch) {
                        stride = NULL;
                        dw_addr = get_tcs_out_current_patch_data_offset(ctx);
                } else {
                        stride = get_tcs_out_vertex_dw_stride(ctx);
                        dw_addr = get_tcs_out_current_patch_offset(ctx);
                }
        }

        if (!param_index) {
                param_index = LLVMConstInt(ctx->i32, const_index, 0);
        }

        ubyte *names;
        ubyte *indices;
        if (load_input) {
                names = info->input_semantic_name;
                indices = info->input_semantic_index;
        } else {
                names = info->output_semantic_name;
                indices = info->output_semantic_index;
        }

        dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
                                                      vertex_index, param_index,
                                                      driver_location,
                                                      names, indices,
                                                      is_patch);

        LLVMValueRef value[4];
        for (unsigned i = 0; i < num_components; i++) {
                unsigned offset = i;
                if (llvm_type_is_64bit(ctx, type))
                        offset *= 2;

                offset += component;
                value[i + component] = lshs_lds_load(bld_base, type, offset, dw_addr);
        }

        return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
}

static LLVMValueRef fetch_output_tcs(
                struct lp_build_tgsi_context *bld_base,
                const struct tgsi_full_src_register *reg,
                enum tgsi_opcode_type type, unsigned swizzle_in)
{
        struct si_shader_context *ctx = si_shader_context(bld_base);
        LLVMValueRef dw_addr, stride;
        unsigned swizzle = (swizzle_in & 0xffff);

        if (reg->Register.Dimension) {
                stride = get_tcs_out_vertex_dw_stride(ctx);
                dw_addr = get_tcs_out_current_patch_offset(ctx);
                dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
        } else {
                dw_addr = get_tcs_out_current_patch_data_offset(ctx);
                dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
        }

        return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
}

static LLVMValueRef fetch_input_tes(
        struct lp_build_tgsi_context *bld_base,
        const struct tgsi_full_src_register *reg,
        enum tgsi_opcode_type type, unsigned swizzle_in)
{
        struct si_shader_context *ctx = si_shader_context(bld_base);
        LLVMValueRef base, addr;
        unsigned swizzle = (swizzle_in & 0xffff);

        base = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);
        addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);

        return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
                           ctx->tess_offchip_ring, base, addr, true);
}

LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
                                   LLVMTypeRef type,
                                   LLVMValueRef vertex_index,
                                   LLVMValueRef param_index,
                                   unsigned const_index,
                                   unsigned location,
                                   unsigned driver_location,
                                   unsigned component,
                                   unsigned num_components,
                                   bool is_patch,
                                   bool is_compact,
                                   bool load_input)
{
        struct si_shader_context *ctx = si_shader_context_from_abi(abi);
        struct tgsi_shader_info *info = &ctx->shader->selector->info;
        LLVMValueRef base, addr;

        driver_location = driver_location / 4;

        base = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);

        if (!param_index) {
                param_index = LLVMConstInt(ctx->i32, const_index, 0);
        }

        addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
                                                               param_index, driver_location,
                                                               info->input_semantic_name,
                                                               info->input_semantic_index,
                                                               is_patch);

        /* TODO: This will generate rather ordinary llvm code, although it
         * should be easy for the optimiser to fix up. In future we might want
         * to refactor buffer_load(), but for now this maximises code sharing
         * between the NIR and TGSI backends.
         */
        LLVMValueRef value[4];
        for (unsigned i = 0; i < num_components; i++) {
                unsigned offset = i;
                if (llvm_type_is_64bit(ctx, type)) {
                        offset *= 2;
                        if (offset == 4) {
                                addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
                                                                                       vertex_index,
                                                                                       param_index,
                                                                                       driver_location + 1,
                                                                                       info->input_semantic_name,
                                                                                       info->input_semantic_index,
                                                                                       is_patch);
                        }

                        offset = offset % 4;
                }

                offset += component;
                value[i + component] = buffer_load(&ctx->bld_base, type, offset,
                                                   ctx->tess_offchip_ring, base, addr, true);
        }

        return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
}

static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
                             const struct tgsi_full_instruction *inst,
                             const struct tgsi_opcode_info *info,
                             unsigned index,
                             LLVMValueRef dst[4])
{
        struct si_shader_context *ctx = si_shader_context(bld_base);
        const struct tgsi_full_dst_register *reg = &inst->Dst[index];
        const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
        unsigned chan_index;
        LLVMValueRef dw_addr, stride;
        LLVMValueRef buffer, base, buf_addr;
        LLVMValueRef values[4];
        bool skip_lds_store;
        bool is_tess_factor = false, is_tess_inner = false;

        /* Only handle per-patch and per-vertex outputs here.
         * Vectors will be lowered to scalars and this function will be called again.
         */
        if (reg->Register.File != TGSI_FILE_OUTPUT ||
            (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
                si_llvm_emit_store(bld_base, inst, info, index, dst);
                return;
        }

        if (reg->Register.Dimension) {
                stride = get_tcs_out_vertex_dw_stride(ctx);
                dw_addr = get_tcs_out_current_patch_offset(ctx);
                dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
                skip_lds_store = !sh_info->reads_pervertex_outputs;
        } else {
                dw_addr = get_tcs_out_current_patch_data_offset(ctx);
                dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
                skip_lds_store = !sh_info->reads_perpatch_outputs;

                if (!reg->Register.Indirect) {
                        int name = sh_info->output_semantic_name[reg->Register.Index];

                        /* Always write tess factors into LDS for the TCS epilog. */
                        if (name == TGSI_SEMANTIC_TESSINNER ||
                            name == TGSI_SEMANTIC_TESSOUTER) {
                                /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
                                skip_lds_store = !sh_info->reads_tessfactor_outputs &&
                                                 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
                                is_tess_factor = true;
                                is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
                        }
                }
        }

        buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);

        base = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);
        buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);

        uint32_t writemask = reg->Register.WriteMask;
        while (writemask) {
                chan_index = u_bit_scan(&writemask);
                LLVMValueRef value = dst[chan_index];

                if (inst->Instruction.Saturate)
                        value = ac_build_clamp(&ctx->ac, value);

                /* Skip LDS stores if there is no LDS read of this output. */
                if (!skip_lds_store)
                        lshs_lds_store(ctx, chan_index, dw_addr, value);

                value = ac_to_integer(&ctx->ac, value);
                values[chan_index] = value;

                if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
                        ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
                                                    buf_addr, base,
                                                    4 * chan_index, ac_glc, false);
                }

                /* Write tess factors into VGPRs for the epilog. */
                if (is_tess_factor &&
                    ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
                        if (!is_tess_inner) {
                                LLVMBuildStore(ctx->ac.builder, value, /* outer */
                                               ctx->invoc0_tess_factors[chan_index]);
                        } else if (chan_index < 2) {
                                LLVMBuildStore(ctx->ac.builder, value, /* inner */
                                               ctx->invoc0_tess_factors[4 + chan_index]);
                        }
                }
        }

        if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
                LLVMValueRef value = ac_build_gather_values(&ctx->ac,
                                                            values, 4);
                ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
                                            base, 0, ac_glc, false);
        }
}

static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
                                    const struct nir_variable *var,
                                    LLVMValueRef vertex_index,
                                    LLVMValueRef param_index,
                                    unsigned const_index,
                                    LLVMValueRef src,
                                    unsigned writemask)
{
        struct si_shader_context *ctx = si_shader_context_from_abi(abi);
        struct tgsi_shader_info *info = &ctx->shader->selector->info;
        const unsigned component = var->data.location_frac;
        const bool is_patch = var->data.patch;
        unsigned driver_location = var->data.driver_location;
        LLVMValueRef dw_addr, stride;
        LLVMValueRef buffer, base, addr;
        LLVMValueRef values[8];
        bool skip_lds_store;
        bool is_tess_factor = false, is_tess_inner = false;

        driver_location = driver_location / 4;

        bool is_const = !param_index;
        if (!param_index)
                param_index = LLVMConstInt(ctx->i32, const_index, 0);

        if (!is_patch) {
                stride = get_tcs_out_vertex_dw_stride(ctx);
                dw_addr = get_tcs_out_current_patch_offset(ctx);
                dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
                                                              vertex_index, param_index,
                                                              driver_location,
                                                              info->output_semantic_name,
                                                              info->output_semantic_index,
                                                              is_patch);

                skip_lds_store = !info->reads_pervertex_outputs;
        } else {
                dw_addr = get_tcs_out_current_patch_data_offset(ctx);
                dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
                                                              vertex_index, param_index,
                                                              driver_location,
                                                              info->output_semantic_name,
                                                              info->output_semantic_index,
                                                              is_patch);

                skip_lds_store = !info->reads_perpatch_outputs;

                if (is_const && const_index == 0) {
                        int name = info->output_semantic_name[driver_location];

                        /* Always write tess factors into LDS for the TCS epilog. */
                        if (name == TGSI_SEMANTIC_TESSINNER ||
                            name == TGSI_SEMANTIC_TESSOUTER) {
                                /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
                                skip_lds_store = !info->reads_tessfactor_outputs &&
                                                 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
                                is_tess_factor = true;
                                is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
                        }
                }
        }

        buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);

        base = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);

        addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
                                                               param_index, driver_location,
                                                               info->output_semantic_name,
                                                               info->output_semantic_index,
                                                               is_patch);

        for (unsigned chan = 0; chan < 8; chan++) {
                if (!(writemask & (1 << chan)))
                        continue;
                LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);

                unsigned buffer_store_offset = chan % 4;
                if (chan == 4) {
                        addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
                                                                               vertex_index,
                                                                               param_index,
                                                                               driver_location + 1,
                                                                               info->output_semantic_name,
                                                                               info->output_semantic_index,
                                                                               is_patch);
                }

                /* Skip LDS stores if there is no LDS read of this output. */
                if (!skip_lds_store)
                        lshs_lds_store(ctx, chan, dw_addr, value);

                value = ac_to_integer(&ctx->ac, value);
                values[chan] = value;

                if (writemask != 0xF && !is_tess_factor) {
                        ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
                                                    addr, base,
                                                    4 * buffer_store_offset,
                                                    ac_glc, false);
                }

                /* Write tess factors into VGPRs for the epilog. */
                if (is_tess_factor &&
                    ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
                        if (!is_tess_inner) {
                                LLVMBuildStore(ctx->ac.builder, value, /* outer */
                                               ctx->invoc0_tess_factors[chan]);
                        } else if (chan < 2) {
                                LLVMBuildStore(ctx->ac.builder, value, /* inner */
                                               ctx->invoc0_tess_factors[4 + chan]);
                        }
                }
        }

        if (writemask == 0xF && !is_tess_factor) {
                LLVMValueRef value = ac_build_gather_values(&ctx->ac,
                                                            values, 4);
                ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
                                            base, 0, ac_glc, false);
        }
}

LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
                                   unsigned input_index,
                                   unsigned vtx_offset_param,
                                   LLVMTypeRef type,
                                   unsigned swizzle)
{
        struct si_shader_context *ctx = si_shader_context_from_abi(abi);
        struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
        struct si_shader *shader = ctx->shader;
        LLVMValueRef vtx_offset, soffset;
        struct tgsi_shader_info *info = &shader->selector->info;
        unsigned semantic_name = info->input_semantic_name[input_index];
        unsigned semantic_index = info->input_semantic_index[input_index];
        unsigned param;
        LLVMValueRef value;

        param = si_shader_io_get_unique_index(semantic_name, semantic_index, false);

        /* GFX9 has the ESGS ring in LDS. */
        if (ctx->screen->info.chip_class >= GFX9) {
                unsigned index = vtx_offset_param;

                switch (index / 2) {
                case 0:
                        vtx_offset = si_unpack_param(ctx, ctx->gs_vtx01_offset,
                                                     index % 2 ? 16 : 0, 16);
                        break;
                case 1:
                        vtx_offset = si_unpack_param(ctx, ctx->gs_vtx23_offset,
                                                     index % 2 ? 16 : 0, 16);
                        break;
                case 2:
                        vtx_offset = si_unpack_param(ctx, ctx->gs_vtx45_offset,
                                                     index % 2 ? 16 : 0, 16);
                        break;
                default:
                        assert(0);
                        return NULL;
                }

                unsigned offset = param * 4 + swizzle;
                vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
                                          LLVMConstInt(ctx->i32, offset, false), "");

                LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->esgs_ring, vtx_offset);
                LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, ptr, "");
                if (llvm_type_is_64bit(ctx, type)) {
                        ptr = LLVMBuildGEP(ctx->ac.builder, ptr,
                                           &ctx->ac.i32_1, 1, "");
                        LLVMValueRef values[2] = {
                                value,
                                LLVMBuildLoad(ctx->ac.builder, ptr, "")
                        };
                        value = ac_build_gather_values(&ctx->ac, values, 2);
                }
                return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
        }

        /* GFX6: input load from the ESGS ring in memory. */
        if (swizzle == ~0) {
                LLVMValueRef values[TGSI_NUM_CHANNELS];
                unsigned chan;
                for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
                        values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
                                                             type, chan);
                }
                return ac_build_gather_values(&ctx->ac, values,
                                              TGSI_NUM_CHANNELS);
        }

        /* Get the vertex offset parameter on GFX6. */
        LLVMValueRef gs_vtx_offset = ac_get_arg(&ctx->ac,
                                                ctx->gs_vtx_offset[vtx_offset_param]);

        vtx_offset = LLVMBuildMul(ctx->ac.builder, gs_vtx_offset,
                                  LLVMConstInt(ctx->i32, 4, 0), "");

        soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);

        value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
                                     vtx_offset, soffset, 0, ac_glc, true, false);
        if (llvm_type_is_64bit(ctx, type)) {
                LLVMValueRef value2;
                soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);

                value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
                                              ctx->i32_0, vtx_offset, soffset,
                                              0, ac_glc, true, false);
                return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
        }
        return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
}

static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
                                         unsigned location,
                                         unsigned driver_location,
                                         unsigned component,
                                         unsigned num_components,
                                         unsigned vertex_index,
                                         unsigned const_index,
                                         LLVMTypeRef type)
{
        struct si_shader_context *ctx = si_shader_context_from_abi(abi);

        LLVMValueRef value[4];
        for (unsigned i = 0; i < num_components; i++) {
                unsigned offset = i;
                if (llvm_type_is_64bit(ctx, type))
                        offset *= 2;

                offset += component;
                value[i + component] = si_llvm_load_input_gs(&ctx->abi, driver_location  / 4 + const_index,
                                                             vertex_index, type, offset);
        }

        return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
}

static LLVMValueRef fetch_input_gs(
        struct lp_build_tgsi_context *bld_base,
        const struct tgsi_full_src_register *reg,
        enum tgsi_opcode_type type,
        unsigned swizzle_in)
{
        struct si_shader_context *ctx = si_shader_context(bld_base);
        struct tgsi_shader_info *info = &ctx->shader->selector->info;
        unsigned swizzle = swizzle_in & 0xffff;

        unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
        if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
                return si_get_primitive_id(ctx, swizzle);

        if (!reg->Register.Dimension)
                return NULL;

        return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
                                     reg->Dimension.Index,
                                     tgsi2llvmtype(bld_base, type),
                                     swizzle);
}

static int lookup_interp_param_index(unsigned interpolate, unsigned location)
{
        switch (interpolate) {
        case TGSI_INTERPOLATE_CONSTANT:
                return 0;

        case TGSI_INTERPOLATE_LINEAR:
                if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
                        return SI_PARAM_LINEAR_SAMPLE;
                else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
                        return SI_PARAM_LINEAR_CENTROID;
                else
                        return SI_PARAM_LINEAR_CENTER;
                break;
        case TGSI_INTERPOLATE_COLOR:
        case TGSI_INTERPOLATE_PERSPECTIVE:
                if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
                        return SI_PARAM_PERSP_SAMPLE;
                else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
                        return SI_PARAM_PERSP_CENTROID;
                else
                        return SI_PARAM_PERSP_CENTER;
                break;
        default:
                fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
                return -1;
        }
}

static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
                                       unsigned attr_index, unsigned chan,
                                       LLVMValueRef prim_mask,
                                       LLVMValueRef i, LLVMValueRef j)
{
        if (i || j) {
                return ac_build_fs_interp(&ctx->ac,
                                          LLVMConstInt(ctx->i32, chan, 0),
                                          LLVMConstInt(ctx->i32, attr_index, 0),
                                          prim_mask, i, j);
        }
        return ac_build_fs_interp_mov(&ctx->ac,
                                      LLVMConstInt(ctx->i32, 2, 0), /* P0 */
                                      LLVMConstInt(ctx->i32, chan, 0),
                                      LLVMConstInt(ctx->i32, attr_index, 0),
                                      prim_mask);
}

/**
 * Interpolate a fragment shader input.
 *
 * @param ctx           context
 * @param input_index           index of the input in hardware
 * @param semantic_name         TGSI_SEMANTIC_*
 * @param semantic_index        semantic index
 * @param num_interp_inputs     number of all interpolated inputs (= BCOLOR offset)
 * @param colors_read_mask      color components read (4 bits for each color, 8 bits in total)
 * @param interp_param          interpolation weights (i,j)
 * @param prim_mask             SI_PARAM_PRIM_MASK
 * @param face                  SI_PARAM_FRONT_FACE
 * @param result                the return value (4 components)
 */
static void interp_fs_input(struct si_shader_context *ctx,
                            unsigned input_index,
                            unsigned semantic_name,
                            unsigned semantic_index,
                            unsigned num_interp_inputs,
                            unsigned colors_read_mask,
                            LLVMValueRef interp_param,
                            LLVMValueRef prim_mask,
                            LLVMValueRef face,
                            LLVMValueRef result[4])
{
        LLVMValueRef i = NULL, j = NULL;
        unsigned chan;

        /* fs.constant returns the param from the middle vertex, so it's not
         * really useful for flat shading. It's meant to be used for custom
         * interpolation (but the intrinsic can't fetch from the other two
         * vertices).
         *
         * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
         * to do the right thing. The only reason we use fs.constant is that
         * fs.interp cannot be used on integers, because they can be equal
         * to NaN.
         *
         * When interp is false we will use fs.constant or for newer llvm,
         * amdgcn.interp.mov.
         */
        bool interp = interp_param != NULL;

        if (interp) {
                interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
                                                LLVMVectorType(ctx->f32, 2), "");

                i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
                                                ctx->i32_0, "");
                j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
                                                ctx->i32_1, "");
        }

        if (semantic_name == TGSI_SEMANTIC_COLOR &&
            ctx->shader->key.part.ps.prolog.color_two_side) {
                LLVMValueRef is_face_positive;

                /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
                 * otherwise it's at offset "num_inputs".
                 */
                unsigned back_attr_offset = num_interp_inputs;
                if (semantic_index == 1 && colors_read_mask & 0xf)
                        back_attr_offset += 1;

                is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
                                                 face, ctx->i32_0, "");

                for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
                        LLVMValueRef front, back;

                        front = si_build_fs_interp(ctx,
                                                   input_index, chan,
                                                   prim_mask, i, j);
                        back = si_build_fs_interp(ctx,
                                                  back_attr_offset, chan,
                                                  prim_mask, i, j);

                        result[chan] = LLVMBuildSelect(ctx->ac.builder,
                                                is_face_positive,
                                                front,
                                                back,
                                                "");
                }
        } else if (semantic_name == TGSI_SEMANTIC_FOG) {
                result[0] = si_build_fs_interp(ctx, input_index,
                                               0, prim_mask, i, j);
                result[1] =
                result[2] = LLVMConstReal(ctx->f32, 0.0f);
                result[3] = LLVMConstReal(ctx->f32, 1.0f);
        } else {
                for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
                        result[chan] = si_build_fs_interp(ctx,
                                                          input_index, chan,
                                                          prim_mask, i, j);
                }
        }
}

void si_llvm_load_input_fs(
        struct si_shader_context *ctx,
        unsigned input_index,
        LLVMValueRef out[4])
{
        struct si_shader *shader = ctx->shader;
        struct tgsi_shader_info *info = &shader->selector->info;
        LLVMValueRef main_fn = ctx->main_fn;
        LLVMValueRef interp_param = NULL;
        int interp_param_idx;
        enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
        unsigned semantic_index = info->input_semantic_index[input_index];
        enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
        enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];

        /* Get colors from input VGPRs (set by the prolog). */
        if (semantic_name == TGSI_SEMANTIC_COLOR) {
                unsigned colors_read = shader->selector->info.colors_read;
                unsigned mask = colors_read >> (semantic_index * 4);
                unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
                                  (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
                LLVMValueRef undef = LLVMGetUndef(ctx->f32);

                out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
                out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
                out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
                out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
                return;
        }

        interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
        if (interp_param_idx == -1)
                return;
        else if (interp_param_idx) {
                interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
        }

        interp_fs_input(ctx, input_index, semantic_name,
                        semantic_index, 0, /* this param is unused */
                        shader->selector->info.colors_read, interp_param,
                        ac_get_arg(&ctx->ac, ctx->args.prim_mask),
                        LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
                        &out[0]);
}

static void declare_input_fs(
        struct si_shader_context *ctx,
        unsigned input_index,
        const struct tgsi_full_declaration *decl,
        LLVMValueRef out[4])
{
        si_llvm_load_input_fs(ctx, input_index, out);
}

LLVMValueRef si_get_sample_id(struct si_shader_context *ctx)
{
        return si_unpack_param(ctx, ctx->args.ancillary, 8, 4);
}

static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
{
        struct si_shader_context *ctx = si_shader_context_from_abi(abi);

        /* For non-indexed draws, the base vertex set by the driver
         * (for direct draws) or the CP (for indirect draws) is the
         * first vertex ID, but GLSL expects 0 to be returned.
         */
        LLVMValueRef vs_state = ac_get_arg(&ctx->ac,
                                           ctx->vs_state_bits);
        LLVMValueRef indexed;

        indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
        indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");

        return LLVMBuildSelect(ctx->ac.builder, indexed,
                               ac_get_arg(&ctx->ac, ctx->args.base_vertex),
                               ctx->i32_0, "");
}

static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
{
        struct si_shader_context *ctx = si_shader_context_from_abi(abi);

        LLVMValueRef values[3];
        LLVMValueRef result;
        unsigned i;
        unsigned *properties = ctx->shader->selector->info.properties;

        if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
                unsigned sizes[3] = {
                        properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
                        properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
                        properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
                };

                for (i = 0; i < 3; ++i)
                        values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);

                result = ac_build_gather_values(&ctx->ac, values, 3);
        } else {
                result = ac_get_arg(&ctx->ac, ctx->block_size);
        }

        return result;
}

/**
 * Load a dword from a constant buffer.
 */
static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
                                      LLVMValueRef resource,
                                      LLVMValueRef offset)
{
        return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
                                    0, 0, true, true);
}

static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
{
        struct si_shader_context *ctx = si_shader_context_from_abi(abi);
        LLVMValueRef desc = ac_get_arg(&ctx->ac, ctx->rw_buffers);
        LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
        LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);

        /* offset = sample_id * 8  (8 = 2 floats containing samplepos.xy) */
        LLVMValueRef offset0 = LLVMBuildMul(ctx->ac.builder, sample_id, LLVMConstInt(ctx->i32, 8, 0), "");
        LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");

        LLVMValueRef pos[4] = {
                buffer_load_const(ctx, resource, offset0),
                buffer_load_const(ctx, resource, offset1),
                LLVMConstReal(ctx->f32, 0),
                LLVMConstReal(ctx->f32, 0)
        };

        return ac_build_gather_values(&ctx->ac, pos, 4);
}

static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
{
        struct si_shader_context *ctx = si_shader_context_from_abi(abi);
        return ac_to_integer(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args.sample_coverage));
}

static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
{
        struct si_shader_context *ctx = si_shader_context_from_abi(abi);
        LLVMValueRef coord[4] = {
                ac_get_arg(&ctx->ac, ctx->tes_u),
                ac_get_arg(&ctx->ac, ctx->tes_v),
                ctx->ac.f32_0,
                ctx->ac.f32_0
        };

        /* For triangles, the vector should be (u, v, 1-u-v). */
        if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
            PIPE_PRIM_TRIANGLES) {
                coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
                                         LLVMBuildFAdd(ctx->ac.builder,
                                                       coord[0], coord[1], ""), "");
        }
        return ac_build_gather_values(&ctx->ac, coord, 4);
}

static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
                                    unsigned semantic_name)
{
        LLVMValueRef base, addr;

        int param = si_shader_io_get_unique_index_patch(semantic_name, 0);

        base = ac_get_arg(&ctx->ac, ctx->tcs_offchip_offset);
        addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
                                          LLVMConstInt(ctx->i32, param, 0));

        return buffer_load(&ctx->bld_base, ctx->f32,
                           ~0, ctx->tess_offchip_ring, base, addr, true);

}

static LLVMValueRef load_tess_level_default(struct si_shader_context *ctx,
                                            unsigned semantic_name)
{
        LLVMValueRef buf, slot, val[4];
        int i, offset;

        slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
        buf = ac_get_arg(&ctx->ac, ctx->rw_buffers);
        buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
        offset = semantic_name == TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL ? 4 : 0;

        for (i = 0; i < 4; i++)
                val[i] = buffer_load_const(ctx, buf,
                                           LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
        return ac_build_gather_values(&ctx->ac, val, 4);
}

static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
                                       unsigned varying_id,
                                       bool load_default_state)
{
        struct si_shader_context *ctx = si_shader_context_from_abi(abi);
        unsigned semantic_name;

        if (load_default_state) {
                switch (varying_id) {
                case VARYING_SLOT_TESS_LEVEL_INNER:
                        semantic_name = TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL;
                        break;
                case VARYING_SLOT_TESS_LEVEL_OUTER:
                        semantic_name = TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL;
                        break;
                default:
                        unreachable("unknown tess level");
                }
                return load_tess_level_default(ctx, semantic_name);
        }

        switch (varying_id) {
        case VARYING_SLOT_TESS_LEVEL_INNER:
                semantic_name = TGSI_SEMANTIC_TESSINNER;
                break;
        case VARYING_SLOT_TESS_LEVEL_OUTER:
                semantic_name = TGSI_SEMANTIC_TESSOUTER;
                break;
        default:
                unreachable("unknown tess level");
        }

        return load_tess_level(ctx, semantic_name);

}

static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
{
        struct si_shader_context *ctx = si_shader_context_from_abi(abi);
        if (ctx->type == PIPE_SHADER_TESS_CTRL)
                return si_unpack_param(ctx, ctx->tcs_out_lds_layout, 13, 6);
        else if (ctx->type == PIPE_SHADER_TESS_EVAL)
                return get_num_tcs_out_vertices(ctx);
        else
                unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
}

void si_load_system_value(struct si_shader_context *ctx,
                          unsigned index,
                          const struct tgsi_full_declaration *decl)
{
        LLVMValueRef value = 0;

        assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);

        switch (decl->Semantic.Name) {
        case TGSI_SEMANTIC_INSTANCEID:
                value = ctx->abi.instance_id;
                break;

        case TGSI_SEMANTIC_VERTEXID:
                value = LLVMBuildAdd(ctx->ac.builder,
                                     ctx->abi.vertex_id,
                                     ac_get_arg(&ctx->ac, ctx->args.base_vertex), "");
                break;

        case TGSI_SEMANTIC_VERTEXID_NOBASE:
                /* Unused. Clarify the meaning in indexed vs. non-indexed
                 * draws if this is ever used again. */
                assert(false);
                break;

        case TGSI_SEMANTIC_BASEVERTEX:
                value = get_base_vertex(&ctx->abi);
                break;

        case TGSI_SEMANTIC_BASEINSTANCE:
                value = ac_get_arg(&ctx->ac, ctx->args.start_instance);
                break;

        case TGSI_SEMANTIC_DRAWID:
                value = ac_get_arg(&ctx->ac, ctx->args.draw_id);
                break;

        case TGSI_SEMANTIC_INVOCATIONID:
                if (ctx->type == PIPE_SHADER_TESS_CTRL) {
                        value = si_unpack_param(ctx, ctx->args.tcs_rel_ids, 8, 5);
                } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
                        if (ctx->screen->info.chip_class >= GFX10) {
                                value = LLVMBuildAnd(ctx->ac.builder,
                                                     ac_get_arg(&ctx->ac, ctx->args.gs_invocation_id),
                                                     LLVMConstInt(ctx->i32, 127, 0), "");
                        } else {
                                value = ac_get_arg(&ctx->ac, ctx->args.gs_invocation_id);
                        }
                } else {
                        assert(!"INVOCATIONID not implemented");
                }
                break;

        case TGSI_SEMANTIC_POSITION:
        {
                LLVMValueRef pos[4] = {
                        LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
                        LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
                        LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
                        ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
                                      LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT)),
                };
                value = ac_build_gather_values(&ctx->ac, pos, 4);
                break;
        }

        case TGSI_SEMANTIC_FACE:
                value = ac_get_arg(&ctx->ac, ctx->args.front_face);
                break;

        case TGSI_SEMANTIC_SAMPLEID:
                value = si_get_sample_id(ctx);
                break;

        case TGSI_SEMANTIC_SAMPLEPOS: {
                LLVMValueRef pos[4] = {
                        LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
                        LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
                        LLVMConstReal(ctx->f32, 0),
                        LLVMConstReal(ctx->f32, 0)
                };
                pos[0] = ac_build_fract(&ctx->ac, pos[0], 32);
                pos[1] = ac_build_fract(&ctx->ac, pos[1], 32);
                value = ac_build_gather_values(&ctx->ac, pos, 4);
                break;
        }

        case TGSI_SEMANTIC_SAMPLEMASK:
                /* This can only occur with the OpenGL Core profile, which
                 * doesn't support smoothing.
                 */
                value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
                break;

        case TGSI_SEMANTIC_TESSCOORD:
                value = si_load_tess_coord(&ctx->abi);
                break;

        case TGSI_SEMANTIC_VERTICESIN:
                value = si_load_patch_vertices_in(&ctx->abi);
                break;

        case TGSI_SEMANTIC_TESSINNER:
        case TGSI_SEMANTIC_TESSOUTER:
                value = load_tess_level(ctx, decl->Semantic.Name);
                break;

        case TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL:
        case TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL:
                value = load_tess_level_default(ctx, decl->Semantic.Name);
                break;

        case TGSI_SEMANTIC_PRIMID:
                value = si_get_primitive_id(ctx, 0);
                break;

        case TGSI_SEMANTIC_GRID_SIZE:
                value = ac_get_arg(&ctx->ac, ctx->args.num_work_groups);
                break;

        case TGSI_SEMANTIC_BLOCK_SIZE:
                value = get_block_size(&ctx->abi);
                break;

        case TGSI_SEMANTIC_BLOCK_ID:
        {
                LLVMValueRef values[3];

                for (int i = 0; i < 3; i++) {
                        values[i] = ctx->i32_0;
                        if (ctx->args.workgroup_ids[i].used) {
                                values[i] = ac_get_arg(&ctx->ac, ctx->args.workgroup_ids[i]);
                        }
                }
                value = ac_build_gather_values(&ctx->ac, values, 3);
                break;
        }

        case TGSI_SEMANTIC_THREAD_ID:
                value = ac_get_arg(&ctx->ac, ctx->args.local_invocation_ids);
                break;

        case TGSI_SEMANTIC_HELPER_INVOCATION:
                value = ac_build_load_helper_invocation(&ctx->ac);
                break;

        case TGSI_SEMANTIC_SUBGROUP_SIZE:
                value = LLVMConstInt(ctx->i32, ctx->ac.wave_size, 0);
                break;

        case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
                value = ac_get_thread_id(&ctx->ac);
                break;

        case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
        {
                LLVMValueRef id = ac_get_thread_id(&ctx->ac);
                if (ctx->ac.wave_size == 64)
                        id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
                value = LLVMBuildShl(ctx->ac.builder,
                                     LLVMConstInt(ctx->ac.iN_wavemask, 1, 0), id, "");
                if (ctx->ac.wave_size == 32)
                        value = LLVMBuildZExt(ctx->ac.builder, value, ctx->i64, "");
                value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
                break;
        }

        case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
        case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
        case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
        case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
        {
                LLVMValueRef id = ac_get_thread_id(&ctx->ac);
                if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
                    decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
                        /* All bits set except LSB */
                        value = LLVMConstInt(ctx->ac.iN_wavemask, -2, 0);
                } else {
                        /* All bits set */
                        value = LLVMConstInt(ctx->ac.iN_wavemask, -1, 0);
                }
                if (ctx->ac.wave_size == 64)
                        id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
                value = LLVMBuildShl(ctx->ac.builder, value, id, "");
                if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
                    decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
                        value = LLVMBuildNot(ctx->ac.builder, value, "");
                if (ctx->ac.wave_size == 32)
                        value = LLVMBuildZExt(ctx->ac.builder, value, ctx->i64, "");
                value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
                break;
        }

        case TGSI_SEMANTIC_CS_USER_DATA_AMD:
                value = ac_get_arg(&ctx->ac, ctx->cs_user_data);
                break;

        default:
                assert(!"unknown system value");
                return;
        }

        ctx->system_values[index] = value;
}

void si_declare_compute_memory(struct si_shader_context *ctx)
{
        struct si_shader_selector *sel = ctx->shader->selector;
        unsigned lds_size = sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE];

        LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_ADDR_SPACE_LDS);
        LLVMValueRef var;

        assert(!ctx->ac.lds);

        var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
                                          LLVMArrayType(ctx->i8, lds_size),
                                          "compute_lds",
                                          AC_ADDR_SPACE_LDS);
        LLVMSetAlignment(var, 64 * 1024);

        ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
}

void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
                                    const struct tgsi_full_declaration *decl)
{
        assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
        assert(decl->Range.First == decl->Range.Last);

        si_declare_compute_memory(ctx);
}

static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
{
        LLVMValueRef ptr =
                ac_get_arg(&ctx->ac, ctx->const_and_shader_buffers);
        struct si_shader_selector *sel = ctx->shader->selector;

        /* Do the bounds checking with a descriptor, because
         * doing computation and manual bounds checking of 64-bit
         * addresses generates horrible VALU code with very high
         * VGPR usage and very low SIMD occupancy.
         */
        ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");

        LLVMValueRef desc0, desc1;
        desc0 = ptr;
        desc1 = LLVMConstInt(ctx->i32,
                             S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);

        uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
                         S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
                         S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
                         S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);

        if (ctx->screen->info.chip_class >= GFX10)
                rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
                         S_008F0C_OOB_SELECT(3) |
                         S_008F0C_RESOURCE_LEVEL(1);
        else
                rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
                         S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);

        LLVMValueRef desc_elems[] = {
                desc0,
                desc1,
                LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
                LLVMConstInt(ctx->i32, rsrc3, false)
        };

        return ac_build_gather_values(&ctx->ac, desc_elems, 4);
}

static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
{
        LLVMValueRef list_ptr = ac_get_arg(&ctx->ac,
                                           ctx->const_and_shader_buffers);

        return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
                                     LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
}

static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
{
        struct si_shader_context *ctx = si_shader_context_from_abi(abi);
        struct si_shader_selector *sel = ctx->shader->selector;

        LLVMValueRef ptr = ac_get_arg(&ctx->ac, ctx->const_and_shader_buffers);

        if (sel->info.const_buffers_declared == 1 &&
            sel->info.shader_buffers_declared == 0) {
                return load_const_buffer_desc_fast_path(ctx);
        }

        index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
        index = LLVMBuildAdd(ctx->ac.builder, index,
                             LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");

        return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
}

static LLVMValueRef
load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
{
        struct si_shader_context *ctx = si_shader_context_from_abi(abi);
        LLVMValueRef rsrc_ptr = ac_get_arg(&ctx->ac,
                                           ctx->const_and_shader_buffers);

        index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
        index = LLVMBuildSub(ctx->ac.builder,
                             LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
                             index, "");

        return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
}

static LLVMValueRef fetch_constant(
        struct lp_build_tgsi_context *bld_base,
        const struct tgsi_full_src_register *reg,
        enum tgsi_opcode_type type,
        unsigned swizzle_in)
{
        struct si_shader_context *ctx = si_shader_context(bld_base);
        struct si_shader_selector *sel = ctx->shader->selector;
        const struct tgsi_ind_register *ireg = &reg->Indirect;
        unsigned buf, idx;
        unsigned swizzle = swizzle_in & 0xffff;

        LLVMValueRef addr, bufp;

        if (swizzle_in == LP_CHAN_ALL) {
                unsigned chan;
                LLVMValueRef values[4];
                for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
                        values[chan] = fetch_constant(bld_base, reg, type, chan);

                return ac_build_gather_values(&ctx->ac, values, 4);
        }

        /* Split 64-bit loads. */
        if (tgsi_type_is_64bit(type)) {
                LLVMValueRef lo, hi;

                lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
                hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, (swizzle_in >> 16));
                return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
                                                lo, hi);
        }

        idx = reg->Register.Index * 4 + swizzle;
        if (reg->Register.Indirect) {
                addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
        } else {
                addr = LLVMConstInt(ctx->i32, idx * 4, 0);
        }

        /* Fast path when user data SGPRs point to constant buffer 0 directly. */
        if (sel->info.const_buffers_declared == 1 &&
            sel->info.shader_buffers_declared == 0) {
                LLVMValueRef desc = load_const_buffer_desc_fast_path(ctx);
                LLVMValueRef result = buffer_load_const(ctx, desc, addr);
                return bitcast(bld_base, type, result);
        }

        assert(reg->Register.Dimension);
        buf = reg->Dimension.Index;

        if (reg->Dimension.Indirect) {
                LLVMValueRef ptr = ac_get_arg(&ctx->ac, ctx->const_and_shader_buffers);
                LLVMValueRef index;
                index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
                                                      reg->Dimension.Index,
                                                      ctx->num_const_buffers);
                index = LLVMBuildAdd(ctx->ac.builder, index,
                                     LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
                bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
        } else
                bufp = load_const_buffer_desc(ctx, buf);

        return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
}

/* Initialize arguments for the shader export intrinsic */
static void si_llvm_init_export_args(struct si_shader_context *ctx,
                                     LLVMValueRef *values,
                                     unsigned target,
                                     struct ac_export_args *args)
{
        LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
        unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
        unsigned chan;
        bool is_int8, is_int10;

        /* Default is 0xf. Adjusted below depending on the format. */
        args->enabled_channels = 0xf; /* writemask */

        /* Specify whether the EXEC mask represents the valid mask */
        args->valid_mask = 0;

        /* Specify whether this is the last export */
        args->done = 0;

        /* Specify the target we are exporting */
        args->target = target;

        if (ctx->type == PIPE_SHADER_FRAGMENT) {
                const struct si_shader_key *key = &ctx->shader->key;
                unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
                int cbuf = target - V_008DFC_SQ_EXP_MRT;

                assert(cbuf >= 0 && cbuf < 8);
                spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
                is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
                is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
        }

        args->compr = false;
        args->out[0] = f32undef;
        args->out[1] = f32undef;
        args->out[2] = f32undef;
        args->out[3] = f32undef;

        LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
        LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
                              unsigned bits, bool hi) = NULL;

        switch (spi_shader_col_format) {
        case V_028714_SPI_SHADER_ZERO:
                args->enabled_channels = 0; /* writemask */
                args->target = V_008DFC_SQ_EXP_NULL;
                break;

        case V_028714_SPI_SHADER_32_R:
                args->enabled_channels = 1; /* writemask */
                args->out[0] = values[0];
                break;

        case V_028714_SPI_SHADER_32_GR:
                args->enabled_channels = 0x3; /* writemask */
                args->out[0] = values[0];
                args->out[1] = values[1];
                break;

        case V_028714_SPI_SHADER_32_AR:
                if (ctx->screen->info.chip_class >= GFX10) {
                        args->enabled_channels = 0x3; /* writemask */
                        args->out[0] = values[0];
                        args->out[1] = values[3];
                } else {
                        args->enabled_channels = 0x9; /* writemask */
                        args->out[0] = values[0];
                        args->out[3] = values[3];
                }
                break;

        case V_028714_SPI_SHADER_FP16_ABGR:
                packf = ac_build_cvt_pkrtz_f16;
                break;

        case V_028714_SPI_SHADER_UNORM16_ABGR:
                packf = ac_build_cvt_pknorm_u16;
                break;

        case V_028714_SPI_SHADER_SNORM16_ABGR:
                packf = ac_build_cvt_pknorm_i16;
                break;

        case V_028714_SPI_SHADER_UINT16_ABGR:
                packi = ac_build_cvt_pk_u16;
                break;

        case V_028714_SPI_SHADER_SINT16_ABGR:
                packi = ac_build_cvt_pk_i16;
                break;

        case V_028714_SPI_SHADER_32_ABGR:
                memcpy(&args->out[0], values, sizeof(values[0]) * 4);
                break;
        }

        /* Pack f16 or norm_i16/u16. */
        if (packf) {
                for (chan = 0; chan < 2; chan++) {
                        LLVMValueRef pack_args[2] = {
                                values[2 * chan],
                                values[2 * chan + 1]
                        };
                        LLVMValueRef packed;

                        packed = packf(&ctx->ac, pack_args);
                        args->out[chan] = ac_to_float(&ctx->ac, packed);
                }
                args->compr = 1; /* COMPR flag */
        }
        /* Pack i16/u16. */
        if (packi) {
                for (chan = 0; chan < 2; chan++) {
                        LLVMValueRef pack_args[2] = {
                                ac_to_integer(&ctx->ac, values[2 * chan]),
                                ac_to_integer(&ctx->ac, values[2 * chan + 1])
                        };
                        LLVMValueRef packed;

                        packed = packi(&ctx->ac, pack_args,
                                       is_int8 ? 8 : is_int10 ? 10 : 16,
                                       chan == 1);
                        args->out[chan] = ac_to_float(&ctx->ac, packed);
                }
                args->compr = 1; /* COMPR flag */
        }
}

static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
                          LLVMValueRef alpha)
{
        struct si_shader_context *ctx = si_shader_context(bld_base);

        if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
                static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
                        [PIPE_FUNC_LESS] = LLVMRealOLT,
                        [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
                        [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
                        [PIPE_FUNC_GREATER] = LLVMRealOGT,
                        [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
                        [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
                };
                LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
                assert(cond);

                LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
                                SI_PARAM_ALPHA_REF);
                LLVMValueRef alpha_pass =
                        LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
                ac_build_kill_if_false(&ctx->ac, alpha_pass);
        } else {
                ac_build_kill_if_false(&ctx->ac, ctx->i1false);
        }
}

static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
                                                  LLVMValueRef alpha,
                                                  unsigned samplemask_param)
{
        struct si_shader_context *ctx = si_shader_context(bld_base);
        LLVMValueRef coverage;

        /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
        coverage = LLVMGetParam(ctx->main_fn,
                                samplemask_param);
        coverage = ac_to_integer(&ctx->ac, coverage);

        coverage = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32",
                                   ctx->i32,
                                   &coverage, 1, AC_FUNC_ATTR_READNONE);

        coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
                                   ctx->f32, "");

        coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
                                 LLVMConstReal(ctx->f32,
                                        1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");

        return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
}

static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
                                    struct ac_export_args *pos, LLVMValueRef *out_elts)
{
        unsigned reg_index;
        unsigned chan;
        unsigned const_chan;
        LLVMValueRef base_elt;
        LLVMValueRef ptr = ac_get_arg(&ctx->ac, ctx->rw_buffers);
        LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
                                                   SI_VS_CONST_CLIP_PLANES, 0);
        LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);

        for (reg_index = 0; reg_index < 2; reg_index ++) {
                struct ac_export_args *args = &pos[2 + reg_index];

                args->out[0] =
                args->out[1] =
                args->out[2] =
                args->out[3] = LLVMConstReal(ctx->f32, 0.0f);

                /* Compute dot products of position and user clip plane vectors */
                for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
                        for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
                                LLVMValueRef addr =
                                        LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
                                                                const_chan) * 4, 0);
                                base_elt = buffer_load_const(ctx, const_resource,
                                                             addr);
                                args->out[chan] = ac_build_fmad(&ctx->ac, base_elt,
                                                                out_elts[const_chan], args->out[chan]);
                        }
                }

                args->enabled_channels = 0xf;
                args->valid_mask = 0;
                args->done = 0;
                args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
                args->compr = 0;
        }
}

static void si_dump_streamout(struct pipe_stream_output_info *so)
{
        unsigned i;

        if (so->num_outputs)
                fprintf(stderr, "STREAMOUT\n");

        for (i = 0; i < so->num_outputs; i++) {
                unsigned mask = ((1 << so->output[i].num_components) - 1) <<
                                so->output[i].start_component;
                fprintf(stderr, "  %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
                        i, so->output[i].output_buffer,
                        so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
                        so->output[i].register_index,
                        mask & 1 ? "x" : "",
                        mask & 2 ? "y" : "",
                        mask & 4 ? "z" : "",
                        mask & 8 ? "w" : "");
        }
}

void si_emit_streamout_output(struct si_shader_context *ctx,
                              LLVMValueRef const *so_buffers,
                              LLVMValueRef const *so_write_offsets,
                              struct pipe_stream_output *stream_out,
                              struct si_shader_output_values *shader_out)
{
        unsigned buf_idx = stream_out->output_buffer;
        unsigned start = stream_out->start_component;
        unsigned num_comps = stream_out->num_components;
        LLVMValueRef out[4];

        assert(num_comps && num_comps <= 4);
        if (!num_comps || num_comps > 4)
                return;

        /* Load the output as int. */
        for (int j = 0; j < num_comps; j++) {
                assert(stream_out->stream == shader_out->vertex_stream[start + j]);

                out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
        }

        /* Pack the output. */
        LLVMValueRef vdata = NULL;

        switch (num_comps) {
        case 1: /* as i32 */
                vdata = out[0];
                break;
        case 2: /* as v2i32 */
        case 3: /* as v3i32 */
                if (ac_has_vec3_support(ctx->screen->info.chip_class, false)) {
                        vdata = ac_build_gather_values(&ctx->ac, out, num_comps);
                        break;
                }
                /* as v4i32 (aligned to 4) */
                out[3] = LLVMGetUndef(ctx->i32);
                /* fall through */
        case 4: /* as v4i32 */
                vdata = ac_build_gather_values(&ctx->ac, out, util_next_power_of_two(num_comps));
                break;
        }

        ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
                                    vdata, num_comps,
                                    so_write_offsets[buf_idx],
                                    ctx->i32_0,
                                    stream_out->dst_offset * 4, ac_glc | ac_slc, false);
}

/**
 * Write streamout data to buffers for vertex stream @p stream (different
 * vertex streams can occur for GS copy shaders).
 */
static void si_llvm_emit_streamout(struct si_shader_context *ctx,
                                   struct si_shader_output_values *outputs,
                                   unsigned noutput, unsigned stream)
{
        struct si_shader_selector *sel = ctx->shader->selector;
        struct pipe_stream_output_info *so = &sel->so;
        LLVMBuilderRef builder = ctx->ac.builder;
        int i;

        /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
        LLVMValueRef so_vtx_count =
                si_unpack_param(ctx, ctx->streamout_config, 16, 7);

        LLVMValueRef tid = ac_get_thread_id(&ctx->ac);

        /* can_emit = tid < so_vtx_count; */
        LLVMValueRef can_emit =
                LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");

        /* Emit the streamout code conditionally. This actually avoids
         * out-of-bounds buffer access. The hw tells us via the SGPR
         * (so_vtx_count) which threads are allowed to emit streamout data. */
        ac_build_ifcc(&ctx->ac, can_emit, 6501);
        {
                /* The buffer offset is computed as follows:
                 *   ByteOffset = streamout_offset[buffer_id]*4 +
                 *                (streamout_write_index + thread_id)*stride[buffer_id] +
                 *                attrib_offset
                 */

                LLVMValueRef so_write_index =
                        ac_get_arg(&ctx->ac,
                                   ctx->streamout_write_index);

                /* Compute (streamout_write_index + thread_id). */
                so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");

                /* Load the descriptor and compute the write offset for each
                 * enabled buffer. */
                LLVMValueRef so_write_offset[4] = {};
                LLVMValueRef so_buffers[4];
                LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac,
                                                  ctx->rw_buffers);

                for (i = 0; i < 4; i++) {
                        if (!so->stride[i])
                                continue;

                        LLVMValueRef offset = LLVMConstInt(ctx->i32,
                                                           SI_VS_STREAMOUT_BUF0 + i, 0);

                        so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);

                        LLVMValueRef so_offset = ac_get_arg(&ctx->ac,
                                                            ctx->streamout_offset[i]);
                        so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");

                        so_write_offset[i] = ac_build_imad(&ctx->ac, so_write_index,
                                                           LLVMConstInt(ctx->i32, so->stride[i]*4, 0),
                                                           so_offset);
                }

                /* Write streamout data. */
                for (i = 0; i < so->num_outputs; i++) {
                        unsigned reg = so->output[i].register_index;

                        if (reg >= noutput)
                                continue;

                        if (stream != so->output[i].stream)
                                continue;

                        si_emit_streamout_output(ctx, so_buffers, so_write_offset,
                                                 &so->output[i], &outputs[reg]);
                }
        }
        ac_build_endif(&ctx->ac, 6501);
}

static void si_export_param(struct si_shader_context *ctx, unsigned index,
                            LLVMValueRef *values)
{
        struct ac_export_args args;

        si_llvm_init_export_args(ctx, values,
                                 V_008DFC_SQ_EXP_PARAM + index, &args);
        ac_build_export(&ctx->ac, &args);
}

static void si_build_param_exports(struct si_shader_context *ctx,
                                   struct si_shader_output_values *outputs,
                                   unsigned noutput)
{
        struct si_shader *shader = ctx->shader;
        unsigned param_count = 0;

        for (unsigned i = 0; i < noutput; i++) {
                unsigned semantic_name = outputs[i].semantic_name;
                unsigned semantic_index = outputs[i].semantic_index;

                if (outputs[i].vertex_stream[0] != 0 &&
                    outputs[i].vertex_stream[1] != 0 &&
                    outputs[i].vertex_stream[2] != 0 &&
                    outputs[i].vertex_stream[3] != 0)
                        continue;

                switch (semantic_name) {
                case TGSI_SEMANTIC_LAYER:
                case TGSI_SEMANTIC_VIEWPORT_INDEX:
                case TGSI_SEMANTIC_CLIPDIST:
                case TGSI_SEMANTIC_COLOR:
                case TGSI_SEMANTIC_BCOLOR:
                case TGSI_SEMANTIC_PRIMID:
                case TGSI_SEMANTIC_FOG:
                case TGSI_SEMANTIC_TEXCOORD:
                case TGSI_SEMANTIC_GENERIC:
                        break;
                default:
                        continue;
                }

                if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
                     semantic_index < SI_MAX_IO_GENERIC) &&
                    shader->key.opt.kill_outputs &
                    (1ull << si_shader_io_get_unique_index(semantic_name,
                                                           semantic_index, true)))
                        continue;

                si_export_param(ctx, param_count, outputs[i].values);

                assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
                shader->info.vs_output_param_offset[i] = param_count++;
        }

        shader->info.nr_param_exports = param_count;
}

/**
 * Vertex color clamping.
 *
 * This uses a state constant loaded in a user data SGPR and
 * an IF statement is added that clamps all colors if the constant
 * is true.
 */
static void si_vertex_color_clamping(struct si_shader_context *ctx,
                                     struct si_shader_output_values *outputs,
                                     unsigned noutput)
{
        LLVMValueRef addr[SI_MAX_VS_OUTPUTS][4];
        bool has_colors = false;

        /* Store original colors to alloca variables. */
        for (unsigned i = 0; i < noutput; i++) {
                if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
                    outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
                        continue;

                for (unsigned j = 0; j < 4; j++) {
                        addr[i][j] = ac_build_alloca_undef(&ctx->ac, ctx->f32, "");
                        LLVMBuildStore(ctx->ac.builder, outputs[i].values[j], addr[i][j]);
                }
                has_colors = true;
        }

        if (!has_colors)
                return;

        /* The state is in the first bit of the user SGPR. */
        LLVMValueRef cond = ac_get_arg(&ctx->ac, ctx->vs_state_bits);
        cond = LLVMBuildTrunc(ctx->ac.builder, cond, ctx->i1, "");

        ac_build_ifcc(&ctx->ac, cond, 6502);

        /* Store clamped colors to alloca variables within the conditional block. */
        for (unsigned i = 0; i < noutput; i++) {
                if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
                    outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
                        continue;

                for (unsigned j = 0; j < 4; j++) {
                        LLVMBuildStore(ctx->ac.builder,
                                       ac_build_clamp(&ctx->ac, outputs[i].values[j]),
                                       addr[i][j]);
                }
        }
        ac_build_endif(&ctx->ac, 6502);

        /* Load clamped colors */
        for (unsigned i = 0; i < noutput; i++) {
                if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
                    outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
                        continue;

                for (unsigned j = 0; j < 4; j++) {
                        outputs[i].values[j] =
                                LLVMBuildLoad(ctx->ac.builder, addr[i][j], "");
                }
        }
}

/* Generate export instructions for hardware VS shader stage or NGG GS stage
 * (position and parameter data only).
 */
void si_llvm_export_vs(struct si_shader_context *ctx,
                       struct si_shader_output_values *outputs,
                       unsigned noutput)
{
        struct si_shader *shader = ctx->shader;
        struct ac_export_args pos_args[4] = {};
        LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
        unsigned pos_idx;
        int i;

        si_vertex_color_clamping(ctx, outputs, noutput);

        /* Build position exports. */
        for (i = 0; i < noutput; i++) {
                switch (outputs[i].semantic_name) {
                case TGSI_SEMANTIC_POSITION:
                        si_llvm_init_export_args(ctx, outputs[i].values,
                                                 V_008DFC_SQ_EXP_POS, &pos_args[0]);
                        break;
                case TGSI_SEMANTIC_PSIZE:
                        psize_value = outputs[i].values[0];
                        break;
                case TGSI_SEMANTIC_LAYER:
                        layer_value = outputs[i].values[0];
                        break;
                case TGSI_SEMANTIC_VIEWPORT_INDEX:
                        viewport_index_value = outputs[i].values[0];
                        break;
                case TGSI_SEMANTIC_EDGEFLAG:
                        edgeflag_value = outputs[i].values[0];
                        break;
                case TGSI_SEMANTIC_CLIPDIST:
                        if (!shader->key.opt.clip_disable) {
                                unsigned index = 2 + outputs[i].semantic_index;