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radeonsi: move si_shader_context initialization into a separate function
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_dump.h"
45
46 #include "si_pipe.h"
47 #include "si_shader.h"
48 #include "sid.h"
49
50 #include <errno.h>
51
52 static const char *scratch_rsrc_dword0_symbol =
53 "SCRATCH_RSRC_DWORD0";
54
55 static const char *scratch_rsrc_dword1_symbol =
56 "SCRATCH_RSRC_DWORD1";
57
58 struct si_shader_output_values
59 {
60 LLVMValueRef values[4];
61 unsigned name;
62 unsigned sid;
63 };
64
65 struct si_shader_context
66 {
67 struct radeon_llvm_context radeon_bld;
68 struct si_shader *shader;
69 struct si_screen *screen;
70 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
71 bool is_gs_copy_shader;
72 int param_streamout_config;
73 int param_streamout_write_index;
74 int param_streamout_offset[4];
75 int param_vertex_id;
76 int param_rel_auto_id;
77 int param_vs_prim_id;
78 int param_instance_id;
79 int param_tes_u;
80 int param_tes_v;
81 int param_tes_rel_patch_id;
82 int param_tes_patch_id;
83 int param_es2gs_offset;
84 LLVMTargetMachineRef tm;
85 LLVMValueRef const_md;
86 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
87 LLVMValueRef lds;
88 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
89 LLVMValueRef sampler_views[SI_NUM_SAMPLER_VIEWS];
90 LLVMValueRef sampler_states[SI_NUM_SAMPLER_STATES];
91 LLVMValueRef so_buffers[4];
92 LLVMValueRef esgs_ring;
93 LLVMValueRef gsvs_ring[4];
94 LLVMValueRef gs_next_vertex[4];
95 };
96
97 static struct si_shader_context * si_shader_context(
98 struct lp_build_tgsi_context * bld_base)
99 {
100 return (struct si_shader_context *)bld_base;
101 }
102
103
104 #define PERSPECTIVE_BASE 0
105 #define LINEAR_BASE 9
106
107 #define SAMPLE_OFFSET 0
108 #define CENTER_OFFSET 2
109 #define CENTROID_OFSET 4
110
111 #define USE_SGPR_MAX_SUFFIX_LEN 5
112 #define CONST_ADDR_SPACE 2
113 #define LOCAL_ADDR_SPACE 3
114 #define USER_SGPR_ADDR_SPACE 8
115
116
117 #define SENDMSG_GS 2
118 #define SENDMSG_GS_DONE 3
119
120 #define SENDMSG_GS_OP_NOP (0 << 4)
121 #define SENDMSG_GS_OP_CUT (1 << 4)
122 #define SENDMSG_GS_OP_EMIT (2 << 4)
123 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
124
125 /**
126 * Returns a unique index for a semantic name and index. The index must be
127 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
128 * calculated.
129 */
130 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
131 {
132 switch (semantic_name) {
133 case TGSI_SEMANTIC_POSITION:
134 return 0;
135 case TGSI_SEMANTIC_PSIZE:
136 return 1;
137 case TGSI_SEMANTIC_CLIPDIST:
138 assert(index <= 1);
139 return 2 + index;
140 case TGSI_SEMANTIC_GENERIC:
141 if (index <= 63-4)
142 return 4 + index;
143 else
144 /* same explanation as in the default statement,
145 * the only user hitting this is st/nine.
146 */
147 return 0;
148
149 /* patch indices are completely separate and thus start from 0 */
150 case TGSI_SEMANTIC_TESSOUTER:
151 return 0;
152 case TGSI_SEMANTIC_TESSINNER:
153 return 1;
154 case TGSI_SEMANTIC_PATCH:
155 return 2 + index;
156
157 default:
158 /* Don't fail here. The result of this function is only used
159 * for LS, TCS, TES, and GS, where legacy GL semantics can't
160 * occur, but this function is called for all vertex shaders
161 * before it's known whether LS will be compiled or not.
162 */
163 return 0;
164 }
165 }
166
167 /**
168 * Get the value of a shader input parameter and extract a bitfield.
169 */
170 static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx,
171 unsigned param, unsigned rshift,
172 unsigned bitwidth)
173 {
174 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
175 LLVMValueRef value = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
176 param);
177
178 if (rshift)
179 value = LLVMBuildLShr(gallivm->builder, value,
180 lp_build_const_int32(gallivm, rshift), "");
181
182 if (rshift + bitwidth < 32) {
183 unsigned mask = (1 << bitwidth) - 1;
184 value = LLVMBuildAnd(gallivm->builder, value,
185 lp_build_const_int32(gallivm, mask), "");
186 }
187
188 return value;
189 }
190
191 static LLVMValueRef get_rel_patch_id(struct si_shader_context *si_shader_ctx)
192 {
193 switch (si_shader_ctx->type) {
194 case TGSI_PROCESSOR_TESS_CTRL:
195 return unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 0, 8);
196
197 case TGSI_PROCESSOR_TESS_EVAL:
198 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
199 si_shader_ctx->param_tes_rel_patch_id);
200
201 default:
202 assert(0);
203 return NULL;
204 }
205 }
206
207 /* Tessellation shaders pass outputs to the next shader using LDS.
208 *
209 * LS outputs = TCS inputs
210 * TCS outputs = TES inputs
211 *
212 * The LDS layout is:
213 * - TCS inputs for patch 0
214 * - TCS inputs for patch 1
215 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
216 * - ...
217 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
218 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
219 * - TCS outputs for patch 1
220 * - Per-patch TCS outputs for patch 1
221 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
222 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
223 * - ...
224 *
225 * All three shaders VS(LS), TCS, TES share the same LDS space.
226 */
227
228 static LLVMValueRef
229 get_tcs_in_patch_stride(struct si_shader_context *si_shader_ctx)
230 {
231 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX)
232 return unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
233 else if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
234 return unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
235 else {
236 assert(0);
237 return NULL;
238 }
239 }
240
241 static LLVMValueRef
242 get_tcs_out_patch_stride(struct si_shader_context *si_shader_ctx)
243 {
244 return unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
245 }
246
247 static LLVMValueRef
248 get_tcs_out_patch0_offset(struct si_shader_context *si_shader_ctx)
249 {
250 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
251 unpack_param(si_shader_ctx,
252 SI_PARAM_TCS_OUT_OFFSETS,
253 0, 16),
254 4);
255 }
256
257 static LLVMValueRef
258 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *si_shader_ctx)
259 {
260 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
261 unpack_param(si_shader_ctx,
262 SI_PARAM_TCS_OUT_OFFSETS,
263 16, 16),
264 4);
265 }
266
267 static LLVMValueRef
268 get_tcs_in_current_patch_offset(struct si_shader_context *si_shader_ctx)
269 {
270 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
271 LLVMValueRef patch_stride = get_tcs_in_patch_stride(si_shader_ctx);
272 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
273
274 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
275 }
276
277 static LLVMValueRef
278 get_tcs_out_current_patch_offset(struct si_shader_context *si_shader_ctx)
279 {
280 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
281 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(si_shader_ctx);
282 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
283 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
284
285 return LLVMBuildAdd(gallivm->builder, patch0_offset,
286 LLVMBuildMul(gallivm->builder, patch_stride,
287 rel_patch_id, ""),
288 "");
289 }
290
291 static LLVMValueRef
292 get_tcs_out_current_patch_data_offset(struct si_shader_context *si_shader_ctx)
293 {
294 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
295 LLVMValueRef patch0_patch_data_offset =
296 get_tcs_out_patch0_patch_data_offset(si_shader_ctx);
297 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
298 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
299
300 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
301 LLVMBuildMul(gallivm->builder, patch_stride,
302 rel_patch_id, ""),
303 "");
304 }
305
306 static void build_indexed_store(struct si_shader_context *si_shader_ctx,
307 LLVMValueRef base_ptr, LLVMValueRef index,
308 LLVMValueRef value)
309 {
310 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
311 struct gallivm_state *gallivm = bld_base->base.gallivm;
312 LLVMValueRef indices[2], pointer;
313
314 indices[0] = bld_base->uint_bld.zero;
315 indices[1] = index;
316
317 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
318 LLVMBuildStore(gallivm->builder, value, pointer);
319 }
320
321 /**
322 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
323 * It's equivalent to doing a load from &base_ptr[index].
324 *
325 * \param base_ptr Where the array starts.
326 * \param index The element index into the array.
327 */
328 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
329 LLVMValueRef base_ptr, LLVMValueRef index)
330 {
331 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
332 struct gallivm_state *gallivm = bld_base->base.gallivm;
333 LLVMValueRef indices[2], pointer;
334
335 indices[0] = bld_base->uint_bld.zero;
336 indices[1] = index;
337
338 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
339 return LLVMBuildLoad(gallivm->builder, pointer, "");
340 }
341
342 /**
343 * Do a load from &base_ptr[index], but also add a flag that it's loading
344 * a constant.
345 */
346 static LLVMValueRef build_indexed_load_const(
347 struct si_shader_context * si_shader_ctx,
348 LLVMValueRef base_ptr, LLVMValueRef index)
349 {
350 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
351 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
352 return result;
353 }
354
355 static LLVMValueRef get_instance_index_for_fetch(
356 struct radeon_llvm_context * radeon_bld,
357 unsigned divisor)
358 {
359 struct si_shader_context *si_shader_ctx =
360 si_shader_context(&radeon_bld->soa.bld_base);
361 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
362
363 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
364 si_shader_ctx->param_instance_id);
365
366 /* The division must be done before START_INSTANCE is added. */
367 if (divisor > 1)
368 result = LLVMBuildUDiv(gallivm->builder, result,
369 lp_build_const_int32(gallivm, divisor), "");
370
371 return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
372 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
373 }
374
375 static void declare_input_vs(
376 struct radeon_llvm_context *radeon_bld,
377 unsigned input_index,
378 const struct tgsi_full_declaration *decl)
379 {
380 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
381 struct gallivm_state *gallivm = base->gallivm;
382 struct si_shader_context *si_shader_ctx =
383 si_shader_context(&radeon_bld->soa.bld_base);
384 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
385
386 unsigned chan;
387
388 LLVMValueRef t_list_ptr;
389 LLVMValueRef t_offset;
390 LLVMValueRef t_list;
391 LLVMValueRef attribute_offset;
392 LLVMValueRef buffer_index;
393 LLVMValueRef args[3];
394 LLVMTypeRef vec4_type;
395 LLVMValueRef input;
396
397 /* Load the T list */
398 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
399
400 t_offset = lp_build_const_int32(gallivm, input_index);
401
402 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
403
404 /* Build the attribute offset */
405 attribute_offset = lp_build_const_int32(gallivm, 0);
406
407 if (divisor) {
408 /* Build index from instance ID, start instance and divisor */
409 si_shader_ctx->shader->uses_instanceid = true;
410 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
411 } else {
412 /* Load the buffer index for vertices. */
413 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
414 si_shader_ctx->param_vertex_id);
415 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
416 SI_PARAM_BASE_VERTEX);
417 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
418 }
419
420 vec4_type = LLVMVectorType(base->elem_type, 4);
421 args[0] = t_list;
422 args[1] = attribute_offset;
423 args[2] = buffer_index;
424 input = lp_build_intrinsic(gallivm->builder,
425 "llvm.SI.vs.load.input", vec4_type, args, 3,
426 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
427
428 /* Break up the vec4 into individual components */
429 for (chan = 0; chan < 4; chan++) {
430 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
431 /* XXX: Use a helper function for this. There is one in
432 * tgsi_llvm.c. */
433 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
434 LLVMBuildExtractElement(gallivm->builder,
435 input, llvm_chan, "");
436 }
437 }
438
439 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
440 unsigned swizzle)
441 {
442 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
443
444 if (swizzle > 0)
445 return bld_base->uint_bld.zero;
446
447 switch (si_shader_ctx->type) {
448 case TGSI_PROCESSOR_VERTEX:
449 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
450 si_shader_ctx->param_vs_prim_id);
451 case TGSI_PROCESSOR_TESS_CTRL:
452 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
453 SI_PARAM_PATCH_ID);
454 case TGSI_PROCESSOR_TESS_EVAL:
455 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
456 si_shader_ctx->param_tes_patch_id);
457 case TGSI_PROCESSOR_GEOMETRY:
458 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
459 SI_PARAM_PRIMITIVE_ID);
460 default:
461 assert(0);
462 return bld_base->uint_bld.zero;
463 }
464 }
465
466 /**
467 * Return the value of tgsi_ind_register for indexing.
468 * This is the indirect index with the constant offset added to it.
469 */
470 static LLVMValueRef get_indirect_index(struct si_shader_context *si_shader_ctx,
471 const struct tgsi_ind_register *ind,
472 int rel_index)
473 {
474 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
475 LLVMValueRef result;
476
477 result = si_shader_ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
478 result = LLVMBuildLoad(gallivm->builder, result, "");
479 result = LLVMBuildAdd(gallivm->builder, result,
480 lp_build_const_int32(gallivm, rel_index), "");
481 return result;
482 }
483
484 /**
485 * Calculate a dword address given an input or output register and a stride.
486 */
487 static LLVMValueRef get_dw_address(struct si_shader_context *si_shader_ctx,
488 const struct tgsi_full_dst_register *dst,
489 const struct tgsi_full_src_register *src,
490 LLVMValueRef vertex_dw_stride,
491 LLVMValueRef base_addr)
492 {
493 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
494 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
495 ubyte *name, *index, *array_first;
496 int first, param;
497 struct tgsi_full_dst_register reg;
498
499 /* Set the register description. The address computation is the same
500 * for sources and destinations. */
501 if (src) {
502 reg.Register.File = src->Register.File;
503 reg.Register.Index = src->Register.Index;
504 reg.Register.Indirect = src->Register.Indirect;
505 reg.Register.Dimension = src->Register.Dimension;
506 reg.Indirect = src->Indirect;
507 reg.Dimension = src->Dimension;
508 reg.DimIndirect = src->DimIndirect;
509 } else
510 reg = *dst;
511
512 /* If the register is 2-dimensional (e.g. an array of vertices
513 * in a primitive), calculate the base address of the vertex. */
514 if (reg.Register.Dimension) {
515 LLVMValueRef index;
516
517 if (reg.Dimension.Indirect)
518 index = get_indirect_index(si_shader_ctx, &reg.DimIndirect,
519 reg.Dimension.Index);
520 else
521 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
522
523 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
524 LLVMBuildMul(gallivm->builder, index,
525 vertex_dw_stride, ""), "");
526 }
527
528 /* Get information about the register. */
529 if (reg.Register.File == TGSI_FILE_INPUT) {
530 name = info->input_semantic_name;
531 index = info->input_semantic_index;
532 array_first = info->input_array_first;
533 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
534 name = info->output_semantic_name;
535 index = info->output_semantic_index;
536 array_first = info->output_array_first;
537 } else {
538 assert(0);
539 return NULL;
540 }
541
542 if (reg.Register.Indirect) {
543 /* Add the relative address of the element. */
544 LLVMValueRef ind_index;
545
546 if (reg.Indirect.ArrayID)
547 first = array_first[reg.Indirect.ArrayID];
548 else
549 first = reg.Register.Index;
550
551 ind_index = get_indirect_index(si_shader_ctx, &reg.Indirect,
552 reg.Register.Index - first);
553
554 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
555 LLVMBuildMul(gallivm->builder, ind_index,
556 lp_build_const_int32(gallivm, 4), ""), "");
557
558 param = si_shader_io_get_unique_index(name[first], index[first]);
559 } else {
560 param = si_shader_io_get_unique_index(name[reg.Register.Index],
561 index[reg.Register.Index]);
562 }
563
564 /* Add the base address of the element. */
565 return LLVMBuildAdd(gallivm->builder, base_addr,
566 lp_build_const_int32(gallivm, param * 4), "");
567 }
568
569 /**
570 * Load from LDS.
571 *
572 * \param type output value type
573 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
574 * \param dw_addr address in dwords
575 */
576 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
577 enum tgsi_opcode_type type, unsigned swizzle,
578 LLVMValueRef dw_addr)
579 {
580 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
581 struct gallivm_state *gallivm = bld_base->base.gallivm;
582 LLVMValueRef value;
583
584 if (swizzle == ~0) {
585 LLVMValueRef values[TGSI_NUM_CHANNELS];
586
587 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
588 values[chan] = lds_load(bld_base, type, chan, dw_addr);
589
590 return lp_build_gather_values(bld_base->base.gallivm, values,
591 TGSI_NUM_CHANNELS);
592 }
593
594 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
595 lp_build_const_int32(gallivm, swizzle));
596
597 value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
598 if (type == TGSI_TYPE_DOUBLE) {
599 LLVMValueRef value2;
600 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
601 lp_build_const_int32(gallivm, swizzle + 1));
602 value2 = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
603 return radeon_llvm_emit_fetch_double(bld_base, value, value2);
604 }
605
606 return LLVMBuildBitCast(gallivm->builder, value,
607 tgsi2llvmtype(bld_base, type), "");
608 }
609
610 /**
611 * Store to LDS.
612 *
613 * \param swizzle offset (typically 0..3)
614 * \param dw_addr address in dwords
615 * \param value value to store
616 */
617 static void lds_store(struct lp_build_tgsi_context * bld_base,
618 unsigned swizzle, LLVMValueRef dw_addr,
619 LLVMValueRef value)
620 {
621 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
622 struct gallivm_state *gallivm = bld_base->base.gallivm;
623
624 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
625 lp_build_const_int32(gallivm, swizzle));
626
627 value = LLVMBuildBitCast(gallivm->builder, value,
628 LLVMInt32TypeInContext(gallivm->context), "");
629 build_indexed_store(si_shader_ctx, si_shader_ctx->lds,
630 dw_addr, value);
631 }
632
633 static LLVMValueRef fetch_input_tcs(
634 struct lp_build_tgsi_context *bld_base,
635 const struct tgsi_full_src_register *reg,
636 enum tgsi_opcode_type type, unsigned swizzle)
637 {
638 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
639 LLVMValueRef dw_addr, stride;
640
641 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
642 dw_addr = get_tcs_in_current_patch_offset(si_shader_ctx);
643 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
644
645 return lds_load(bld_base, type, swizzle, dw_addr);
646 }
647
648 static LLVMValueRef fetch_output_tcs(
649 struct lp_build_tgsi_context *bld_base,
650 const struct tgsi_full_src_register *reg,
651 enum tgsi_opcode_type type, unsigned swizzle)
652 {
653 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
654 LLVMValueRef dw_addr, stride;
655
656 if (reg->Register.Dimension) {
657 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
658 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
659 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
660 } else {
661 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
662 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
663 }
664
665 return lds_load(bld_base, type, swizzle, dw_addr);
666 }
667
668 static LLVMValueRef fetch_input_tes(
669 struct lp_build_tgsi_context *bld_base,
670 const struct tgsi_full_src_register *reg,
671 enum tgsi_opcode_type type, unsigned swizzle)
672 {
673 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
674 LLVMValueRef dw_addr, stride;
675
676 if (reg->Register.Dimension) {
677 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
678 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
679 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
680 } else {
681 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
682 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
683 }
684
685 return lds_load(bld_base, type, swizzle, dw_addr);
686 }
687
688 static void store_output_tcs(struct lp_build_tgsi_context * bld_base,
689 const struct tgsi_full_instruction * inst,
690 const struct tgsi_opcode_info * info,
691 LLVMValueRef dst[4])
692 {
693 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
694 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
695 unsigned chan_index;
696 LLVMValueRef dw_addr, stride;
697
698 /* Only handle per-patch and per-vertex outputs here.
699 * Vectors will be lowered to scalars and this function will be called again.
700 */
701 if (reg->Register.File != TGSI_FILE_OUTPUT ||
702 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
703 radeon_llvm_emit_store(bld_base, inst, info, dst);
704 return;
705 }
706
707 if (reg->Register.Dimension) {
708 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
709 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
710 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, stride, dw_addr);
711 } else {
712 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
713 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, NULL, dw_addr);
714 }
715
716 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
717 LLVMValueRef value = dst[chan_index];
718
719 if (inst->Instruction.Saturate)
720 value = radeon_llvm_saturate(bld_base, value);
721
722 lds_store(bld_base, chan_index, dw_addr, value);
723 }
724 }
725
726 static LLVMValueRef fetch_input_gs(
727 struct lp_build_tgsi_context *bld_base,
728 const struct tgsi_full_src_register *reg,
729 enum tgsi_opcode_type type,
730 unsigned swizzle)
731 {
732 struct lp_build_context *base = &bld_base->base;
733 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
734 struct si_shader *shader = si_shader_ctx->shader;
735 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
736 struct gallivm_state *gallivm = base->gallivm;
737 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
738 LLVMValueRef vtx_offset;
739 LLVMValueRef args[9];
740 unsigned vtx_offset_param;
741 struct tgsi_shader_info *info = &shader->selector->info;
742 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
743 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
744 unsigned param;
745 LLVMValueRef value;
746
747 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
748 return get_primitive_id(bld_base, swizzle);
749
750 if (!reg->Register.Dimension)
751 return NULL;
752
753 if (swizzle == ~0) {
754 LLVMValueRef values[TGSI_NUM_CHANNELS];
755 unsigned chan;
756 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
757 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
758 }
759 return lp_build_gather_values(bld_base->base.gallivm, values,
760 TGSI_NUM_CHANNELS);
761 }
762
763 /* Get the vertex offset parameter */
764 vtx_offset_param = reg->Dimension.Index;
765 if (vtx_offset_param < 2) {
766 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
767 } else {
768 assert(vtx_offset_param < 6);
769 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
770 }
771 vtx_offset = lp_build_mul_imm(uint,
772 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
773 vtx_offset_param),
774 4);
775
776 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
777 args[0] = si_shader_ctx->esgs_ring;
778 args[1] = vtx_offset;
779 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
780 args[3] = uint->zero;
781 args[4] = uint->one; /* OFFEN */
782 args[5] = uint->zero; /* IDXEN */
783 args[6] = uint->one; /* GLC */
784 args[7] = uint->zero; /* SLC */
785 args[8] = uint->zero; /* TFE */
786
787 value = lp_build_intrinsic(gallivm->builder,
788 "llvm.SI.buffer.load.dword.i32.i32",
789 i32, args, 9,
790 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
791 if (type == TGSI_TYPE_DOUBLE) {
792 LLVMValueRef value2;
793 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
794 value2 = lp_build_intrinsic(gallivm->builder,
795 "llvm.SI.buffer.load.dword.i32.i32",
796 i32, args, 9,
797 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
798 return radeon_llvm_emit_fetch_double(bld_base,
799 value, value2);
800 }
801 return LLVMBuildBitCast(gallivm->builder,
802 value,
803 tgsi2llvmtype(bld_base, type), "");
804 }
805
806 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
807 {
808 switch (interpolate) {
809 case TGSI_INTERPOLATE_CONSTANT:
810 return 0;
811
812 case TGSI_INTERPOLATE_LINEAR:
813 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
814 return SI_PARAM_LINEAR_SAMPLE;
815 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
816 return SI_PARAM_LINEAR_CENTROID;
817 else
818 return SI_PARAM_LINEAR_CENTER;
819 break;
820 case TGSI_INTERPOLATE_COLOR:
821 case TGSI_INTERPOLATE_PERSPECTIVE:
822 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
823 return SI_PARAM_PERSP_SAMPLE;
824 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
825 return SI_PARAM_PERSP_CENTROID;
826 else
827 return SI_PARAM_PERSP_CENTER;
828 break;
829 default:
830 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
831 return -1;
832 }
833 }
834
835 /* This shouldn't be used by explicit INTERP opcodes. */
836 static LLVMValueRef get_interp_param(struct si_shader_context *si_shader_ctx,
837 unsigned param)
838 {
839 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
840 unsigned sample_param = 0;
841 LLVMValueRef default_ij, sample_ij, force_sample;
842
843 default_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, param);
844
845 /* If the shader doesn't use center/centroid, just return the parameter.
846 *
847 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
848 * switch between center/centroid and sample without shader changes.
849 */
850 switch (param) {
851 case SI_PARAM_PERSP_CENTROID:
852 case SI_PARAM_PERSP_CENTER:
853 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_persp)
854 return default_ij;
855
856 sample_param = SI_PARAM_PERSP_SAMPLE;
857 break;
858
859 case SI_PARAM_LINEAR_CENTROID:
860 case SI_PARAM_LINEAR_CENTER:
861 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_linear)
862 return default_ij;
863
864 sample_param = SI_PARAM_LINEAR_SAMPLE;
865 break;
866
867 default:
868 return default_ij;
869 }
870
871 /* Otherwise, we have to select (i,j) based on a user data SGPR. */
872 sample_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, sample_param);
873
874 /* TODO: this can be done more efficiently by switching between
875 * 2 prologs.
876 */
877 force_sample = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
878 SI_PARAM_PS_STATE_BITS);
879 force_sample = LLVMBuildTrunc(gallivm->builder, force_sample,
880 LLVMInt1TypeInContext(gallivm->context), "");
881 return LLVMBuildSelect(gallivm->builder, force_sample,
882 sample_ij, default_ij, "");
883 }
884
885 static void declare_input_fs(
886 struct radeon_llvm_context *radeon_bld,
887 unsigned input_index,
888 const struct tgsi_full_declaration *decl)
889 {
890 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
891 struct si_shader_context *si_shader_ctx =
892 si_shader_context(&radeon_bld->soa.bld_base);
893 struct si_shader *shader = si_shader_ctx->shader;
894 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
895 struct gallivm_state *gallivm = base->gallivm;
896 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
897 LLVMValueRef main_fn = radeon_bld->main_fn;
898
899 LLVMValueRef interp_param = NULL;
900 int interp_param_idx;
901 const char * intr_name;
902
903 /* This value is:
904 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
905 * quad begins a new primitive. Bit 0 always needs
906 * to be unset)
907 * [32:16] ParamOffset
908 *
909 */
910 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
911 LLVMValueRef attr_number;
912
913 unsigned chan;
914
915 shader->ps_input_param_offset[input_index] = shader->nparam++;
916 attr_number = lp_build_const_int32(gallivm,
917 shader->ps_input_param_offset[input_index]);
918
919 shader->ps_input_interpolate[input_index] = decl->Interp.Interpolate;
920 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
921 decl->Interp.Location);
922 if (interp_param_idx == -1)
923 return;
924 else if (interp_param_idx)
925 interp_param = get_interp_param(si_shader_ctx, interp_param_idx);
926
927 /* fs.constant returns the param from the middle vertex, so it's not
928 * really useful for flat shading. It's meant to be used for custom
929 * interpolation (but the intrinsic can't fetch from the other two
930 * vertices).
931 *
932 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
933 * to do the right thing. The only reason we use fs.constant is that
934 * fs.interp cannot be used on integers, because they can be equal
935 * to NaN.
936 */
937 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
938
939 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
940 si_shader_ctx->shader->key.ps.color_two_side) {
941 LLVMValueRef args[4];
942 LLVMValueRef face, is_face_positive;
943 LLVMValueRef back_attr_number =
944 lp_build_const_int32(gallivm,
945 shader->ps_input_param_offset[input_index] + 1);
946
947 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
948
949 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
950 face, uint->zero, "");
951
952 args[2] = params;
953 args[3] = interp_param;
954 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
955 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
956 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
957 LLVMValueRef front, back;
958
959 args[0] = llvm_chan;
960 args[1] = attr_number;
961 front = lp_build_intrinsic(gallivm->builder, intr_name,
962 input_type, args, args[3] ? 4 : 3,
963 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
964
965 args[1] = back_attr_number;
966 back = lp_build_intrinsic(gallivm->builder, intr_name,
967 input_type, args, args[3] ? 4 : 3,
968 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
969
970 radeon_bld->inputs[soa_index] =
971 LLVMBuildSelect(gallivm->builder,
972 is_face_positive,
973 front,
974 back,
975 "");
976 }
977
978 shader->nparam++;
979 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
980 LLVMValueRef args[4];
981
982 args[0] = uint->zero;
983 args[1] = attr_number;
984 args[2] = params;
985 args[3] = interp_param;
986 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
987 lp_build_intrinsic(gallivm->builder, intr_name,
988 input_type, args, args[3] ? 4 : 3,
989 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
990 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
991 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
992 lp_build_const_float(gallivm, 0.0f);
993 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
994 lp_build_const_float(gallivm, 1.0f);
995 } else {
996 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
997 LLVMValueRef args[4];
998 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
999 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
1000 args[0] = llvm_chan;
1001 args[1] = attr_number;
1002 args[2] = params;
1003 args[3] = interp_param;
1004 radeon_bld->inputs[soa_index] =
1005 lp_build_intrinsic(gallivm->builder, intr_name,
1006 input_type, args, args[3] ? 4 : 3,
1007 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1008 }
1009 }
1010 }
1011
1012 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1013 {
1014 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1015 SI_PARAM_ANCILLARY, 8, 4);
1016 }
1017
1018 /**
1019 * Load a dword from a constant buffer.
1020 */
1021 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1022 LLVMValueRef offset, LLVMTypeRef return_type)
1023 {
1024 LLVMValueRef args[2] = {resource, offset};
1025
1026 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1027 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1028 }
1029
1030 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1031 {
1032 struct si_shader_context *si_shader_ctx =
1033 si_shader_context(&radeon_bld->soa.bld_base);
1034 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1035 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1036 LLVMBuilderRef builder = gallivm->builder;
1037 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1038 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1039 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
1040
1041 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1042 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1043 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1044
1045 LLVMValueRef pos[4] = {
1046 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
1047 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
1048 lp_build_const_float(gallivm, 0),
1049 lp_build_const_float(gallivm, 0)
1050 };
1051
1052 return lp_build_gather_values(gallivm, pos, 4);
1053 }
1054
1055 static void declare_system_value(
1056 struct radeon_llvm_context * radeon_bld,
1057 unsigned index,
1058 const struct tgsi_full_declaration *decl)
1059 {
1060 struct si_shader_context *si_shader_ctx =
1061 si_shader_context(&radeon_bld->soa.bld_base);
1062 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1063 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1064 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1065 LLVMValueRef value = 0;
1066
1067 switch (decl->Semantic.Name) {
1068 case TGSI_SEMANTIC_INSTANCEID:
1069 value = LLVMGetParam(radeon_bld->main_fn,
1070 si_shader_ctx->param_instance_id);
1071 break;
1072
1073 case TGSI_SEMANTIC_VERTEXID:
1074 value = LLVMBuildAdd(gallivm->builder,
1075 LLVMGetParam(radeon_bld->main_fn,
1076 si_shader_ctx->param_vertex_id),
1077 LLVMGetParam(radeon_bld->main_fn,
1078 SI_PARAM_BASE_VERTEX), "");
1079 break;
1080
1081 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1082 value = LLVMGetParam(radeon_bld->main_fn,
1083 si_shader_ctx->param_vertex_id);
1084 break;
1085
1086 case TGSI_SEMANTIC_BASEVERTEX:
1087 value = LLVMGetParam(radeon_bld->main_fn,
1088 SI_PARAM_BASE_VERTEX);
1089 break;
1090
1091 case TGSI_SEMANTIC_INVOCATIONID:
1092 if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1093 value = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1094 else if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY)
1095 value = LLVMGetParam(radeon_bld->main_fn,
1096 SI_PARAM_GS_INSTANCE_ID);
1097 else
1098 assert(!"INVOCATIONID not implemented");
1099 break;
1100
1101 case TGSI_SEMANTIC_POSITION:
1102 {
1103 LLVMValueRef pos[4] = {
1104 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1105 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1106 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1107 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1108 LLVMGetParam(radeon_bld->main_fn,
1109 SI_PARAM_POS_W_FLOAT)),
1110 };
1111 value = lp_build_gather_values(gallivm, pos, 4);
1112 break;
1113 }
1114
1115 case TGSI_SEMANTIC_FACE:
1116 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1117 break;
1118
1119 case TGSI_SEMANTIC_SAMPLEID:
1120 value = get_sample_id(radeon_bld);
1121 break;
1122
1123 case TGSI_SEMANTIC_SAMPLEPOS: {
1124 LLVMValueRef pos[4] = {
1125 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1126 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1127 lp_build_const_float(gallivm, 0),
1128 lp_build_const_float(gallivm, 0)
1129 };
1130 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1131 TGSI_OPCODE_FRC, pos[0]);
1132 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1133 TGSI_OPCODE_FRC, pos[1]);
1134 value = lp_build_gather_values(gallivm, pos, 4);
1135 break;
1136 }
1137
1138 case TGSI_SEMANTIC_SAMPLEMASK:
1139 /* Smoothing isn't MSAA in GL, but it's MSAA in hardware.
1140 * Therefore, force gl_SampleMaskIn to 1 for GL. */
1141 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
1142 value = uint_bld->one;
1143 else
1144 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1145 break;
1146
1147 case TGSI_SEMANTIC_TESSCOORD:
1148 {
1149 LLVMValueRef coord[4] = {
1150 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_u),
1151 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_v),
1152 bld->zero,
1153 bld->zero
1154 };
1155
1156 /* For triangles, the vector should be (u, v, 1-u-v). */
1157 if (si_shader_ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1158 PIPE_PRIM_TRIANGLES)
1159 coord[2] = lp_build_sub(bld, bld->one,
1160 lp_build_add(bld, coord[0], coord[1]));
1161
1162 value = lp_build_gather_values(gallivm, coord, 4);
1163 break;
1164 }
1165
1166 case TGSI_SEMANTIC_VERTICESIN:
1167 value = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1168 break;
1169
1170 case TGSI_SEMANTIC_TESSINNER:
1171 case TGSI_SEMANTIC_TESSOUTER:
1172 {
1173 LLVMValueRef dw_addr;
1174 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1175
1176 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1177 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1178 lp_build_const_int32(gallivm, param * 4), "");
1179
1180 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1181 ~0, dw_addr);
1182 break;
1183 }
1184
1185 case TGSI_SEMANTIC_PRIMID:
1186 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1187 break;
1188
1189 default:
1190 assert(!"unknown system value");
1191 return;
1192 }
1193
1194 radeon_bld->system_values[index] = value;
1195 }
1196
1197 static LLVMValueRef fetch_constant(
1198 struct lp_build_tgsi_context * bld_base,
1199 const struct tgsi_full_src_register *reg,
1200 enum tgsi_opcode_type type,
1201 unsigned swizzle)
1202 {
1203 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1204 struct lp_build_context * base = &bld_base->base;
1205 const struct tgsi_ind_register *ireg = &reg->Indirect;
1206 unsigned buf, idx;
1207
1208 LLVMValueRef addr, bufp;
1209 LLVMValueRef result;
1210
1211 if (swizzle == LP_CHAN_ALL) {
1212 unsigned chan;
1213 LLVMValueRef values[4];
1214 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1215 values[chan] = fetch_constant(bld_base, reg, type, chan);
1216
1217 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1218 }
1219
1220 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1221 idx = reg->Register.Index * 4 + swizzle;
1222
1223 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1224 if (type != TGSI_TYPE_DOUBLE)
1225 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
1226 else {
1227 return radeon_llvm_emit_fetch_double(bld_base,
1228 si_shader_ctx->constants[buf][idx],
1229 si_shader_ctx->constants[buf][idx + 1]);
1230 }
1231 }
1232
1233 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1234 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1235 LLVMValueRef index;
1236 index = get_indirect_index(si_shader_ctx, &reg->DimIndirect,
1237 reg->Dimension.Index);
1238 bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
1239 } else
1240 bufp = si_shader_ctx->const_buffers[buf];
1241
1242 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1243 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1244 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1245 addr = lp_build_add(&bld_base->uint_bld, addr,
1246 lp_build_const_int32(base->gallivm, idx * 4));
1247
1248 result = buffer_load_const(base->gallivm->builder, bufp,
1249 addr, bld_base->base.elem_type);
1250
1251 if (type != TGSI_TYPE_DOUBLE)
1252 result = bitcast(bld_base, type, result);
1253 else {
1254 LLVMValueRef addr2, result2;
1255 addr2 = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1256 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1257 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1258 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1259 lp_build_const_int32(base->gallivm, idx * 4));
1260
1261 result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_buffers[buf],
1262 addr2, bld_base->base.elem_type);
1263
1264 result = radeon_llvm_emit_fetch_double(bld_base,
1265 result, result2);
1266 }
1267 return result;
1268 }
1269
1270 /* Upper 16 bits must be zero. */
1271 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1272 LLVMValueRef val[2])
1273 {
1274 return LLVMBuildOr(gallivm->builder, val[0],
1275 LLVMBuildShl(gallivm->builder, val[1],
1276 lp_build_const_int32(gallivm, 16),
1277 ""), "");
1278 }
1279
1280 /* Upper 16 bits are ignored and will be dropped. */
1281 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1282 LLVMValueRef val[2])
1283 {
1284 LLVMValueRef v[2] = {
1285 LLVMBuildAnd(gallivm->builder, val[0],
1286 lp_build_const_int32(gallivm, 0xffff), ""),
1287 val[1],
1288 };
1289 return si_llvm_pack_two_int16(gallivm, v);
1290 }
1291
1292 /* Initialize arguments for the shader export intrinsic */
1293 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1294 LLVMValueRef *values,
1295 unsigned target,
1296 LLVMValueRef *args)
1297 {
1298 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1299 struct lp_build_context *uint =
1300 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1301 struct lp_build_context *base = &bld_base->base;
1302 struct gallivm_state *gallivm = base->gallivm;
1303 LLVMBuilderRef builder = base->gallivm->builder;
1304 LLVMValueRef val[4];
1305 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1306 unsigned chan;
1307 bool is_int8;
1308
1309 /* Default is 0xf. Adjusted below depending on the format. */
1310 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1311
1312 /* Specify whether the EXEC mask represents the valid mask */
1313 args[1] = uint->zero;
1314
1315 /* Specify whether this is the last export */
1316 args[2] = uint->zero;
1317
1318 /* Specify the target we are exporting */
1319 args[3] = lp_build_const_int32(base->gallivm, target);
1320
1321 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1322 const union si_shader_key *key = &si_shader_ctx->shader->key;
1323 unsigned col_formats = key->ps.spi_shader_col_format;
1324 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1325
1326 assert(cbuf >= 0 && cbuf < 8);
1327 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1328 is_int8 = (key->ps.color_is_int8 >> cbuf) & 0x1;
1329 }
1330
1331 args[4] = uint->zero; /* COMPR flag */
1332 args[5] = base->undef;
1333 args[6] = base->undef;
1334 args[7] = base->undef;
1335 args[8] = base->undef;
1336
1337 switch (spi_shader_col_format) {
1338 case V_028714_SPI_SHADER_ZERO:
1339 args[0] = uint->zero; /* writemask */
1340 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1341 break;
1342
1343 case V_028714_SPI_SHADER_32_R:
1344 args[0] = uint->one; /* writemask */
1345 args[5] = values[0];
1346 break;
1347
1348 case V_028714_SPI_SHADER_32_GR:
1349 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1350 args[5] = values[0];
1351 args[6] = values[1];
1352 break;
1353
1354 case V_028714_SPI_SHADER_32_AR:
1355 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1356 args[5] = values[0];
1357 args[8] = values[3];
1358 break;
1359
1360 case V_028714_SPI_SHADER_FP16_ABGR:
1361 args[4] = uint->one; /* COMPR flag */
1362
1363 for (chan = 0; chan < 2; chan++) {
1364 LLVMValueRef pack_args[2] = {
1365 values[2 * chan],
1366 values[2 * chan + 1]
1367 };
1368 LLVMValueRef packed;
1369
1370 packed = lp_build_intrinsic(base->gallivm->builder,
1371 "llvm.SI.packf16",
1372 uint->elem_type, pack_args, 2,
1373 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1374 args[chan + 5] =
1375 LLVMBuildBitCast(base->gallivm->builder,
1376 packed, base->elem_type, "");
1377 }
1378 break;
1379
1380 case V_028714_SPI_SHADER_UNORM16_ABGR:
1381 for (chan = 0; chan < 4; chan++) {
1382 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
1383 val[chan] = LLVMBuildFMul(builder, val[chan],
1384 lp_build_const_float(gallivm, 65535), "");
1385 val[chan] = LLVMBuildFAdd(builder, val[chan],
1386 lp_build_const_float(gallivm, 0.5), "");
1387 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1388 uint->elem_type, "");
1389 }
1390
1391 args[4] = uint->one; /* COMPR flag */
1392 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1393 si_llvm_pack_two_int16(gallivm, val));
1394 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1395 si_llvm_pack_two_int16(gallivm, val+2));
1396 break;
1397
1398 case V_028714_SPI_SHADER_SNORM16_ABGR:
1399 for (chan = 0; chan < 4; chan++) {
1400 /* Clamp between [-1, 1]. */
1401 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1402 values[chan],
1403 lp_build_const_float(gallivm, 1));
1404 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1405 val[chan],
1406 lp_build_const_float(gallivm, -1));
1407 /* Convert to a signed integer in [-32767, 32767]. */
1408 val[chan] = LLVMBuildFMul(builder, val[chan],
1409 lp_build_const_float(gallivm, 32767), "");
1410 /* If positive, add 0.5, else add -0.5. */
1411 val[chan] = LLVMBuildFAdd(builder, val[chan],
1412 LLVMBuildSelect(builder,
1413 LLVMBuildFCmp(builder, LLVMRealOGE,
1414 val[chan], base->zero, ""),
1415 lp_build_const_float(gallivm, 0.5),
1416 lp_build_const_float(gallivm, -0.5), ""), "");
1417 val[chan] = LLVMBuildFPToSI(builder, val[chan], uint->elem_type, "");
1418 }
1419
1420 args[4] = uint->one; /* COMPR flag */
1421 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1422 si_llvm_pack_two_int32_as_int16(gallivm, val));
1423 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1424 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1425 break;
1426
1427 case V_028714_SPI_SHADER_UINT16_ABGR: {
1428 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1429 255 : 65535);
1430 /* Clamp. */
1431 for (chan = 0; chan < 4; chan++) {
1432 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1433 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1434 val[chan], max);
1435 }
1436
1437 args[4] = uint->one; /* COMPR flag */
1438 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1439 si_llvm_pack_two_int16(gallivm, val));
1440 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1441 si_llvm_pack_two_int16(gallivm, val+2));
1442 break;
1443 }
1444
1445 case V_028714_SPI_SHADER_SINT16_ABGR: {
1446 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1447 127 : 32767);
1448 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
1449 -128 : -32768);
1450 /* Clamp. */
1451 for (chan = 0; chan < 4; chan++) {
1452 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1453 val[chan] = lp_build_emit_llvm_binary(bld_base,
1454 TGSI_OPCODE_IMIN,
1455 val[chan], max);
1456 val[chan] = lp_build_emit_llvm_binary(bld_base,
1457 TGSI_OPCODE_IMAX,
1458 val[chan], min);
1459 }
1460
1461 args[4] = uint->one; /* COMPR flag */
1462 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1463 si_llvm_pack_two_int32_as_int16(gallivm, val));
1464 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1465 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1466 break;
1467 }
1468
1469 case V_028714_SPI_SHADER_32_ABGR:
1470 memcpy(&args[5], values, sizeof(values[0]) * 4);
1471 break;
1472 }
1473 }
1474
1475 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1476 LLVMValueRef alpha)
1477 {
1478 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1479 struct gallivm_state *gallivm = bld_base->base.gallivm;
1480
1481 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
1482 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1483 SI_PARAM_ALPHA_REF);
1484
1485 LLVMValueRef alpha_pass =
1486 lp_build_cmp(&bld_base->base,
1487 si_shader_ctx->shader->key.ps.alpha_func,
1488 alpha, alpha_ref);
1489 LLVMValueRef arg =
1490 lp_build_select(&bld_base->base,
1491 alpha_pass,
1492 lp_build_const_float(gallivm, 1.0f),
1493 lp_build_const_float(gallivm, -1.0f));
1494
1495 lp_build_intrinsic(gallivm->builder,
1496 "llvm.AMDGPU.kill",
1497 LLVMVoidTypeInContext(gallivm->context),
1498 &arg, 1, 0);
1499 } else {
1500 lp_build_intrinsic(gallivm->builder,
1501 "llvm.AMDGPU.kilp",
1502 LLVMVoidTypeInContext(gallivm->context),
1503 NULL, 0, 0);
1504 }
1505 }
1506
1507 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1508 LLVMValueRef alpha)
1509 {
1510 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1511 struct gallivm_state *gallivm = bld_base->base.gallivm;
1512 LLVMValueRef coverage;
1513
1514 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1515 coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1516 SI_PARAM_SAMPLE_COVERAGE);
1517 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1518
1519 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1520 bld_base->int_bld.elem_type,
1521 &coverage, 1, LLVMReadNoneAttribute);
1522
1523 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1524 bld_base->base.elem_type, "");
1525
1526 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1527 lp_build_const_float(gallivm,
1528 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1529
1530 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1531 }
1532
1533 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
1534 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1535 {
1536 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1537 struct lp_build_context *base = &bld_base->base;
1538 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1539 unsigned reg_index;
1540 unsigned chan;
1541 unsigned const_chan;
1542 LLVMValueRef base_elt;
1543 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1544 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1545 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
1546
1547 for (reg_index = 0; reg_index < 2; reg_index ++) {
1548 LLVMValueRef *args = pos[2 + reg_index];
1549
1550 args[5] =
1551 args[6] =
1552 args[7] =
1553 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1554
1555 /* Compute dot products of position and user clip plane vectors */
1556 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1557 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1558 args[1] = lp_build_const_int32(base->gallivm,
1559 ((reg_index * 4 + chan) * 4 +
1560 const_chan) * 4);
1561 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1562 args[1], base->elem_type);
1563 args[5 + chan] =
1564 lp_build_add(base, args[5 + chan],
1565 lp_build_mul(base, base_elt,
1566 out_elts[const_chan]));
1567 }
1568 }
1569
1570 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1571 args[1] = uint->zero;
1572 args[2] = uint->zero;
1573 args[3] = lp_build_const_int32(base->gallivm,
1574 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1575 args[4] = uint->zero;
1576 }
1577 }
1578
1579 static void si_dump_streamout(struct pipe_stream_output_info *so)
1580 {
1581 unsigned i;
1582
1583 if (so->num_outputs)
1584 fprintf(stderr, "STREAMOUT\n");
1585
1586 for (i = 0; i < so->num_outputs; i++) {
1587 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1588 so->output[i].start_component;
1589 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1590 i, so->output[i].output_buffer,
1591 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1592 so->output[i].register_index,
1593 mask & 1 ? "x" : "",
1594 mask & 2 ? "y" : "",
1595 mask & 4 ? "z" : "",
1596 mask & 8 ? "w" : "");
1597 }
1598 }
1599
1600 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1601 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1602 * or v4i32 (num_channels=3,4). */
1603 static void build_tbuffer_store(struct si_shader_context *shader,
1604 LLVMValueRef rsrc,
1605 LLVMValueRef vdata,
1606 unsigned num_channels,
1607 LLVMValueRef vaddr,
1608 LLVMValueRef soffset,
1609 unsigned inst_offset,
1610 unsigned dfmt,
1611 unsigned nfmt,
1612 unsigned offen,
1613 unsigned idxen,
1614 unsigned glc,
1615 unsigned slc,
1616 unsigned tfe)
1617 {
1618 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1619 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1620 LLVMValueRef args[] = {
1621 rsrc,
1622 vdata,
1623 LLVMConstInt(i32, num_channels, 0),
1624 vaddr,
1625 soffset,
1626 LLVMConstInt(i32, inst_offset, 0),
1627 LLVMConstInt(i32, dfmt, 0),
1628 LLVMConstInt(i32, nfmt, 0),
1629 LLVMConstInt(i32, offen, 0),
1630 LLVMConstInt(i32, idxen, 0),
1631 LLVMConstInt(i32, glc, 0),
1632 LLVMConstInt(i32, slc, 0),
1633 LLVMConstInt(i32, tfe, 0)
1634 };
1635
1636 /* The instruction offset field has 12 bits */
1637 assert(offen || inst_offset < (1 << 12));
1638
1639 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1640 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1641 const char *types[] = {"i32", "v2i32", "v4i32"};
1642 char name[256];
1643 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1644
1645 lp_build_intrinsic(gallivm->builder, name,
1646 LLVMVoidTypeInContext(gallivm->context),
1647 args, Elements(args), 0);
1648 }
1649
1650 static void build_tbuffer_store_dwords(struct si_shader_context *shader,
1651 LLVMValueRef rsrc,
1652 LLVMValueRef vdata,
1653 unsigned num_channels,
1654 LLVMValueRef vaddr,
1655 LLVMValueRef soffset,
1656 unsigned inst_offset)
1657 {
1658 static unsigned dfmt[] = {
1659 V_008F0C_BUF_DATA_FORMAT_32,
1660 V_008F0C_BUF_DATA_FORMAT_32_32,
1661 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1662 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1663 };
1664 assert(num_channels >= 1 && num_channels <= 4);
1665
1666 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
1667 inst_offset, dfmt[num_channels-1],
1668 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1669 }
1670
1671 /* On SI, the vertex shader is responsible for writing streamout data
1672 * to buffers. */
1673 static void si_llvm_emit_streamout(struct si_shader_context *shader,
1674 struct si_shader_output_values *outputs,
1675 unsigned noutput)
1676 {
1677 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1678 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1679 LLVMBuilderRef builder = gallivm->builder;
1680 int i, j;
1681 struct lp_build_if_state if_ctx;
1682
1683 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1684
1685 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1686 LLVMValueRef so_vtx_count =
1687 unpack_param(shader, shader->param_streamout_config, 16, 7);
1688
1689 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", i32,
1690 NULL, 0, LLVMReadNoneAttribute);
1691
1692 /* can_emit = tid < so_vtx_count; */
1693 LLVMValueRef can_emit =
1694 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1695
1696 LLVMValueRef stream_id =
1697 unpack_param(shader, shader->param_streamout_config, 24, 2);
1698
1699 /* Emit the streamout code conditionally. This actually avoids
1700 * out-of-bounds buffer access. The hw tells us via the SGPR
1701 * (so_vtx_count) which threads are allowed to emit streamout data. */
1702 lp_build_if(&if_ctx, gallivm, can_emit);
1703 {
1704 /* The buffer offset is computed as follows:
1705 * ByteOffset = streamout_offset[buffer_id]*4 +
1706 * (streamout_write_index + thread_id)*stride[buffer_id] +
1707 * attrib_offset
1708 */
1709
1710 LLVMValueRef so_write_index =
1711 LLVMGetParam(shader->radeon_bld.main_fn,
1712 shader->param_streamout_write_index);
1713
1714 /* Compute (streamout_write_index + thread_id). */
1715 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1716
1717 /* Compute the write offset for each enabled buffer. */
1718 LLVMValueRef so_write_offset[4] = {};
1719 for (i = 0; i < 4; i++) {
1720 if (!so->stride[i])
1721 continue;
1722
1723 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1724 shader->param_streamout_offset[i]);
1725 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1726
1727 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1728 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1729 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1730 }
1731
1732 /* Write streamout data. */
1733 for (i = 0; i < so->num_outputs; i++) {
1734 unsigned buf_idx = so->output[i].output_buffer;
1735 unsigned reg = so->output[i].register_index;
1736 unsigned start = so->output[i].start_component;
1737 unsigned num_comps = so->output[i].num_components;
1738 unsigned stream = so->output[i].stream;
1739 LLVMValueRef out[4];
1740 struct lp_build_if_state if_ctx_stream;
1741
1742 assert(num_comps && num_comps <= 4);
1743 if (!num_comps || num_comps > 4)
1744 continue;
1745
1746 if (reg >= noutput)
1747 continue;
1748
1749 /* Load the output as int. */
1750 for (j = 0; j < num_comps; j++) {
1751 out[j] = LLVMBuildBitCast(builder,
1752 outputs[reg].values[start+j],
1753 i32, "");
1754 }
1755
1756 /* Pack the output. */
1757 LLVMValueRef vdata = NULL;
1758
1759 switch (num_comps) {
1760 case 1: /* as i32 */
1761 vdata = out[0];
1762 break;
1763 case 2: /* as v2i32 */
1764 case 3: /* as v4i32 (aligned to 4) */
1765 case 4: /* as v4i32 */
1766 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1767 for (j = 0; j < num_comps; j++) {
1768 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1769 LLVMConstInt(i32, j, 0), "");
1770 }
1771 break;
1772 }
1773
1774 LLVMValueRef can_emit_stream =
1775 LLVMBuildICmp(builder, LLVMIntEQ,
1776 stream_id,
1777 lp_build_const_int32(gallivm, stream), "");
1778
1779 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1780 build_tbuffer_store_dwords(shader, shader->so_buffers[buf_idx],
1781 vdata, num_comps,
1782 so_write_offset[buf_idx],
1783 LLVMConstInt(i32, 0, 0),
1784 so->output[i].dst_offset*4);
1785 lp_build_endif(&if_ctx_stream);
1786 }
1787 }
1788 lp_build_endif(&if_ctx);
1789 }
1790
1791
1792 /* Generate export instructions for hardware VS shader stage */
1793 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1794 struct si_shader_output_values *outputs,
1795 unsigned noutput)
1796 {
1797 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1798 struct si_shader * shader = si_shader_ctx->shader;
1799 struct lp_build_context * base = &bld_base->base;
1800 struct lp_build_context * uint =
1801 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1802 LLVMValueRef args[9];
1803 LLVMValueRef pos_args[4][9] = { { 0 } };
1804 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1805 unsigned semantic_name, semantic_index;
1806 unsigned target;
1807 unsigned param_count = 0;
1808 unsigned pos_idx;
1809 int i;
1810
1811 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1812 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1813 }
1814
1815 for (i = 0; i < noutput; i++) {
1816 semantic_name = outputs[i].name;
1817 semantic_index = outputs[i].sid;
1818
1819 handle_semantic:
1820 /* Select the correct target */
1821 switch(semantic_name) {
1822 case TGSI_SEMANTIC_PSIZE:
1823 psize_value = outputs[i].values[0];
1824 continue;
1825 case TGSI_SEMANTIC_EDGEFLAG:
1826 edgeflag_value = outputs[i].values[0];
1827 continue;
1828 case TGSI_SEMANTIC_LAYER:
1829 layer_value = outputs[i].values[0];
1830 semantic_name = TGSI_SEMANTIC_GENERIC;
1831 goto handle_semantic;
1832 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1833 viewport_index_value = outputs[i].values[0];
1834 semantic_name = TGSI_SEMANTIC_GENERIC;
1835 goto handle_semantic;
1836 case TGSI_SEMANTIC_POSITION:
1837 target = V_008DFC_SQ_EXP_POS;
1838 break;
1839 case TGSI_SEMANTIC_COLOR:
1840 case TGSI_SEMANTIC_BCOLOR:
1841 target = V_008DFC_SQ_EXP_PARAM + param_count;
1842 shader->vs_output_param_offset[i] = param_count;
1843 param_count++;
1844 break;
1845 case TGSI_SEMANTIC_CLIPDIST:
1846 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1847 break;
1848 case TGSI_SEMANTIC_CLIPVERTEX:
1849 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1850 continue;
1851 case TGSI_SEMANTIC_PRIMID:
1852 case TGSI_SEMANTIC_FOG:
1853 case TGSI_SEMANTIC_TEXCOORD:
1854 case TGSI_SEMANTIC_GENERIC:
1855 target = V_008DFC_SQ_EXP_PARAM + param_count;
1856 shader->vs_output_param_offset[i] = param_count;
1857 param_count++;
1858 break;
1859 default:
1860 target = 0;
1861 fprintf(stderr,
1862 "Warning: SI unhandled vs output type:%d\n",
1863 semantic_name);
1864 }
1865
1866 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1867
1868 if (target >= V_008DFC_SQ_EXP_POS &&
1869 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1870 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1871 args, sizeof(args));
1872 } else {
1873 lp_build_intrinsic(base->gallivm->builder,
1874 "llvm.SI.export",
1875 LLVMVoidTypeInContext(base->gallivm->context),
1876 args, 9, 0);
1877 }
1878
1879 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1880 semantic_name = TGSI_SEMANTIC_GENERIC;
1881 goto handle_semantic;
1882 }
1883 }
1884
1885 shader->nr_param_exports = param_count;
1886
1887 /* We need to add the position output manually if it's missing. */
1888 if (!pos_args[0][0]) {
1889 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1890 pos_args[0][1] = uint->zero; /* EXEC mask */
1891 pos_args[0][2] = uint->zero; /* last export? */
1892 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1893 pos_args[0][4] = uint->zero; /* COMPR flag */
1894 pos_args[0][5] = base->zero; /* X */
1895 pos_args[0][6] = base->zero; /* Y */
1896 pos_args[0][7] = base->zero; /* Z */
1897 pos_args[0][8] = base->one; /* W */
1898 }
1899
1900 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1901 if (shader->selector->info.writes_psize ||
1902 shader->selector->info.writes_edgeflag ||
1903 shader->selector->info.writes_viewport_index ||
1904 shader->selector->info.writes_layer) {
1905 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1906 shader->selector->info.writes_psize |
1907 (shader->selector->info.writes_edgeflag << 1) |
1908 (shader->selector->info.writes_layer << 2) |
1909 (shader->selector->info.writes_viewport_index << 3));
1910 pos_args[1][1] = uint->zero; /* EXEC mask */
1911 pos_args[1][2] = uint->zero; /* last export? */
1912 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1913 pos_args[1][4] = uint->zero; /* COMPR flag */
1914 pos_args[1][5] = base->zero; /* X */
1915 pos_args[1][6] = base->zero; /* Y */
1916 pos_args[1][7] = base->zero; /* Z */
1917 pos_args[1][8] = base->zero; /* W */
1918
1919 if (shader->selector->info.writes_psize)
1920 pos_args[1][5] = psize_value;
1921
1922 if (shader->selector->info.writes_edgeflag) {
1923 /* The output is a float, but the hw expects an integer
1924 * with the first bit containing the edge flag. */
1925 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1926 edgeflag_value,
1927 bld_base->uint_bld.elem_type, "");
1928 edgeflag_value = lp_build_min(&bld_base->int_bld,
1929 edgeflag_value,
1930 bld_base->int_bld.one);
1931
1932 /* The LLVM intrinsic expects a float. */
1933 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1934 edgeflag_value,
1935 base->elem_type, "");
1936 }
1937
1938 if (shader->selector->info.writes_layer)
1939 pos_args[1][7] = layer_value;
1940
1941 if (shader->selector->info.writes_viewport_index)
1942 pos_args[1][8] = viewport_index_value;
1943 }
1944
1945 for (i = 0; i < 4; i++)
1946 if (pos_args[i][0])
1947 shader->nr_pos_exports++;
1948
1949 pos_idx = 0;
1950 for (i = 0; i < 4; i++) {
1951 if (!pos_args[i][0])
1952 continue;
1953
1954 /* Specify the target we are exporting */
1955 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1956
1957 if (pos_idx == shader->nr_pos_exports)
1958 /* Specify that this is the last export */
1959 pos_args[i][2] = uint->one;
1960
1961 lp_build_intrinsic(base->gallivm->builder,
1962 "llvm.SI.export",
1963 LLVMVoidTypeInContext(base->gallivm->context),
1964 pos_args[i], 9, 0);
1965 }
1966 }
1967
1968 /* This only writes the tessellation factor levels. */
1969 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
1970 {
1971 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1972 struct gallivm_state *gallivm = bld_base->base.gallivm;
1973 struct si_shader *shader = si_shader_ctx->shader;
1974 unsigned tess_inner_index, tess_outer_index;
1975 LLVMValueRef lds_base, lds_inner, lds_outer;
1976 LLVMValueRef tf_base, rel_patch_id, byteoffset, buffer, rw_buffers;
1977 LLVMValueRef out[6], vec0, vec1, invocation_id;
1978 unsigned stride, outer_comps, inner_comps, i;
1979 struct lp_build_if_state if_ctx;
1980
1981 invocation_id = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1982
1983 /* Do this only for invocation 0, because the tess levels are per-patch,
1984 * not per-vertex.
1985 *
1986 * This can't jump, because invocation 0 executes this. It should
1987 * at least mask out the loads and stores for other invocations.
1988 */
1989 lp_build_if(&if_ctx, gallivm,
1990 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
1991 invocation_id, bld_base->uint_bld.zero, ""));
1992
1993 /* Determine the layout of one tess factor element in the buffer. */
1994 switch (shader->key.tcs.prim_mode) {
1995 case PIPE_PRIM_LINES:
1996 stride = 2; /* 2 dwords, 1 vec2 store */
1997 outer_comps = 2;
1998 inner_comps = 0;
1999 break;
2000 case PIPE_PRIM_TRIANGLES:
2001 stride = 4; /* 4 dwords, 1 vec4 store */
2002 outer_comps = 3;
2003 inner_comps = 1;
2004 break;
2005 case PIPE_PRIM_QUADS:
2006 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2007 outer_comps = 4;
2008 inner_comps = 2;
2009 break;
2010 default:
2011 assert(0);
2012 return;
2013 }
2014
2015 /* Load tess_inner and tess_outer from LDS.
2016 * Any invocation can write them, so we can't get them from a temporary.
2017 */
2018 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2019 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2020
2021 lds_base = get_tcs_out_current_patch_data_offset(si_shader_ctx);
2022 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2023 lp_build_const_int32(gallivm,
2024 tess_inner_index * 4), "");
2025 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2026 lp_build_const_int32(gallivm,
2027 tess_outer_index * 4), "");
2028
2029 for (i = 0; i < outer_comps; i++)
2030 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2031 for (i = 0; i < inner_comps; i++)
2032 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2033
2034 /* Convert the outputs to vectors for stores. */
2035 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2036 vec1 = NULL;
2037
2038 if (stride > 4)
2039 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2040
2041 /* Get the buffer. */
2042 rw_buffers = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2043 SI_PARAM_RW_BUFFERS);
2044 buffer = build_indexed_load_const(si_shader_ctx, rw_buffers,
2045 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
2046
2047 /* Get the offset. */
2048 tf_base = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2049 SI_PARAM_TESS_FACTOR_OFFSET);
2050 rel_patch_id = get_rel_patch_id(si_shader_ctx);
2051 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2052 lp_build_const_int32(gallivm, 4 * stride), "");
2053
2054 /* Store the outputs. */
2055 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec0,
2056 MIN2(stride, 4), byteoffset, tf_base, 0);
2057 if (vec1)
2058 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec1,
2059 stride - 4, byteoffset, tf_base, 16);
2060 lp_build_endif(&if_ctx);
2061 }
2062
2063 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context * bld_base)
2064 {
2065 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2066 struct si_shader *shader = si_shader_ctx->shader;
2067 struct tgsi_shader_info *info = &shader->selector->info;
2068 struct gallivm_state *gallivm = bld_base->base.gallivm;
2069 unsigned i, chan;
2070 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2071 si_shader_ctx->param_rel_auto_id);
2072 LLVMValueRef vertex_dw_stride =
2073 unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2074 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2075 vertex_dw_stride, "");
2076
2077 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2078 * its inputs from it. */
2079 for (i = 0; i < info->num_outputs; i++) {
2080 LLVMValueRef *out_ptr = si_shader_ctx->radeon_bld.soa.outputs[i];
2081 unsigned name = info->output_semantic_name[i];
2082 unsigned index = info->output_semantic_index[i];
2083 int param = si_shader_io_get_unique_index(name, index);
2084 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2085 lp_build_const_int32(gallivm, param * 4), "");
2086
2087 for (chan = 0; chan < 4; chan++) {
2088 lds_store(bld_base, chan, dw_addr,
2089 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2090 }
2091 }
2092 }
2093
2094 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
2095 {
2096 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2097 struct gallivm_state *gallivm = bld_base->base.gallivm;
2098 struct si_shader *es = si_shader_ctx->shader;
2099 struct tgsi_shader_info *info = &es->selector->info;
2100 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2101 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2102 si_shader_ctx->param_es2gs_offset);
2103 unsigned chan;
2104 int i;
2105
2106 for (i = 0; i < info->num_outputs; i++) {
2107 LLVMValueRef *out_ptr =
2108 si_shader_ctx->radeon_bld.soa.outputs[i];
2109 int param_index;
2110
2111 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2112 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2113 continue;
2114
2115 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2116 info->output_semantic_index[i]);
2117
2118 for (chan = 0; chan < 4; chan++) {
2119 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2120 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2121
2122 build_tbuffer_store(si_shader_ctx,
2123 si_shader_ctx->esgs_ring,
2124 out_val, 1,
2125 LLVMGetUndef(i32), soffset,
2126 (4 * param_index + chan) * 4,
2127 V_008F0C_BUF_DATA_FORMAT_32,
2128 V_008F0C_BUF_NUM_FORMAT_UINT,
2129 0, 0, 1, 1, 0);
2130 }
2131 }
2132 }
2133
2134 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2135 {
2136 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2137 struct gallivm_state *gallivm = bld_base->base.gallivm;
2138 LLVMValueRef args[2];
2139
2140 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2141 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2142 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2143 LLVMVoidTypeInContext(gallivm->context), args, 2,
2144 LLVMNoUnwindAttribute);
2145 }
2146
2147 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
2148 {
2149 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2150 struct gallivm_state *gallivm = bld_base->base.gallivm;
2151 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
2152 struct si_shader_output_values *outputs = NULL;
2153 int i,j;
2154
2155 assert(!si_shader_ctx->is_gs_copy_shader);
2156
2157 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2158
2159 /* Vertex color clamping.
2160 *
2161 * This uses a state constant loaded in a user data SGPR and
2162 * an IF statement is added that clamps all colors if the constant
2163 * is true.
2164 */
2165 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
2166 struct lp_build_if_state if_ctx;
2167 LLVMValueRef cond = NULL;
2168 LLVMValueRef addr, val;
2169
2170 for (i = 0; i < info->num_outputs; i++) {
2171 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2172 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2173 continue;
2174
2175 /* We've found a color. */
2176 if (!cond) {
2177 /* The state is in the first bit of the user SGPR. */
2178 cond = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2179 SI_PARAM_VS_STATE_BITS);
2180 cond = LLVMBuildTrunc(gallivm->builder, cond,
2181 LLVMInt1TypeInContext(gallivm->context), "");
2182 lp_build_if(&if_ctx, gallivm, cond);
2183 }
2184
2185 for (j = 0; j < 4; j++) {
2186 addr = si_shader_ctx->radeon_bld.soa.outputs[i][j];
2187 val = LLVMBuildLoad(gallivm->builder, addr, "");
2188 val = radeon_llvm_saturate(bld_base, val);
2189 LLVMBuildStore(gallivm->builder, val, addr);
2190 }
2191 }
2192
2193 if (cond)
2194 lp_build_endif(&if_ctx);
2195 }
2196
2197 for (i = 0; i < info->num_outputs; i++) {
2198 outputs[i].name = info->output_semantic_name[i];
2199 outputs[i].sid = info->output_semantic_index[i];
2200
2201 for (j = 0; j < 4; j++)
2202 outputs[i].values[j] =
2203 LLVMBuildLoad(gallivm->builder,
2204 si_shader_ctx->radeon_bld.soa.outputs[i][j],
2205 "");
2206 }
2207
2208 /* Export PrimitiveID when PS needs it. */
2209 if (si_vs_exports_prim_id(si_shader_ctx->shader)) {
2210 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2211 outputs[i].sid = 0;
2212 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2213 get_primitive_id(bld_base, 0));
2214 outputs[i].values[1] = bld_base->base.undef;
2215 outputs[i].values[2] = bld_base->base.undef;
2216 outputs[i].values[3] = bld_base->base.undef;
2217 i++;
2218 }
2219
2220 si_llvm_export_vs(bld_base, outputs, i);
2221 FREE(outputs);
2222 }
2223
2224 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2225 LLVMValueRef depth, LLVMValueRef stencil,
2226 LLVMValueRef samplemask)
2227 {
2228 struct si_screen *sscreen = si_shader_context(bld_base)->screen;
2229 struct lp_build_context *base = &bld_base->base;
2230 struct lp_build_context *uint = &bld_base->uint_bld;
2231 LLVMValueRef args[9];
2232 unsigned mask = 0;
2233
2234 assert(depth || stencil || samplemask);
2235
2236 args[1] = uint->one; /* whether the EXEC mask is valid */
2237 args[2] = uint->one; /* DONE bit */
2238
2239 /* Specify the target we are exporting */
2240 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2241
2242 args[4] = uint->zero; /* COMP flag */
2243 args[5] = base->undef; /* R, depth */
2244 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2245 args[7] = base->undef; /* B, sample mask */
2246 args[8] = base->undef; /* A, alpha to mask */
2247
2248 if (depth) {
2249 args[5] = depth;
2250 mask |= 0x1;
2251 }
2252
2253 if (stencil) {
2254 args[6] = stencil;
2255 mask |= 0x2;
2256 }
2257
2258 if (samplemask) {
2259 args[7] = samplemask;
2260 mask |= 0x4;
2261 }
2262
2263 /* SI (except OLAND) has a bug that it only looks
2264 * at the X writemask component. */
2265 if (sscreen->b.chip_class == SI &&
2266 sscreen->b.family != CHIP_OLAND)
2267 mask |= 0x1;
2268
2269 /* Specify which components to enable */
2270 args[0] = lp_build_const_int32(base->gallivm, mask);
2271
2272 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2273 LLVMVoidTypeInContext(base->gallivm->context),
2274 args, 9, 0);
2275 }
2276
2277 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2278 LLVMValueRef *color, unsigned index,
2279 bool is_last)
2280 {
2281 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2282 struct lp_build_context *base = &bld_base->base;
2283 LLVMValueRef args[9];
2284 int i;
2285
2286 /* Clamp color */
2287 if (si_shader_ctx->shader->key.ps.clamp_color)
2288 for (i = 0; i < 4; i++)
2289 color[i] = radeon_llvm_saturate(bld_base, color[i]);
2290
2291 /* Alpha to one */
2292 if (si_shader_ctx->shader->key.ps.alpha_to_one)
2293 color[3] = base->one;
2294
2295 /* Alpha test */
2296 if (index == 0 &&
2297 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
2298 si_alpha_test(bld_base, color[3]);
2299
2300 /* Line & polygon smoothing */
2301 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
2302 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3]);
2303
2304 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2305 if (index == 0 &&
2306 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
2307 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
2308 si_llvm_init_export_args(bld_base, color,
2309 V_008DFC_SQ_EXP_MRT + c, args);
2310 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2311 LLVMVoidTypeInContext(base->gallivm->context),
2312 args, 9, 0);
2313 }
2314 }
2315
2316 /* Export */
2317 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2318 args);
2319 if (is_last) {
2320 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2321 args[2] = bld_base->uint_bld.one; /* DONE bit */
2322 }
2323 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2324 LLVMVoidTypeInContext(base->gallivm->context),
2325 args, 9, 0);
2326 }
2327
2328 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2329 {
2330 struct lp_build_context *base = &bld_base->base;
2331 struct lp_build_context *uint = &bld_base->uint_bld;
2332 LLVMValueRef args[9];
2333
2334 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
2335 args[1] = uint->one; /* whether the EXEC mask is valid */
2336 args[2] = uint->one; /* DONE bit */
2337 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2338 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
2339 args[5] = uint->undef; /* R */
2340 args[6] = uint->undef; /* G */
2341 args[7] = uint->undef; /* B */
2342 args[8] = uint->undef; /* A */
2343
2344 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2345 LLVMVoidTypeInContext(base->gallivm->context),
2346 args, 9, 0);
2347 }
2348
2349 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
2350 {
2351 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
2352 struct si_shader * shader = si_shader_ctx->shader;
2353 struct lp_build_context * base = &bld_base->base;
2354 struct tgsi_shader_info *info = &shader->selector->info;
2355 LLVMBuilderRef builder = base->gallivm->builder;
2356 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2357 int last_color_export = -1;
2358 int i;
2359
2360 /* If there are no outputs, add a dummy export. */
2361 if (!info->num_outputs) {
2362 si_export_null(bld_base);
2363 return;
2364 }
2365
2366 /* Determine the last export. If MRTZ is present, it's always last.
2367 * Otherwise, find the last color export.
2368 */
2369 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask)
2370 for (i = 0; i < info->num_outputs; i++)
2371 if (info->output_semantic_name[i] == TGSI_SEMANTIC_COLOR)
2372 last_color_export = i;
2373
2374 for (i = 0; i < info->num_outputs; i++) {
2375 unsigned semantic_name = info->output_semantic_name[i];
2376 unsigned semantic_index = info->output_semantic_index[i];
2377 unsigned j;
2378 LLVMValueRef color[4] = {};
2379
2380 /* Select the correct target */
2381 switch (semantic_name) {
2382 case TGSI_SEMANTIC_POSITION:
2383 depth = LLVMBuildLoad(builder,
2384 si_shader_ctx->radeon_bld.soa.outputs[i][2], "");
2385 break;
2386 case TGSI_SEMANTIC_STENCIL:
2387 stencil = LLVMBuildLoad(builder,
2388 si_shader_ctx->radeon_bld.soa.outputs[i][1], "");
2389 break;
2390 case TGSI_SEMANTIC_SAMPLEMASK:
2391 samplemask = LLVMBuildLoad(builder,
2392 si_shader_ctx->radeon_bld.soa.outputs[i][0], "");
2393 break;
2394 case TGSI_SEMANTIC_COLOR:
2395 for (j = 0; j < 4; j++)
2396 color[j] = LLVMBuildLoad(builder,
2397 si_shader_ctx->radeon_bld.soa.outputs[i][j], "");
2398
2399 si_export_mrt_color(bld_base, color, semantic_index,
2400 last_color_export == i);
2401 break;
2402 default:
2403 fprintf(stderr,
2404 "Warning: SI unhandled fs output type:%d\n",
2405 semantic_name);
2406 }
2407 }
2408
2409 if (depth || stencil || samplemask)
2410 si_export_mrt_z(bld_base, depth, stencil, samplemask);
2411 }
2412
2413 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2414 struct lp_build_tgsi_context * bld_base,
2415 struct lp_build_emit_data * emit_data);
2416
2417 static bool tgsi_is_array_sampler(unsigned target)
2418 {
2419 return target == TGSI_TEXTURE_1D_ARRAY ||
2420 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2421 target == TGSI_TEXTURE_2D_ARRAY ||
2422 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2423 target == TGSI_TEXTURE_CUBE_ARRAY ||
2424 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2425 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2426 }
2427
2428 static void set_tex_fetch_args(struct gallivm_state *gallivm,
2429 struct lp_build_emit_data *emit_data,
2430 unsigned opcode, unsigned target,
2431 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
2432 LLVMValueRef *param, unsigned count,
2433 unsigned dmask)
2434 {
2435 unsigned num_args;
2436 unsigned is_rect = target == TGSI_TEXTURE_RECT;
2437 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2438
2439 /* Pad to power of two vector */
2440 while (count < util_next_power_of_two(count))
2441 param[count++] = LLVMGetUndef(i32);
2442
2443 /* Texture coordinates. */
2444 if (count > 1)
2445 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
2446 else
2447 emit_data->args[0] = param[0];
2448
2449 /* Resource. */
2450 emit_data->args[1] = res_ptr;
2451 num_args = 2;
2452
2453 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
2454 emit_data->dst_type = LLVMVectorType(i32, 4);
2455 else {
2456 emit_data->dst_type = LLVMVectorType(
2457 LLVMFloatTypeInContext(gallivm->context), 4);
2458
2459 emit_data->args[num_args++] = samp_ptr;
2460 }
2461
2462 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
2463 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
2464 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
2465 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
2466 tgsi_is_array_sampler(target)); /* da */
2467 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
2468 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
2469 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
2470 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
2471
2472 emit_data->arg_count = num_args;
2473 }
2474
2475 static const struct lp_build_tgsi_action tex_action;
2476
2477 static void tex_fetch_ptrs(
2478 struct lp_build_tgsi_context * bld_base,
2479 struct lp_build_emit_data * emit_data,
2480 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
2481 {
2482 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2483 struct gallivm_state *gallivm = bld_base->base.gallivm;
2484 const struct tgsi_full_instruction * inst = emit_data->inst;
2485 unsigned target = inst->Texture.Texture;
2486 unsigned sampler_src;
2487 unsigned sampler_index;
2488
2489 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
2490 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
2491
2492 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
2493 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
2494 LLVMValueRef ind_index;
2495
2496 ind_index = get_indirect_index(si_shader_ctx, &reg->Indirect, reg->Register.Index);
2497
2498 *res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
2499 *res_ptr = build_indexed_load_const(si_shader_ctx, *res_ptr, ind_index);
2500
2501 *samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
2502 *samp_ptr = build_indexed_load_const(si_shader_ctx, *samp_ptr, ind_index);
2503
2504 if (target == TGSI_TEXTURE_2D_MSAA ||
2505 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2506 ind_index = LLVMBuildAdd(gallivm->builder, ind_index,
2507 lp_build_const_int32(gallivm,
2508 SI_FMASK_TEX_OFFSET), "");
2509 *fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
2510 *fmask_ptr = build_indexed_load_const(si_shader_ctx, *fmask_ptr, ind_index);
2511 }
2512 } else {
2513 *res_ptr = si_shader_ctx->sampler_views[sampler_index];
2514 *samp_ptr = si_shader_ctx->sampler_states[sampler_index];
2515 *fmask_ptr = si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + sampler_index];
2516 }
2517 }
2518
2519 static void tex_fetch_args(
2520 struct lp_build_tgsi_context * bld_base,
2521 struct lp_build_emit_data * emit_data)
2522 {
2523 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2524 struct gallivm_state *gallivm = bld_base->base.gallivm;
2525 LLVMBuilderRef builder = gallivm->builder;
2526 const struct tgsi_full_instruction * inst = emit_data->inst;
2527 unsigned opcode = inst->Instruction.Opcode;
2528 unsigned target = inst->Texture.Texture;
2529 LLVMValueRef coords[5], derivs[6];
2530 LLVMValueRef address[16];
2531 int ref_pos;
2532 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
2533 unsigned count = 0;
2534 unsigned chan;
2535 unsigned num_deriv_channels = 0;
2536 bool has_offset = inst->Texture.NumOffsets > 0;
2537 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2538 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2539 unsigned dmask = 0xf;
2540
2541 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2542
2543 if (opcode == TGSI_OPCODE_TXQ) {
2544 if (target == TGSI_TEXTURE_BUFFER) {
2545 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2546
2547 /* Read the size from the buffer descriptor directly. */
2548 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2549 LLVMValueRef size = LLVMBuildExtractElement(builder, res,
2550 lp_build_const_int32(gallivm, 6), "");
2551
2552 if (si_shader_ctx->screen->b.chip_class >= VI) {
2553 /* On VI, the descriptor contains the size in bytes,
2554 * but TXQ must return the size in elements.
2555 * The stride is always non-zero for resources using TXQ.
2556 */
2557 LLVMValueRef stride =
2558 LLVMBuildExtractElement(builder, res,
2559 lp_build_const_int32(gallivm, 5), "");
2560 stride = LLVMBuildLShr(builder, stride,
2561 lp_build_const_int32(gallivm, 16), "");
2562 stride = LLVMBuildAnd(builder, stride,
2563 lp_build_const_int32(gallivm, 0x3FFF), "");
2564
2565 size = LLVMBuildUDiv(builder, size, stride, "");
2566 }
2567
2568 emit_data->args[0] = size;
2569 return;
2570 }
2571
2572 /* Textures - set the mip level. */
2573 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2574
2575 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2576 NULL, address, count, 0xf);
2577 return;
2578 }
2579
2580 if (target == TGSI_TEXTURE_BUFFER) {
2581 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
2582 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
2583 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
2584 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
2585
2586 /* Bitcast and truncate v8i32 to v16i8. */
2587 LLVMValueRef res = res_ptr;
2588 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
2589 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
2590 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
2591
2592 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
2593 emit_data->args[0] = res;
2594 emit_data->args[1] = bld_base->uint_bld.zero;
2595 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
2596 emit_data->arg_count = 3;
2597 return;
2598 }
2599
2600 /* Fetch and project texture coordinates */
2601 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
2602 for (chan = 0; chan < 3; chan++ ) {
2603 coords[chan] = lp_build_emit_fetch(bld_base,
2604 emit_data->inst, 0,
2605 chan);
2606 if (opcode == TGSI_OPCODE_TXP)
2607 coords[chan] = lp_build_emit_llvm_binary(bld_base,
2608 TGSI_OPCODE_DIV,
2609 coords[chan],
2610 coords[3]);
2611 }
2612
2613 if (opcode == TGSI_OPCODE_TXP)
2614 coords[3] = bld_base->base.one;
2615
2616 /* Pack offsets. */
2617 if (has_offset && opcode != TGSI_OPCODE_TXF) {
2618 /* The offsets are six-bit signed integers packed like this:
2619 * X=[5:0], Y=[13:8], and Z=[21:16].
2620 */
2621 LLVMValueRef offset[3], pack;
2622
2623 assert(inst->Texture.NumOffsets == 1);
2624
2625 for (chan = 0; chan < 3; chan++) {
2626 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
2627 emit_data->inst, 0, chan);
2628 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
2629 lp_build_const_int32(gallivm, 0x3f), "");
2630 if (chan)
2631 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
2632 lp_build_const_int32(gallivm, chan*8), "");
2633 }
2634
2635 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
2636 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
2637 address[count++] = pack;
2638 }
2639
2640 /* Pack LOD bias value */
2641 if (opcode == TGSI_OPCODE_TXB)
2642 address[count++] = coords[3];
2643 if (opcode == TGSI_OPCODE_TXB2)
2644 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2645
2646 /* Pack depth comparison value */
2647 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
2648 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2649 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2650 } else {
2651 assert(ref_pos >= 0);
2652 address[count++] = coords[ref_pos];
2653 }
2654 }
2655
2656 /* Pack user derivatives */
2657 if (opcode == TGSI_OPCODE_TXD) {
2658 int param, num_src_deriv_channels;
2659
2660 switch (target) {
2661 case TGSI_TEXTURE_3D:
2662 num_src_deriv_channels = 3;
2663 num_deriv_channels = 3;
2664 break;
2665 case TGSI_TEXTURE_2D:
2666 case TGSI_TEXTURE_SHADOW2D:
2667 case TGSI_TEXTURE_RECT:
2668 case TGSI_TEXTURE_SHADOWRECT:
2669 case TGSI_TEXTURE_2D_ARRAY:
2670 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2671 num_src_deriv_channels = 2;
2672 num_deriv_channels = 2;
2673 break;
2674 case TGSI_TEXTURE_CUBE:
2675 case TGSI_TEXTURE_SHADOWCUBE:
2676 case TGSI_TEXTURE_CUBE_ARRAY:
2677 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
2678 /* Cube derivatives will be converted to 2D. */
2679 num_src_deriv_channels = 3;
2680 num_deriv_channels = 2;
2681 break;
2682 case TGSI_TEXTURE_1D:
2683 case TGSI_TEXTURE_SHADOW1D:
2684 case TGSI_TEXTURE_1D_ARRAY:
2685 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2686 num_src_deriv_channels = 1;
2687 num_deriv_channels = 1;
2688 break;
2689 default:
2690 unreachable("invalid target");
2691 }
2692
2693 for (param = 0; param < 2; param++)
2694 for (chan = 0; chan < num_src_deriv_channels; chan++)
2695 derivs[param * num_src_deriv_channels + chan] =
2696 lp_build_emit_fetch(bld_base, inst, param+1, chan);
2697 }
2698
2699 if (target == TGSI_TEXTURE_CUBE ||
2700 target == TGSI_TEXTURE_CUBE_ARRAY ||
2701 target == TGSI_TEXTURE_SHADOWCUBE ||
2702 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2703 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
2704
2705 if (opcode == TGSI_OPCODE_TXD)
2706 for (int i = 0; i < num_deriv_channels * 2; i++)
2707 address[count++] = derivs[i];
2708
2709 /* Pack texture coordinates */
2710 address[count++] = coords[0];
2711 if (num_coords > 1)
2712 address[count++] = coords[1];
2713 if (num_coords > 2)
2714 address[count++] = coords[2];
2715
2716 /* Pack LOD or sample index */
2717 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
2718 address[count++] = coords[3];
2719 else if (opcode == TGSI_OPCODE_TXL2)
2720 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2721
2722 if (count > 16) {
2723 assert(!"Cannot handle more than 16 texture address parameters");
2724 count = 16;
2725 }
2726
2727 for (chan = 0; chan < count; chan++ ) {
2728 address[chan] = LLVMBuildBitCast(gallivm->builder,
2729 address[chan], i32, "");
2730 }
2731
2732 /* Adjust the sample index according to FMASK.
2733 *
2734 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2735 * which is the identity mapping. Each nibble says which physical sample
2736 * should be fetched to get that sample.
2737 *
2738 * For example, 0x11111100 means there are only 2 samples stored and
2739 * the second sample covers 3/4 of the pixel. When reading samples 0
2740 * and 1, return physical sample 0 (determined by the first two 0s
2741 * in FMASK), otherwise return physical sample 1.
2742 *
2743 * The sample index should be adjusted as follows:
2744 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2745 */
2746 if (target == TGSI_TEXTURE_2D_MSAA ||
2747 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2748 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2749 struct lp_build_emit_data txf_emit_data = *emit_data;
2750 LLVMValueRef txf_address[4];
2751 unsigned txf_count = count;
2752 struct tgsi_full_instruction inst = {};
2753
2754 memcpy(txf_address, address, sizeof(txf_address));
2755
2756 if (target == TGSI_TEXTURE_2D_MSAA) {
2757 txf_address[2] = bld_base->uint_bld.zero;
2758 }
2759 txf_address[3] = bld_base->uint_bld.zero;
2760
2761 /* Read FMASK using TXF. */
2762 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
2763 inst.Texture.Texture = target;
2764 txf_emit_data.inst = &inst;
2765 txf_emit_data.chan = 0;
2766 set_tex_fetch_args(gallivm, &txf_emit_data, TGSI_OPCODE_TXF,
2767 target, fmask_ptr, NULL,
2768 txf_address, txf_count, 0xf);
2769 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
2770
2771 /* Initialize some constants. */
2772 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
2773 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
2774
2775 /* Apply the formula. */
2776 LLVMValueRef fmask =
2777 LLVMBuildExtractElement(gallivm->builder,
2778 txf_emit_data.output[0],
2779 uint_bld->zero, "");
2780
2781 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
2782
2783 LLVMValueRef sample_index4 =
2784 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
2785
2786 LLVMValueRef shifted_fmask =
2787 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
2788
2789 LLVMValueRef final_sample =
2790 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
2791
2792 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2793 * resource descriptor is 0 (invalid),
2794 */
2795 LLVMValueRef fmask_desc =
2796 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
2797 LLVMVectorType(uint_bld->elem_type, 8), "");
2798
2799 LLVMValueRef fmask_word1 =
2800 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
2801 uint_bld->one, "");
2802
2803 LLVMValueRef word1_is_nonzero =
2804 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
2805 fmask_word1, uint_bld->zero, "");
2806
2807 /* Replace the MSAA sample index. */
2808 address[sample_chan] =
2809 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
2810 final_sample, address[sample_chan], "");
2811 }
2812
2813 if (opcode == TGSI_OPCODE_TXF) {
2814 /* add tex offsets */
2815 if (inst->Texture.NumOffsets) {
2816 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2817 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
2818 const struct tgsi_texture_offset * off = inst->TexOffsets;
2819
2820 assert(inst->Texture.NumOffsets == 1);
2821
2822 switch (target) {
2823 case TGSI_TEXTURE_3D:
2824 address[2] = lp_build_add(uint_bld, address[2],
2825 bld->immediates[off->Index][off->SwizzleZ]);
2826 /* fall through */
2827 case TGSI_TEXTURE_2D:
2828 case TGSI_TEXTURE_SHADOW2D:
2829 case TGSI_TEXTURE_RECT:
2830 case TGSI_TEXTURE_SHADOWRECT:
2831 case TGSI_TEXTURE_2D_ARRAY:
2832 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2833 address[1] =
2834 lp_build_add(uint_bld, address[1],
2835 bld->immediates[off->Index][off->SwizzleY]);
2836 /* fall through */
2837 case TGSI_TEXTURE_1D:
2838 case TGSI_TEXTURE_SHADOW1D:
2839 case TGSI_TEXTURE_1D_ARRAY:
2840 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2841 address[0] =
2842 lp_build_add(uint_bld, address[0],
2843 bld->immediates[off->Index][off->SwizzleX]);
2844 break;
2845 /* texture offsets do not apply to other texture targets */
2846 }
2847 }
2848 }
2849
2850 if (opcode == TGSI_OPCODE_TG4) {
2851 unsigned gather_comp = 0;
2852
2853 /* DMASK was repurposed for GATHER4. 4 components are always
2854 * returned and DMASK works like a swizzle - it selects
2855 * the component to fetch. The only valid DMASK values are
2856 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2857 * (red,red,red,red) etc.) The ISA document doesn't mention
2858 * this.
2859 */
2860
2861 /* Get the component index from src1.x for Gather4. */
2862 if (!tgsi_is_shadow_target(target)) {
2863 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
2864 LLVMValueRef comp_imm;
2865 struct tgsi_src_register src1 = inst->Src[1].Register;
2866
2867 assert(src1.File == TGSI_FILE_IMMEDIATE);
2868
2869 comp_imm = imms[src1.Index][src1.SwizzleX];
2870 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
2871 gather_comp = CLAMP(gather_comp, 0, 3);
2872 }
2873
2874 dmask = 1 << gather_comp;
2875 }
2876
2877 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2878 samp_ptr, address, count, dmask);
2879 }
2880
2881 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2882 struct lp_build_tgsi_context * bld_base,
2883 struct lp_build_emit_data * emit_data)
2884 {
2885 struct lp_build_context * base = &bld_base->base;
2886 unsigned opcode = emit_data->inst->Instruction.Opcode;
2887 unsigned target = emit_data->inst->Texture.Texture;
2888 char intr_name[127];
2889 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
2890 bool is_shadow = tgsi_is_shadow_target(target);
2891 char type[64];
2892 const char *name = "llvm.SI.image.sample";
2893 const char *infix = "";
2894
2895 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
2896 /* Just return the buffer size. */
2897 emit_data->output[emit_data->chan] = emit_data->args[0];
2898 return;
2899 }
2900
2901 if (target == TGSI_TEXTURE_BUFFER) {
2902 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2903 base->gallivm->builder,
2904 "llvm.SI.vs.load.input", emit_data->dst_type,
2905 emit_data->args, emit_data->arg_count,
2906 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2907 return;
2908 }
2909
2910 switch (opcode) {
2911 case TGSI_OPCODE_TXF:
2912 name = target == TGSI_TEXTURE_2D_MSAA ||
2913 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
2914 "llvm.SI.image.load" :
2915 "llvm.SI.image.load.mip";
2916 is_shadow = false;
2917 has_offset = false;
2918 break;
2919 case TGSI_OPCODE_TXQ:
2920 name = "llvm.SI.getresinfo";
2921 is_shadow = false;
2922 has_offset = false;
2923 break;
2924 case TGSI_OPCODE_LODQ:
2925 name = "llvm.SI.getlod";
2926 is_shadow = false;
2927 has_offset = false;
2928 break;
2929 case TGSI_OPCODE_TEX:
2930 case TGSI_OPCODE_TEX2:
2931 case TGSI_OPCODE_TXP:
2932 break;
2933 case TGSI_OPCODE_TXB:
2934 case TGSI_OPCODE_TXB2:
2935 infix = ".b";
2936 break;
2937 case TGSI_OPCODE_TXL:
2938 case TGSI_OPCODE_TXL2:
2939 infix = ".l";
2940 break;
2941 case TGSI_OPCODE_TXD:
2942 infix = ".d";
2943 break;
2944 case TGSI_OPCODE_TG4:
2945 name = "llvm.SI.gather4";
2946 break;
2947 default:
2948 assert(0);
2949 return;
2950 }
2951
2952 if (LLVMGetTypeKind(LLVMTypeOf(emit_data->args[0])) == LLVMVectorTypeKind)
2953 sprintf(type, ".v%ui32",
2954 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2955 else
2956 strcpy(type, ".i32");
2957
2958 /* Add the type and suffixes .c, .o if needed. */
2959 sprintf(intr_name, "%s%s%s%s%s",
2960 name, is_shadow ? ".c" : "", infix,
2961 has_offset ? ".o" : "", type);
2962
2963 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2964 base->gallivm->builder, intr_name, emit_data->dst_type,
2965 emit_data->args, emit_data->arg_count,
2966 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2967
2968 /* Divide the number of layers by 6 to get the number of cubes. */
2969 if (opcode == TGSI_OPCODE_TXQ &&
2970 (target == TGSI_TEXTURE_CUBE_ARRAY ||
2971 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
2972 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2973 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2974 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2975
2976 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2977 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2978 z = LLVMBuildSDiv(builder, z, six, "");
2979
2980 emit_data->output[emit_data->chan] =
2981 LLVMBuildInsertElement(builder, v4, z, two, "");
2982 }
2983 }
2984
2985 static void si_llvm_emit_txqs(
2986 const struct lp_build_tgsi_action * action,
2987 struct lp_build_tgsi_context * bld_base,
2988 struct lp_build_emit_data * emit_data)
2989 {
2990 struct gallivm_state *gallivm = bld_base->base.gallivm;
2991 LLVMBuilderRef builder = gallivm->builder;
2992 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2993 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2994 LLVMValueRef res, samples;
2995 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2996
2997 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2998
2999
3000 /* Read the samples from the descriptor directly. */
3001 res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
3002 samples = LLVMBuildExtractElement(
3003 builder, res,
3004 lp_build_const_int32(gallivm, 3), "");
3005 samples = LLVMBuildLShr(builder, samples,
3006 lp_build_const_int32(gallivm, 16), "");
3007 samples = LLVMBuildAnd(builder, samples,
3008 lp_build_const_int32(gallivm, 0xf), "");
3009 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
3010 samples, "");
3011
3012 emit_data->output[emit_data->chan] = samples;
3013 }
3014
3015 /*
3016 * SI implements derivatives using the local data store (LDS)
3017 * All writes to the LDS happen in all executing threads at
3018 * the same time. TID is the Thread ID for the current
3019 * thread and is a value between 0 and 63, representing
3020 * the thread's position in the wavefront.
3021 *
3022 * For the pixel shader threads are grouped into quads of four pixels.
3023 * The TIDs of the pixels of a quad are:
3024 *
3025 * +------+------+
3026 * |4n + 0|4n + 1|
3027 * +------+------+
3028 * |4n + 2|4n + 3|
3029 * +------+------+
3030 *
3031 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
3032 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
3033 * the current pixel's column, and masking with 0xfffffffe yields the TID
3034 * of the left pixel of the current pixel's row.
3035 *
3036 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
3037 * adding 2 yields the TID of the pixel below the top pixel.
3038 */
3039 /* masks for thread ID. */
3040 #define TID_MASK_TOP_LEFT 0xfffffffc
3041 #define TID_MASK_TOP 0xfffffffd
3042 #define TID_MASK_LEFT 0xfffffffe
3043
3044 static void si_llvm_emit_ddxy(
3045 const struct lp_build_tgsi_action * action,
3046 struct lp_build_tgsi_context * bld_base,
3047 struct lp_build_emit_data * emit_data)
3048 {
3049 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3050 struct gallivm_state *gallivm = bld_base->base.gallivm;
3051 struct lp_build_context * base = &bld_base->base;
3052 const struct tgsi_full_instruction *inst = emit_data->inst;
3053 unsigned opcode = inst->Instruction.Opcode;
3054 LLVMValueRef indices[2];
3055 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
3056 LLVMValueRef tl, trbl, result[4];
3057 LLVMTypeRef i32;
3058 unsigned swizzle[4];
3059 unsigned c;
3060 int idx;
3061 unsigned mask;
3062
3063 i32 = LLVMInt32TypeInContext(gallivm->context);
3064
3065 indices[0] = bld_base->uint_bld.zero;
3066 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
3067 NULL, 0, LLVMReadNoneAttribute);
3068 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3069 indices, 2, "");
3070
3071 if (opcode == TGSI_OPCODE_DDX_FINE)
3072 mask = TID_MASK_LEFT;
3073 else if (opcode == TGSI_OPCODE_DDY_FINE)
3074 mask = TID_MASK_TOP;
3075 else
3076 mask = TID_MASK_TOP_LEFT;
3077
3078 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
3079 lp_build_const_int32(gallivm, mask), "");
3080 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3081 indices, 2, "");
3082
3083 /* for DDX we want to next X pixel, DDY next Y pixel. */
3084 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3085 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
3086 lp_build_const_int32(gallivm, idx), "");
3087 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3088 indices, 2, "");
3089
3090 for (c = 0; c < 4; ++c) {
3091 unsigned i;
3092
3093 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
3094 for (i = 0; i < c; ++i) {
3095 if (swizzle[i] == swizzle[c]) {
3096 result[c] = result[i];
3097 break;
3098 }
3099 }
3100 if (i != c)
3101 continue;
3102
3103 LLVMBuildStore(gallivm->builder,
3104 LLVMBuildBitCast(gallivm->builder,
3105 lp_build_emit_fetch(bld_base, inst, 0, c),
3106 i32, ""),
3107 store_ptr);
3108
3109 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
3110 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3111
3112 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
3113 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
3114
3115 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
3116 }
3117
3118 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
3119 }
3120
3121 /*
3122 * this takes an I,J coordinate pair,
3123 * and works out the X and Y derivatives.
3124 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3125 */
3126 static LLVMValueRef si_llvm_emit_ddxy_interp(
3127 struct lp_build_tgsi_context *bld_base,
3128 LLVMValueRef interp_ij)
3129 {
3130 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3131 struct gallivm_state *gallivm = bld_base->base.gallivm;
3132 struct lp_build_context *base = &bld_base->base;
3133 LLVMValueRef indices[2];
3134 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
3135 LLVMValueRef tl, tr, bl, result[4];
3136 LLVMTypeRef i32;
3137 unsigned c;
3138
3139 i32 = LLVMInt32TypeInContext(gallivm->context);
3140
3141 indices[0] = bld_base->uint_bld.zero;
3142 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
3143 NULL, 0, LLVMReadNoneAttribute);
3144 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3145 indices, 2, "");
3146
3147 temp = LLVMBuildAnd(gallivm->builder, indices[1],
3148 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
3149
3150 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
3151 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
3152
3153 indices[1] = temp;
3154 load_ptr_x = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3155 indices, 2, "");
3156
3157 indices[1] = temp2;
3158 load_ptr_y = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3159 indices, 2, "");
3160
3161 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
3162 lp_build_const_int32(gallivm, 1), "");
3163 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3164 indices, 2, "");
3165
3166 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
3167 lp_build_const_int32(gallivm, 2), "");
3168 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3169 indices, 2, "");
3170
3171 for (c = 0; c < 2; ++c) {
3172 LLVMValueRef store_val;
3173 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
3174
3175 store_val = LLVMBuildExtractElement(gallivm->builder,
3176 interp_ij, c_ll, "");
3177 LLVMBuildStore(gallivm->builder,
3178 store_val,
3179 store_ptr);
3180
3181 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
3182 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3183
3184 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
3185 tr = LLVMBuildBitCast(gallivm->builder, tr, base->elem_type, "");
3186
3187 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
3188
3189 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
3190 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3191
3192 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
3193 bl = LLVMBuildBitCast(gallivm->builder, bl, base->elem_type, "");
3194
3195 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
3196 }
3197
3198 return lp_build_gather_values(gallivm, result, 4);
3199 }
3200
3201 static void interp_fetch_args(
3202 struct lp_build_tgsi_context *bld_base,
3203 struct lp_build_emit_data *emit_data)
3204 {
3205 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3206 struct gallivm_state *gallivm = bld_base->base.gallivm;
3207 const struct tgsi_full_instruction *inst = emit_data->inst;
3208
3209 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3210 /* offset is in second src, first two channels */
3211 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3212 emit_data->inst, 1,
3213 TGSI_CHAN_X);
3214 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3215 emit_data->inst, 1,
3216 TGSI_CHAN_Y);
3217 emit_data->arg_count = 2;
3218 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3219 LLVMValueRef sample_position;
3220 LLVMValueRef sample_id;
3221 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
3222
3223 /* fetch sample ID, then fetch its sample position,
3224 * and place into first two channels.
3225 */
3226 sample_id = lp_build_emit_fetch(bld_base,
3227 emit_data->inst, 1, TGSI_CHAN_X);
3228 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3229 LLVMInt32TypeInContext(gallivm->context),
3230 "");
3231 sample_position = load_sample_position(&si_shader_ctx->radeon_bld, sample_id);
3232
3233 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3234 sample_position,
3235 lp_build_const_int32(gallivm, 0), "");
3236
3237 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3238 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3239 sample_position,
3240 lp_build_const_int32(gallivm, 1), "");
3241 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3242 emit_data->arg_count = 2;
3243 }
3244 }
3245
3246 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3247 struct lp_build_tgsi_context *bld_base,
3248 struct lp_build_emit_data *emit_data)
3249 {
3250 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3251 struct si_shader *shader = si_shader_ctx->shader;
3252 struct gallivm_state *gallivm = bld_base->base.gallivm;
3253 LLVMValueRef interp_param;
3254 const struct tgsi_full_instruction *inst = emit_data->inst;
3255 const char *intr_name;
3256 int input_index;
3257 int chan;
3258 int i;
3259 LLVMValueRef attr_number;
3260 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
3261 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
3262 int interp_param_idx;
3263 unsigned location;
3264
3265 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
3266 input_index = inst->Src[0].Register.Index;
3267
3268 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3269 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3270 location = TGSI_INTERPOLATE_LOC_CENTER;
3271 else
3272 location = TGSI_INTERPOLATE_LOC_CENTROID;
3273
3274 interp_param_idx = lookup_interp_param_index(shader->ps_input_interpolate[input_index],
3275 location);
3276 if (interp_param_idx == -1)
3277 return;
3278 else if (interp_param_idx)
3279 interp_param = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, interp_param_idx);
3280 else
3281 interp_param = NULL;
3282
3283 attr_number = lp_build_const_int32(gallivm,
3284 shader->ps_input_param_offset[input_index]);
3285
3286 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3287 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3288 LLVMValueRef ij_out[2];
3289 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3290
3291 /*
3292 * take the I then J parameters, and the DDX/Y for it, and
3293 * calculate the IJ inputs for the interpolator.
3294 * temp1 = ddx * offset/sample.x + I;
3295 * interp_param.I = ddy * offset/sample.y + temp1;
3296 * temp1 = ddx * offset/sample.x + J;
3297 * interp_param.J = ddy * offset/sample.y + temp1;
3298 */
3299 for (i = 0; i < 2; i++) {
3300 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
3301 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
3302 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3303 ddxy_out, ix_ll, "");
3304 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3305 ddxy_out, iy_ll, "");
3306 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3307 interp_param, ix_ll, "");
3308 LLVMValueRef temp1, temp2;
3309
3310 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3311 LLVMFloatTypeInContext(gallivm->context), "");
3312
3313 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3314
3315 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3316
3317 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3318
3319 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3320
3321 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
3322 temp2,
3323 LLVMIntTypeInContext(gallivm->context, 32), "");
3324 }
3325 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
3326 }
3327
3328 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3329 for (chan = 0; chan < 2; chan++) {
3330 LLVMValueRef args[4];
3331 LLVMValueRef llvm_chan;
3332 unsigned schan;
3333
3334 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3335 llvm_chan = lp_build_const_int32(gallivm, schan);
3336
3337 args[0] = llvm_chan;
3338 args[1] = attr_number;
3339 args[2] = params;
3340 args[3] = interp_param;
3341
3342 emit_data->output[chan] =
3343 lp_build_intrinsic(gallivm->builder, intr_name,
3344 input_type, args, args[3] ? 4 : 3,
3345 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3346 }
3347 }
3348
3349 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3350 struct lp_build_emit_data *emit_data)
3351 {
3352 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3353 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3354 unsigned stream;
3355
3356 assert(src0.File == TGSI_FILE_IMMEDIATE);
3357
3358 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
3359 return stream;
3360 }
3361
3362 /* Emit one vertex from the geometry shader */
3363 static void si_llvm_emit_vertex(
3364 const struct lp_build_tgsi_action *action,
3365 struct lp_build_tgsi_context *bld_base,
3366 struct lp_build_emit_data *emit_data)
3367 {
3368 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3369 struct lp_build_context *uint = &bld_base->uint_bld;
3370 struct si_shader *shader = si_shader_ctx->shader;
3371 struct tgsi_shader_info *info = &shader->selector->info;
3372 struct gallivm_state *gallivm = bld_base->base.gallivm;
3373 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
3374 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3375 SI_PARAM_GS2VS_OFFSET);
3376 LLVMValueRef gs_next_vertex;
3377 LLVMValueRef can_emit, kill;
3378 LLVMValueRef args[2];
3379 unsigned chan;
3380 int i;
3381 unsigned stream;
3382
3383 stream = si_llvm_get_stream(bld_base, emit_data);
3384
3385 /* Write vertex attribute values to GSVS ring */
3386 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3387 si_shader_ctx->gs_next_vertex[stream],
3388 "");
3389
3390 /* If this thread has already emitted the declared maximum number of
3391 * vertices, kill it: excessive vertex emissions are not supposed to
3392 * have any effect, and GS threads have no externally observable
3393 * effects other than emitting vertices.
3394 */
3395 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
3396 lp_build_const_int32(gallivm,
3397 shader->selector->gs_max_out_vertices), "");
3398 kill = lp_build_select(&bld_base->base, can_emit,
3399 lp_build_const_float(gallivm, 1.0f),
3400 lp_build_const_float(gallivm, -1.0f));
3401
3402 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
3403 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
3404
3405 for (i = 0; i < info->num_outputs; i++) {
3406 LLVMValueRef *out_ptr =
3407 si_shader_ctx->radeon_bld.soa.outputs[i];
3408
3409 for (chan = 0; chan < 4; chan++) {
3410 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3411 LLVMValueRef voffset =
3412 lp_build_const_int32(gallivm, (i * 4 + chan) *
3413 shader->selector->gs_max_out_vertices);
3414
3415 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3416 voffset = lp_build_mul_imm(uint, voffset, 4);
3417
3418 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
3419
3420 build_tbuffer_store(si_shader_ctx,
3421 si_shader_ctx->gsvs_ring[stream],
3422 out_val, 1,
3423 voffset, soffset, 0,
3424 V_008F0C_BUF_DATA_FORMAT_32,
3425 V_008F0C_BUF_NUM_FORMAT_UINT,
3426 1, 0, 1, 1, 0);
3427 }
3428 }
3429 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
3430 lp_build_const_int32(gallivm, 1));
3431
3432 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex[stream]);
3433
3434 /* Signal vertex emission */
3435 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
3436 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3437 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3438 LLVMVoidTypeInContext(gallivm->context), args, 2,
3439 LLVMNoUnwindAttribute);
3440 }
3441
3442 /* Cut one primitive from the geometry shader */
3443 static void si_llvm_emit_primitive(
3444 const struct lp_build_tgsi_action *action,
3445 struct lp_build_tgsi_context *bld_base,
3446 struct lp_build_emit_data *emit_data)
3447 {
3448 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3449 struct gallivm_state *gallivm = bld_base->base.gallivm;
3450 LLVMValueRef args[2];
3451 unsigned stream;
3452
3453 /* Signal primitive cut */
3454 stream = si_llvm_get_stream(bld_base, emit_data);
3455 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
3456 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3457 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3458 LLVMVoidTypeInContext(gallivm->context), args, 2,
3459 LLVMNoUnwindAttribute);
3460 }
3461
3462 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
3463 struct lp_build_tgsi_context *bld_base,
3464 struct lp_build_emit_data *emit_data)
3465 {
3466 struct gallivm_state *gallivm = bld_base->base.gallivm;
3467
3468 lp_build_intrinsic(gallivm->builder,
3469 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
3470 : "llvm.AMDGPU.barrier.local",
3471 LLVMVoidTypeInContext(gallivm->context), NULL, 0,
3472 LLVMNoUnwindAttribute);
3473 }
3474
3475 static const struct lp_build_tgsi_action tex_action = {
3476 .fetch_args = tex_fetch_args,
3477 .emit = build_tex_intrinsic,
3478 };
3479
3480 static const struct lp_build_tgsi_action interp_action = {
3481 .fetch_args = interp_fetch_args,
3482 .emit = build_interp_intrinsic,
3483 };
3484
3485 static void create_meta_data(struct si_shader_context *si_shader_ctx)
3486 {
3487 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3488 LLVMValueRef args[3];
3489
3490 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
3491 args[1] = 0;
3492 args[2] = lp_build_const_int32(gallivm, 1);
3493
3494 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
3495 }
3496
3497 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3498 {
3499 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3500 CONST_ADDR_SPACE);
3501 }
3502
3503 static void declare_streamout_params(struct si_shader_context *si_shader_ctx,
3504 struct pipe_stream_output_info *so,
3505 LLVMTypeRef *params, LLVMTypeRef i32,
3506 unsigned *num_params)
3507 {
3508 int i;
3509
3510 /* Streamout SGPRs. */
3511 if (so->num_outputs) {
3512 params[si_shader_ctx->param_streamout_config = (*num_params)++] = i32;
3513 params[si_shader_ctx->param_streamout_write_index = (*num_params)++] = i32;
3514 }
3515 /* A streamout buffer offset is loaded if the stride is non-zero. */
3516 for (i = 0; i < 4; i++) {
3517 if (!so->stride[i])
3518 continue;
3519
3520 params[si_shader_ctx->param_streamout_offset[i] = (*num_params)++] = i32;
3521 }
3522 }
3523
3524 static void create_function(struct si_shader_context *si_shader_ctx)
3525 {
3526 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3527 struct gallivm_state *gallivm = bld_base->base.gallivm;
3528 struct si_shader *shader = si_shader_ctx->shader;
3529 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
3530 unsigned i, last_array_pointer, last_sgpr, num_params;
3531
3532 i8 = LLVMInt8TypeInContext(gallivm->context);
3533 i32 = LLVMInt32TypeInContext(gallivm->context);
3534 f32 = LLVMFloatTypeInContext(gallivm->context);
3535 v2i32 = LLVMVectorType(i32, 2);
3536 v3i32 = LLVMVectorType(i32, 3);
3537 v4i32 = LLVMVectorType(i32, 4);
3538 v8i32 = LLVMVectorType(i32, 8);
3539 v16i8 = LLVMVectorType(i8, 16);
3540
3541 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
3542 params[SI_PARAM_CONST_BUFFERS] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
3543 params[SI_PARAM_SAMPLER_STATES] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
3544 params[SI_PARAM_SAMPLER_VIEWS] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
3545 last_array_pointer = SI_PARAM_SAMPLER_VIEWS;
3546
3547 switch (si_shader_ctx->type) {
3548 case TGSI_PROCESSOR_VERTEX:
3549 params[SI_PARAM_VERTEX_BUFFERS] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
3550 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
3551 params[SI_PARAM_BASE_VERTEX] = i32;
3552 params[SI_PARAM_START_INSTANCE] = i32;
3553 num_params = SI_PARAM_START_INSTANCE+1;
3554
3555 if (shader->key.vs.as_es) {
3556 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3557 } else if (shader->key.vs.as_ls) {
3558 params[SI_PARAM_LS_OUT_LAYOUT] = i32;
3559 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
3560 } else {
3561 if (si_shader_ctx->is_gs_copy_shader) {
3562 last_array_pointer = SI_PARAM_CONST_BUFFERS;
3563 num_params = SI_PARAM_CONST_BUFFERS+1;
3564 } else {
3565 params[SI_PARAM_VS_STATE_BITS] = i32;
3566 num_params = SI_PARAM_VS_STATE_BITS+1;
3567 }
3568
3569 /* The locations of the other parameters are assigned dynamically. */
3570 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3571 params, i32, &num_params);
3572 }
3573
3574 last_sgpr = num_params-1;
3575
3576 /* VGPRs */
3577 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
3578 params[si_shader_ctx->param_rel_auto_id = num_params++] = i32;
3579 params[si_shader_ctx->param_vs_prim_id = num_params++] = i32;
3580 params[si_shader_ctx->param_instance_id = num_params++] = i32;
3581 break;
3582
3583 case TGSI_PROCESSOR_TESS_CTRL:
3584 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3585 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3586 params[SI_PARAM_TCS_IN_LAYOUT] = i32;
3587 params[SI_PARAM_TESS_FACTOR_OFFSET] = i32;
3588 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
3589
3590 /* VGPRs */
3591 params[SI_PARAM_PATCH_ID] = i32;
3592 params[SI_PARAM_REL_IDS] = i32;
3593 num_params = SI_PARAM_REL_IDS+1;
3594 break;
3595
3596 case TGSI_PROCESSOR_TESS_EVAL:
3597 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3598 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3599 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
3600
3601 if (shader->key.tes.as_es) {
3602 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3603 } else {
3604 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3605 params, i32, &num_params);
3606 }
3607 last_sgpr = num_params - 1;
3608
3609 /* VGPRs */
3610 params[si_shader_ctx->param_tes_u = num_params++] = f32;
3611 params[si_shader_ctx->param_tes_v = num_params++] = f32;
3612 params[si_shader_ctx->param_tes_rel_patch_id = num_params++] = i32;
3613 params[si_shader_ctx->param_tes_patch_id = num_params++] = i32;
3614 break;
3615
3616 case TGSI_PROCESSOR_GEOMETRY:
3617 params[SI_PARAM_GS2VS_OFFSET] = i32;
3618 params[SI_PARAM_GS_WAVE_ID] = i32;
3619 last_sgpr = SI_PARAM_GS_WAVE_ID;
3620
3621 /* VGPRs */
3622 params[SI_PARAM_VTX0_OFFSET] = i32;
3623 params[SI_PARAM_VTX1_OFFSET] = i32;
3624 params[SI_PARAM_PRIMITIVE_ID] = i32;
3625 params[SI_PARAM_VTX2_OFFSET] = i32;
3626 params[SI_PARAM_VTX3_OFFSET] = i32;
3627 params[SI_PARAM_VTX4_OFFSET] = i32;
3628 params[SI_PARAM_VTX5_OFFSET] = i32;
3629 params[SI_PARAM_GS_INSTANCE_ID] = i32;
3630 num_params = SI_PARAM_GS_INSTANCE_ID+1;
3631 break;
3632
3633 case TGSI_PROCESSOR_FRAGMENT:
3634 params[SI_PARAM_ALPHA_REF] = f32;
3635 params[SI_PARAM_PS_STATE_BITS] = i32;
3636 params[SI_PARAM_PRIM_MASK] = i32;
3637 last_sgpr = SI_PARAM_PRIM_MASK;
3638 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
3639 params[SI_PARAM_PERSP_CENTER] = v2i32;
3640 params[SI_PARAM_PERSP_CENTROID] = v2i32;
3641 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
3642 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
3643 params[SI_PARAM_LINEAR_CENTER] = v2i32;
3644 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
3645 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
3646 params[SI_PARAM_POS_X_FLOAT] = f32;
3647 params[SI_PARAM_POS_Y_FLOAT] = f32;
3648 params[SI_PARAM_POS_Z_FLOAT] = f32;
3649 params[SI_PARAM_POS_W_FLOAT] = f32;
3650 params[SI_PARAM_FRONT_FACE] = i32;
3651 params[SI_PARAM_ANCILLARY] = i32;
3652 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
3653 params[SI_PARAM_POS_FIXED_PT] = f32;
3654 num_params = SI_PARAM_POS_FIXED_PT+1;
3655 break;
3656
3657 default:
3658 assert(0 && "unimplemented shader");
3659 return;
3660 }
3661
3662 assert(num_params <= Elements(params));
3663 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
3664 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
3665
3666 if (shader->dx10_clamp_mode)
3667 LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
3668 "enable-no-nans-fp-math", "true");
3669
3670 for (i = 0; i <= last_sgpr; ++i) {
3671 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
3672
3673 /* We tell llvm that array inputs are passed by value to allow Sinking pass
3674 * to move load. Inputs are constant so this is fine. */
3675 if (i <= last_array_pointer)
3676 LLVMAddAttribute(P, LLVMByValAttribute);
3677 else
3678 LLVMAddAttribute(P, LLVMInRegAttribute);
3679 }
3680
3681 if (bld_base->info &&
3682 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
3683 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
3684 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
3685 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
3686 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
3687 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
3688 si_shader_ctx->lds =
3689 LLVMAddGlobalInAddressSpace(gallivm->module,
3690 LLVMArrayType(i32, 64),
3691 "ddxy_lds",
3692 LOCAL_ADDR_SPACE);
3693
3694 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
3695 si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
3696 si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
3697 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
3698 unsigned vertex_data_dw_size = 32*32*4;
3699 unsigned patch_data_dw_size = 32*4;
3700 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
3701 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
3702 unsigned lds_dwords = patch_dw_size;
3703
3704 /* The actual size is computed outside of the shader to reduce
3705 * the number of shader variants. */
3706 si_shader_ctx->lds =
3707 LLVMAddGlobalInAddressSpace(gallivm->module,
3708 LLVMArrayType(i32, lds_dwords),
3709 "tess_lds",
3710 LOCAL_ADDR_SPACE);
3711 }
3712 }
3713
3714 static void preload_constants(struct si_shader_context *si_shader_ctx)
3715 {
3716 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3717 struct gallivm_state * gallivm = bld_base->base.gallivm;
3718 const struct tgsi_shader_info * info = bld_base->info;
3719 unsigned buf;
3720 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
3721
3722 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
3723 unsigned i, num_const = info->const_file_max[buf] + 1;
3724
3725 if (num_const == 0)
3726 continue;
3727
3728 /* Allocate space for the constant values */
3729 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
3730
3731 /* Load the resource descriptor */
3732 si_shader_ctx->const_buffers[buf] =
3733 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
3734
3735 /* Load the constants, we rely on the code sinking to do the rest */
3736 for (i = 0; i < num_const * 4; ++i) {
3737 si_shader_ctx->constants[buf][i] =
3738 buffer_load_const(gallivm->builder,
3739 si_shader_ctx->const_buffers[buf],
3740 lp_build_const_int32(gallivm, i * 4),
3741 bld_base->base.elem_type);
3742 }
3743 }
3744 }
3745
3746 static void preload_samplers(struct si_shader_context *si_shader_ctx)
3747 {
3748 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3749 struct gallivm_state * gallivm = bld_base->base.gallivm;
3750 const struct tgsi_shader_info * info = bld_base->info;
3751
3752 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
3753
3754 LLVMValueRef res_ptr, samp_ptr;
3755 LLVMValueRef offset;
3756
3757 if (num_samplers == 0)
3758 return;
3759
3760 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
3761 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
3762
3763 /* Load the resources and samplers, we rely on the code sinking to do the rest */
3764 for (i = 0; i < num_samplers; ++i) {
3765 /* Resource */
3766 offset = lp_build_const_int32(gallivm, i);
3767 si_shader_ctx->sampler_views[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3768
3769 /* Sampler */
3770 offset = lp_build_const_int32(gallivm, i);
3771 si_shader_ctx->sampler_states[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
3772
3773 /* FMASK resource */
3774 if (info->is_msaa_sampler[i]) {
3775 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
3776 si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + i] =
3777 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3778 }
3779 }
3780 }
3781
3782 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
3783 {
3784 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3785 struct gallivm_state * gallivm = bld_base->base.gallivm;
3786 unsigned i;
3787
3788 /* Streamout can only be used if the shader is compiled as VS. */
3789 if (!si_shader_ctx->shader->selector->so.num_outputs ||
3790 (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3791 (si_shader_ctx->shader->key.vs.as_es ||
3792 si_shader_ctx->shader->key.vs.as_ls)) ||
3793 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3794 si_shader_ctx->shader->key.tes.as_es))
3795 return;
3796
3797 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3798 SI_PARAM_RW_BUFFERS);
3799
3800 /* Load the resources, we rely on the code sinking to do the rest */
3801 for (i = 0; i < 4; ++i) {
3802 if (si_shader_ctx->shader->selector->so.stride[i]) {
3803 LLVMValueRef offset = lp_build_const_int32(gallivm,
3804 SI_SO_BUF_OFFSET + i);
3805
3806 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3807 }
3808 }
3809 }
3810
3811 /**
3812 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
3813 * for later use.
3814 */
3815 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
3816 {
3817 struct gallivm_state *gallivm =
3818 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3819
3820 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3821 SI_PARAM_RW_BUFFERS);
3822
3823 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3824 si_shader_ctx->shader->key.vs.as_es) ||
3825 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3826 si_shader_ctx->shader->key.tes.as_es) ||
3827 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3828 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
3829
3830 si_shader_ctx->esgs_ring =
3831 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3832 }
3833
3834 if (si_shader_ctx->is_gs_copy_shader) {
3835 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
3836
3837 si_shader_ctx->gsvs_ring[0] =
3838 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3839 }
3840 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3841 int i;
3842 for (i = 0; i < 4; i++) {
3843 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
3844
3845 si_shader_ctx->gsvs_ring[i] =
3846 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3847 }
3848 }
3849 }
3850
3851 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
3852 struct si_shader_config *conf,
3853 unsigned symbol_offset)
3854 {
3855 unsigned i;
3856 const unsigned char *config =
3857 radeon_shader_binary_config_start(binary, symbol_offset);
3858
3859 /* XXX: We may be able to emit some of these values directly rather than
3860 * extracting fields to be emitted later.
3861 */
3862
3863 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
3864 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
3865 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
3866 switch (reg) {
3867 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
3868 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
3869 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
3870 case R_00B848_COMPUTE_PGM_RSRC1:
3871 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
3872 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
3873 conf->float_mode = G_00B028_FLOAT_MODE(value);
3874 conf->rsrc1 = value;
3875 break;
3876 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
3877 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
3878 break;
3879 case R_00B84C_COMPUTE_PGM_RSRC2:
3880 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
3881 conf->rsrc2 = value;
3882 break;
3883 case R_0286CC_SPI_PS_INPUT_ENA:
3884 conf->spi_ps_input_ena = value;
3885 break;
3886 case R_0286D0_SPI_PS_INPUT_ADDR:
3887 /* Not used yet, but will be in the future */
3888 break;
3889 case R_0286E8_SPI_TMPRING_SIZE:
3890 case R_00B860_COMPUTE_TMPRING_SIZE:
3891 /* WAVESIZE is in units of 256 dwords. */
3892 conf->scratch_bytes_per_wave =
3893 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
3894 break;
3895 default:
3896 {
3897 static bool printed;
3898
3899 if (!printed) {
3900 fprintf(stderr, "Warning: LLVM emitted unknown "
3901 "config register: 0x%x\n", reg);
3902 printed = true;
3903 }
3904 }
3905 break;
3906 }
3907 }
3908 }
3909
3910 void si_shader_apply_scratch_relocs(struct si_context *sctx,
3911 struct si_shader *shader,
3912 uint64_t scratch_va)
3913 {
3914 unsigned i;
3915 uint32_t scratch_rsrc_dword0 = scratch_va;
3916 uint32_t scratch_rsrc_dword1 =
3917 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
3918 | S_008F04_STRIDE(shader->config.scratch_bytes_per_wave / 64);
3919
3920 for (i = 0 ; i < shader->binary.reloc_count; i++) {
3921 const struct radeon_shader_reloc *reloc =
3922 &shader->binary.relocs[i];
3923 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
3924 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3925 &scratch_rsrc_dword0, 4);
3926 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
3927 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3928 &scratch_rsrc_dword1, 4);
3929 }
3930 }
3931 }
3932
3933 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
3934 {
3935 const struct radeon_shader_binary *binary = &shader->binary;
3936 unsigned code_size = binary->code_size + binary->rodata_size;
3937 unsigned char *ptr;
3938
3939 r600_resource_reference(&shader->bo, NULL);
3940 shader->bo = si_resource_create_custom(&sscreen->b.b,
3941 PIPE_USAGE_IMMUTABLE,
3942 code_size);
3943 if (!shader->bo)
3944 return -ENOMEM;
3945
3946 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
3947 PIPE_TRANSFER_READ_WRITE);
3948 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
3949 if (binary->rodata_size > 0) {
3950 ptr += binary->code_size;
3951 util_memcpy_cpu_to_le32(ptr, binary->rodata,
3952 binary->rodata_size);
3953 }
3954
3955 sscreen->b.ws->buffer_unmap(shader->bo->buf);
3956 return 0;
3957 }
3958
3959 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
3960 struct pipe_debug_callback *debug)
3961 {
3962 char *line, *p;
3963 unsigned i, count;
3964
3965 if (binary->disasm_string) {
3966 fprintf(stderr, "\nShader Disassembly:\n\n");
3967 fprintf(stderr, "%s\n", binary->disasm_string);
3968
3969 if (debug && debug->debug_message) {
3970 /* Very long debug messages are cut off, so send the
3971 * disassembly one line at a time. This causes more
3972 * overhead, but on the plus side it simplifies
3973 * parsing of resulting logs.
3974 */
3975 pipe_debug_message(debug, SHADER_INFO,
3976 "Shader Disassembly Begin");
3977
3978 line = binary->disasm_string;
3979 while (*line) {
3980 p = strchrnul(line, '\n');
3981 count = p - line;
3982
3983 if (count) {
3984 pipe_debug_message(debug, SHADER_INFO,
3985 "%.*s", count, line);
3986 }
3987
3988 if (!*p)
3989 break;
3990 line = p + 1;
3991 }
3992
3993 pipe_debug_message(debug, SHADER_INFO,
3994 "Shader Disassembly End");
3995 }
3996 } else {
3997 fprintf(stderr, "SI CODE:\n");
3998 for (i = 0; i < binary->code_size; i += 4) {
3999 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i,
4000 binary->code[i + 3], binary->code[i + 2],
4001 binary->code[i + 1], binary->code[i]);
4002 }
4003 }
4004 }
4005
4006 static void si_shader_dump_stats(struct si_screen *sscreen,
4007 struct si_shader_config *conf,
4008 unsigned num_inputs,
4009 unsigned code_size,
4010 struct pipe_debug_callback *debug,
4011 unsigned processor)
4012 {
4013 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
4014 unsigned lds_per_wave = 0;
4015 unsigned max_simd_waves = 10;
4016
4017 /* Compute LDS usage for PS. */
4018 if (processor == TGSI_PROCESSOR_FRAGMENT) {
4019 /* The minimum usage per wave is (num_inputs * 36). The maximum
4020 * usage is (num_inputs * 36 * 16).
4021 * We can get anything in between and it varies between waves.
4022 *
4023 * Other stages don't know the size at compile time or don't
4024 * allocate LDS per wave, but instead they do it per thread group.
4025 */
4026 lds_per_wave = conf->lds_size * lds_increment +
4027 align(num_inputs * 36, lds_increment);
4028 }
4029
4030 /* Compute the per-SIMD wave counts. */
4031 if (conf->num_sgprs) {
4032 if (sscreen->b.chip_class >= VI)
4033 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
4034 else
4035 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
4036 }
4037
4038 if (conf->num_vgprs)
4039 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
4040
4041 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
4042 * that PS can use.
4043 */
4044 if (lds_per_wave)
4045 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
4046
4047 if (r600_can_dump_shader(&sscreen->b, processor)) {
4048 fprintf(stderr, "*** SHADER STATS ***\n"
4049 "SGPRS: %d\n"
4050 "VGPRS: %d\n"
4051 "Code Size: %d bytes\n"
4052 "LDS: %d blocks\n"
4053 "Scratch: %d bytes per wave\n"
4054 "Max Waves: %d\n"
4055 "********************\n",
4056 conf->num_sgprs, conf->num_vgprs, code_size,
4057 conf->lds_size, conf->scratch_bytes_per_wave,
4058 max_simd_waves);
4059 }
4060
4061 pipe_debug_message(debug, SHADER_INFO,
4062 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
4063 "LDS: %d Scratch: %d Max Waves: %d",
4064 conf->num_sgprs, conf->num_vgprs, code_size,
4065 conf->lds_size, conf->scratch_bytes_per_wave,
4066 max_simd_waves);
4067 }
4068
4069 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
4070 struct pipe_debug_callback *debug, unsigned processor)
4071 {
4072 if (r600_can_dump_shader(&sscreen->b, processor))
4073 if (!(sscreen->b.debug_flags & DBG_NO_ASM))
4074 si_shader_dump_disassembly(&shader->binary, debug);
4075
4076 si_shader_dump_stats(sscreen, &shader->config,
4077 shader->selector ? shader->selector->info.num_inputs : 0,
4078 shader->binary.code_size, debug, processor);
4079 }
4080
4081 int si_compile_llvm(struct si_screen *sscreen,
4082 struct radeon_shader_binary *binary,
4083 struct si_shader_config *conf,
4084 LLVMTargetMachineRef tm,
4085 LLVMModuleRef mod,
4086 struct pipe_debug_callback *debug,
4087 unsigned processor)
4088 {
4089 int r = 0;
4090 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
4091
4092 if (r600_can_dump_shader(&sscreen->b, processor)) {
4093 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
4094
4095 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR)))
4096 LLVMDumpModule(mod);
4097 }
4098
4099 if (!si_replace_shader(count, binary)) {
4100 r = radeon_llvm_compile(mod, binary,
4101 r600_get_llvm_processor_name(sscreen->b.family), tm,
4102 debug);
4103 if (r)
4104 return r;
4105 }
4106
4107 si_shader_binary_read_config(binary, conf, 0);
4108
4109 FREE(binary->config);
4110 FREE(binary->global_symbol_offsets);
4111 binary->config = NULL;
4112 binary->global_symbol_offsets = NULL;
4113 return r;
4114 }
4115
4116 /* Generate code for the hardware VS shader stage to go with a geometry shader */
4117 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
4118 struct si_shader_context *si_shader_ctx,
4119 struct si_shader *gs, bool dump,
4120 struct pipe_debug_callback *debug)
4121 {
4122 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
4123 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
4124 struct lp_build_context *base = &bld_base->base;
4125 struct lp_build_context *uint = &bld_base->uint_bld;
4126 struct si_shader_output_values *outputs;
4127 struct tgsi_shader_info *gsinfo = &gs->selector->info;
4128 LLVMValueRef args[9];
4129 int i, r;
4130
4131 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
4132
4133 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
4134 si_shader_ctx->is_gs_copy_shader = true;
4135
4136 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
4137
4138 create_meta_data(si_shader_ctx);
4139 create_function(si_shader_ctx);
4140 preload_streamout_buffers(si_shader_ctx);
4141 preload_ring_buffers(si_shader_ctx);
4142
4143 args[0] = si_shader_ctx->gsvs_ring[0];
4144 args[1] = lp_build_mul_imm(uint,
4145 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
4146 si_shader_ctx->param_vertex_id),
4147 4);
4148 args[3] = uint->zero;
4149 args[4] = uint->one; /* OFFEN */
4150 args[5] = uint->zero; /* IDXEN */
4151 args[6] = uint->one; /* GLC */
4152 args[7] = uint->one; /* SLC */
4153 args[8] = uint->zero; /* TFE */
4154
4155 /* Fetch vertex data from GSVS ring */
4156 for (i = 0; i < gsinfo->num_outputs; ++i) {
4157 unsigned chan;
4158
4159 outputs[i].name = gsinfo->output_semantic_name[i];
4160 outputs[i].sid = gsinfo->output_semantic_index[i];
4161
4162 for (chan = 0; chan < 4; chan++) {
4163 args[2] = lp_build_const_int32(gallivm,
4164 (i * 4 + chan) *
4165 gs->selector->gs_max_out_vertices * 16 * 4);
4166
4167 outputs[i].values[chan] =
4168 LLVMBuildBitCast(gallivm->builder,
4169 lp_build_intrinsic(gallivm->builder,
4170 "llvm.SI.buffer.load.dword.i32.i32",
4171 LLVMInt32TypeInContext(gallivm->context),
4172 args, 9,
4173 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
4174 base->elem_type, "");
4175 }
4176 }
4177
4178 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
4179
4180 LLVMBuildRetVoid(bld_base->base.gallivm->builder);
4181
4182 /* Dump LLVM IR before any optimization passes */
4183 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
4184 r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
4185 LLVMDumpModule(bld_base->base.gallivm->module);
4186
4187 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
4188
4189 if (dump)
4190 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
4191
4192 r = si_compile_llvm(sscreen, &si_shader_ctx->shader->binary,
4193 &si_shader_ctx->shader->config, si_shader_ctx->tm,
4194 bld_base->base.gallivm->module,
4195 debug, TGSI_PROCESSOR_GEOMETRY);
4196 if (!r) {
4197 si_shader_dump(sscreen, si_shader_ctx->shader, debug,
4198 TGSI_PROCESSOR_GEOMETRY);
4199 r = si_shader_binary_upload(sscreen, si_shader_ctx->shader);
4200 }
4201
4202 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
4203
4204 FREE(outputs);
4205 return r;
4206 }
4207
4208 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
4209 {
4210 int i;
4211
4212 fprintf(f, "SHADER KEY\n");
4213
4214 switch (shader) {
4215 case PIPE_SHADER_VERTEX:
4216 fprintf(f, " instance_divisors = {");
4217 for (i = 0; i < Elements(key->vs.instance_divisors); i++)
4218 fprintf(f, !i ? "%u" : ", %u",
4219 key->vs.instance_divisors[i]);
4220 fprintf(f, "}\n");
4221 fprintf(f, " as_es = %u\n", key->vs.as_es);
4222 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
4223 fprintf(f, " export_prim_id = %u\n", key->vs.export_prim_id);
4224 break;
4225
4226 case PIPE_SHADER_TESS_CTRL:
4227 fprintf(f, " prim_mode = %u\n", key->tcs.prim_mode);
4228 break;
4229
4230 case PIPE_SHADER_TESS_EVAL:
4231 fprintf(f, " as_es = %u\n", key->tes.as_es);
4232 fprintf(f, " export_prim_id = %u\n", key->tes.export_prim_id);
4233 break;
4234
4235 case PIPE_SHADER_GEOMETRY:
4236 break;
4237
4238 case PIPE_SHADER_FRAGMENT:
4239 fprintf(f, " spi_shader_col_format = 0x%x\n", key->ps.spi_shader_col_format);
4240 fprintf(f, " last_cbuf = %u\n", key->ps.last_cbuf);
4241 fprintf(f, " color_two_side = %u\n", key->ps.color_two_side);
4242 fprintf(f, " alpha_func = %u\n", key->ps.alpha_func);
4243 fprintf(f, " alpha_to_one = %u\n", key->ps.alpha_to_one);
4244 fprintf(f, " poly_stipple = %u\n", key->ps.poly_stipple);
4245 fprintf(f, " clamp_color = %u\n", key->ps.clamp_color);
4246 break;
4247
4248 default:
4249 assert(0);
4250 }
4251 }
4252
4253 static void si_init_shader_ctx(struct si_shader_context *ctx,
4254 struct si_screen *sscreen,
4255 struct si_shader *shader,
4256 LLVMTargetMachineRef tm,
4257 struct tgsi_shader_info *info)
4258 {
4259 struct lp_build_tgsi_context *bld_base;
4260
4261 memset(ctx, 0, sizeof(*ctx));
4262 radeon_llvm_context_init(&ctx->radeon_bld);
4263 ctx->tm = tm;
4264 ctx->screen = sscreen;
4265 if (shader && shader->selector)
4266 ctx->type = shader->selector->info.processor;
4267 else
4268 ctx->type = -1;
4269 ctx->shader = shader;
4270
4271 bld_base = &ctx->radeon_bld.soa.bld_base;
4272 bld_base->info = info;
4273 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
4274
4275 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
4276 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
4277 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
4278
4279 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
4280 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
4281 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
4282 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
4283 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
4284 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
4285 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
4286 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
4287 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
4288 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
4289 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
4290 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
4291 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
4292
4293 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
4294 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
4295 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
4296 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
4297
4298 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
4299 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
4300 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
4301
4302 if (HAVE_LLVM >= 0x0306) {
4303 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
4304 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
4305 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
4306 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
4307 }
4308 }
4309
4310 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
4311 struct si_shader *shader,
4312 struct pipe_debug_callback *debug)
4313 {
4314 struct si_shader_selector *sel = shader->selector;
4315 struct tgsi_token *tokens = sel->tokens;
4316 struct si_shader_context si_shader_ctx;
4317 struct lp_build_tgsi_context * bld_base;
4318 struct tgsi_shader_info stipple_shader_info;
4319 LLVMModuleRef mod;
4320 int r = 0;
4321 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
4322 shader->key.ps.poly_stipple;
4323 bool dump = r600_can_dump_shader(&sscreen->b, sel->info.processor);
4324
4325 if (poly_stipple) {
4326 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
4327 SI_POLY_STIPPLE_SAMPLER,
4328 TGSI_FILE_SYSTEM_VALUE);
4329 tgsi_scan_shader(tokens, &stipple_shader_info);
4330 }
4331
4332 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
4333 * conversion fails. */
4334 if (dump && !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
4335 si_dump_shader_key(sel->type, &shader->key, stderr);
4336 tgsi_dump(tokens, 0);
4337 si_dump_streamout(&sel->so);
4338 }
4339
4340 assert(shader->nparam == 0);
4341
4342 si_init_shader_ctx(&si_shader_ctx, sscreen, shader, tm,
4343 poly_stipple ? &stipple_shader_info : &sel->info);
4344
4345 if (sel->type != PIPE_SHADER_COMPUTE)
4346 shader->dx10_clamp_mode = true;
4347
4348 shader->uses_instanceid = sel->info.uses_instanceid;
4349
4350 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
4351 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
4352
4353 switch (si_shader_ctx.type) {
4354 case TGSI_PROCESSOR_VERTEX:
4355 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
4356 if (shader->key.vs.as_ls)
4357 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
4358 else if (shader->key.vs.as_es)
4359 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4360 else
4361 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4362 break;
4363 case TGSI_PROCESSOR_TESS_CTRL:
4364 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
4365 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
4366 bld_base->emit_store = store_output_tcs;
4367 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
4368 break;
4369 case TGSI_PROCESSOR_TESS_EVAL:
4370 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
4371 if (shader->key.tes.as_es)
4372 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4373 else
4374 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4375 break;
4376 case TGSI_PROCESSOR_GEOMETRY:
4377 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
4378 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
4379 break;
4380 case TGSI_PROCESSOR_FRAGMENT:
4381 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
4382 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
4383 break;
4384 default:
4385 assert(!"Unsupported shader type");
4386 return -1;
4387 }
4388
4389 create_meta_data(&si_shader_ctx);
4390 create_function(&si_shader_ctx);
4391 preload_constants(&si_shader_ctx);
4392 preload_samplers(&si_shader_ctx);
4393 preload_streamout_buffers(&si_shader_ctx);
4394 preload_ring_buffers(&si_shader_ctx);
4395
4396 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4397 int i;
4398 for (i = 0; i < 4; i++) {
4399 si_shader_ctx.gs_next_vertex[i] =
4400 lp_build_alloca(bld_base->base.gallivm,
4401 bld_base->uint_bld.elem_type, "");
4402 }
4403 }
4404
4405 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
4406 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
4407 goto out;
4408 }
4409
4410 LLVMBuildRetVoid(bld_base->base.gallivm->builder);
4411 mod = bld_base->base.gallivm->module;
4412
4413 /* Dump LLVM IR before any optimization passes */
4414 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
4415 r600_can_dump_shader(&sscreen->b, si_shader_ctx.type))
4416 LLVMDumpModule(mod);
4417
4418 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
4419
4420 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
4421 mod, debug, si_shader_ctx.type);
4422 if (r) {
4423 fprintf(stderr, "LLVM failed to compile shader\n");
4424 goto out;
4425 }
4426
4427 si_shader_dump(sscreen, shader, debug, si_shader_ctx.type);
4428
4429 r = si_shader_binary_upload(sscreen, shader);
4430 if (r) {
4431 fprintf(stderr, "LLVM failed to upload shader\n");
4432 goto out;
4433 }
4434
4435 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
4436
4437 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4438 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
4439 shader->gs_copy_shader->selector = shader->selector;
4440 si_shader_ctx.shader = shader->gs_copy_shader;
4441 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
4442 shader, dump, debug))) {
4443 free(shader->gs_copy_shader);
4444 shader->gs_copy_shader = NULL;
4445 goto out;
4446 }
4447 }
4448
4449 out:
4450 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
4451 FREE(si_shader_ctx.constants[i]);
4452 if (poly_stipple)
4453 tgsi_free_tokens(tokens);
4454 return r;
4455 }
4456
4457 void si_shader_destroy(struct si_shader *shader)
4458 {
4459 if (shader->gs_copy_shader) {
4460 si_shader_destroy(shader->gs_copy_shader);
4461 FREE(shader->gs_copy_shader);
4462 }
4463
4464 if (shader->scratch_bo)
4465 r600_resource_reference(&shader->scratch_bo, NULL);
4466
4467 r600_resource_reference(&shader->bo, NULL);
4468
4469 radeon_shader_binary_clean(&shader->binary);
4470 }