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[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include <llvm/Config/llvm-config.h>
26
27 #include "util/u_memory.h"
28 #include "util/u_string.h"
29 #include "tgsi/tgsi_build.h"
30 #include "tgsi/tgsi_strings.h"
31 #include "tgsi/tgsi_util.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_from_mesa.h"
34
35 #include "ac_binary.h"
36 #include "ac_exp_param.h"
37 #include "ac_shader_util.h"
38 #include "ac_rtld.h"
39 #include "ac_llvm_util.h"
40 #include "si_shader_internal.h"
41 #include "si_pipe.h"
42 #include "sid.h"
43
44 #include "compiler/nir/nir.h"
45 #include "compiler/nir/nir_serialize.h"
46
47 static const char scratch_rsrc_dword0_symbol[] =
48 "SCRATCH_RSRC_DWORD0";
49
50 static const char scratch_rsrc_dword1_symbol[] =
51 "SCRATCH_RSRC_DWORD1";
52
53 static void si_init_shader_ctx(struct si_shader_context *ctx,
54 struct si_screen *sscreen,
55 struct ac_llvm_compiler *compiler,
56 unsigned wave_size,
57 bool nir);
58
59 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
60 struct lp_build_tgsi_context *bld_base,
61 struct lp_build_emit_data *emit_data);
62
63 static void si_dump_shader_key(const struct si_shader *shader, FILE *f);
64
65 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
66 union si_shader_part_key *key);
67 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
68 union si_shader_part_key *key);
69 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
70 union si_shader_part_key *key);
71 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
72 union si_shader_part_key *key);
73 static void si_fix_resource_usage(struct si_screen *sscreen,
74 struct si_shader *shader);
75
76 /* Ideally pass the sample mask input to the PS epilog as v14, which
77 * is its usual location, so that the shader doesn't have to add v_mov.
78 */
79 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 14
80
81 static bool llvm_type_is_64bit(struct si_shader_context *ctx,
82 LLVMTypeRef type)
83 {
84 if (type == ctx->ac.i64 || type == ctx->ac.f64)
85 return true;
86
87 return false;
88 }
89
90 /** Whether the shader runs as a combination of multiple API shaders */
91 static bool is_multi_part_shader(struct si_shader_context *ctx)
92 {
93 if (ctx->screen->info.chip_class <= GFX8)
94 return false;
95
96 return ctx->shader->key.as_ls ||
97 ctx->shader->key.as_es ||
98 ctx->type == PIPE_SHADER_TESS_CTRL ||
99 ctx->type == PIPE_SHADER_GEOMETRY;
100 }
101
102 /** Whether the shader runs on a merged HW stage (LSHS or ESGS) */
103 static bool is_merged_shader(struct si_shader_context *ctx)
104 {
105 return ctx->shader->key.as_ngg || is_multi_part_shader(ctx);
106 }
107
108 void si_init_function_info(struct si_function_info *fninfo)
109 {
110 fninfo->num_params = 0;
111 fninfo->num_sgpr_params = 0;
112 }
113
114 unsigned add_arg_assign(struct si_function_info *fninfo,
115 enum si_arg_regfile regfile, LLVMTypeRef type,
116 LLVMValueRef *assign)
117 {
118 assert(regfile != ARG_SGPR || fninfo->num_sgpr_params == fninfo->num_params);
119
120 unsigned idx = fninfo->num_params++;
121 assert(idx < ARRAY_SIZE(fninfo->types));
122
123 if (regfile == ARG_SGPR)
124 fninfo->num_sgpr_params = fninfo->num_params;
125
126 fninfo->types[idx] = type;
127 fninfo->assign[idx] = assign;
128 return idx;
129 }
130
131 static unsigned add_arg(struct si_function_info *fninfo,
132 enum si_arg_regfile regfile, LLVMTypeRef type)
133 {
134 return add_arg_assign(fninfo, regfile, type, NULL);
135 }
136
137 static void add_arg_assign_checked(struct si_function_info *fninfo,
138 enum si_arg_regfile regfile, LLVMTypeRef type,
139 LLVMValueRef *assign, unsigned idx)
140 {
141 ASSERTED unsigned actual = add_arg_assign(fninfo, regfile, type, assign);
142 assert(actual == idx);
143 }
144
145 static void add_arg_checked(struct si_function_info *fninfo,
146 enum si_arg_regfile regfile, LLVMTypeRef type,
147 unsigned idx)
148 {
149 add_arg_assign_checked(fninfo, regfile, type, NULL, idx);
150 }
151
152 /**
153 * Returns a unique index for a per-patch semantic name and index. The index
154 * must be less than 32, so that a 32-bit bitmask of used inputs or outputs
155 * can be calculated.
156 */
157 unsigned si_shader_io_get_unique_index_patch(unsigned semantic_name, unsigned index)
158 {
159 switch (semantic_name) {
160 case TGSI_SEMANTIC_TESSOUTER:
161 return 0;
162 case TGSI_SEMANTIC_TESSINNER:
163 return 1;
164 case TGSI_SEMANTIC_PATCH:
165 assert(index < 30);
166 return 2 + index;
167
168 default:
169 assert(!"invalid semantic name");
170 return 0;
171 }
172 }
173
174 /**
175 * Returns a unique index for a semantic name and index. The index must be
176 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
177 * calculated.
178 */
179 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index,
180 unsigned is_varying)
181 {
182 switch (semantic_name) {
183 case TGSI_SEMANTIC_POSITION:
184 return 0;
185 case TGSI_SEMANTIC_GENERIC:
186 /* Since some shader stages use the the highest used IO index
187 * to determine the size to allocate for inputs/outputs
188 * (in LDS, tess and GS rings). GENERIC should be placed right
189 * after POSITION to make that size as small as possible.
190 */
191 if (index < SI_MAX_IO_GENERIC)
192 return 1 + index;
193
194 assert(!"invalid generic index");
195 return 0;
196 case TGSI_SEMANTIC_FOG:
197 return SI_MAX_IO_GENERIC + 1;
198 case TGSI_SEMANTIC_COLOR:
199 assert(index < 2);
200 return SI_MAX_IO_GENERIC + 2 + index;
201 case TGSI_SEMANTIC_BCOLOR:
202 assert(index < 2);
203 /* If it's a varying, COLOR and BCOLOR alias. */
204 if (is_varying)
205 return SI_MAX_IO_GENERIC + 2 + index;
206 else
207 return SI_MAX_IO_GENERIC + 4 + index;
208 case TGSI_SEMANTIC_TEXCOORD:
209 assert(index < 8);
210 return SI_MAX_IO_GENERIC + 6 + index;
211
212 /* These are rarely used between LS and HS or ES and GS. */
213 case TGSI_SEMANTIC_CLIPDIST:
214 assert(index < 2);
215 return SI_MAX_IO_GENERIC + 6 + 8 + index;
216 case TGSI_SEMANTIC_CLIPVERTEX:
217 return SI_MAX_IO_GENERIC + 6 + 8 + 2;
218 case TGSI_SEMANTIC_PSIZE:
219 return SI_MAX_IO_GENERIC + 6 + 8 + 3;
220
221 /* These can't be written by LS, HS, and ES. */
222 case TGSI_SEMANTIC_LAYER:
223 return SI_MAX_IO_GENERIC + 6 + 8 + 4;
224 case TGSI_SEMANTIC_VIEWPORT_INDEX:
225 return SI_MAX_IO_GENERIC + 6 + 8 + 5;
226 case TGSI_SEMANTIC_PRIMID:
227 STATIC_ASSERT(SI_MAX_IO_GENERIC + 6 + 8 + 6 <= 63);
228 return SI_MAX_IO_GENERIC + 6 + 8 + 6;
229 default:
230 fprintf(stderr, "invalid semantic name = %u\n", semantic_name);
231 assert(!"invalid semantic name");
232 return 0;
233 }
234 }
235
236 /**
237 * Get the value of a shader input parameter and extract a bitfield.
238 */
239 static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
240 LLVMValueRef value, unsigned rshift,
241 unsigned bitwidth)
242 {
243 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
244 value = ac_to_integer(&ctx->ac, value);
245
246 if (rshift)
247 value = LLVMBuildLShr(ctx->ac.builder, value,
248 LLVMConstInt(ctx->i32, rshift, 0), "");
249
250 if (rshift + bitwidth < 32) {
251 unsigned mask = (1 << bitwidth) - 1;
252 value = LLVMBuildAnd(ctx->ac.builder, value,
253 LLVMConstInt(ctx->i32, mask, 0), "");
254 }
255
256 return value;
257 }
258
259 LLVMValueRef si_unpack_param(struct si_shader_context *ctx,
260 unsigned param, unsigned rshift,
261 unsigned bitwidth)
262 {
263 LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
264
265 return unpack_llvm_param(ctx, value, rshift, bitwidth);
266 }
267
268 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
269 {
270 switch (ctx->type) {
271 case PIPE_SHADER_TESS_CTRL:
272 return unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 0, 8);
273
274 case PIPE_SHADER_TESS_EVAL:
275 return LLVMGetParam(ctx->main_fn,
276 ctx->param_tes_rel_patch_id);
277
278 default:
279 assert(0);
280 return NULL;
281 }
282 }
283
284 /* Tessellation shaders pass outputs to the next shader using LDS.
285 *
286 * LS outputs = TCS inputs
287 * TCS outputs = TES inputs
288 *
289 * The LDS layout is:
290 * - TCS inputs for patch 0
291 * - TCS inputs for patch 1
292 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
293 * - ...
294 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
295 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
296 * - TCS outputs for patch 1
297 * - Per-patch TCS outputs for patch 1
298 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
299 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
300 * - ...
301 *
302 * All three shaders VS(LS), TCS, TES share the same LDS space.
303 */
304
305 static LLVMValueRef
306 get_tcs_in_patch_stride(struct si_shader_context *ctx)
307 {
308 return si_unpack_param(ctx, ctx->param_vs_state_bits, 8, 13);
309 }
310
311 static unsigned get_tcs_out_vertex_dw_stride_constant(struct si_shader_context *ctx)
312 {
313 assert(ctx->type == PIPE_SHADER_TESS_CTRL);
314
315 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
316 return util_last_bit64(ctx->shader->key.mono.u.ff_tcs_inputs_to_copy) * 4;
317
318 return util_last_bit64(ctx->shader->selector->outputs_written) * 4;
319 }
320
321 static LLVMValueRef get_tcs_out_vertex_dw_stride(struct si_shader_context *ctx)
322 {
323 unsigned stride = get_tcs_out_vertex_dw_stride_constant(ctx);
324
325 return LLVMConstInt(ctx->i32, stride, 0);
326 }
327
328 static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
329 {
330 if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
331 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 0, 13);
332
333 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
334 unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
335 unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
336 unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
337 unsigned patch_dw_stride = tcs_out_vertices * vertex_dw_stride +
338 num_patch_outputs * 4;
339 return LLVMConstInt(ctx->i32, patch_dw_stride, 0);
340 }
341
342 static LLVMValueRef
343 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
344 {
345 return LLVMBuildMul(ctx->ac.builder,
346 si_unpack_param(ctx,
347 ctx->param_tcs_out_lds_offsets,
348 0, 16),
349 LLVMConstInt(ctx->i32, 4, 0), "");
350 }
351
352 static LLVMValueRef
353 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
354 {
355 return LLVMBuildMul(ctx->ac.builder,
356 si_unpack_param(ctx,
357 ctx->param_tcs_out_lds_offsets,
358 16, 16),
359 LLVMConstInt(ctx->i32, 4, 0), "");
360 }
361
362 static LLVMValueRef
363 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
364 {
365 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
366 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
367
368 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
369 }
370
371 static LLVMValueRef
372 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
373 {
374 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
375 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
376 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
377
378 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_offset);
379 }
380
381 static LLVMValueRef
382 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
383 {
384 LLVMValueRef patch0_patch_data_offset =
385 get_tcs_out_patch0_patch_data_offset(ctx);
386 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
387 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
388
389 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset);
390 }
391
392 static LLVMValueRef get_num_tcs_out_vertices(struct si_shader_context *ctx)
393 {
394 unsigned tcs_out_vertices =
395 ctx->shader->selector ?
396 ctx->shader->selector->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] : 0;
397
398 /* If !tcs_out_vertices, it's either the fixed-func TCS or the TCS epilog. */
399 if (ctx->type == PIPE_SHADER_TESS_CTRL && tcs_out_vertices)
400 return LLVMConstInt(ctx->i32, tcs_out_vertices, 0);
401
402 return si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 6, 6);
403 }
404
405 static LLVMValueRef get_tcs_in_vertex_dw_stride(struct si_shader_context *ctx)
406 {
407 unsigned stride;
408
409 switch (ctx->type) {
410 case PIPE_SHADER_VERTEX:
411 stride = ctx->shader->selector->lshs_vertex_stride / 4;
412 return LLVMConstInt(ctx->i32, stride, 0);
413
414 case PIPE_SHADER_TESS_CTRL:
415 if (ctx->screen->info.chip_class >= GFX9 &&
416 ctx->shader->is_monolithic) {
417 stride = ctx->shader->key.part.tcs.ls->lshs_vertex_stride / 4;
418 return LLVMConstInt(ctx->i32, stride, 0);
419 }
420 return si_unpack_param(ctx, ctx->param_vs_state_bits, 24, 8);
421
422 default:
423 assert(0);
424 return NULL;
425 }
426 }
427
428 static LLVMValueRef unpack_sint16(struct si_shader_context *ctx,
429 LLVMValueRef i32, unsigned index)
430 {
431 assert(index <= 1);
432
433 if (index == 1)
434 return LLVMBuildAShr(ctx->ac.builder, i32,
435 LLVMConstInt(ctx->i32, 16, 0), "");
436
437 return LLVMBuildSExt(ctx->ac.builder,
438 LLVMBuildTrunc(ctx->ac.builder, i32,
439 ctx->ac.i16, ""),
440 ctx->i32, "");
441 }
442
443 void si_llvm_load_input_vs(
444 struct si_shader_context *ctx,
445 unsigned input_index,
446 LLVMValueRef out[4])
447 {
448 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
449 unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
450
451 if (vs_blit_property) {
452 LLVMValueRef vertex_id = ctx->abi.vertex_id;
453 LLVMValueRef sel_x1 = LLVMBuildICmp(ctx->ac.builder,
454 LLVMIntULE, vertex_id,
455 ctx->i32_1, "");
456 /* Use LLVMIntNE, because we have 3 vertices and only
457 * the middle one should use y2.
458 */
459 LLVMValueRef sel_y1 = LLVMBuildICmp(ctx->ac.builder,
460 LLVMIntNE, vertex_id,
461 ctx->i32_1, "");
462
463 if (input_index == 0) {
464 /* Position: */
465 LLVMValueRef x1y1 = LLVMGetParam(ctx->main_fn,
466 ctx->param_vs_blit_inputs);
467 LLVMValueRef x2y2 = LLVMGetParam(ctx->main_fn,
468 ctx->param_vs_blit_inputs + 1);
469
470 LLVMValueRef x1 = unpack_sint16(ctx, x1y1, 0);
471 LLVMValueRef y1 = unpack_sint16(ctx, x1y1, 1);
472 LLVMValueRef x2 = unpack_sint16(ctx, x2y2, 0);
473 LLVMValueRef y2 = unpack_sint16(ctx, x2y2, 1);
474
475 LLVMValueRef x = LLVMBuildSelect(ctx->ac.builder, sel_x1,
476 x1, x2, "");
477 LLVMValueRef y = LLVMBuildSelect(ctx->ac.builder, sel_y1,
478 y1, y2, "");
479
480 out[0] = LLVMBuildSIToFP(ctx->ac.builder, x, ctx->f32, "");
481 out[1] = LLVMBuildSIToFP(ctx->ac.builder, y, ctx->f32, "");
482 out[2] = LLVMGetParam(ctx->main_fn,
483 ctx->param_vs_blit_inputs + 2);
484 out[3] = ctx->ac.f32_1;
485 return;
486 }
487
488 /* Color or texture coordinates: */
489 assert(input_index == 1);
490
491 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
492 for (int i = 0; i < 4; i++) {
493 out[i] = LLVMGetParam(ctx->main_fn,
494 ctx->param_vs_blit_inputs + 3 + i);
495 }
496 } else {
497 assert(vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD);
498 LLVMValueRef x1 = LLVMGetParam(ctx->main_fn,
499 ctx->param_vs_blit_inputs + 3);
500 LLVMValueRef y1 = LLVMGetParam(ctx->main_fn,
501 ctx->param_vs_blit_inputs + 4);
502 LLVMValueRef x2 = LLVMGetParam(ctx->main_fn,
503 ctx->param_vs_blit_inputs + 5);
504 LLVMValueRef y2 = LLVMGetParam(ctx->main_fn,
505 ctx->param_vs_blit_inputs + 6);
506
507 out[0] = LLVMBuildSelect(ctx->ac.builder, sel_x1,
508 x1, x2, "");
509 out[1] = LLVMBuildSelect(ctx->ac.builder, sel_y1,
510 y1, y2, "");
511 out[2] = LLVMGetParam(ctx->main_fn,
512 ctx->param_vs_blit_inputs + 7);
513 out[3] = LLVMGetParam(ctx->main_fn,
514 ctx->param_vs_blit_inputs + 8);
515 }
516 return;
517 }
518
519 union si_vs_fix_fetch fix_fetch;
520 LLVMValueRef t_list_ptr;
521 LLVMValueRef t_offset;
522 LLVMValueRef t_list;
523 LLVMValueRef vertex_index;
524 LLVMValueRef tmp;
525
526 /* Load the T list */
527 t_list_ptr = LLVMGetParam(ctx->main_fn, ctx->param_vertex_buffers);
528
529 t_offset = LLVMConstInt(ctx->i32, input_index, 0);
530
531 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
532
533 vertex_index = LLVMGetParam(ctx->main_fn,
534 ctx->param_vertex_index0 +
535 input_index);
536
537 /* Use the open-coded implementation for all loads of doubles and
538 * of dword-sized data that needs fixups. We need to insert conversion
539 * code anyway, and the amd/common code does it for us.
540 *
541 * Note: On LLVM <= 8, we can only open-code formats with
542 * channel size >= 4 bytes.
543 */
544 bool opencode = ctx->shader->key.mono.vs_fetch_opencode & (1 << input_index);
545 fix_fetch.bits = ctx->shader->key.mono.vs_fix_fetch[input_index].bits;
546 if (opencode ||
547 (fix_fetch.u.log_size == 3 && fix_fetch.u.format == AC_FETCH_FORMAT_FLOAT) ||
548 (fix_fetch.u.log_size == 2)) {
549 tmp = ac_build_opencoded_load_format(
550 &ctx->ac, fix_fetch.u.log_size, fix_fetch.u.num_channels_m1 + 1,
551 fix_fetch.u.format, fix_fetch.u.reverse, !opencode,
552 t_list, vertex_index, ctx->ac.i32_0, ctx->ac.i32_0, 0, true);
553 for (unsigned i = 0; i < 4; ++i)
554 out[i] = LLVMBuildExtractElement(ctx->ac.builder, tmp, LLVMConstInt(ctx->i32, i, false), "");
555 return;
556 }
557
558 /* Do multiple loads for special formats. */
559 unsigned required_channels = util_last_bit(info->input_usage_mask[input_index]);
560 LLVMValueRef fetches[4];
561 unsigned num_fetches;
562 unsigned fetch_stride;
563 unsigned channels_per_fetch;
564
565 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2) {
566 num_fetches = MIN2(required_channels, 3);
567 fetch_stride = 1 << fix_fetch.u.log_size;
568 channels_per_fetch = 1;
569 } else {
570 num_fetches = 1;
571 fetch_stride = 0;
572 channels_per_fetch = required_channels;
573 }
574
575 for (unsigned i = 0; i < num_fetches; ++i) {
576 LLVMValueRef voffset = LLVMConstInt(ctx->i32, fetch_stride * i, 0);
577 fetches[i] = ac_build_buffer_load_format(&ctx->ac, t_list, vertex_index, voffset,
578 channels_per_fetch, 0, true);
579 }
580
581 if (num_fetches == 1 && channels_per_fetch > 1) {
582 LLVMValueRef fetch = fetches[0];
583 for (unsigned i = 0; i < channels_per_fetch; ++i) {
584 tmp = LLVMConstInt(ctx->i32, i, false);
585 fetches[i] = LLVMBuildExtractElement(
586 ctx->ac.builder, fetch, tmp, "");
587 }
588 num_fetches = channels_per_fetch;
589 channels_per_fetch = 1;
590 }
591
592 for (unsigned i = num_fetches; i < 4; ++i)
593 fetches[i] = LLVMGetUndef(ctx->f32);
594
595 if (fix_fetch.u.log_size <= 1 && fix_fetch.u.num_channels_m1 == 2 &&
596 required_channels == 4) {
597 if (fix_fetch.u.format == AC_FETCH_FORMAT_UINT || fix_fetch.u.format == AC_FETCH_FORMAT_SINT)
598 fetches[3] = ctx->ac.i32_1;
599 else
600 fetches[3] = ctx->ac.f32_1;
601 } else if (fix_fetch.u.log_size == 3 &&
602 (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ||
603 fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED ||
604 fix_fetch.u.format == AC_FETCH_FORMAT_SINT) &&
605 required_channels == 4) {
606 /* For 2_10_10_10, the hardware returns an unsigned value;
607 * convert it to a signed one.
608 */
609 LLVMValueRef tmp = fetches[3];
610 LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
611
612 /* First, recover the sign-extended signed integer value. */
613 if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED)
614 tmp = LLVMBuildFPToUI(ctx->ac.builder, tmp, ctx->i32, "");
615 else
616 tmp = ac_to_integer(&ctx->ac, tmp);
617
618 /* For the integer-like cases, do a natural sign extension.
619 *
620 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
621 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
622 * exponent.
623 */
624 tmp = LLVMBuildShl(ctx->ac.builder, tmp,
625 fix_fetch.u.format == AC_FETCH_FORMAT_SNORM ?
626 LLVMConstInt(ctx->i32, 7, 0) : c30, "");
627 tmp = LLVMBuildAShr(ctx->ac.builder, tmp, c30, "");
628
629 /* Convert back to the right type. */
630 if (fix_fetch.u.format == AC_FETCH_FORMAT_SNORM) {
631 LLVMValueRef clamp;
632 LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
633 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
634 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, tmp, neg_one, "");
635 tmp = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, tmp, "");
636 } else if (fix_fetch.u.format == AC_FETCH_FORMAT_SSCALED) {
637 tmp = LLVMBuildSIToFP(ctx->ac.builder, tmp, ctx->f32, "");
638 }
639
640 fetches[3] = tmp;
641 }
642
643 for (unsigned i = 0; i < 4; ++i)
644 out[i] = ac_to_float(&ctx->ac, fetches[i]);
645 }
646
647 static void declare_input_vs(
648 struct si_shader_context *ctx,
649 unsigned input_index,
650 const struct tgsi_full_declaration *decl,
651 LLVMValueRef out[4])
652 {
653 si_llvm_load_input_vs(ctx, input_index, out);
654 }
655
656 LLVMValueRef si_get_primitive_id(struct si_shader_context *ctx,
657 unsigned swizzle)
658 {
659 if (swizzle > 0)
660 return ctx->i32_0;
661
662 switch (ctx->type) {
663 case PIPE_SHADER_VERTEX:
664 return LLVMGetParam(ctx->main_fn,
665 ctx->param_vs_prim_id);
666 case PIPE_SHADER_TESS_CTRL:
667 return ctx->abi.tcs_patch_id;
668 case PIPE_SHADER_TESS_EVAL:
669 return ctx->abi.tes_patch_id;
670 case PIPE_SHADER_GEOMETRY:
671 return ctx->abi.gs_prim_id;
672 default:
673 assert(0);
674 return ctx->i32_0;
675 }
676 }
677
678 /**
679 * Return the value of tgsi_ind_register for indexing.
680 * This is the indirect index with the constant offset added to it.
681 */
682 LLVMValueRef si_get_indirect_index(struct si_shader_context *ctx,
683 const struct tgsi_ind_register *ind,
684 unsigned addr_mul,
685 int rel_index)
686 {
687 LLVMValueRef result;
688
689 if (ind->File == TGSI_FILE_ADDRESS) {
690 result = ctx->addrs[ind->Index][ind->Swizzle];
691 result = LLVMBuildLoad(ctx->ac.builder, result, "");
692 } else {
693 struct tgsi_full_src_register src = {};
694
695 src.Register.File = ind->File;
696 src.Register.Index = ind->Index;
697
698 /* Set the second index to 0 for constants. */
699 if (ind->File == TGSI_FILE_CONSTANT)
700 src.Register.Dimension = 1;
701
702 result = ctx->bld_base.emit_fetch_funcs[ind->File](&ctx->bld_base, &src,
703 TGSI_TYPE_SIGNED,
704 ind->Swizzle);
705 result = ac_to_integer(&ctx->ac, result);
706 }
707
708 return ac_build_imad(&ctx->ac, result, LLVMConstInt(ctx->i32, addr_mul, 0),
709 LLVMConstInt(ctx->i32, rel_index, 0));
710 }
711
712 /**
713 * Like si_get_indirect_index, but restricts the return value to a (possibly
714 * undefined) value inside [0..num).
715 */
716 LLVMValueRef si_get_bounded_indirect_index(struct si_shader_context *ctx,
717 const struct tgsi_ind_register *ind,
718 int rel_index, unsigned num)
719 {
720 LLVMValueRef result = si_get_indirect_index(ctx, ind, 1, rel_index);
721
722 return si_llvm_bound_index(ctx, result, num);
723 }
724
725 static LLVMValueRef get_dw_address_from_generic_indices(struct si_shader_context *ctx,
726 LLVMValueRef vertex_dw_stride,
727 LLVMValueRef base_addr,
728 LLVMValueRef vertex_index,
729 LLVMValueRef param_index,
730 unsigned input_index,
731 ubyte *name,
732 ubyte *index,
733 bool is_patch)
734 {
735 if (vertex_dw_stride) {
736 base_addr = ac_build_imad(&ctx->ac, vertex_index,
737 vertex_dw_stride, base_addr);
738 }
739
740 if (param_index) {
741 base_addr = ac_build_imad(&ctx->ac, param_index,
742 LLVMConstInt(ctx->i32, 4, 0), base_addr);
743 }
744
745 int param = is_patch ?
746 si_shader_io_get_unique_index_patch(name[input_index],
747 index[input_index]) :
748 si_shader_io_get_unique_index(name[input_index],
749 index[input_index], false);
750
751 /* Add the base address of the element. */
752 return LLVMBuildAdd(ctx->ac.builder, base_addr,
753 LLVMConstInt(ctx->i32, param * 4, 0), "");
754 }
755
756 /**
757 * Calculate a dword address given an input or output register and a stride.
758 */
759 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
760 const struct tgsi_full_dst_register *dst,
761 const struct tgsi_full_src_register *src,
762 LLVMValueRef vertex_dw_stride,
763 LLVMValueRef base_addr)
764 {
765 struct tgsi_shader_info *info = &ctx->shader->selector->info;
766 ubyte *name, *index, *array_first;
767 int input_index;
768 struct tgsi_full_dst_register reg;
769 LLVMValueRef vertex_index = NULL;
770 LLVMValueRef ind_index = NULL;
771
772 /* Set the register description. The address computation is the same
773 * for sources and destinations. */
774 if (src) {
775 reg.Register.File = src->Register.File;
776 reg.Register.Index = src->Register.Index;
777 reg.Register.Indirect = src->Register.Indirect;
778 reg.Register.Dimension = src->Register.Dimension;
779 reg.Indirect = src->Indirect;
780 reg.Dimension = src->Dimension;
781 reg.DimIndirect = src->DimIndirect;
782 } else
783 reg = *dst;
784
785 /* If the register is 2-dimensional (e.g. an array of vertices
786 * in a primitive), calculate the base address of the vertex. */
787 if (reg.Register.Dimension) {
788 if (reg.Dimension.Indirect)
789 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
790 1, reg.Dimension.Index);
791 else
792 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
793 }
794
795 /* Get information about the register. */
796 if (reg.Register.File == TGSI_FILE_INPUT) {
797 name = info->input_semantic_name;
798 index = info->input_semantic_index;
799 array_first = info->input_array_first;
800 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
801 name = info->output_semantic_name;
802 index = info->output_semantic_index;
803 array_first = info->output_array_first;
804 } else {
805 assert(0);
806 return NULL;
807 }
808
809 if (reg.Register.Indirect) {
810 /* Add the relative address of the element. */
811 if (reg.Indirect.ArrayID)
812 input_index = array_first[reg.Indirect.ArrayID];
813 else
814 input_index = reg.Register.Index;
815
816 ind_index = si_get_indirect_index(ctx, &reg.Indirect,
817 1, reg.Register.Index - input_index);
818 } else {
819 input_index = reg.Register.Index;
820 }
821
822 return get_dw_address_from_generic_indices(ctx, vertex_dw_stride,
823 base_addr, vertex_index,
824 ind_index, input_index,
825 name, index,
826 !reg.Register.Dimension);
827 }
828
829 /* The offchip buffer layout for TCS->TES is
830 *
831 * - attribute 0 of patch 0 vertex 0
832 * - attribute 0 of patch 0 vertex 1
833 * - attribute 0 of patch 0 vertex 2
834 * ...
835 * - attribute 0 of patch 1 vertex 0
836 * - attribute 0 of patch 1 vertex 1
837 * ...
838 * - attribute 1 of patch 0 vertex 0
839 * - attribute 1 of patch 0 vertex 1
840 * ...
841 * - per patch attribute 0 of patch 0
842 * - per patch attribute 0 of patch 1
843 * ...
844 *
845 * Note that every attribute has 4 components.
846 */
847 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
848 LLVMValueRef rel_patch_id,
849 LLVMValueRef vertex_index,
850 LLVMValueRef param_index)
851 {
852 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
853 LLVMValueRef param_stride, constant16;
854
855 vertices_per_patch = get_num_tcs_out_vertices(ctx);
856 num_patches = si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 0, 6);
857 total_vertices = LLVMBuildMul(ctx->ac.builder, vertices_per_patch,
858 num_patches, "");
859
860 constant16 = LLVMConstInt(ctx->i32, 16, 0);
861 if (vertex_index) {
862 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
863 vertices_per_patch, vertex_index);
864 param_stride = total_vertices;
865 } else {
866 base_addr = rel_patch_id;
867 param_stride = num_patches;
868 }
869
870 base_addr = ac_build_imad(&ctx->ac, param_index, param_stride, base_addr);
871 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
872
873 if (!vertex_index) {
874 LLVMValueRef patch_data_offset =
875 si_unpack_param(ctx, ctx->param_tcs_offchip_layout, 12, 20);
876
877 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
878 patch_data_offset, "");
879 }
880 return base_addr;
881 }
882
883 /* This is a generic helper that can be shared by the NIR and TGSI backends */
884 static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
885 struct si_shader_context *ctx,
886 LLVMValueRef vertex_index,
887 LLVMValueRef param_index,
888 unsigned param_base,
889 ubyte *name,
890 ubyte *index,
891 bool is_patch)
892 {
893 unsigned param_index_base;
894
895 param_index_base = is_patch ?
896 si_shader_io_get_unique_index_patch(name[param_base], index[param_base]) :
897 si_shader_io_get_unique_index(name[param_base], index[param_base], false);
898
899 if (param_index) {
900 param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
901 LLVMConstInt(ctx->i32, param_index_base, 0),
902 "");
903 } else {
904 param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
905 }
906
907 return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
908 vertex_index, param_index);
909 }
910
911 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
912 struct si_shader_context *ctx,
913 const struct tgsi_full_dst_register *dst,
914 const struct tgsi_full_src_register *src)
915 {
916 struct tgsi_shader_info *info = &ctx->shader->selector->info;
917 ubyte *name, *index, *array_first;
918 struct tgsi_full_src_register reg;
919 LLVMValueRef vertex_index = NULL;
920 LLVMValueRef param_index = NULL;
921 unsigned param_base;
922
923 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
924
925 if (reg.Register.Dimension) {
926
927 if (reg.Dimension.Indirect)
928 vertex_index = si_get_indirect_index(ctx, &reg.DimIndirect,
929 1, reg.Dimension.Index);
930 else
931 vertex_index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
932 }
933
934 /* Get information about the register. */
935 if (reg.Register.File == TGSI_FILE_INPUT) {
936 name = info->input_semantic_name;
937 index = info->input_semantic_index;
938 array_first = info->input_array_first;
939 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
940 name = info->output_semantic_name;
941 index = info->output_semantic_index;
942 array_first = info->output_array_first;
943 } else {
944 assert(0);
945 return NULL;
946 }
947
948 if (reg.Register.Indirect) {
949 if (reg.Indirect.ArrayID)
950 param_base = array_first[reg.Indirect.ArrayID];
951 else
952 param_base = reg.Register.Index;
953
954 param_index = si_get_indirect_index(ctx, &reg.Indirect,
955 1, reg.Register.Index - param_base);
956
957 } else {
958 param_base = reg.Register.Index;
959 }
960
961 return get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
962 param_index, param_base,
963 name, index, !reg.Register.Dimension);
964 }
965
966 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
967 LLVMTypeRef type, unsigned swizzle,
968 LLVMValueRef buffer, LLVMValueRef offset,
969 LLVMValueRef base, bool can_speculate)
970 {
971 struct si_shader_context *ctx = si_shader_context(bld_base);
972 LLVMValueRef value, value2;
973 LLVMTypeRef vec_type = LLVMVectorType(type, 4);
974
975 if (swizzle == ~0) {
976 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
977 0, ac_glc, can_speculate, false);
978
979 return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
980 }
981
982 if (!llvm_type_is_64bit(ctx, type)) {
983 value = ac_build_buffer_load(&ctx->ac, buffer, 4, NULL, base, offset,
984 0, ac_glc, can_speculate, false);
985
986 value = LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
987 return LLVMBuildExtractElement(ctx->ac.builder, value,
988 LLVMConstInt(ctx->i32, swizzle, 0), "");
989 }
990
991 value = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
992 swizzle * 4, ac_glc, can_speculate, false);
993
994 value2 = ac_build_buffer_load(&ctx->ac, buffer, 1, NULL, base, offset,
995 swizzle * 4 + 4, ac_glc, can_speculate, false);
996
997 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
998 }
999
1000 /**
1001 * Load from LSHS LDS storage.
1002 *
1003 * \param type output value type
1004 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
1005 * \param dw_addr address in dwords
1006 */
1007 static LLVMValueRef lshs_lds_load(struct lp_build_tgsi_context *bld_base,
1008 LLVMTypeRef type, unsigned swizzle,
1009 LLVMValueRef dw_addr)
1010 {
1011 struct si_shader_context *ctx = si_shader_context(bld_base);
1012 LLVMValueRef value;
1013
1014 if (swizzle == ~0) {
1015 LLVMValueRef values[TGSI_NUM_CHANNELS];
1016
1017 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
1018 values[chan] = lshs_lds_load(bld_base, type, chan, dw_addr);
1019
1020 return ac_build_gather_values(&ctx->ac, values,
1021 TGSI_NUM_CHANNELS);
1022 }
1023
1024 /* Split 64-bit loads. */
1025 if (llvm_type_is_64bit(ctx, type)) {
1026 LLVMValueRef lo, hi;
1027
1028 lo = lshs_lds_load(bld_base, ctx->i32, swizzle, dw_addr);
1029 hi = lshs_lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
1030 return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
1031 }
1032
1033 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1034 LLVMConstInt(ctx->i32, swizzle, 0), "");
1035
1036 value = ac_lds_load(&ctx->ac, dw_addr);
1037
1038 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1039 }
1040
1041 /**
1042 * Store to LSHS LDS storage.
1043 *
1044 * \param swizzle offset (typically 0..3)
1045 * \param dw_addr address in dwords
1046 * \param value value to store
1047 */
1048 static void lshs_lds_store(struct si_shader_context *ctx,
1049 unsigned dw_offset_imm, LLVMValueRef dw_addr,
1050 LLVMValueRef value)
1051 {
1052 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1053 LLVMConstInt(ctx->i32, dw_offset_imm, 0), "");
1054
1055 ac_lds_store(&ctx->ac, dw_addr, value);
1056 }
1057
1058 enum si_tess_ring {
1059 TCS_FACTOR_RING,
1060 TESS_OFFCHIP_RING_TCS,
1061 TESS_OFFCHIP_RING_TES,
1062 };
1063
1064 static LLVMValueRef get_tess_ring_descriptor(struct si_shader_context *ctx,
1065 enum si_tess_ring ring)
1066 {
1067 LLVMBuilderRef builder = ctx->ac.builder;
1068 unsigned param = ring == TESS_OFFCHIP_RING_TES ? ctx->param_tes_offchip_addr :
1069 ctx->param_tcs_out_lds_layout;
1070 LLVMValueRef addr = LLVMGetParam(ctx->main_fn, param);
1071
1072 /* TCS only receives high 13 bits of the address. */
1073 if (ring == TESS_OFFCHIP_RING_TCS || ring == TCS_FACTOR_RING) {
1074 addr = LLVMBuildAnd(builder, addr,
1075 LLVMConstInt(ctx->i32, 0xfff80000, 0), "");
1076 }
1077
1078 if (ring == TCS_FACTOR_RING) {
1079 unsigned tf_offset = ctx->screen->tess_offchip_ring_size;
1080 addr = LLVMBuildAdd(builder, addr,
1081 LLVMConstInt(ctx->i32, tf_offset, 0), "");
1082 }
1083
1084 uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1085 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1086 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1087 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1088
1089 if (ctx->screen->info.chip_class >= GFX10)
1090 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1091 S_008F0C_OOB_SELECT(3) |
1092 S_008F0C_RESOURCE_LEVEL(1);
1093 else
1094 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1095 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1096
1097 LLVMValueRef desc[4];
1098 desc[0] = addr;
1099 desc[1] = LLVMConstInt(ctx->i32,
1100 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
1101 desc[2] = LLVMConstInt(ctx->i32, 0xffffffff, 0);
1102 desc[3] = LLVMConstInt(ctx->i32, rsrc3, false);
1103
1104 return ac_build_gather_values(&ctx->ac, desc, 4);
1105 }
1106
1107 static LLVMValueRef fetch_input_tcs(
1108 struct lp_build_tgsi_context *bld_base,
1109 const struct tgsi_full_src_register *reg,
1110 enum tgsi_opcode_type type, unsigned swizzle_in)
1111 {
1112 struct si_shader_context *ctx = si_shader_context(bld_base);
1113 LLVMValueRef dw_addr, stride;
1114 unsigned swizzle = swizzle_in & 0xffff;
1115 stride = get_tcs_in_vertex_dw_stride(ctx);
1116 dw_addr = get_tcs_in_current_patch_offset(ctx);
1117 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1118
1119 return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1120 }
1121
1122 static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
1123 LLVMTypeRef type,
1124 LLVMValueRef vertex_index,
1125 LLVMValueRef param_index,
1126 unsigned const_index,
1127 unsigned location,
1128 unsigned driver_location,
1129 unsigned component,
1130 unsigned num_components,
1131 bool is_patch,
1132 bool is_compact,
1133 bool load_input)
1134 {
1135 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1136 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1137 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1138 LLVMValueRef dw_addr, stride;
1139
1140 driver_location = driver_location / 4;
1141
1142 if (load_input) {
1143 stride = get_tcs_in_vertex_dw_stride(ctx);
1144 dw_addr = get_tcs_in_current_patch_offset(ctx);
1145 } else {
1146 if (is_patch) {
1147 stride = NULL;
1148 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1149 } else {
1150 stride = get_tcs_out_vertex_dw_stride(ctx);
1151 dw_addr = get_tcs_out_current_patch_offset(ctx);
1152 }
1153 }
1154
1155 if (!param_index) {
1156 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1157 }
1158
1159 ubyte *names;
1160 ubyte *indices;
1161 if (load_input) {
1162 names = info->input_semantic_name;
1163 indices = info->input_semantic_index;
1164 } else {
1165 names = info->output_semantic_name;
1166 indices = info->output_semantic_index;
1167 }
1168
1169 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1170 vertex_index, param_index,
1171 driver_location,
1172 names, indices,
1173 is_patch);
1174
1175 LLVMValueRef value[4];
1176 for (unsigned i = 0; i < num_components; i++) {
1177 unsigned offset = i;
1178 if (llvm_type_is_64bit(ctx, type))
1179 offset *= 2;
1180
1181 offset += component;
1182 value[i + component] = lshs_lds_load(bld_base, type, offset, dw_addr);
1183 }
1184
1185 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1186 }
1187
1188 static LLVMValueRef fetch_output_tcs(
1189 struct lp_build_tgsi_context *bld_base,
1190 const struct tgsi_full_src_register *reg,
1191 enum tgsi_opcode_type type, unsigned swizzle_in)
1192 {
1193 struct si_shader_context *ctx = si_shader_context(bld_base);
1194 LLVMValueRef dw_addr, stride;
1195 unsigned swizzle = (swizzle_in & 0xffff);
1196
1197 if (reg->Register.Dimension) {
1198 stride = get_tcs_out_vertex_dw_stride(ctx);
1199 dw_addr = get_tcs_out_current_patch_offset(ctx);
1200 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1201 } else {
1202 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1203 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1204 }
1205
1206 return lshs_lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, dw_addr);
1207 }
1208
1209 static LLVMValueRef fetch_input_tes(
1210 struct lp_build_tgsi_context *bld_base,
1211 const struct tgsi_full_src_register *reg,
1212 enum tgsi_opcode_type type, unsigned swizzle_in)
1213 {
1214 struct si_shader_context *ctx = si_shader_context(bld_base);
1215 LLVMValueRef base, addr;
1216 unsigned swizzle = (swizzle_in & 0xffff);
1217
1218 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1219 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1220
1221 return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
1222 ctx->tess_offchip_ring, base, addr, true);
1223 }
1224
1225 LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
1226 LLVMTypeRef type,
1227 LLVMValueRef vertex_index,
1228 LLVMValueRef param_index,
1229 unsigned const_index,
1230 unsigned location,
1231 unsigned driver_location,
1232 unsigned component,
1233 unsigned num_components,
1234 bool is_patch,
1235 bool is_compact,
1236 bool load_input)
1237 {
1238 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1239 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1240 LLVMValueRef base, addr;
1241
1242 driver_location = driver_location / 4;
1243
1244 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1245
1246 if (!param_index) {
1247 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1248 }
1249
1250 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1251 param_index, driver_location,
1252 info->input_semantic_name,
1253 info->input_semantic_index,
1254 is_patch);
1255
1256 /* TODO: This will generate rather ordinary llvm code, although it
1257 * should be easy for the optimiser to fix up. In future we might want
1258 * to refactor buffer_load(), but for now this maximises code sharing
1259 * between the NIR and TGSI backends.
1260 */
1261 LLVMValueRef value[4];
1262 for (unsigned i = 0; i < num_components; i++) {
1263 unsigned offset = i;
1264 if (llvm_type_is_64bit(ctx, type)) {
1265 offset *= 2;
1266 if (offset == 4) {
1267 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1268 vertex_index,
1269 param_index,
1270 driver_location + 1,
1271 info->input_semantic_name,
1272 info->input_semantic_index,
1273 is_patch);
1274 }
1275
1276 offset = offset % 4;
1277 }
1278
1279 offset += component;
1280 value[i + component] = buffer_load(&ctx->bld_base, type, offset,
1281 ctx->tess_offchip_ring, base, addr, true);
1282 }
1283
1284 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1285 }
1286
1287 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1288 const struct tgsi_full_instruction *inst,
1289 const struct tgsi_opcode_info *info,
1290 unsigned index,
1291 LLVMValueRef dst[4])
1292 {
1293 struct si_shader_context *ctx = si_shader_context(bld_base);
1294 const struct tgsi_full_dst_register *reg = &inst->Dst[index];
1295 const struct tgsi_shader_info *sh_info = &ctx->shader->selector->info;
1296 unsigned chan_index;
1297 LLVMValueRef dw_addr, stride;
1298 LLVMValueRef buffer, base, buf_addr;
1299 LLVMValueRef values[4];
1300 bool skip_lds_store;
1301 bool is_tess_factor = false, is_tess_inner = false;
1302
1303 /* Only handle per-patch and per-vertex outputs here.
1304 * Vectors will be lowered to scalars and this function will be called again.
1305 */
1306 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1307 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1308 si_llvm_emit_store(bld_base, inst, info, index, dst);
1309 return;
1310 }
1311
1312 if (reg->Register.Dimension) {
1313 stride = get_tcs_out_vertex_dw_stride(ctx);
1314 dw_addr = get_tcs_out_current_patch_offset(ctx);
1315 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1316 skip_lds_store = !sh_info->reads_pervertex_outputs;
1317 } else {
1318 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1319 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1320 skip_lds_store = !sh_info->reads_perpatch_outputs;
1321
1322 if (!reg->Register.Indirect) {
1323 int name = sh_info->output_semantic_name[reg->Register.Index];
1324
1325 /* Always write tess factors into LDS for the TCS epilog. */
1326 if (name == TGSI_SEMANTIC_TESSINNER ||
1327 name == TGSI_SEMANTIC_TESSOUTER) {
1328 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1329 skip_lds_store = !sh_info->reads_tessfactor_outputs &&
1330 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1331 is_tess_factor = true;
1332 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1333 }
1334 }
1335 }
1336
1337 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1338
1339 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1340 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1341
1342 uint32_t writemask = reg->Register.WriteMask;
1343 while (writemask) {
1344 chan_index = u_bit_scan(&writemask);
1345 LLVMValueRef value = dst[chan_index];
1346
1347 if (inst->Instruction.Saturate)
1348 value = ac_build_clamp(&ctx->ac, value);
1349
1350 /* Skip LDS stores if there is no LDS read of this output. */
1351 if (!skip_lds_store)
1352 lshs_lds_store(ctx, chan_index, dw_addr, value);
1353
1354 value = ac_to_integer(&ctx->ac, value);
1355 values[chan_index] = value;
1356
1357 if (reg->Register.WriteMask != 0xF && !is_tess_factor) {
1358 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1359 buf_addr, base,
1360 4 * chan_index, ac_glc, false);
1361 }
1362
1363 /* Write tess factors into VGPRs for the epilog. */
1364 if (is_tess_factor &&
1365 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1366 if (!is_tess_inner) {
1367 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1368 ctx->invoc0_tess_factors[chan_index]);
1369 } else if (chan_index < 2) {
1370 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1371 ctx->invoc0_tess_factors[4 + chan_index]);
1372 }
1373 }
1374 }
1375
1376 if (reg->Register.WriteMask == 0xF && !is_tess_factor) {
1377 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1378 values, 4);
1379 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buf_addr,
1380 base, 0, ac_glc, false);
1381 }
1382 }
1383
1384 static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
1385 const struct nir_variable *var,
1386 LLVMValueRef vertex_index,
1387 LLVMValueRef param_index,
1388 unsigned const_index,
1389 LLVMValueRef src,
1390 unsigned writemask)
1391 {
1392 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1393 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1394 const unsigned component = var->data.location_frac;
1395 const bool is_patch = var->data.patch;
1396 unsigned driver_location = var->data.driver_location;
1397 LLVMValueRef dw_addr, stride;
1398 LLVMValueRef buffer, base, addr;
1399 LLVMValueRef values[8];
1400 bool skip_lds_store;
1401 bool is_tess_factor = false, is_tess_inner = false;
1402
1403 driver_location = driver_location / 4;
1404
1405 bool is_const = !param_index;
1406 if (!param_index)
1407 param_index = LLVMConstInt(ctx->i32, const_index, 0);
1408
1409 if (!is_patch) {
1410 stride = get_tcs_out_vertex_dw_stride(ctx);
1411 dw_addr = get_tcs_out_current_patch_offset(ctx);
1412 dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
1413 vertex_index, param_index,
1414 driver_location,
1415 info->output_semantic_name,
1416 info->output_semantic_index,
1417 is_patch);
1418
1419 skip_lds_store = !info->reads_pervertex_outputs;
1420 } else {
1421 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1422 dw_addr = get_dw_address_from_generic_indices(ctx, NULL, dw_addr,
1423 vertex_index, param_index,
1424 driver_location,
1425 info->output_semantic_name,
1426 info->output_semantic_index,
1427 is_patch);
1428
1429 skip_lds_store = !info->reads_perpatch_outputs;
1430
1431 if (is_const && const_index == 0) {
1432 int name = info->output_semantic_name[driver_location];
1433
1434 /* Always write tess factors into LDS for the TCS epilog. */
1435 if (name == TGSI_SEMANTIC_TESSINNER ||
1436 name == TGSI_SEMANTIC_TESSOUTER) {
1437 /* The epilog doesn't read LDS if invocation 0 defines tess factors. */
1438 skip_lds_store = !info->reads_tessfactor_outputs &&
1439 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
1440 is_tess_factor = true;
1441 is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
1442 }
1443 }
1444 }
1445
1446 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
1447
1448 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1449
1450 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, vertex_index,
1451 param_index, driver_location,
1452 info->output_semantic_name,
1453 info->output_semantic_index,
1454 is_patch);
1455
1456 for (unsigned chan = 0; chan < 8; chan++) {
1457 if (!(writemask & (1 << chan)))
1458 continue;
1459 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1460
1461 unsigned buffer_store_offset = chan % 4;
1462 if (chan == 4) {
1463 addr = get_tcs_tes_buffer_address_from_generic_indices(ctx,
1464 vertex_index,
1465 param_index,
1466 driver_location + 1,
1467 info->output_semantic_name,
1468 info->output_semantic_index,
1469 is_patch);
1470 }
1471
1472 /* Skip LDS stores if there is no LDS read of this output. */
1473 if (!skip_lds_store)
1474 lshs_lds_store(ctx, chan, dw_addr, value);
1475
1476 value = ac_to_integer(&ctx->ac, value);
1477 values[chan] = value;
1478
1479 if (writemask != 0xF && !is_tess_factor) {
1480 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 1,
1481 addr, base,
1482 4 * buffer_store_offset,
1483 ac_glc, false);
1484 }
1485
1486 /* Write tess factors into VGPRs for the epilog. */
1487 if (is_tess_factor &&
1488 ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
1489 if (!is_tess_inner) {
1490 LLVMBuildStore(ctx->ac.builder, value, /* outer */
1491 ctx->invoc0_tess_factors[chan]);
1492 } else if (chan < 2) {
1493 LLVMBuildStore(ctx->ac.builder, value, /* inner */
1494 ctx->invoc0_tess_factors[4 + chan]);
1495 }
1496 }
1497 }
1498
1499 if (writemask == 0xF && !is_tess_factor) {
1500 LLVMValueRef value = ac_build_gather_values(&ctx->ac,
1501 values, 4);
1502 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, addr,
1503 base, 0, ac_glc, false);
1504 }
1505 }
1506
1507 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
1508 unsigned input_index,
1509 unsigned vtx_offset_param,
1510 LLVMTypeRef type,
1511 unsigned swizzle)
1512 {
1513 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1514 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1515 struct si_shader *shader = ctx->shader;
1516 LLVMValueRef vtx_offset, soffset;
1517 struct tgsi_shader_info *info = &shader->selector->info;
1518 unsigned semantic_name = info->input_semantic_name[input_index];
1519 unsigned semantic_index = info->input_semantic_index[input_index];
1520 unsigned param;
1521 LLVMValueRef value;
1522
1523 param = si_shader_io_get_unique_index(semantic_name, semantic_index, false);
1524
1525 /* GFX9 has the ESGS ring in LDS. */
1526 if (ctx->screen->info.chip_class >= GFX9) {
1527 unsigned index = vtx_offset_param;
1528
1529 switch (index / 2) {
1530 case 0:
1531 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx01_offset,
1532 index % 2 ? 16 : 0, 16);
1533 break;
1534 case 1:
1535 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx23_offset,
1536 index % 2 ? 16 : 0, 16);
1537 break;
1538 case 2:
1539 vtx_offset = si_unpack_param(ctx, ctx->param_gs_vtx45_offset,
1540 index % 2 ? 16 : 0, 16);
1541 break;
1542 default:
1543 assert(0);
1544 return NULL;
1545 }
1546
1547 unsigned offset = param * 4 + swizzle;
1548 vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
1549 LLVMConstInt(ctx->i32, offset, false), "");
1550
1551 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, ctx->esgs_ring, vtx_offset);
1552 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, ptr, "");
1553 if (llvm_type_is_64bit(ctx, type)) {
1554 ptr = LLVMBuildGEP(ctx->ac.builder, ptr,
1555 &ctx->ac.i32_1, 1, "");
1556 LLVMValueRef values[2] = {
1557 value,
1558 LLVMBuildLoad(ctx->ac.builder, ptr, "")
1559 };
1560 value = ac_build_gather_values(&ctx->ac, values, 2);
1561 }
1562 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1563 }
1564
1565 /* GFX6: input load from the ESGS ring in memory. */
1566 if (swizzle == ~0) {
1567 LLVMValueRef values[TGSI_NUM_CHANNELS];
1568 unsigned chan;
1569 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1570 values[chan] = si_llvm_load_input_gs(abi, input_index, vtx_offset_param,
1571 type, chan);
1572 }
1573 return ac_build_gather_values(&ctx->ac, values,
1574 TGSI_NUM_CHANNELS);
1575 }
1576
1577 /* Get the vertex offset parameter on GFX6. */
1578 LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
1579
1580 vtx_offset = LLVMBuildMul(ctx->ac.builder, gs_vtx_offset,
1581 LLVMConstInt(ctx->i32, 4, 0), "");
1582
1583 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle) * 256, 0);
1584
1585 value = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1, ctx->i32_0,
1586 vtx_offset, soffset, 0, ac_glc, true, false);
1587 if (llvm_type_is_64bit(ctx, type)) {
1588 LLVMValueRef value2;
1589 soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 256, 0);
1590
1591 value2 = ac_build_buffer_load(&ctx->ac, ctx->esgs_ring, 1,
1592 ctx->i32_0, vtx_offset, soffset,
1593 0, ac_glc, true, false);
1594 return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
1595 }
1596 return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
1597 }
1598
1599 static LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
1600 unsigned location,
1601 unsigned driver_location,
1602 unsigned component,
1603 unsigned num_components,
1604 unsigned vertex_index,
1605 unsigned const_index,
1606 LLVMTypeRef type)
1607 {
1608 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1609
1610 LLVMValueRef value[4];
1611 for (unsigned i = 0; i < num_components; i++) {
1612 unsigned offset = i;
1613 if (llvm_type_is_64bit(ctx, type))
1614 offset *= 2;
1615
1616 offset += component;
1617 value[i + component] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4 + const_index,
1618 vertex_index, type, offset);
1619 }
1620
1621 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1622 }
1623
1624 static LLVMValueRef fetch_input_gs(
1625 struct lp_build_tgsi_context *bld_base,
1626 const struct tgsi_full_src_register *reg,
1627 enum tgsi_opcode_type type,
1628 unsigned swizzle_in)
1629 {
1630 struct si_shader_context *ctx = si_shader_context(bld_base);
1631 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1632 unsigned swizzle = swizzle_in & 0xffff;
1633
1634 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1635 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1636 return si_get_primitive_id(ctx, swizzle);
1637
1638 if (!reg->Register.Dimension)
1639 return NULL;
1640
1641 return si_llvm_load_input_gs(&ctx->abi, reg->Register.Index,
1642 reg->Dimension.Index,
1643 tgsi2llvmtype(bld_base, type),
1644 swizzle);
1645 }
1646
1647 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1648 {
1649 switch (interpolate) {
1650 case TGSI_INTERPOLATE_CONSTANT:
1651 return 0;
1652
1653 case TGSI_INTERPOLATE_LINEAR:
1654 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1655 return SI_PARAM_LINEAR_SAMPLE;
1656 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1657 return SI_PARAM_LINEAR_CENTROID;
1658 else
1659 return SI_PARAM_LINEAR_CENTER;
1660 break;
1661 case TGSI_INTERPOLATE_COLOR:
1662 case TGSI_INTERPOLATE_PERSPECTIVE:
1663 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1664 return SI_PARAM_PERSP_SAMPLE;
1665 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1666 return SI_PARAM_PERSP_CENTROID;
1667 else
1668 return SI_PARAM_PERSP_CENTER;
1669 break;
1670 default:
1671 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1672 return -1;
1673 }
1674 }
1675
1676 static LLVMValueRef si_build_fs_interp(struct si_shader_context *ctx,
1677 unsigned attr_index, unsigned chan,
1678 LLVMValueRef prim_mask,
1679 LLVMValueRef i, LLVMValueRef j)
1680 {
1681 if (i || j) {
1682 return ac_build_fs_interp(&ctx->ac,
1683 LLVMConstInt(ctx->i32, chan, 0),
1684 LLVMConstInt(ctx->i32, attr_index, 0),
1685 prim_mask, i, j);
1686 }
1687 return ac_build_fs_interp_mov(&ctx->ac,
1688 LLVMConstInt(ctx->i32, 2, 0), /* P0 */
1689 LLVMConstInt(ctx->i32, chan, 0),
1690 LLVMConstInt(ctx->i32, attr_index, 0),
1691 prim_mask);
1692 }
1693
1694 /**
1695 * Interpolate a fragment shader input.
1696 *
1697 * @param ctx context
1698 * @param input_index index of the input in hardware
1699 * @param semantic_name TGSI_SEMANTIC_*
1700 * @param semantic_index semantic index
1701 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1702 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1703 * @param interp_param interpolation weights (i,j)
1704 * @param prim_mask SI_PARAM_PRIM_MASK
1705 * @param face SI_PARAM_FRONT_FACE
1706 * @param result the return value (4 components)
1707 */
1708 static void interp_fs_input(struct si_shader_context *ctx,
1709 unsigned input_index,
1710 unsigned semantic_name,
1711 unsigned semantic_index,
1712 unsigned num_interp_inputs,
1713 unsigned colors_read_mask,
1714 LLVMValueRef interp_param,
1715 LLVMValueRef prim_mask,
1716 LLVMValueRef face,
1717 LLVMValueRef result[4])
1718 {
1719 LLVMValueRef i = NULL, j = NULL;
1720 unsigned chan;
1721
1722 /* fs.constant returns the param from the middle vertex, so it's not
1723 * really useful for flat shading. It's meant to be used for custom
1724 * interpolation (but the intrinsic can't fetch from the other two
1725 * vertices).
1726 *
1727 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1728 * to do the right thing. The only reason we use fs.constant is that
1729 * fs.interp cannot be used on integers, because they can be equal
1730 * to NaN.
1731 *
1732 * When interp is false we will use fs.constant or for newer llvm,
1733 * amdgcn.interp.mov.
1734 */
1735 bool interp = interp_param != NULL;
1736
1737 if (interp) {
1738 interp_param = LLVMBuildBitCast(ctx->ac.builder, interp_param,
1739 LLVMVectorType(ctx->f32, 2), "");
1740
1741 i = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1742 ctx->i32_0, "");
1743 j = LLVMBuildExtractElement(ctx->ac.builder, interp_param,
1744 ctx->i32_1, "");
1745 }
1746
1747 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1748 ctx->shader->key.part.ps.prolog.color_two_side) {
1749 LLVMValueRef is_face_positive;
1750
1751 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1752 * otherwise it's at offset "num_inputs".
1753 */
1754 unsigned back_attr_offset = num_interp_inputs;
1755 if (semantic_index == 1 && colors_read_mask & 0xf)
1756 back_attr_offset += 1;
1757
1758 is_face_positive = LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
1759 face, ctx->i32_0, "");
1760
1761 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1762 LLVMValueRef front, back;
1763
1764 front = si_build_fs_interp(ctx,
1765 input_index, chan,
1766 prim_mask, i, j);
1767 back = si_build_fs_interp(ctx,
1768 back_attr_offset, chan,
1769 prim_mask, i, j);
1770
1771 result[chan] = LLVMBuildSelect(ctx->ac.builder,
1772 is_face_positive,
1773 front,
1774 back,
1775 "");
1776 }
1777 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1778 result[0] = si_build_fs_interp(ctx, input_index,
1779 0, prim_mask, i, j);
1780 result[1] =
1781 result[2] = LLVMConstReal(ctx->f32, 0.0f);
1782 result[3] = LLVMConstReal(ctx->f32, 1.0f);
1783 } else {
1784 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1785 result[chan] = si_build_fs_interp(ctx,
1786 input_index, chan,
1787 prim_mask, i, j);
1788 }
1789 }
1790 }
1791
1792 void si_llvm_load_input_fs(
1793 struct si_shader_context *ctx,
1794 unsigned input_index,
1795 LLVMValueRef out[4])
1796 {
1797 struct si_shader *shader = ctx->shader;
1798 struct tgsi_shader_info *info = &shader->selector->info;
1799 LLVMValueRef main_fn = ctx->main_fn;
1800 LLVMValueRef interp_param = NULL;
1801 int interp_param_idx;
1802 enum tgsi_semantic semantic_name = info->input_semantic_name[input_index];
1803 unsigned semantic_index = info->input_semantic_index[input_index];
1804 enum tgsi_interpolate_mode interp_mode = info->input_interpolate[input_index];
1805 enum tgsi_interpolate_loc interp_loc = info->input_interpolate_loc[input_index];
1806
1807 /* Get colors from input VGPRs (set by the prolog). */
1808 if (semantic_name == TGSI_SEMANTIC_COLOR) {
1809 unsigned colors_read = shader->selector->info.colors_read;
1810 unsigned mask = colors_read >> (semantic_index * 4);
1811 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1812 (semantic_index ? util_bitcount(colors_read & 0xf) : 0);
1813 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1814
1815 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1816 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1817 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1818 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1819 return;
1820 }
1821
1822 interp_param_idx = lookup_interp_param_index(interp_mode, interp_loc);
1823 if (interp_param_idx == -1)
1824 return;
1825 else if (interp_param_idx) {
1826 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
1827 }
1828
1829 interp_fs_input(ctx, input_index, semantic_name,
1830 semantic_index, 0, /* this param is unused */
1831 shader->selector->info.colors_read, interp_param,
1832 ctx->abi.prim_mask,
1833 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1834 &out[0]);
1835 }
1836
1837 static void declare_input_fs(
1838 struct si_shader_context *ctx,
1839 unsigned input_index,
1840 const struct tgsi_full_declaration *decl,
1841 LLVMValueRef out[4])
1842 {
1843 si_llvm_load_input_fs(ctx, input_index, out);
1844 }
1845
1846 LLVMValueRef si_get_sample_id(struct si_shader_context *ctx)
1847 {
1848 return si_unpack_param(ctx, SI_PARAM_ANCILLARY, 8, 4);
1849 }
1850
1851 static LLVMValueRef get_base_vertex(struct ac_shader_abi *abi)
1852 {
1853 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1854
1855 /* For non-indexed draws, the base vertex set by the driver
1856 * (for direct draws) or the CP (for indirect draws) is the
1857 * first vertex ID, but GLSL expects 0 to be returned.
1858 */
1859 LLVMValueRef vs_state = LLVMGetParam(ctx->main_fn,
1860 ctx->param_vs_state_bits);
1861 LLVMValueRef indexed;
1862
1863 indexed = LLVMBuildLShr(ctx->ac.builder, vs_state, ctx->i32_1, "");
1864 indexed = LLVMBuildTrunc(ctx->ac.builder, indexed, ctx->i1, "");
1865
1866 return LLVMBuildSelect(ctx->ac.builder, indexed, ctx->abi.base_vertex,
1867 ctx->i32_0, "");
1868 }
1869
1870 static LLVMValueRef get_block_size(struct ac_shader_abi *abi)
1871 {
1872 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1873
1874 LLVMValueRef values[3];
1875 LLVMValueRef result;
1876 unsigned i;
1877 unsigned *properties = ctx->shader->selector->info.properties;
1878
1879 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1880 unsigned sizes[3] = {
1881 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1882 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1883 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1884 };
1885
1886 for (i = 0; i < 3; ++i)
1887 values[i] = LLVMConstInt(ctx->i32, sizes[i], 0);
1888
1889 result = ac_build_gather_values(&ctx->ac, values, 3);
1890 } else {
1891 result = LLVMGetParam(ctx->main_fn, ctx->param_block_size);
1892 }
1893
1894 return result;
1895 }
1896
1897 /**
1898 * Load a dword from a constant buffer.
1899 */
1900 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1901 LLVMValueRef resource,
1902 LLVMValueRef offset)
1903 {
1904 return ac_build_buffer_load(&ctx->ac, resource, 1, NULL, offset, NULL,
1905 0, 0, true, true);
1906 }
1907
1908 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi, LLVMValueRef sample_id)
1909 {
1910 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1911 LLVMValueRef desc = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1912 LLVMValueRef buf_index = LLVMConstInt(ctx->i32, SI_PS_CONST_SAMPLE_POSITIONS, 0);
1913 LLVMValueRef resource = ac_build_load_to_sgpr(&ctx->ac, desc, buf_index);
1914
1915 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1916 LLVMValueRef offset0 = LLVMBuildMul(ctx->ac.builder, sample_id, LLVMConstInt(ctx->i32, 8, 0), "");
1917 LLVMValueRef offset1 = LLVMBuildAdd(ctx->ac.builder, offset0, LLVMConstInt(ctx->i32, 4, 0), "");
1918
1919 LLVMValueRef pos[4] = {
1920 buffer_load_const(ctx, resource, offset0),
1921 buffer_load_const(ctx, resource, offset1),
1922 LLVMConstReal(ctx->f32, 0),
1923 LLVMConstReal(ctx->f32, 0)
1924 };
1925
1926 return ac_build_gather_values(&ctx->ac, pos, 4);
1927 }
1928
1929 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1930 {
1931 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1932 return ac_to_integer(&ctx->ac, abi->sample_coverage);
1933 }
1934
1935 static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
1936 {
1937 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1938 LLVMValueRef coord[4] = {
1939 LLVMGetParam(ctx->main_fn, ctx->param_tes_u),
1940 LLVMGetParam(ctx->main_fn, ctx->param_tes_v),
1941 ctx->ac.f32_0,
1942 ctx->ac.f32_0
1943 };
1944
1945 /* For triangles, the vector should be (u, v, 1-u-v). */
1946 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1947 PIPE_PRIM_TRIANGLES) {
1948 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1949 LLVMBuildFAdd(ctx->ac.builder,
1950 coord[0], coord[1], ""), "");
1951 }
1952 return ac_build_gather_values(&ctx->ac, coord, 4);
1953 }
1954
1955 static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
1956 unsigned semantic_name)
1957 {
1958 LLVMValueRef base, addr;
1959
1960 int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
1961
1962 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
1963 addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
1964 LLVMConstInt(ctx->i32, param, 0));
1965
1966 return buffer_load(&ctx->bld_base, ctx->f32,
1967 ~0, ctx->tess_offchip_ring, base, addr, true);
1968
1969 }
1970
1971 static LLVMValueRef load_tess_level_default(struct si_shader_context *ctx,
1972 unsigned semantic_name)
1973 {
1974 LLVMValueRef buf, slot, val[4];
1975 int i, offset;
1976
1977 slot = LLVMConstInt(ctx->i32, SI_HS_CONST_DEFAULT_TESS_LEVELS, 0);
1978 buf = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1979 buf = ac_build_load_to_sgpr(&ctx->ac, buf, slot);
1980 offset = semantic_name == TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL ? 4 : 0;
1981
1982 for (i = 0; i < 4; i++)
1983 val[i] = buffer_load_const(ctx, buf,
1984 LLVMConstInt(ctx->i32, (offset + i) * 4, 0));
1985 return ac_build_gather_values(&ctx->ac, val, 4);
1986 }
1987
1988 static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
1989 unsigned varying_id,
1990 bool load_default_state)
1991 {
1992 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1993 unsigned semantic_name;
1994
1995 if (load_default_state) {
1996 switch (varying_id) {
1997 case VARYING_SLOT_TESS_LEVEL_INNER:
1998 semantic_name = TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL;
1999 break;
2000 case VARYING_SLOT_TESS_LEVEL_OUTER:
2001 semantic_name = TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL;
2002 break;
2003 default:
2004 unreachable("unknown tess level");
2005 }
2006 return load_tess_level_default(ctx, semantic_name);
2007 }
2008
2009 switch (varying_id) {
2010 case VARYING_SLOT_TESS_LEVEL_INNER:
2011 semantic_name = TGSI_SEMANTIC_TESSINNER;
2012 break;
2013 case VARYING_SLOT_TESS_LEVEL_OUTER:
2014 semantic_name = TGSI_SEMANTIC_TESSOUTER;
2015 break;
2016 default:
2017 unreachable("unknown tess level");
2018 }
2019
2020 return load_tess_level(ctx, semantic_name);
2021
2022 }
2023
2024 static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
2025 {
2026 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2027 if (ctx->type == PIPE_SHADER_TESS_CTRL)
2028 return si_unpack_param(ctx, ctx->param_tcs_out_lds_layout, 13, 6);
2029 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
2030 return get_num_tcs_out_vertices(ctx);
2031 else
2032 unreachable("invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
2033 }
2034
2035 void si_load_system_value(struct si_shader_context *ctx,
2036 unsigned index,
2037 const struct tgsi_full_declaration *decl)
2038 {
2039 LLVMValueRef value = 0;
2040
2041 assert(index < RADEON_LLVM_MAX_SYSTEM_VALUES);
2042
2043 switch (decl->Semantic.Name) {
2044 case TGSI_SEMANTIC_INSTANCEID:
2045 value = ctx->abi.instance_id;
2046 break;
2047
2048 case TGSI_SEMANTIC_VERTEXID:
2049 value = LLVMBuildAdd(ctx->ac.builder,
2050 ctx->abi.vertex_id,
2051 ctx->abi.base_vertex, "");
2052 break;
2053
2054 case TGSI_SEMANTIC_VERTEXID_NOBASE:
2055 /* Unused. Clarify the meaning in indexed vs. non-indexed
2056 * draws if this is ever used again. */
2057 assert(false);
2058 break;
2059
2060 case TGSI_SEMANTIC_BASEVERTEX:
2061 value = get_base_vertex(&ctx->abi);
2062 break;
2063
2064 case TGSI_SEMANTIC_BASEINSTANCE:
2065 value = ctx->abi.start_instance;
2066 break;
2067
2068 case TGSI_SEMANTIC_DRAWID:
2069 value = ctx->abi.draw_id;
2070 break;
2071
2072 case TGSI_SEMANTIC_INVOCATIONID:
2073 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
2074 value = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
2075 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
2076 if (ctx->screen->info.chip_class >= GFX10) {
2077 value = LLVMBuildAnd(ctx->ac.builder,
2078 ctx->abi.gs_invocation_id,
2079 LLVMConstInt(ctx->i32, 127, 0), "");
2080 } else {
2081 value = ctx->abi.gs_invocation_id;
2082 }
2083 } else {
2084 assert(!"INVOCATIONID not implemented");
2085 }
2086 break;
2087
2088 case TGSI_SEMANTIC_POSITION:
2089 {
2090 LLVMValueRef pos[4] = {
2091 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2092 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2093 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT),
2094 ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
2095 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT)),
2096 };
2097 value = ac_build_gather_values(&ctx->ac, pos, 4);
2098 break;
2099 }
2100
2101 case TGSI_SEMANTIC_FACE:
2102 value = ctx->abi.front_face;
2103 break;
2104
2105 case TGSI_SEMANTIC_SAMPLEID:
2106 value = si_get_sample_id(ctx);
2107 break;
2108
2109 case TGSI_SEMANTIC_SAMPLEPOS: {
2110 LLVMValueRef pos[4] = {
2111 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT),
2112 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT),
2113 LLVMConstReal(ctx->f32, 0),
2114 LLVMConstReal(ctx->f32, 0)
2115 };
2116 pos[0] = ac_build_fract(&ctx->ac, pos[0], 32);
2117 pos[1] = ac_build_fract(&ctx->ac, pos[1], 32);
2118 value = ac_build_gather_values(&ctx->ac, pos, 4);
2119 break;
2120 }
2121
2122 case TGSI_SEMANTIC_SAMPLEMASK:
2123 /* This can only occur with the OpenGL Core profile, which
2124 * doesn't support smoothing.
2125 */
2126 value = LLVMGetParam(ctx->main_fn, SI_PARAM_SAMPLE_COVERAGE);
2127 break;
2128
2129 case TGSI_SEMANTIC_TESSCOORD:
2130 value = si_load_tess_coord(&ctx->abi);
2131 break;
2132
2133 case TGSI_SEMANTIC_VERTICESIN:
2134 value = si_load_patch_vertices_in(&ctx->abi);
2135 break;
2136
2137 case TGSI_SEMANTIC_TESSINNER:
2138 case TGSI_SEMANTIC_TESSOUTER:
2139 value = load_tess_level(ctx, decl->Semantic.Name);
2140 break;
2141
2142 case TGSI_SEMANTIC_TESS_DEFAULT_OUTER_LEVEL:
2143 case TGSI_SEMANTIC_TESS_DEFAULT_INNER_LEVEL:
2144 value = load_tess_level_default(ctx, decl->Semantic.Name);
2145 break;
2146
2147 case TGSI_SEMANTIC_PRIMID:
2148 value = si_get_primitive_id(ctx, 0);
2149 break;
2150
2151 case TGSI_SEMANTIC_GRID_SIZE:
2152 value = ctx->abi.num_work_groups;
2153 break;
2154
2155 case TGSI_SEMANTIC_BLOCK_SIZE:
2156 value = get_block_size(&ctx->abi);
2157 break;
2158
2159 case TGSI_SEMANTIC_BLOCK_ID:
2160 {
2161 LLVMValueRef values[3];
2162
2163 for (int i = 0; i < 3; i++) {
2164 values[i] = ctx->i32_0;
2165 if (ctx->abi.workgroup_ids[i]) {
2166 values[i] = ctx->abi.workgroup_ids[i];
2167 }
2168 }
2169 value = ac_build_gather_values(&ctx->ac, values, 3);
2170 break;
2171 }
2172
2173 case TGSI_SEMANTIC_THREAD_ID:
2174 value = ctx->abi.local_invocation_ids;
2175 break;
2176
2177 case TGSI_SEMANTIC_HELPER_INVOCATION:
2178 value = ac_build_load_helper_invocation(&ctx->ac);
2179 break;
2180
2181 case TGSI_SEMANTIC_SUBGROUP_SIZE:
2182 value = LLVMConstInt(ctx->i32, ctx->ac.wave_size, 0);
2183 break;
2184
2185 case TGSI_SEMANTIC_SUBGROUP_INVOCATION:
2186 value = ac_get_thread_id(&ctx->ac);
2187 break;
2188
2189 case TGSI_SEMANTIC_SUBGROUP_EQ_MASK:
2190 {
2191 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2192 if (ctx->ac.wave_size == 64)
2193 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2194 value = LLVMBuildShl(ctx->ac.builder,
2195 LLVMConstInt(ctx->ac.iN_wavemask, 1, 0), id, "");
2196 if (ctx->ac.wave_size == 32)
2197 value = LLVMBuildZExt(ctx->ac.builder, value, ctx->i64, "");
2198 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2199 break;
2200 }
2201
2202 case TGSI_SEMANTIC_SUBGROUP_GE_MASK:
2203 case TGSI_SEMANTIC_SUBGROUP_GT_MASK:
2204 case TGSI_SEMANTIC_SUBGROUP_LE_MASK:
2205 case TGSI_SEMANTIC_SUBGROUP_LT_MASK:
2206 {
2207 LLVMValueRef id = ac_get_thread_id(&ctx->ac);
2208 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_GT_MASK ||
2209 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK) {
2210 /* All bits set except LSB */
2211 value = LLVMConstInt(ctx->ac.iN_wavemask, -2, 0);
2212 } else {
2213 /* All bits set */
2214 value = LLVMConstInt(ctx->ac.iN_wavemask, -1, 0);
2215 }
2216 if (ctx->ac.wave_size == 64)
2217 id = LLVMBuildZExt(ctx->ac.builder, id, ctx->i64, "");
2218 value = LLVMBuildShl(ctx->ac.builder, value, id, "");
2219 if (decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LE_MASK ||
2220 decl->Semantic.Name == TGSI_SEMANTIC_SUBGROUP_LT_MASK)
2221 value = LLVMBuildNot(ctx->ac.builder, value, "");
2222 if (ctx->ac.wave_size == 32)
2223 value = LLVMBuildZExt(ctx->ac.builder, value, ctx->i64, "");
2224 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->v2i32, "");
2225 break;
2226 }
2227
2228 case TGSI_SEMANTIC_CS_USER_DATA_AMD:
2229 value = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
2230 break;
2231
2232 default:
2233 assert(!"unknown system value");
2234 return;
2235 }
2236
2237 ctx->system_values[index] = value;
2238 }
2239
2240 void si_declare_compute_memory(struct si_shader_context *ctx)
2241 {
2242 struct si_shader_selector *sel = ctx->shader->selector;
2243 unsigned lds_size = sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE];
2244
2245 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, AC_ADDR_SPACE_LDS);
2246 LLVMValueRef var;
2247
2248 assert(!ctx->ac.lds);
2249
2250 var = LLVMAddGlobalInAddressSpace(ctx->ac.module,
2251 LLVMArrayType(ctx->i8, lds_size),
2252 "compute_lds",
2253 AC_ADDR_SPACE_LDS);
2254 LLVMSetAlignment(var, 64 * 1024);
2255
2256 ctx->ac.lds = LLVMBuildBitCast(ctx->ac.builder, var, i8p, "");
2257 }
2258
2259 void si_tgsi_declare_compute_memory(struct si_shader_context *ctx,
2260 const struct tgsi_full_declaration *decl)
2261 {
2262 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
2263 assert(decl->Range.First == decl->Range.Last);
2264
2265 si_declare_compute_memory(ctx);
2266 }
2267
2268 static LLVMValueRef load_const_buffer_desc_fast_path(struct si_shader_context *ctx)
2269 {
2270 LLVMValueRef ptr =
2271 LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2272 struct si_shader_selector *sel = ctx->shader->selector;
2273
2274 /* Do the bounds checking with a descriptor, because
2275 * doing computation and manual bounds checking of 64-bit
2276 * addresses generates horrible VALU code with very high
2277 * VGPR usage and very low SIMD occupancy.
2278 */
2279 ptr = LLVMBuildPtrToInt(ctx->ac.builder, ptr, ctx->ac.intptr, "");
2280
2281 LLVMValueRef desc0, desc1;
2282 desc0 = ptr;
2283 desc1 = LLVMConstInt(ctx->i32,
2284 S_008F04_BASE_ADDRESS_HI(ctx->screen->info.address32_hi), 0);
2285
2286 uint32_t rsrc3 = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2287 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2288 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2289 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2290
2291 if (ctx->screen->info.chip_class >= GFX10)
2292 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2293 S_008F0C_OOB_SELECT(3) |
2294 S_008F0C_RESOURCE_LEVEL(1);
2295 else
2296 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2297 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2298
2299 LLVMValueRef desc_elems[] = {
2300 desc0,
2301 desc1,
2302 LLVMConstInt(ctx->i32, (sel->info.const_file_max[0] + 1) * 16, 0),
2303 LLVMConstInt(ctx->i32, rsrc3, false)
2304 };
2305
2306 return ac_build_gather_values(&ctx->ac, desc_elems, 4);
2307 }
2308
2309 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
2310 {
2311 LLVMValueRef list_ptr = LLVMGetParam(ctx->main_fn,
2312 ctx->param_const_and_shader_buffers);
2313
2314 return ac_build_load_to_sgpr(&ctx->ac, list_ptr,
2315 LLVMConstInt(ctx->i32, si_get_constbuf_slot(i), 0));
2316 }
2317
2318 static LLVMValueRef load_ubo(struct ac_shader_abi *abi, LLVMValueRef index)
2319 {
2320 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2321 struct si_shader_selector *sel = ctx->shader->selector;
2322
2323 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2324
2325 if (sel->info.const_buffers_declared == 1 &&
2326 sel->info.shader_buffers_declared == 0) {
2327 return load_const_buffer_desc_fast_path(ctx);
2328 }
2329
2330 index = si_llvm_bound_index(ctx, index, ctx->num_const_buffers);
2331 index = LLVMBuildAdd(ctx->ac.builder, index,
2332 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2333
2334 return ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2335 }
2336
2337 static LLVMValueRef
2338 load_ssbo(struct ac_shader_abi *abi, LLVMValueRef index, bool write)
2339 {
2340 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
2341 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
2342 ctx->param_const_and_shader_buffers);
2343
2344 index = si_llvm_bound_index(ctx, index, ctx->num_shader_buffers);
2345 index = LLVMBuildSub(ctx->ac.builder,
2346 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS - 1, 0),
2347 index, "");
2348
2349 return ac_build_load_to_sgpr(&ctx->ac, rsrc_ptr, index);
2350 }
2351
2352 static LLVMValueRef fetch_constant(
2353 struct lp_build_tgsi_context *bld_base,
2354 const struct tgsi_full_src_register *reg,
2355 enum tgsi_opcode_type type,
2356 unsigned swizzle_in)
2357 {
2358 struct si_shader_context *ctx = si_shader_context(bld_base);
2359 struct si_shader_selector *sel = ctx->shader->selector;
2360 const struct tgsi_ind_register *ireg = &reg->Indirect;
2361 unsigned buf, idx;
2362 unsigned swizzle = swizzle_in & 0xffff;
2363
2364 LLVMValueRef addr, bufp;
2365
2366 if (swizzle_in == LP_CHAN_ALL) {
2367 unsigned chan;
2368 LLVMValueRef values[4];
2369 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
2370 values[chan] = fetch_constant(bld_base, reg, type, chan);
2371
2372 return ac_build_gather_values(&ctx->ac, values, 4);
2373 }
2374
2375 /* Split 64-bit loads. */
2376 if (tgsi_type_is_64bit(type)) {
2377 LLVMValueRef lo, hi;
2378
2379 lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
2380 hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, (swizzle_in >> 16));
2381 return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
2382 lo, hi);
2383 }
2384
2385 idx = reg->Register.Index * 4 + swizzle;
2386 if (reg->Register.Indirect) {
2387 addr = si_get_indirect_index(ctx, ireg, 16, idx * 4);
2388 } else {
2389 addr = LLVMConstInt(ctx->i32, idx * 4, 0);
2390 }
2391
2392 /* Fast path when user data SGPRs point to constant buffer 0 directly. */
2393 if (sel->info.const_buffers_declared == 1 &&
2394 sel->info.shader_buffers_declared == 0) {
2395 LLVMValueRef desc = load_const_buffer_desc_fast_path(ctx);
2396 LLVMValueRef result = buffer_load_const(ctx, desc, addr);
2397 return bitcast(bld_base, type, result);
2398 }
2399
2400 assert(reg->Register.Dimension);
2401 buf = reg->Dimension.Index;
2402
2403 if (reg->Dimension.Indirect) {
2404 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_const_and_shader_buffers);
2405 LLVMValueRef index;
2406 index = si_get_bounded_indirect_index(ctx, &reg->DimIndirect,
2407 reg->Dimension.Index,
2408 ctx->num_const_buffers);
2409 index = LLVMBuildAdd(ctx->ac.builder, index,
2410 LLVMConstInt(ctx->i32, SI_NUM_SHADER_BUFFERS, 0), "");
2411 bufp = ac_build_load_to_sgpr(&ctx->ac, ptr, index);
2412 } else
2413 bufp = load_const_buffer_desc(ctx, buf);
2414
2415 return bitcast(bld_base, type, buffer_load_const(ctx, bufp, addr));
2416 }
2417
2418 /* Initialize arguments for the shader export intrinsic */
2419 static void si_llvm_init_export_args(struct si_shader_context *ctx,
2420 LLVMValueRef *values,
2421 unsigned target,
2422 struct ac_export_args *args)
2423 {
2424 LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
2425 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
2426 unsigned chan;
2427 bool is_int8, is_int10;
2428
2429 /* Default is 0xf. Adjusted below depending on the format. */
2430 args->enabled_channels = 0xf; /* writemask */
2431
2432 /* Specify whether the EXEC mask represents the valid mask */
2433 args->valid_mask = 0;
2434
2435 /* Specify whether this is the last export */
2436 args->done = 0;
2437
2438 /* Specify the target we are exporting */
2439 args->target = target;
2440
2441 if (ctx->type == PIPE_SHADER_FRAGMENT) {
2442 const struct si_shader_key *key = &ctx->shader->key;
2443 unsigned col_formats = key->part.ps.epilog.spi_shader_col_format;
2444 int cbuf = target - V_008DFC_SQ_EXP_MRT;
2445
2446 assert(cbuf >= 0 && cbuf < 8);
2447 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
2448 is_int8 = (key->part.ps.epilog.color_is_int8 >> cbuf) & 0x1;
2449 is_int10 = (key->part.ps.epilog.color_is_int10 >> cbuf) & 0x1;
2450 }
2451
2452 args->compr = false;
2453 args->out[0] = f32undef;
2454 args->out[1] = f32undef;
2455 args->out[2] = f32undef;
2456 args->out[3] = f32undef;
2457
2458 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2459 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2460 unsigned bits, bool hi) = NULL;
2461
2462 switch (spi_shader_col_format) {
2463 case V_028714_SPI_SHADER_ZERO:
2464 args->enabled_channels = 0; /* writemask */
2465 args->target = V_008DFC_SQ_EXP_NULL;
2466 break;
2467
2468 case V_028714_SPI_SHADER_32_R:
2469 args->enabled_channels = 1; /* writemask */
2470 args->out[0] = values[0];
2471 break;
2472
2473 case V_028714_SPI_SHADER_32_GR:
2474 args->enabled_channels = 0x3; /* writemask */
2475 args->out[0] = values[0];
2476 args->out[1] = values[1];
2477 break;
2478
2479 case V_028714_SPI_SHADER_32_AR:
2480 if (ctx->screen->info.chip_class >= GFX10) {
2481 args->enabled_channels = 0x3; /* writemask */
2482 args->out[0] = values[0];
2483 args->out[1] = values[3];
2484 } else {
2485 args->enabled_channels = 0x9; /* writemask */
2486 args->out[0] = values[0];
2487 args->out[3] = values[3];
2488 }
2489 break;
2490
2491 case V_028714_SPI_SHADER_FP16_ABGR:
2492 packf = ac_build_cvt_pkrtz_f16;
2493 break;
2494
2495 case V_028714_SPI_SHADER_UNORM16_ABGR:
2496 packf = ac_build_cvt_pknorm_u16;
2497 break;
2498
2499 case V_028714_SPI_SHADER_SNORM16_ABGR:
2500 packf = ac_build_cvt_pknorm_i16;
2501 break;
2502
2503 case V_028714_SPI_SHADER_UINT16_ABGR:
2504 packi = ac_build_cvt_pk_u16;
2505 break;
2506
2507 case V_028714_SPI_SHADER_SINT16_ABGR:
2508 packi = ac_build_cvt_pk_i16;
2509 break;
2510
2511 case V_028714_SPI_SHADER_32_ABGR:
2512 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2513 break;
2514 }
2515
2516 /* Pack f16 or norm_i16/u16. */
2517 if (packf) {
2518 for (chan = 0; chan < 2; chan++) {
2519 LLVMValueRef pack_args[2] = {
2520 values[2 * chan],
2521 values[2 * chan + 1]
2522 };
2523 LLVMValueRef packed;
2524
2525 packed = packf(&ctx->ac, pack_args);
2526 args->out[chan] = ac_to_float(&ctx->ac, packed);
2527 }
2528 args->compr = 1; /* COMPR flag */
2529 }
2530 /* Pack i16/u16. */
2531 if (packi) {
2532 for (chan = 0; chan < 2; chan++) {
2533 LLVMValueRef pack_args[2] = {
2534 ac_to_integer(&ctx->ac, values[2 * chan]),
2535 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2536 };
2537 LLVMValueRef packed;
2538
2539 packed = packi(&ctx->ac, pack_args,
2540 is_int8 ? 8 : is_int10 ? 10 : 16,
2541 chan == 1);
2542 args->out[chan] = ac_to_float(&ctx->ac, packed);
2543 }
2544 args->compr = 1; /* COMPR flag */
2545 }
2546 }
2547
2548 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2549 LLVMValueRef alpha)
2550 {
2551 struct si_shader_context *ctx = si_shader_context(bld_base);
2552
2553 if (ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2554 static LLVMRealPredicate cond_map[PIPE_FUNC_ALWAYS + 1] = {
2555 [PIPE_FUNC_LESS] = LLVMRealOLT,
2556 [PIPE_FUNC_EQUAL] = LLVMRealOEQ,
2557 [PIPE_FUNC_LEQUAL] = LLVMRealOLE,
2558 [PIPE_FUNC_GREATER] = LLVMRealOGT,
2559 [PIPE_FUNC_NOTEQUAL] = LLVMRealONE,
2560 [PIPE_FUNC_GEQUAL] = LLVMRealOGE,
2561 };
2562 LLVMRealPredicate cond = cond_map[ctx->shader->key.part.ps.epilog.alpha_func];
2563 assert(cond);
2564
2565 LLVMValueRef alpha_ref = LLVMGetParam(ctx->main_fn,
2566 SI_PARAM_ALPHA_REF);
2567 LLVMValueRef alpha_pass =
2568 LLVMBuildFCmp(ctx->ac.builder, cond, alpha, alpha_ref, "");
2569 ac_build_kill_if_false(&ctx->ac, alpha_pass);
2570 } else {
2571 ac_build_kill_if_false(&ctx->ac, ctx->i1false);
2572 }
2573 }
2574
2575 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2576 LLVMValueRef alpha,
2577 unsigned samplemask_param)
2578 {
2579 struct si_shader_context *ctx = si_shader_context(bld_base);
2580 LLVMValueRef coverage;
2581
2582 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2583 coverage = LLVMGetParam(ctx->main_fn,
2584 samplemask_param);
2585 coverage = ac_to_integer(&ctx->ac, coverage);
2586
2587 coverage = ac_build_intrinsic(&ctx->ac, "llvm.ctpop.i32",
2588 ctx->i32,
2589 &coverage, 1, AC_FUNC_ATTR_READNONE);
2590
2591 coverage = LLVMBuildUIToFP(ctx->ac.builder, coverage,
2592 ctx->f32, "");
2593
2594 coverage = LLVMBuildFMul(ctx->ac.builder, coverage,
2595 LLVMConstReal(ctx->f32,
2596 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2597
2598 return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
2599 }
2600
2601 static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
2602 struct ac_export_args *pos, LLVMValueRef *out_elts)
2603 {
2604 unsigned reg_index;
2605 unsigned chan;
2606 unsigned const_chan;
2607 LLVMValueRef base_elt;
2608 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
2609 LLVMValueRef constbuf_index = LLVMConstInt(ctx->i32,
2610 SI_VS_CONST_CLIP_PLANES, 0);
2611 LLVMValueRef const_resource = ac_build_load_to_sgpr(&ctx->ac, ptr, constbuf_index);
2612
2613 for (reg_index = 0; reg_index < 2; reg_index ++) {
2614 struct ac_export_args *args = &pos[2 + reg_index];
2615
2616 args->out[0] =
2617 args->out[1] =
2618 args->out[2] =
2619 args->out[3] = LLVMConstReal(ctx->f32, 0.0f);
2620
2621 /* Compute dot products of position and user clip plane vectors */
2622 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2623 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2624 LLVMValueRef addr =
2625 LLVMConstInt(ctx->i32, ((reg_index * 4 + chan) * 4 +
2626 const_chan) * 4, 0);
2627 base_elt = buffer_load_const(ctx, const_resource,
2628 addr);
2629 args->out[chan] = ac_build_fmad(&ctx->ac, base_elt,
2630 out_elts[const_chan], args->out[chan]);
2631 }
2632 }
2633
2634 args->enabled_channels = 0xf;
2635 args->valid_mask = 0;
2636 args->done = 0;
2637 args->target = V_008DFC_SQ_EXP_POS + 2 + reg_index;
2638 args->compr = 0;
2639 }
2640 }
2641
2642 static void si_dump_streamout(struct pipe_stream_output_info *so)
2643 {
2644 unsigned i;
2645
2646 if (so->num_outputs)
2647 fprintf(stderr, "STREAMOUT\n");
2648
2649 for (i = 0; i < so->num_outputs; i++) {
2650 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2651 so->output[i].start_component;
2652 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2653 i, so->output[i].output_buffer,
2654 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2655 so->output[i].register_index,
2656 mask & 1 ? "x" : "",
2657 mask & 2 ? "y" : "",
2658 mask & 4 ? "z" : "",
2659 mask & 8 ? "w" : "");
2660 }
2661 }
2662
2663 void si_emit_streamout_output(struct si_shader_context *ctx,
2664 LLVMValueRef const *so_buffers,
2665 LLVMValueRef const *so_write_offsets,
2666 struct pipe_stream_output *stream_out,
2667 struct si_shader_output_values *shader_out)
2668 {
2669 unsigned buf_idx = stream_out->output_buffer;
2670 unsigned start = stream_out->start_component;
2671 unsigned num_comps = stream_out->num_components;
2672 LLVMValueRef out[4];
2673
2674 assert(num_comps && num_comps <= 4);
2675 if (!num_comps || num_comps > 4)
2676 return;
2677
2678 /* Load the output as int. */
2679 for (int j = 0; j < num_comps; j++) {
2680 assert(stream_out->stream == shader_out->vertex_stream[start + j]);
2681
2682 out[j] = ac_to_integer(&ctx->ac, shader_out->values[start + j]);
2683 }
2684
2685 /* Pack the output. */
2686 LLVMValueRef vdata = NULL;
2687
2688 switch (num_comps) {
2689 case 1: /* as i32 */
2690 vdata = out[0];
2691 break;
2692 case 2: /* as v2i32 */
2693 case 3: /* as v3i32 */
2694 if (ac_has_vec3_support(ctx->screen->info.chip_class, false)) {
2695 vdata = ac_build_gather_values(&ctx->ac, out, num_comps);
2696 break;
2697 }
2698 /* as v4i32 (aligned to 4) */
2699 out[3] = LLVMGetUndef(ctx->i32);
2700 /* fall through */
2701 case 4: /* as v4i32 */
2702 vdata = ac_build_gather_values(&ctx->ac, out, util_next_power_of_two(num_comps));
2703 break;
2704 }
2705
2706 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf_idx],
2707 vdata, num_comps,
2708 so_write_offsets[buf_idx],
2709 ctx->i32_0,
2710 stream_out->dst_offset * 4, ac_glc | ac_slc, false);
2711 }
2712
2713 /**
2714 * Write streamout data to buffers for vertex stream @p stream (different
2715 * vertex streams can occur for GS copy shaders).
2716 */
2717 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2718 struct si_shader_output_values *outputs,
2719 unsigned noutput, unsigned stream)
2720 {
2721 struct si_shader_selector *sel = ctx->shader->selector;
2722 struct pipe_stream_output_info *so = &sel->so;
2723 LLVMBuilderRef builder = ctx->ac.builder;
2724 int i;
2725
2726 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2727 LLVMValueRef so_vtx_count =
2728 si_unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2729
2730 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2731
2732 /* can_emit = tid < so_vtx_count; */
2733 LLVMValueRef can_emit =
2734 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2735
2736 /* Emit the streamout code conditionally. This actually avoids
2737 * out-of-bounds buffer access. The hw tells us via the SGPR
2738 * (so_vtx_count) which threads are allowed to emit streamout data. */
2739 ac_build_ifcc(&ctx->ac, can_emit, 6501);
2740 {
2741 /* The buffer offset is computed as follows:
2742 * ByteOffset = streamout_offset[buffer_id]*4 +
2743 * (streamout_write_index + thread_id)*stride[buffer_id] +
2744 * attrib_offset
2745 */
2746
2747 LLVMValueRef so_write_index =
2748 LLVMGetParam(ctx->main_fn,
2749 ctx->param_streamout_write_index);
2750
2751 /* Compute (streamout_write_index + thread_id). */
2752 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2753
2754 /* Load the descriptor and compute the write offset for each
2755 * enabled buffer. */
2756 LLVMValueRef so_write_offset[4] = {};
2757 LLVMValueRef so_buffers[4];
2758 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
2759 ctx->param_rw_buffers);
2760
2761 for (i = 0; i < 4; i++) {
2762 if (!so->stride[i])
2763 continue;
2764
2765 LLVMValueRef offset = LLVMConstInt(ctx->i32,
2766 SI_VS_STREAMOUT_BUF0 + i, 0);
2767
2768 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
2769
2770 LLVMValueRef so_offset = LLVMGetParam(ctx->main_fn,
2771 ctx->param_streamout_offset[i]);
2772 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2773
2774 so_write_offset[i] = ac_build_imad(&ctx->ac, so_write_index,
2775 LLVMConstInt(ctx->i32, so->stride[i]*4, 0),
2776 so_offset);
2777 }
2778
2779 /* Write streamout data. */
2780 for (i = 0; i < so->num_outputs; i++) {
2781 unsigned reg = so->output[i].register_index;
2782
2783 if (reg >= noutput)
2784 continue;
2785
2786 if (stream != so->output[i].stream)
2787 continue;
2788
2789 si_emit_streamout_output(ctx, so_buffers, so_write_offset,
2790 &so->output[i], &outputs[reg]);
2791 }
2792 }
2793 ac_build_endif(&ctx->ac, 6501);
2794 }
2795
2796 static void si_export_param(struct si_shader_context *ctx, unsigned index,
2797 LLVMValueRef *values)
2798 {
2799 struct ac_export_args args;
2800
2801 si_llvm_init_export_args(ctx, values,
2802 V_008DFC_SQ_EXP_PARAM + index, &args);
2803 ac_build_export(&ctx->ac, &args);
2804 }
2805
2806 static void si_build_param_exports(struct si_shader_context *ctx,
2807 struct si_shader_output_values *outputs,
2808 unsigned noutput)
2809 {
2810 struct si_shader *shader = ctx->shader;
2811 unsigned param_count = 0;
2812
2813 for (unsigned i = 0; i < noutput; i++) {
2814 unsigned semantic_name = outputs[i].semantic_name;
2815 unsigned semantic_index = outputs[i].semantic_index;
2816
2817 if (outputs[i].vertex_stream[0] != 0 &&
2818 outputs[i].vertex_stream[1] != 0 &&
2819 outputs[i].vertex_stream[2] != 0 &&
2820 outputs[i].vertex_stream[3] != 0)
2821 continue;
2822
2823 switch (semantic_name) {
2824 case TGSI_SEMANTIC_LAYER:
2825 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2826 case TGSI_SEMANTIC_CLIPDIST:
2827 case TGSI_SEMANTIC_COLOR:
2828 case TGSI_SEMANTIC_BCOLOR:
2829 case TGSI_SEMANTIC_PRIMID:
2830 case TGSI_SEMANTIC_FOG:
2831 case TGSI_SEMANTIC_TEXCOORD:
2832 case TGSI_SEMANTIC_GENERIC:
2833 break;
2834 default:
2835 continue;
2836 }
2837
2838 if ((semantic_name != TGSI_SEMANTIC_GENERIC ||
2839 semantic_index < SI_MAX_IO_GENERIC) &&
2840 shader->key.opt.kill_outputs &
2841 (1ull << si_shader_io_get_unique_index(semantic_name,
2842 semantic_index, true)))
2843 continue;
2844
2845 si_export_param(ctx, param_count, outputs[i].values);
2846
2847 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2848 shader->info.vs_output_param_offset[i] = param_count++;
2849 }
2850
2851 shader->info.nr_param_exports = param_count;
2852 }
2853
2854 /**
2855 * Vertex color clamping.
2856 *
2857 * This uses a state constant loaded in a user data SGPR and
2858 * an IF statement is added that clamps all colors if the constant
2859 * is true.
2860 */
2861 static void si_vertex_color_clamping(struct si_shader_context *ctx,
2862 struct si_shader_output_values *outputs,
2863 unsigned noutput)
2864 {
2865 LLVMValueRef addr[SI_MAX_VS_OUTPUTS][4];
2866 bool has_colors = false;
2867
2868 /* Store original colors to alloca variables. */
2869 for (unsigned i = 0; i < noutput; i++) {
2870 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2871 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2872 continue;
2873
2874 for (unsigned j = 0; j < 4; j++) {
2875 addr[i][j] = ac_build_alloca_undef(&ctx->ac, ctx->f32, "");
2876 LLVMBuildStore(ctx->ac.builder, outputs[i].values[j], addr[i][j]);
2877 }
2878 has_colors = true;
2879 }
2880
2881 if (!has_colors)
2882 return;
2883
2884 /* The state is in the first bit of the user SGPR. */
2885 LLVMValueRef cond = LLVMGetParam(ctx->main_fn, ctx->param_vs_state_bits);
2886 cond = LLVMBuildTrunc(ctx->ac.builder, cond, ctx->i1, "");
2887
2888 ac_build_ifcc(&ctx->ac, cond, 6502);
2889
2890 /* Store clamped colors to alloca variables within the conditional block. */
2891 for (unsigned i = 0; i < noutput; i++) {
2892 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2893 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2894 continue;
2895
2896 for (unsigned j = 0; j < 4; j++) {
2897 LLVMBuildStore(ctx->ac.builder,
2898 ac_build_clamp(&ctx->ac, outputs[i].values[j]),
2899 addr[i][j]);
2900 }
2901 }
2902 ac_build_endif(&ctx->ac, 6502);
2903
2904 /* Load clamped colors */
2905 for (unsigned i = 0; i < noutput; i++) {
2906 if (outputs[i].semantic_name != TGSI_SEMANTIC_COLOR &&
2907 outputs[i].semantic_name != TGSI_SEMANTIC_BCOLOR)
2908 continue;
2909
2910 for (unsigned j = 0; j < 4; j++) {
2911 outputs[i].values[j] =
2912 LLVMBuildLoad(ctx->ac.builder, addr[i][j], "");
2913 }
2914 }
2915 }
2916
2917 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2918 * (position and parameter data only).
2919 */
2920 void si_llvm_export_vs(struct si_shader_context *ctx,
2921 struct si_shader_output_values *outputs,
2922 unsigned noutput)
2923 {
2924 struct si_shader *shader = ctx->shader;
2925 struct ac_export_args pos_args[4] = {};
2926 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2927 unsigned pos_idx;
2928 int i;
2929
2930 si_vertex_color_clamping(ctx, outputs, noutput);
2931
2932 /* Build position exports. */
2933 for (i = 0; i < noutput; i++) {
2934 switch (outputs[i].semantic_name) {
2935 case TGSI_SEMANTIC_POSITION:
2936 si_llvm_init_export_args(ctx, outputs[i].values,
2937 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2938 break;
2939 case TGSI_SEMANTIC_PSIZE:
2940 psize_value = outputs[i].values[0];
2941 break;
2942 case TGSI_SEMANTIC_LAYER:
2943 layer_value = outputs[i].values[0];
2944 break;
2945 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2946 viewport_index_value = outputs[i].values[0];
2947 break;
2948 case TGSI_SEMANTIC_EDGEFLAG:
2949 edgeflag_value = outputs[i].values[0];
2950 break;
2951 case TGSI_SEMANTIC_CLIPDIST:
2952 if (!shader->key.opt.clip_disable) {
2953 unsigned index = 2 + outputs[i].semantic_index;
2954 si_llvm_init_export_args(ctx, outputs[i].values,
2955 V_008DFC_SQ_EXP_POS + index,
2956 &pos_args[index]);
2957 }
2958 break;
2959 case TGSI_SEMANTIC_CLIPVERTEX:
2960 if (!shader->key.opt.clip_disable) {
2961 si_llvm_emit_clipvertex(ctx, pos_args,
2962 outputs[i].values);
2963 }
2964 break;
2965 }
2966 }
2967
2968 /* We need to add the position output manually if it's missing. */
2969 if (!pos_args[0].out[0]) {
2970 pos_args[0].enabled_channels = 0xf; /* writemask */
2971 pos_args[0].valid_mask = 0; /* EXEC mask */
2972 pos_args[0].done = 0; /* last export? */
2973 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2974 pos_args[0].compr = 0; /* COMPR flag */
2975 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2976 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2977 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2978 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2979 }
2980
2981 bool pos_writes_edgeflag = shader->selector->info.writes_edgeflag &&
2982 !shader->key.as_ngg;
2983
2984 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2985 if (shader->selector->info.writes_psize ||
2986 pos_writes_edgeflag ||
2987 shader->selector->info.writes_viewport_index ||
2988 shader->selector->info.writes_layer) {
2989 pos_args[1].enabled_channels = shader->selector->info.writes_psize |
2990 (pos_writes_edgeflag << 1) |
2991 (shader->selector->info.writes_layer << 2);
2992
2993 pos_args[1].valid_mask = 0; /* EXEC mask */
2994 pos_args[1].done = 0; /* last export? */
2995 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2996 pos_args[1].compr = 0; /* COMPR flag */
2997 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2998 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2999 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
3000 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
3001
3002 if (shader->selector->info.writes_psize)
3003 pos_args[1].out[0] = psize_value;
3004
3005 if (pos_writes_edgeflag) {
3006 /* The output is a float, but the hw expects an integer
3007 * with the first bit containing the edge flag. */
3008 edgeflag_value = LLVMBuildFPToUI(ctx->ac.builder,
3009 edgeflag_value,
3010 ctx->i32, "");
3011 edgeflag_value = ac_build_umin(&ctx->ac,
3012 edgeflag_value,
3013 ctx->i32_1);
3014
3015 /* The LLVM intrinsic expects a float. */
3016 pos_args[1].out[1] = ac_to_float(&ctx->ac, edgeflag_value);
3017 }
3018
3019 if (ctx->screen->info.chip_class >= GFX9) {
3020 /* GFX9 has the layer in out.z[10:0] and the viewport
3021 * index in out.z[19:16].
3022 */
3023 if (shader->selector->info.writes_layer)
3024 pos_args[1].out[2] = layer_value;
3025
3026 if (shader->selector->info.writes_viewport_index) {
3027 LLVMValueRef v = viewport_index_value;
3028
3029 v = ac_to_integer(&ctx->ac, v);
3030 v = LLVMBuildShl(ctx->ac.builder, v,
3031 LLVMConstInt(ctx->i32, 16, 0), "");
3032 v = LLVMBuildOr(ctx->ac.builder, v,
3033 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
3034 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
3035 pos_args[1].enabled_channels |= 1 << 2;
3036 }
3037 } else {
3038 if (shader->selector->info.writes_layer)
3039 pos_args[1].out[2] = layer_value;
3040
3041 if (shader->selector->info.writes_viewport_index) {
3042 pos_args[1].out[3] = viewport_index_value;
3043 pos_args[1].enabled_channels |= 1 << 3;
3044 }
3045 }
3046 }
3047
3048 for (i = 0; i < 4; i++)
3049 if (pos_args[i].out[0])
3050 shader->info.nr_pos_exports++;
3051
3052 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
3053 * Setting valid_mask=1 prevents it and has no other effect.
3054 */
3055 if (ctx->screen->info.family == CHIP_NAVI10 ||
3056 ctx->screen->info.family == CHIP_NAVI12 ||
3057 ctx->screen->info.family == CHIP_NAVI14)
3058 pos_args[0].valid_mask = 1;
3059
3060 pos_idx = 0;
3061 for (i = 0; i < 4; i++) {
3062 if (!pos_args[i].out[0])
3063 continue;
3064
3065 /* Specify the target we are exporting */
3066 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
3067
3068 if (pos_idx == shader->info.nr_pos_exports)
3069 /* Specify that this is the last export */
3070 pos_args[i].done = 1;
3071
3072 ac_build_export(&ctx->ac, &pos_args[i]);
3073 }
3074
3075 /* Build parameter exports. */
3076 si_build_param_exports(ctx, outputs, noutput);
3077 }
3078
3079 /**
3080 * Forward all outputs from the vertex shader to the TES. This is only used
3081 * for the fixed function TCS.
3082 */
3083 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
3084 {
3085 struct si_shader_context *ctx = si_shader_context(bld_base);
3086 LLVMValueRef invocation_id, buffer, buffer_offset;
3087 LLVMValueRef lds_vertex_stride, lds_base;
3088 uint64_t inputs;
3089
3090 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3091 buffer = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3092 buffer_offset = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3093
3094 lds_vertex_stride = get_tcs_in_vertex_dw_stride(ctx);
3095 lds_base = get_tcs_in_current_patch_offset(ctx);
3096 lds_base = ac_build_imad(&ctx->ac, invocation_id, lds_vertex_stride,
3097 lds_base);
3098
3099 inputs = ctx->shader->key.mono.u.ff_tcs_inputs_to_copy;
3100 while (inputs) {
3101 unsigned i = u_bit_scan64(&inputs);
3102
3103 LLVMValueRef lds_ptr = LLVMBuildAdd(ctx->ac.builder, lds_base,
3104 LLVMConstInt(ctx->i32, 4 * i, 0),
3105 "");
3106
3107 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
3108 get_rel_patch_id(ctx),
3109 invocation_id,
3110 LLVMConstInt(ctx->i32, i, 0));
3111
3112 LLVMValueRef value = lshs_lds_load(bld_base, ctx->ac.i32, ~0, lds_ptr);
3113
3114 ac_build_buffer_store_dword(&ctx->ac, buffer, value, 4, buffer_addr,
3115 buffer_offset, 0, ac_glc, false);
3116 }
3117 }
3118
3119 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
3120 LLVMValueRef rel_patch_id,
3121 LLVMValueRef invocation_id,
3122 LLVMValueRef tcs_out_current_patch_data_offset,
3123 LLVMValueRef invoc0_tf_outer[4],
3124 LLVMValueRef invoc0_tf_inner[2])
3125 {
3126 struct si_shader_context *ctx = si_shader_context(bld_base);
3127 struct si_shader *shader = ctx->shader;
3128 unsigned tess_inner_index, tess_outer_index;
3129 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
3130 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3131 unsigned stride, outer_comps, inner_comps, i, offset;
3132
3133 /* Add a barrier before loading tess factors from LDS. */
3134 if (!shader->key.part.tcs.epilog.invoc0_tess_factors_are_def)
3135 si_llvm_emit_barrier(NULL, bld_base, NULL);
3136
3137 /* Do this only for invocation 0, because the tess levels are per-patch,
3138 * not per-vertex.
3139 *
3140 * This can't jump, because invocation 0 executes this. It should
3141 * at least mask out the loads and stores for other invocations.
3142 */
3143 ac_build_ifcc(&ctx->ac,
3144 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3145 invocation_id, ctx->i32_0, ""), 6503);
3146
3147 /* Determine the layout of one tess factor element in the buffer. */
3148 switch (shader->key.part.tcs.epilog.prim_mode) {
3149 case PIPE_PRIM_LINES:
3150 stride = 2; /* 2 dwords, 1 vec2 store */
3151 outer_comps = 2;
3152 inner_comps = 0;
3153 break;
3154 case PIPE_PRIM_TRIANGLES:
3155 stride = 4; /* 4 dwords, 1 vec4 store */
3156 outer_comps = 3;
3157 inner_comps = 1;
3158 break;
3159 case PIPE_PRIM_QUADS:
3160 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
3161 outer_comps = 4;
3162 inner_comps = 2;
3163 break;
3164 default:
3165 assert(0);
3166 return;
3167 }
3168
3169 for (i = 0; i < 4; i++) {
3170 inner[i] = LLVMGetUndef(ctx->i32);
3171 outer[i] = LLVMGetUndef(ctx->i32);
3172 }
3173
3174 if (shader->key.part.tcs.epilog.invoc0_tess_factors_are_def) {
3175 /* Tess factors are in VGPRs. */
3176 for (i = 0; i < outer_comps; i++)
3177 outer[i] = out[i] = invoc0_tf_outer[i];
3178 for (i = 0; i < inner_comps; i++)
3179 inner[i] = out[outer_comps+i] = invoc0_tf_inner[i];
3180 } else {
3181 /* Load tess_inner and tess_outer from LDS.
3182 * Any invocation can write them, so we can't get them from a temporary.
3183 */
3184 tess_inner_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0);
3185 tess_outer_index = si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0);
3186
3187 lds_base = tcs_out_current_patch_data_offset;
3188 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3189 LLVMConstInt(ctx->i32,
3190 tess_inner_index * 4, 0), "");
3191 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3192 LLVMConstInt(ctx->i32,
3193 tess_outer_index * 4, 0), "");
3194
3195 for (i = 0; i < outer_comps; i++) {
3196 outer[i] = out[i] =
3197 lshs_lds_load(bld_base, ctx->ac.i32, i, lds_outer);
3198 }
3199 for (i = 0; i < inner_comps; i++) {
3200 inner[i] = out[outer_comps+i] =
3201 lshs_lds_load(bld_base, ctx->ac.i32, i, lds_inner);
3202 }
3203 }
3204
3205 if (shader->key.part.tcs.epilog.prim_mode == PIPE_PRIM_LINES) {
3206 /* For isolines, the hardware expects tess factors in the
3207 * reverse order from what GLSL / TGSI specify.
3208 */
3209 LLVMValueRef tmp = out[0];
3210 out[0] = out[1];
3211 out[1] = tmp;
3212 }
3213
3214 /* Convert the outputs to vectors for stores. */
3215 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3216 vec1 = NULL;
3217
3218 if (stride > 4)
3219 vec1 = ac_build_gather_values(&ctx->ac, out+4, stride - 4);
3220
3221 /* Get the buffer. */
3222 buffer = get_tess_ring_descriptor(ctx, TCS_FACTOR_RING);
3223
3224 /* Get the offset. */
3225 tf_base = LLVMGetParam(ctx->main_fn,
3226 ctx->param_tcs_factor_offset);
3227 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3228 LLVMConstInt(ctx->i32, 4 * stride, 0), "");
3229
3230 ac_build_ifcc(&ctx->ac,
3231 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3232 rel_patch_id, ctx->i32_0, ""), 6504);
3233
3234 /* Store the dynamic HS control word. */
3235 offset = 0;
3236 if (ctx->screen->info.chip_class <= GFX8) {
3237 ac_build_buffer_store_dword(&ctx->ac, buffer,
3238 LLVMConstInt(ctx->i32, 0x80000000, 0),
3239 1, ctx->i32_0, tf_base,
3240 offset, ac_glc, false);
3241 offset += 4;
3242 }
3243
3244 ac_build_endif(&ctx->ac, 6504);
3245
3246 /* Store the tessellation factors. */
3247 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3248 MIN2(stride, 4), byteoffset, tf_base,
3249 offset, ac_glc, false);
3250 offset += 16;
3251 if (vec1)
3252 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3253 stride - 4, byteoffset, tf_base,
3254 offset, ac_glc, false);
3255
3256 /* Store the tess factors into the offchip buffer if TES reads them. */
3257 if (shader->key.part.tcs.epilog.tes_reads_tess_factors) {
3258 LLVMValueRef buf, base, inner_vec, outer_vec, tf_outer_offset;
3259 LLVMValueRef tf_inner_offset;
3260 unsigned param_outer, param_inner;
3261
3262 buf = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TCS);
3263 base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
3264
3265 param_outer = si_shader_io_get_unique_index_patch(
3266 TGSI_SEMANTIC_TESSOUTER, 0);
3267 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3268 LLVMConstInt(ctx->i32, param_outer, 0));
3269
3270 unsigned outer_vec_size =
3271 ac_has_vec3_support(ctx->screen->info.chip_class, false) ?
3272 outer_comps : util_next_power_of_two(outer_comps);
3273 outer_vec = ac_build_gather_values(&ctx->ac, outer, outer_vec_size);
3274
3275 ac_build_buffer_store_dword(&ctx->ac, buf, outer_vec,
3276 outer_comps, tf_outer_offset,
3277 base, 0, ac_glc, false);
3278 if (inner_comps) {
3279 param_inner = si_shader_io_get_unique_index_patch(
3280 TGSI_SEMANTIC_TESSINNER, 0);
3281 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL,
3282 LLVMConstInt(ctx->i32, param_inner, 0));
3283
3284 inner_vec = inner_comps == 1 ? inner[0] :
3285 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3286 ac_build_buffer_store_dword(&ctx->ac, buf, inner_vec,
3287 inner_comps, tf_inner_offset,
3288 base, 0, ac_glc, false);
3289 }
3290 }
3291
3292 ac_build_endif(&ctx->ac, 6503);
3293 }
3294
3295 static LLVMValueRef
3296 si_insert_input_ret(struct si_shader_context *ctx, LLVMValueRef ret,
3297 unsigned param, unsigned return_index)
3298 {
3299 return LLVMBuildInsertValue(ctx->ac.builder, ret,
3300 LLVMGetParam(ctx->main_fn, param),
3301 return_index, "");
3302 }
3303
3304 static LLVMValueRef
3305 si_insert_input_ret_float(struct si_shader_context *ctx, LLVMValueRef ret,
3306 unsigned param, unsigned return_index)
3307 {
3308 LLVMBuilderRef builder = ctx->ac.builder;
3309 LLVMValueRef p = LLVMGetParam(ctx->main_fn, param);
3310
3311 return LLVMBuildInsertValue(builder, ret,
3312 ac_to_float(&ctx->ac, p),
3313 return_index, "");
3314 }
3315
3316 static LLVMValueRef
3317 si_insert_input_ptr(struct si_shader_context *ctx, LLVMValueRef ret,
3318 unsigned param, unsigned return_index)
3319 {
3320 LLVMBuilderRef builder = ctx->ac.builder;
3321 LLVMValueRef ptr = LLVMGetParam(ctx->main_fn, param);
3322 ptr = LLVMBuildPtrToInt(builder, ptr, ctx->i32, "");
3323 return LLVMBuildInsertValue(builder, ret, ptr, return_index, "");
3324 }
3325
3326 /* This only writes the tessellation factor levels. */
3327 static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
3328 unsigned max_outputs,
3329 LLVMValueRef *addrs)
3330 {
3331 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3332 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
3333 LLVMBuilderRef builder = ctx->ac.builder;
3334 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
3335
3336 si_copy_tcs_inputs(bld_base);
3337
3338 rel_patch_id = get_rel_patch_id(ctx);
3339 invocation_id = unpack_llvm_param(ctx, ctx->abi.tcs_rel_ids, 8, 5);
3340 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
3341
3342 if (ctx->screen->info.chip_class >= GFX9) {
3343 LLVMBasicBlockRef blocks[2] = {
3344 LLVMGetInsertBlock(builder),
3345 ctx->merged_wrap_if_entry_block
3346 };
3347 LLVMValueRef values[2];
3348
3349 ac_build_endif(&ctx->ac, ctx->merged_wrap_if_label);
3350
3351 values[0] = rel_patch_id;
3352 values[1] = LLVMGetUndef(ctx->i32);
3353 rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3354
3355 values[0] = tf_lds_offset;
3356 values[1] = LLVMGetUndef(ctx->i32);
3357 tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3358
3359 values[0] = invocation_id;
3360 values[1] = ctx->i32_1; /* cause the epilog to skip threads */
3361 invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
3362 }
3363
3364 /* Return epilog parameters from this function. */
3365 LLVMValueRef ret = ctx->return_value;
3366 unsigned vgpr;
3367
3368 if (ctx->screen->info.chip_class >= GFX9) {
3369 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3370 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3371 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3372 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3373 /* Tess offchip and tess factor offsets are at the beginning. */
3374 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3375 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3376 vgpr = 8 + GFX9_SGPR_TCS_OUT_LAYOUT + 1;
3377 } else {
3378 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3379 GFX6_SGPR_TCS_OFFCHIP_LAYOUT);
3380 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3381 GFX6_SGPR_TCS_OUT_LAYOUT);
3382 /* Tess offchip and tess factor offsets are after user SGPRs. */
3383 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset,
3384 GFX6_TCS_NUM_USER_SGPR);
3385 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset,
3386 GFX6_TCS_NUM_USER_SGPR + 1);
3387 vgpr = GFX6_TCS_NUM_USER_SGPR + 2;
3388 }
3389
3390 /* VGPRs */
3391 rel_patch_id = ac_to_float(&ctx->ac, rel_patch_id);
3392 invocation_id = ac_to_float(&ctx->ac, invocation_id);
3393 tf_lds_offset = ac_to_float(&ctx->ac, tf_lds_offset);
3394
3395 /* Leave a hole corresponding to the two input VGPRs. This ensures that
3396 * the invocation_id output does not alias the tcs_rel_ids input,
3397 * which saves a V_MOV on gfx9.
3398 */
3399 vgpr += 2;
3400
3401 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
3402 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
3403
3404 if (ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs) {
3405 vgpr++; /* skip the tess factor LDS offset */
3406 for (unsigned i = 0; i < 6; i++) {
3407 LLVMValueRef value =
3408 LLVMBuildLoad(builder, ctx->invoc0_tess_factors[i], "");
3409 value = ac_to_float(&ctx->ac, value);
3410 ret = LLVMBuildInsertValue(builder, ret, value, vgpr++, "");
3411 }
3412 } else {
3413 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
3414 }
3415 ctx->return_value = ret;
3416 }
3417
3418 /* Pass TCS inputs from LS to TCS on GFX9. */
3419 static void si_set_ls_return_value_for_tcs(struct si_shader_context *ctx)
3420 {
3421 LLVMValueRef ret = ctx->return_value;
3422
3423 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3424 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3425 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_offset, 2);
3426 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3427 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_factor_offset, 4);
3428 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3429
3430 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3431 8 + SI_SGPR_RW_BUFFERS);
3432 ret = si_insert_input_ptr(ctx, ret,
3433 ctx->param_bindless_samplers_and_images,
3434 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3435
3436 ret = si_insert_input_ret(ctx, ret, ctx->param_vs_state_bits,
3437 8 + SI_SGPR_VS_STATE_BITS);
3438
3439 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_offchip_layout,
3440 8 + GFX9_SGPR_TCS_OFFCHIP_LAYOUT);
3441 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_offsets,
3442 8 + GFX9_SGPR_TCS_OUT_OFFSETS);
3443 ret = si_insert_input_ret(ctx, ret, ctx->param_tcs_out_lds_layout,
3444 8 + GFX9_SGPR_TCS_OUT_LAYOUT);
3445
3446 unsigned vgpr = 8 + GFX9_TCS_NUM_USER_SGPR;
3447 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3448 ac_to_float(&ctx->ac, ctx->abi.tcs_patch_id),
3449 vgpr++, "");
3450 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
3451 ac_to_float(&ctx->ac, ctx->abi.tcs_rel_ids),
3452 vgpr++, "");
3453 ctx->return_value = ret;
3454 }
3455
3456 /* Pass GS inputs from ES to GS on GFX9. */
3457 static void si_set_es_return_value_for_gs(struct si_shader_context *ctx)
3458 {
3459 LLVMBuilderRef builder = ctx->ac.builder;
3460 LLVMValueRef ret = ctx->return_value;
3461
3462 ret = si_insert_input_ptr(ctx, ret, 0, 0);
3463 ret = si_insert_input_ptr(ctx, ret, 1, 1);
3464 if (ctx->shader->key.as_ngg)
3465 ret = LLVMBuildInsertValue(builder, ret, ctx->gs_tg_info, 2, "");
3466 else
3467 ret = si_insert_input_ret(ctx, ret, ctx->param_gs2vs_offset, 2);
3468 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_wave_info, 3);
3469 ret = si_insert_input_ret(ctx, ret, ctx->param_merged_scratch_offset, 5);
3470
3471 ret = si_insert_input_ptr(ctx, ret, ctx->param_rw_buffers,
3472 8 + SI_SGPR_RW_BUFFERS);
3473 ret = si_insert_input_ptr(ctx, ret,
3474 ctx->param_bindless_samplers_and_images,
3475 8 + SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES);
3476 if (ctx->screen->use_ngg) {
3477 ret = si_insert_input_ptr(ctx, ret, ctx->param_vs_state_bits,
3478 8 + SI_SGPR_VS_STATE_BITS);
3479 }
3480
3481 unsigned vgpr;
3482 if (ctx->type == PIPE_SHADER_VERTEX)
3483 vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
3484 else
3485 vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
3486
3487 for (unsigned i = 0; i < 5; i++) {
3488 unsigned param = ctx->param_gs_vtx01_offset + i;
3489 ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
3490 }
3491 ctx->return_value = ret;
3492 }
3493
3494 static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
3495 unsigned max_outputs,
3496 LLVMValueRef *addrs)
3497 {
3498 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3499 struct si_shader *shader = ctx->shader;
3500 struct tgsi_shader_info *info = &shader->selector->info;
3501 unsigned i, chan;
3502 LLVMValueRef vertex_id = LLVMGetParam(ctx->main_fn,
3503 ctx->param_rel_auto_id);
3504 LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
3505 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
3506 vertex_dw_stride, "");
3507
3508 /* Write outputs to LDS. The next shader (TCS aka HS) will read
3509 * its inputs from it. */
3510 for (i = 0; i < info->num_outputs; i++) {
3511 unsigned name = info->output_semantic_name[i];
3512 unsigned index = info->output_semantic_index[i];
3513
3514 /* The ARB_shader_viewport_layer_array spec contains the
3515 * following issue:
3516 *
3517 * 2) What happens if gl_ViewportIndex or gl_Layer is
3518 * written in the vertex shader and a geometry shader is
3519 * present?
3520 *
3521 * RESOLVED: The value written by the last vertex processing
3522 * stage is used. If the last vertex processing stage
3523 * (vertex, tessellation evaluation or geometry) does not
3524 * statically assign to gl_ViewportIndex or gl_Layer, index
3525 * or layer zero is assumed.
3526 *
3527 * So writes to those outputs in VS-as-LS are simply ignored.
3528 */
3529 if (name == TGSI_SEMANTIC_LAYER ||
3530 name == TGSI_SEMANTIC_VIEWPORT_INDEX)
3531 continue;
3532
3533 int param = si_shader_io_get_unique_index(name, index, false);
3534 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
3535 LLVMConstInt(ctx->i32, param * 4, 0), "");
3536
3537 for (chan = 0; chan < 4; chan++) {
3538 if (!(info->output_usagemask[i] & (1 << chan)))
3539 continue;
3540
3541 lshs_lds_store(ctx, chan, dw_addr,
3542 LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], ""));
3543 }
3544 }
3545
3546 if (ctx->screen->info.chip_class >= GFX9)
3547 si_set_ls_return_value_for_tcs(ctx);
3548 }
3549
3550 static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
3551 unsigned max_outputs,
3552 LLVMValueRef *addrs)
3553 {
3554 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3555 struct si_shader *es = ctx->shader;
3556 struct tgsi_shader_info *info = &es->selector->info;
3557 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
3558 ctx->param_es2gs_offset);
3559 LLVMValueRef lds_base = NULL;
3560 unsigned chan;
3561 int i;
3562
3563 if (ctx->screen->info.chip_class >= GFX9 && info->num_outputs) {
3564 unsigned itemsize_dw = es->selector->esgs_itemsize / 4;
3565 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
3566 LLVMValueRef wave_idx = si_unpack_param(ctx, ctx->param_merged_wave_info, 24, 4);
3567 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
3568 LLVMBuildMul(ctx->ac.builder, wave_idx,
3569 LLVMConstInt(ctx->i32, ctx->ac.wave_size, false), ""), "");
3570 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
3571 LLVMConstInt(ctx->i32, itemsize_dw, 0), "");
3572 }
3573
3574 for (i = 0; i < info->num_outputs; i++) {
3575 int param;
3576
3577 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
3578 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
3579 continue;
3580
3581 param = si_shader_io_get_unique_index(info->output_semantic_name[i],
3582 info->output_semantic_index[i], false);
3583
3584 for (chan = 0; chan < 4; chan++) {
3585 if (!(info->output_usagemask[i] & (1 << chan)))
3586 continue;
3587
3588 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3589 out_val = ac_to_integer(&ctx->ac, out_val);
3590
3591 /* GFX9 has the ESGS ring in LDS. */
3592 if (ctx->screen->info.chip_class >= GFX9) {
3593 LLVMValueRef idx = LLVMConstInt(ctx->i32, param * 4 + chan, false);
3594 idx = LLVMBuildAdd(ctx->ac.builder, lds_base, idx, "");
3595 ac_build_indexed_store(&ctx->ac, ctx->esgs_ring, idx, out_val);
3596 continue;
3597 }
3598
3599 ac_build_buffer_store_dword(&ctx->ac,
3600 ctx->esgs_ring,
3601 out_val, 1, NULL, soffset,
3602 (4 * param + chan) * 4,
3603 ac_glc | ac_slc, true);
3604 }
3605 }
3606
3607 if (ctx->screen->info.chip_class >= GFX9)
3608 si_set_es_return_value_for_gs(ctx);
3609 }
3610
3611 static LLVMValueRef si_get_gs_wave_id(struct si_shader_context *ctx)
3612 {
3613 if (ctx->screen->info.chip_class >= GFX9)
3614 return si_unpack_param(ctx, ctx->param_merged_wave_info, 16, 8);
3615 else
3616 return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
3617 }
3618
3619 static void emit_gs_epilogue(struct si_shader_context *ctx)
3620 {
3621 if (ctx->shader->key.as_ngg) {
3622 gfx10_ngg_gs_emit_epilogue(ctx);
3623 return;
3624 }
3625
3626 if (ctx->screen->info.chip_class >= GFX10)
3627 LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
3628
3629 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
3630 si_get_gs_wave_id(ctx));
3631
3632 if (ctx->screen->info.chip_class >= GFX9)
3633 ac_build_endif(&ctx->ac, ctx->merged_wrap_if_label);
3634 }
3635
3636 static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
3637 unsigned max_outputs,
3638 LLVMValueRef *addrs)
3639 {
3640 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3641 struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
3642
3643 assert(info->num_outputs <= max_outputs);
3644
3645 emit_gs_epilogue(ctx);
3646 }
3647
3648 static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
3649 {
3650 struct si_shader_context *ctx = si_shader_context(bld_base);
3651 emit_gs_epilogue(ctx);
3652 }
3653
3654 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
3655 unsigned max_outputs,
3656 LLVMValueRef *addrs)
3657 {
3658 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3659 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3660 struct si_shader_output_values *outputs = NULL;
3661 int i,j;
3662
3663 assert(!ctx->shader->is_gs_copy_shader);
3664 assert(info->num_outputs <= max_outputs);
3665
3666 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
3667
3668 for (i = 0; i < info->num_outputs; i++) {
3669 outputs[i].semantic_name = info->output_semantic_name[i];
3670 outputs[i].semantic_index = info->output_semantic_index[i];
3671
3672 for (j = 0; j < 4; j++) {
3673 outputs[i].values[j] =
3674 LLVMBuildLoad(ctx->ac.builder,
3675 addrs[4 * i + j],
3676 "");
3677 outputs[i].vertex_stream[j] =
3678 (info->output_streams[i] >> (2 * j)) & 3;
3679 }
3680 }
3681
3682 if (!ctx->screen->use_ngg_streamout &&
3683 ctx->shader->selector->so.num_outputs)
3684 si_llvm_emit_streamout(ctx, outputs, i, 0);
3685
3686 /* Export PrimitiveID. */
3687 if (ctx->shader->key.mono.u.vs_export_prim_id) {
3688 outputs[i].semantic_name = TGSI_SEMANTIC_PRIMID;
3689 outputs[i].semantic_index = 0;
3690 outputs[i].values[0] = ac_to_float(&ctx->ac, si_get_primitive_id(ctx, 0));
3691 for (j = 1; j < 4; j++)
3692 outputs[i].values[j] = LLVMConstReal(ctx->f32, 0);
3693
3694 memset(outputs[i].vertex_stream, 0,
3695 sizeof(outputs[i].vertex_stream));
3696 i++;
3697 }
3698
3699 si_llvm_export_vs(ctx, outputs, i);
3700 FREE(outputs);
3701 }
3702
3703 static void si_llvm_emit_prim_discard_cs_epilogue(struct ac_shader_abi *abi,
3704 unsigned max_outputs,
3705 LLVMValueRef *addrs)
3706 {
3707 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3708 struct tgsi_shader_info *info = &ctx->shader->selector->info;
3709 LLVMValueRef pos[4] = {};
3710
3711 assert(info->num_outputs <= max_outputs);
3712
3713 for (unsigned i = 0; i < info->num_outputs; i++) {
3714 if (info->output_semantic_name[i] != TGSI_SEMANTIC_POSITION)
3715 continue;
3716
3717 for (unsigned chan = 0; chan < 4; chan++)
3718 pos[chan] = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
3719 break;
3720 }
3721 assert(pos[0] != NULL);
3722
3723 /* Return the position output. */
3724 LLVMValueRef ret = ctx->return_value;
3725 for (unsigned chan = 0; chan < 4; chan++)
3726 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, pos[chan], chan, "");
3727 ctx->return_value = ret;
3728 }
3729
3730 static void si_tgsi_emit_epilogue(struct lp_build_tgsi_context *bld_base)
3731 {
3732 struct si_shader_context *ctx = si_shader_context(bld_base);
3733
3734 ctx->abi.emit_outputs(&ctx->abi, RADEON_LLVM_MAX_OUTPUTS,
3735 &ctx->outputs[0][0]);
3736 }
3737
3738 struct si_ps_exports {
3739 unsigned num;
3740 struct ac_export_args args[10];
3741 };
3742
3743 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
3744 LLVMValueRef depth, LLVMValueRef stencil,
3745 LLVMValueRef samplemask, struct si_ps_exports *exp)
3746 {
3747 struct si_shader_context *ctx = si_shader_context(bld_base);
3748 struct ac_export_args args;
3749
3750 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3751
3752 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3753 }
3754
3755 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3756 LLVMValueRef *color, unsigned index,
3757 unsigned samplemask_param,
3758 bool is_last, struct si_ps_exports *exp)
3759 {
3760 struct si_shader_context *ctx = si_shader_context(bld_base);
3761 int i;
3762
3763 /* Clamp color */
3764 if (ctx->shader->key.part.ps.epilog.clamp_color)
3765 for (i = 0; i < 4; i++)
3766 color[i] = ac_build_clamp(&ctx->ac, color[i]);
3767
3768 /* Alpha to one */
3769 if (ctx->shader->key.part.ps.epilog.alpha_to_one)
3770 color[3] = ctx->ac.f32_1;
3771
3772 /* Alpha test */
3773 if (index == 0 &&
3774 ctx->shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3775 si_alpha_test(bld_base, color[3]);
3776
3777 /* Line & polygon smoothing */
3778 if (ctx->shader->key.part.ps.epilog.poly_line_smoothing)
3779 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3780 samplemask_param);
3781
3782 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3783 if (ctx->shader->key.part.ps.epilog.last_cbuf > 0) {
3784 struct ac_export_args args[8];
3785 int c, last = -1;
3786
3787 /* Get the export arguments, also find out what the last one is. */
3788 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3789 si_llvm_init_export_args(ctx, color,
3790 V_008DFC_SQ_EXP_MRT + c, &args[c]);
3791 if (args[c].enabled_channels)
3792 last = c;
3793 }
3794
3795 /* Emit all exports. */
3796 for (c = 0; c <= ctx->shader->key.part.ps.epilog.last_cbuf; c++) {
3797 if (is_last && last == c) {
3798 args[c].valid_mask = 1; /* whether the EXEC mask is valid */
3799 args[c].done = 1; /* DONE bit */
3800 } else if (!args[c].enabled_channels)
3801 continue; /* unnecessary NULL export */
3802
3803 memcpy(&exp->args[exp->num++], &args[c], sizeof(args[c]));
3804 }
3805 } else {
3806 struct ac_export_args args;
3807
3808 /* Export */
3809 si_llvm_init_export_args(ctx, color, V_008DFC_SQ_EXP_MRT + index,
3810 &args);
3811 if (is_last) {
3812 args.valid_mask = 1; /* whether the EXEC mask is valid */
3813 args.done = 1; /* DONE bit */
3814 } else if (!args.enabled_channels)
3815 return; /* unnecessary NULL export */
3816
3817 memcpy(&exp->args[exp->num++], &args, sizeof(args));
3818 }
3819 }
3820
3821 static void si_emit_ps_exports(struct si_shader_context *ctx,
3822 struct si_ps_exports *exp)
3823 {
3824 for (unsigned i = 0; i < exp->num; i++)
3825 ac_build_export(&ctx->ac, &exp->args[i]);
3826 }
3827
3828 /**
3829 * Return PS outputs in this order:
3830 *
3831 * v[0:3] = color0.xyzw
3832 * v[4:7] = color1.xyzw
3833 * ...
3834 * vN+0 = Depth
3835 * vN+1 = Stencil
3836 * vN+2 = SampleMask
3837 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3838 *
3839 * The alpha-ref SGPR is returned via its original location.
3840 */
3841 static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
3842 unsigned max_outputs,
3843 LLVMValueRef *addrs)
3844 {
3845 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
3846 struct si_shader *shader = ctx->shader;
3847 struct tgsi_shader_info *info = &shader->selector->info;
3848 LLVMBuilderRef builder = ctx->ac.builder;
3849 unsigned i, j, first_vgpr, vgpr;
3850
3851 LLVMValueRef color[8][4] = {};
3852 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3853 LLVMValueRef ret;
3854
3855 if (ctx->postponed_kill)
3856 ac_build_kill_if_false(&ctx->ac, LLVMBuildLoad(builder, ctx->postponed_kill, ""));
3857
3858 /* Read the output values. */
3859 for (i = 0; i < info->num_outputs; i++) {
3860 unsigned semantic_name = info->output_semantic_name[i];
3861 unsigned semantic_index = info->output_semantic_index[i];
3862
3863 switch (semantic_name) {
3864 case TGSI_SEMANTIC_COLOR:
3865 assert(semantic_index < 8);
3866 for (j = 0; j < 4; j++) {
3867 LLVMValueRef ptr = addrs[4 * i + j];
3868 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3869 color[semantic_index][j] = result;
3870 }
3871 break;
3872 case TGSI_SEMANTIC_POSITION:
3873 depth = LLVMBuildLoad(builder,
3874 addrs[4 * i + 2], "");
3875 break;
3876 case TGSI_SEMANTIC_STENCIL:
3877 stencil = LLVMBuildLoad(builder,
3878 addrs[4 * i + 1], "");
3879 break;
3880 case TGSI_SEMANTIC_SAMPLEMASK:
3881 samplemask = LLVMBuildLoad(builder,
3882 addrs[4 * i + 0], "");
3883 break;
3884 default:
3885 fprintf(stderr, "Warning: GFX6 unhandled fs output type:%d\n",
3886 semantic_name);
3887 }
3888 }
3889
3890 /* Fill the return structure. */
3891 ret = ctx->return_value;
3892
3893 /* Set SGPRs. */
3894 ret = LLVMBuildInsertValue(builder, ret,
3895 ac_to_integer(&ctx->ac,
3896 LLVMGetParam(ctx->main_fn,
3897 SI_PARAM_ALPHA_REF)),
3898 SI_SGPR_ALPHA_REF, "");
3899
3900 /* Set VGPRs */
3901 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3902 for (i = 0; i < ARRAY_SIZE(color); i++) {
3903 if (!color[i][0])
3904 continue;
3905
3906 for (j = 0; j < 4; j++)
3907 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3908 }
3909 if (depth)
3910 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3911 if (stencil)
3912 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3913 if (samplemask)
3914 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3915
3916 /* Add the input sample mask for smoothing at the end. */
3917 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3918 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3919 ret = LLVMBuildInsertValue(builder, ret,
3920 LLVMGetParam(ctx->main_fn,
3921 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3922
3923 ctx->return_value = ret;
3924 }
3925
3926 static void membar_emit(
3927 const struct lp_build_tgsi_action *action,
3928 struct lp_build_tgsi_context *bld_base,
3929 struct lp_build_emit_data *emit_data)
3930 {
3931 struct si_shader_context *ctx = si_shader_context(bld_base);
3932 LLVMValueRef src0 = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
3933 unsigned flags = LLVMConstIntGetZExtValue(src0);
3934 unsigned wait_flags = 0;
3935
3936 if (flags & TGSI_MEMBAR_THREAD_GROUP)
3937 wait_flags |= AC_WAIT_LGKM | AC_WAIT_VLOAD | AC_WAIT_VSTORE;
3938
3939 if (flags & (TGSI_MEMBAR_ATOMIC_BUFFER |
3940 TGSI_MEMBAR_SHADER_BUFFER |
3941 TGSI_MEMBAR_SHADER_IMAGE))
3942 wait_flags |= AC_WAIT_VLOAD | AC_WAIT_VSTORE;
3943
3944 if (flags & TGSI_MEMBAR_SHARED)
3945 wait_flags |= AC_WAIT_LGKM;
3946
3947 ac_build_waitcnt(&ctx->ac, wait_flags);
3948 }
3949
3950 static void clock_emit(
3951 const struct lp_build_tgsi_action *action,
3952 struct lp_build_tgsi_context *bld_base,
3953 struct lp_build_emit_data *emit_data)
3954 {
3955 struct si_shader_context *ctx = si_shader_context(bld_base);
3956 LLVMValueRef tmp = ac_build_shader_clock(&ctx->ac);
3957
3958 emit_data->output[0] =
3959 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_0, "");
3960 emit_data->output[1] =
3961 LLVMBuildExtractElement(ctx->ac.builder, tmp, ctx->i32_1, "");
3962 }
3963
3964 static void si_llvm_emit_ddxy(
3965 const struct lp_build_tgsi_action *action,
3966 struct lp_build_tgsi_context *bld_base,
3967 struct lp_build_emit_data *emit_data)
3968 {
3969 struct si_shader_context *ctx = si_shader_context(bld_base);
3970 unsigned opcode = emit_data->info->opcode;
3971 LLVMValueRef val;
3972 int idx;
3973 unsigned mask;
3974
3975 if (opcode == TGSI_OPCODE_DDX_FINE)
3976 mask = AC_TID_MASK_LEFT;
3977 else if (opcode == TGSI_OPCODE_DDY_FINE)
3978 mask = AC_TID_MASK_TOP;
3979 else
3980 mask = AC_TID_MASK_TOP_LEFT;
3981
3982 /* for DDX we want to next X pixel, DDY next Y pixel. */
3983 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3984
3985 val = ac_to_integer(&ctx->ac, emit_data->args[0]);
3986 val = ac_build_ddxy(&ctx->ac, mask, idx, val);
3987 emit_data->output[emit_data->chan] = val;
3988 }
3989
3990 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3991 struct lp_build_tgsi_context *bld_base,
3992 struct lp_build_emit_data *emit_data)
3993 {
3994 struct si_shader_context *ctx = si_shader_context(bld_base);
3995 struct si_shader *shader = ctx->shader;
3996 const struct tgsi_shader_info *info = &shader->selector->info;
3997 LLVMValueRef interp_param;
3998 const struct tgsi_full_instruction *inst = emit_data->inst;
3999 const struct tgsi_full_src_register *input = &inst->Src[0];
4000 int input_base, input_array_size;
4001 int chan;
4002 int i;
4003 LLVMValueRef prim_mask = ctx->abi.prim_mask;
4004 LLVMValueRef array_idx, offset_x = NULL, offset_y = NULL;
4005 int interp_param_idx;
4006 unsigned interp;
4007 unsigned location;
4008
4009 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
4010 /* offset is in second src, first two channels */
4011 offset_x = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
4012 TGSI_CHAN_X);
4013 offset_y = lp_build_emit_fetch(bld_base, emit_data->inst, 1,
4014 TGSI_CHAN_Y);
4015 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4016 LLVMValueRef sample_position;
4017 LLVMValueRef sample_id;
4018 LLVMValueRef halfval = LLVMConstReal(ctx->f32, 0.5f);
4019
4020 /* fetch sample ID, then fetch its sample position,
4021 * and place into first two channels.
4022 */
4023 sample_id = lp_build_emit_fetch(bld_base,
4024 emit_data->inst, 1, TGSI_CHAN_X);
4025 sample_id = ac_to_integer(&ctx->ac, sample_id);
4026
4027 /* Section 8.13.2 (Interpolation Functions) of the OpenGL Shading
4028 * Language 4.50 spec says about interpolateAtSample:
4029 *
4030 * "Returns the value of the input interpolant variable at
4031 * the location of sample number sample. If multisample
4032 * buffers are not available, the input variable will be
4033 * evaluated at the center of the pixel. If sample sample
4034 * does not exist, the position used to interpolate the
4035 * input variable is undefined."
4036 *
4037 * This means that sample_id values outside of the valid are
4038 * in fact valid input, and the usual mechanism for loading the
4039 * sample position doesn't work.
4040 */
4041 if (ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center) {
4042 LLVMValueRef center[4] = {
4043 LLVMConstReal(ctx->f32, 0.5),
4044 LLVMConstReal(ctx->f32, 0.5),
4045 ctx->ac.f32_0,
4046 ctx->ac.f32_0,
4047 };
4048
4049 sample_position = ac_build_gather_values(&ctx->ac, center, 4);
4050 } else {
4051 sample_position = load_sample_position(&ctx->abi, sample_id);
4052 }
4053
4054 offset_x = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
4055 ctx->i32_0, "");
4056
4057 offset_x = LLVMBuildFSub(ctx->ac.builder, offset_x, halfval, "");
4058 offset_y = LLVMBuildExtractElement(ctx->ac.builder, sample_position,
4059 ctx->i32_1, "");
4060 offset_y = LLVMBuildFSub(ctx->ac.builder, offset_y, halfval, "");
4061 }
4062
4063 assert(input->Register.File == TGSI_FILE_INPUT);
4064
4065 if (input->Register.Indirect) {
4066 unsigned array_id = input->Indirect.ArrayID;
4067
4068 if (array_id) {
4069 input_base = info->input_array_first[array_id];
4070 input_array_size = info->input_array_last[array_id] - input_base + 1;
4071 } else {
4072 input_base = inst->Src[0].Register.Index;
4073 input_array_size = info->num_inputs - input_base;
4074 }
4075
4076 array_idx = si_get_indirect_index(ctx, &input->Indirect,
4077 1, input->Register.Index - input_base);
4078 } else {
4079 input_base = inst->Src[0].Register.Index;
4080 input_array_size = 1;
4081 array_idx = ctx->i32_0;
4082 }
4083
4084 interp = shader->selector->info.input_interpolate[input_base];
4085
4086 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4087 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
4088 location = TGSI_INTERPOLATE_LOC_CENTER;
4089 else
4090 location = TGSI_INTERPOLATE_LOC_CENTROID;
4091
4092 interp_param_idx = lookup_interp_param_index(interp, location);
4093 if (interp_param_idx == -1)
4094 return;
4095 else if (interp_param_idx)
4096 interp_param = LLVMGetParam(ctx->main_fn, interp_param_idx);
4097 else
4098 interp_param = NULL;
4099
4100 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
4101 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
4102 LLVMValueRef ij_out[2];
4103 LLVMValueRef ddxy_out = ac_build_ddxy_interp(&ctx->ac, interp_param);
4104
4105 /*
4106 * take the I then J parameters, and the DDX/Y for it, and
4107 * calculate the IJ inputs for the interpolator.
4108 * temp1 = ddx * offset/sample.x + I;
4109 * interp_param.I = ddy * offset/sample.y + temp1;
4110 * temp1 = ddx * offset/sample.x + J;
4111 * interp_param.J = ddy * offset/sample.y + temp1;
4112 */
4113 for (i = 0; i < 2; i++) {
4114 LLVMValueRef ix_ll = LLVMConstInt(ctx->i32, i, 0);
4115 LLVMValueRef iy_ll = LLVMConstInt(ctx->i32, i + 2, 0);
4116 LLVMValueRef ddx_el = LLVMBuildExtractElement(ctx->ac.builder,
4117 ddxy_out, ix_ll, "");
4118 LLVMValueRef ddy_el = LLVMBuildExtractElement(ctx->ac.builder,
4119 ddxy_out, iy_ll, "");
4120 LLVMValueRef interp_el = LLVMBuildExtractElement(ctx->ac.builder,
4121 interp_param, ix_ll, "");
4122 LLVMValueRef temp;
4123
4124 interp_el = ac_to_float(&ctx->ac, interp_el);
4125
4126 temp = ac_build_fmad(&ctx->ac, ddx_el, offset_x, interp_el);
4127 ij_out[i] = ac_build_fmad(&ctx->ac, ddy_el, offset_y, temp);
4128 }
4129 interp_param = ac_build_gather_values(&ctx->ac, ij_out, 2);
4130 }
4131
4132 if (interp_param)
4133 interp_param = ac_to_float(&ctx->ac, interp_param);
4134
4135 for (chan = 0; chan < 4; chan++) {
4136 LLVMValueRef gather = LLVMGetUndef(LLVMVectorType(ctx->f32, input_array_size));
4137 unsigned schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
4138
4139 for (unsigned idx = 0; idx < input_array_size; ++idx) {
4140 LLVMValueRef v, i = NULL, j = NULL;
4141
4142 if (interp_param) {
4143 i = LLVMBuildExtractElement(
4144 ctx->ac.builder, interp_param, ctx->i32_0, "");
4145 j = LLVMBuildExtractElement(
4146 ctx->ac.builder, interp_param, ctx->i32_1, "");
4147 }
4148 v = si_build_fs_interp(ctx, input_base + idx, schan,
4149 prim_mask, i, j);
4150
4151 gather = LLVMBuildInsertElement(ctx->ac.builder,
4152 gather, v, LLVMConstInt(ctx->i32, idx, false), "");
4153 }
4154
4155 emit_data->output[chan] = LLVMBuildExtractElement(
4156 ctx->ac.builder, gather, array_idx, "");
4157 }
4158 }
4159
4160 static void vote_all_emit(
4161 const struct lp_build_tgsi_action *action,
4162 struct lp_build_tgsi_context *bld_base,
4163 struct lp_build_emit_data *emit_data)
4164 {
4165 struct si_shader_context *ctx = si_shader_context(bld_base);
4166
4167 LLVMValueRef tmp = ac_build_vote_all(&ctx->ac, emit_data->args[0]);
4168 emit_data->output[emit_data->chan] =
4169 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4170 }
4171
4172 static void vote_any_emit(
4173 const struct lp_build_tgsi_action *action,
4174 struct lp_build_tgsi_context *bld_base,
4175 struct lp_build_emit_data *emit_data)
4176 {
4177 struct si_shader_context *ctx = si_shader_context(bld_base);
4178
4179 LLVMValueRef tmp = ac_build_vote_any(&ctx->ac, emit_data->args[0]);
4180 emit_data->output[emit_data->chan] =
4181 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4182 }
4183
4184 static void vote_eq_emit(
4185 const struct lp_build_tgsi_action *action,
4186 struct lp_build_tgsi_context *bld_base,
4187 struct lp_build_emit_data *emit_data)
4188 {
4189 struct si_shader_context *ctx = si_shader_context(bld_base);
4190
4191 LLVMValueRef tmp = ac_build_vote_eq(&ctx->ac, emit_data->args[0]);
4192 emit_data->output[emit_data->chan] =
4193 LLVMBuildSExt(ctx->ac.builder, tmp, ctx->i32, "");
4194 }
4195
4196 static void ballot_emit(
4197 const struct lp_build_tgsi_action *action,
4198 struct lp_build_tgsi_context *bld_base,
4199 struct lp_build_emit_data *emit_data)
4200 {
4201 struct si_shader_context *ctx = si_shader_context(bld_base);
4202 LLVMBuilderRef builder = ctx->ac.builder;
4203 LLVMValueRef tmp;
4204
4205 tmp = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4206 tmp = ac_build_ballot(&ctx->ac, tmp);
4207
4208 emit_data->output[0] = LLVMBuildTrunc(builder, tmp, ctx->i32, "");
4209
4210 if (ctx->ac.wave_size == 32) {
4211 emit_data->output[1] = ctx->i32_0;
4212 } else {
4213 tmp = LLVMBuildLShr(builder, tmp, LLVMConstInt(ctx->i64, 32, 0), "");
4214 emit_data->output[1] = LLVMBuildTrunc(builder, tmp, ctx->i32, "");
4215 }
4216 }
4217
4218 static void read_lane_emit(
4219 const struct lp_build_tgsi_action *action,
4220 struct lp_build_tgsi_context *bld_base,
4221 struct lp_build_emit_data *emit_data)
4222 {
4223 struct si_shader_context *ctx = si_shader_context(bld_base);
4224
4225 if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_READ_INVOC) {
4226 emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst,
4227 0, emit_data->src_chan);
4228
4229 /* Always read the source invocation (= lane) from the X channel. */
4230 emit_data->args[1] = lp_build_emit_fetch(bld_base, emit_data->inst,
4231 1, TGSI_CHAN_X);
4232 emit_data->arg_count = 2;
4233 }
4234
4235 /* We currently have no other way to prevent LLVM from lifting the icmp
4236 * calls to a dominating basic block.
4237 */
4238 ac_build_optimization_barrier(&ctx->ac, &emit_data->args[0]);
4239
4240 for (unsigned i = 0; i < emit_data->arg_count; ++i)
4241 emit_data->args[i] = ac_to_integer(&ctx->ac, emit_data->args[i]);
4242
4243 emit_data->output[emit_data->chan] =
4244 ac_build_intrinsic(&ctx->ac, action->intr_name,
4245 ctx->i32, emit_data->args, emit_data->arg_count,
4246 AC_FUNC_ATTR_READNONE |
4247 AC_FUNC_ATTR_CONVERGENT);
4248 }
4249
4250 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
4251 struct lp_build_emit_data *emit_data)
4252 {
4253 struct si_shader_context *ctx = si_shader_context(bld_base);
4254 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
4255 LLVMValueRef imm;
4256 unsigned stream;
4257
4258 assert(src0.File == TGSI_FILE_IMMEDIATE);
4259
4260 imm = ctx->imms[src0.Index * TGSI_NUM_CHANNELS + src0.SwizzleX];
4261 stream = LLVMConstIntGetZExtValue(imm) & 0x3;
4262 return stream;
4263 }
4264
4265 /* Emit one vertex from the geometry shader */
4266 static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
4267 unsigned stream,
4268 LLVMValueRef *addrs)
4269 {
4270 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4271
4272 if (ctx->shader->key.as_ngg) {
4273 gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
4274 return;
4275 }
4276
4277 struct tgsi_shader_info *info = &ctx->shader->selector->info;
4278 struct si_shader *shader = ctx->shader;
4279 LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
4280 ctx->param_gs2vs_offset);
4281 LLVMValueRef gs_next_vertex;
4282 LLVMValueRef can_emit;
4283 unsigned chan, offset;
4284 int i;
4285
4286 /* Write vertex attribute values to GSVS ring */
4287 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
4288 ctx->gs_next_vertex[stream],
4289 "");
4290
4291 /* If this thread has already emitted the declared maximum number of
4292 * vertices, skip the write: excessive vertex emissions are not
4293 * supposed to have any effect.
4294 *
4295 * If the shader has no writes to memory, kill it instead. This skips
4296 * further memory loads and may allow LLVM to skip to the end
4297 * altogether.
4298 */
4299 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
4300 LLVMConstInt(ctx->i32,
4301 shader->selector->gs_max_out_vertices, 0), "");
4302
4303 bool use_kill = !info->writes_memory;
4304 if (use_kill) {
4305 ac_build_kill_if_false(&ctx->ac, can_emit);
4306 } else {
4307 ac_build_ifcc(&ctx->ac, can_emit, 6505);
4308 }
4309
4310 offset = 0;
4311 for (i = 0; i < info->num_outputs; i++) {
4312 for (chan = 0; chan < 4; chan++) {
4313 if (!(info->output_usagemask[i] & (1 << chan)) ||
4314 ((info->output_streams[i] >> (2 * chan)) & 3) != stream)
4315 continue;
4316
4317 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + chan], "");
4318 LLVMValueRef voffset =
4319 LLVMConstInt(ctx->i32, offset *
4320 shader->selector->gs_max_out_vertices, 0);
4321 offset++;
4322
4323 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
4324 voffset = LLVMBuildMul(ctx->ac.builder, voffset,
4325 LLVMConstInt(ctx->i32, 4, 0), "");
4326
4327 out_val = ac_to_integer(&ctx->ac, out_val);
4328
4329 ac_build_buffer_store_dword(&ctx->ac,
4330 ctx->gsvs_ring[stream],
4331 out_val, 1,
4332 voffset, soffset, 0,
4333 ac_glc | ac_slc, true);
4334 }
4335 }
4336
4337 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex, ctx->i32_1, "");
4338 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
4339
4340 /* Signal vertex emission if vertex data was written. */
4341 if (offset) {
4342 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
4343 si_get_gs_wave_id(ctx));
4344 }
4345
4346 if (!use_kill)
4347 ac_build_endif(&ctx->ac, 6505);
4348 }
4349
4350 /* Emit one vertex from the geometry shader */
4351 static void si_tgsi_emit_vertex(
4352 const struct lp_build_tgsi_action *action,
4353 struct lp_build_tgsi_context *bld_base,
4354 struct lp_build_emit_data *emit_data)
4355 {
4356 struct si_shader_context *ctx = si_shader_context(bld_base);
4357 unsigned stream = si_llvm_get_stream(bld_base, emit_data);
4358
4359 si_llvm_emit_vertex(&ctx->abi, stream, ctx->outputs[0]);
4360 }
4361
4362 /* Cut one primitive from the geometry shader */
4363 static void si_llvm_emit_primitive(struct ac_shader_abi *abi,
4364 unsigned stream)
4365 {
4366 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
4367
4368 if (ctx->shader->key.as_ngg) {
4369 LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
4370 return;
4371 }
4372
4373 /* Signal primitive cut */
4374 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8),
4375 si_get_gs_wave_id(ctx));
4376 }
4377
4378 /* Cut one primitive from the geometry shader */
4379 static void si_tgsi_emit_primitive(
4380 const struct lp_build_tgsi_action *action,
4381 struct lp_build_tgsi_context *bld_base,
4382 struct lp_build_emit_data *emit_data)
4383 {
4384 struct si_shader_context *ctx = si_shader_context(bld_base);
4385
4386 si_llvm_emit_primitive(&ctx->abi, si_llvm_get_stream(bld_base, emit_data));
4387 }
4388
4389 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
4390 struct lp_build_tgsi_context *bld_base,
4391 struct lp_build_emit_data *emit_data)
4392 {
4393 struct si_shader_context *ctx = si_shader_context(bld_base);
4394
4395 /* GFX6 only (thanks to a hw bug workaround):
4396 * The real barrier instruction isn’t needed, because an entire patch
4397 * always fits into a single wave.
4398 */
4399 if (ctx->screen->info.chip_class == GFX6 &&
4400 ctx->type == PIPE_SHADER_TESS_CTRL) {
4401 ac_build_waitcnt(&ctx->ac, AC_WAIT_LGKM | AC_WAIT_VLOAD | AC_WAIT_VSTORE);
4402 return;
4403 }
4404
4405 ac_build_s_barrier(&ctx->ac);
4406 }
4407
4408 void si_create_function(struct si_shader_context *ctx,
4409 const char *name,
4410 LLVMTypeRef *returns, unsigned num_returns,
4411 struct si_function_info *fninfo,
4412 unsigned max_workgroup_size)
4413 {
4414 int i;
4415
4416 si_llvm_create_func(ctx, name, returns, num_returns,
4417 fninfo->types, fninfo->num_params);
4418 ctx->return_value = LLVMGetUndef(ctx->return_type);
4419
4420 for (i = 0; i < fninfo->num_sgpr_params; ++i) {
4421 LLVMValueRef P = LLVMGetParam(ctx->main_fn, i);
4422
4423 /* The combination of:
4424 * - noalias
4425 * - dereferenceable
4426 * - invariant.load
4427 * allows the optimization passes to move loads and reduces
4428 * SGPR spilling significantly.
4429 */
4430 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4431 AC_FUNC_ATTR_INREG);
4432
4433 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
4434 ac_add_function_attr(ctx->ac.context, ctx->main_fn, i + 1,
4435 AC_FUNC_ATTR_NOALIAS);
4436 ac_add_attr_dereferenceable(P, UINT64_MAX);
4437 }
4438 }
4439
4440 for (i = 0; i < fninfo->num_params; ++i) {
4441 if (fninfo->assign[i])
4442 *fninfo->assign[i] = LLVMGetParam(ctx->main_fn, i);
4443 }
4444
4445 if (ctx->screen->info.address32_hi) {
4446 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
4447 "amdgpu-32bit-address-high-bits",
4448 ctx->screen->info.address32_hi);
4449 }
4450
4451 ac_llvm_set_workgroup_size(ctx->main_fn, max_workgroup_size);
4452
4453 LLVMAddTargetDependentFunctionAttr(ctx->main_fn,
4454 "no-signed-zeros-fp-math",
4455 "true");
4456 }
4457
4458 static void declare_streamout_params(struct si_shader_context *ctx,
4459 struct pipe_stream_output_info *so,
4460 struct si_function_info *fninfo)
4461 {
4462 if (ctx->screen->use_ngg_streamout)
4463 return;
4464
4465 /* Streamout SGPRs. */
4466 if (so->num_outputs) {
4467 if (ctx->type != PIPE_SHADER_TESS_EVAL)
4468 ctx->param_streamout_config = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4469 else
4470 ctx->param_streamout_config = fninfo->num_params - 1;
4471
4472 ctx->param_streamout_write_index = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4473 }
4474 /* A streamout buffer offset is loaded if the stride is non-zero. */
4475 for (int i = 0; i < 4; i++) {
4476 if (!so->stride[i])
4477 continue;
4478
4479 ctx->param_streamout_offset[i] = add_arg(fninfo, ARG_SGPR, ctx->ac.i32);
4480 }
4481 }
4482
4483 static unsigned si_get_max_workgroup_size(const struct si_shader *shader)
4484 {
4485 switch (shader->selector->type) {
4486 case PIPE_SHADER_VERTEX:
4487 case PIPE_SHADER_TESS_EVAL:
4488 return shader->key.as_ngg ? 128 : 0;
4489
4490 case PIPE_SHADER_TESS_CTRL:
4491 /* Return this so that LLVM doesn't remove s_barrier
4492 * instructions on chips where we use s_barrier. */
4493 return shader->selector->screen->info.chip_class >= GFX7 ? 128 : 0;
4494
4495 case PIPE_SHADER_GEOMETRY:
4496 return shader->selector->screen->info.chip_class >= GFX9 ? 128 : 0;
4497
4498 case PIPE_SHADER_COMPUTE:
4499 break; /* see below */
4500
4501 default:
4502 return 0;
4503 }
4504
4505 const unsigned *properties = shader->selector->info.properties;
4506 unsigned max_work_group_size =
4507 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
4508 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
4509 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
4510
4511 if (!max_work_group_size) {
4512 /* This is a variable group size compute shader,
4513 * compile it for the maximum possible group size.
4514 */
4515 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
4516 }
4517 return max_work_group_size;
4518 }
4519
4520 static void declare_const_and_shader_buffers(struct si_shader_context *ctx,
4521 struct si_function_info *fninfo,
4522 bool assign_params)
4523 {
4524 LLVMTypeRef const_shader_buf_type;
4525
4526 if (ctx->shader->selector->info.const_buffers_declared == 1 &&
4527 ctx->shader->selector->info.shader_buffers_declared == 0)
4528 const_shader_buf_type = ctx->f32;
4529 else
4530 const_shader_buf_type = ctx->v4i32;
4531
4532 unsigned const_and_shader_buffers =
4533 add_arg(fninfo, ARG_SGPR,
4534 ac_array_in_const32_addr_space(const_shader_buf_type));
4535
4536 if (assign_params)
4537 ctx->param_const_and_shader_buffers = const_and_shader_buffers;
4538 }
4539
4540 static void declare_samplers_and_images(struct si_shader_context *ctx,
4541 struct si_function_info *fninfo,
4542 bool assign_params)
4543 {
4544 unsigned samplers_and_images =
4545 add_arg(fninfo, ARG_SGPR,
4546 ac_array_in_const32_addr_space(ctx->v8i32));
4547
4548 if (assign_params)
4549 ctx->param_samplers_and_images = samplers_and_images;
4550 }
4551
4552 static void declare_per_stage_desc_pointers(struct si_shader_context *ctx,
4553 struct si_function_info *fninfo,
4554 bool assign_params)
4555 {
4556 declare_const_and_shader_buffers(ctx, fninfo, assign_params);
4557 declare_samplers_and_images(ctx, fninfo, assign_params);
4558 }
4559
4560 static void declare_global_desc_pointers(struct si_shader_context *ctx,
4561 struct si_function_info *fninfo)
4562 {
4563 ctx->param_rw_buffers = add_arg(fninfo, ARG_SGPR,
4564 ac_array_in_const32_addr_space(ctx->v4i32));
4565 ctx->param_bindless_samplers_and_images = add_arg(fninfo, ARG_SGPR,
4566 ac_array_in_const32_addr_space(ctx->v8i32));
4567 }
4568
4569 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
4570 struct si_function_info *fninfo)
4571 {
4572 ctx->param_vs_state_bits = add_arg(fninfo, ARG_SGPR, ctx->i32);
4573 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.base_vertex);
4574 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.start_instance);
4575 add_arg_assign(fninfo, ARG_SGPR, ctx->i32, &ctx->abi.draw_id);
4576 }
4577
4578 static void declare_vs_input_vgprs(struct si_shader_context *ctx,
4579 struct si_function_info *fninfo,
4580 unsigned *num_prolog_vgprs)
4581 {
4582 struct si_shader *shader = ctx->shader;
4583
4584 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.vertex_id);
4585 if (shader->key.as_ls) {
4586 ctx->param_rel_auto_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4587 if (ctx->screen->info.chip_class >= GFX10) {
4588 add_arg(fninfo, ARG_VGPR, ctx->i32); /* user VGPR */
4589 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4590 } else {
4591 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4592 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4593 }
4594 } else if (ctx->screen->info.chip_class >= GFX10) {
4595 add_arg(fninfo, ARG_VGPR, ctx->i32); /* user vgpr */
4596 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32); /* user vgpr or PrimID (legacy) */
4597 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4598 } else {
4599 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.instance_id);
4600 ctx->param_vs_prim_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4601 add_arg(fninfo, ARG_VGPR, ctx->i32); /* unused */
4602 }
4603
4604 if (!shader->is_gs_copy_shader) {
4605 /* Vertex load indices. */
4606 ctx->param_vertex_index0 = fninfo->num_params;
4607 for (unsigned i = 0; i < shader->selector->info.num_inputs; i++)
4608 add_arg(fninfo, ARG_VGPR, ctx->i32);
4609 *num_prolog_vgprs += shader->selector->info.num_inputs;
4610 }
4611 }
4612
4613 static void declare_vs_blit_inputs(struct si_shader_context *ctx,
4614 struct si_function_info *fninfo,
4615 unsigned vs_blit_property)
4616 {
4617 ctx->param_vs_blit_inputs = fninfo->num_params;
4618 add_arg(fninfo, ARG_SGPR, ctx->i32); /* i16 x1, y1 */
4619 add_arg(fninfo, ARG_SGPR, ctx->i32); /* i16 x2, y2 */
4620 add_arg(fninfo, ARG_SGPR, ctx->f32); /* depth */
4621
4622 if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_COLOR) {
4623 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color0 */
4624 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color1 */
4625 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color2 */
4626 add_arg(fninfo, ARG_SGPR, ctx->f32); /* color3 */
4627 } else if (vs_blit_property == SI_VS_BLIT_SGPRS_POS_TEXCOORD) {
4628 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.x1 */
4629 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.y1 */
4630 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.x2 */
4631 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.y2 */
4632 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.z */
4633 add_arg(fninfo, ARG_SGPR, ctx->f32); /* texcoord.w */
4634 }
4635 }
4636
4637 static void declare_tes_input_vgprs(struct si_shader_context *ctx,
4638 struct si_function_info *fninfo)
4639 {
4640 ctx->param_tes_u = add_arg(fninfo, ARG_VGPR, ctx->f32);
4641 ctx->param_tes_v = add_arg(fninfo, ARG_VGPR, ctx->f32);
4642 ctx->param_tes_rel_patch_id = add_arg(fninfo, ARG_VGPR, ctx->i32);
4643 add_arg_assign(fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tes_patch_id);
4644 }
4645
4646 enum {
4647 /* Convenient merged shader definitions. */
4648 SI_SHADER_MERGED_VERTEX_TESSCTRL = PIPE_SHADER_TYPES,
4649 SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY,
4650 };
4651
4652 static void create_function(struct si_shader_context *ctx)
4653 {
4654 struct si_shader *shader = ctx->shader;
4655 struct si_function_info fninfo;
4656 LLVMTypeRef returns[16+32*4];
4657 unsigned i, num_return_sgprs;
4658 unsigned num_returns = 0;
4659 unsigned num_prolog_vgprs = 0;
4660 unsigned type = ctx->type;
4661 unsigned vs_blit_property =
4662 shader->selector->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
4663
4664 si_init_function_info(&fninfo);
4665
4666 /* Set MERGED shaders. */
4667 if (ctx->screen->info.chip_class >= GFX9) {
4668 if (shader->key.as_ls || type == PIPE_SHADER_TESS_CTRL)
4669 type = SI_SHADER_MERGED_VERTEX_TESSCTRL; /* LS or HS */
4670 else if (shader->key.as_es || shader->key.as_ngg || type == PIPE_SHADER_GEOMETRY)
4671 type = SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY;
4672 }
4673
4674 LLVMTypeRef v3i32 = LLVMVectorType(ctx->i32, 3);
4675
4676 switch (type) {
4677 case PIPE_SHADER_VERTEX:
4678 declare_global_desc_pointers(ctx, &fninfo);
4679
4680 if (vs_blit_property) {
4681 declare_vs_blit_inputs(ctx, &fninfo, vs_blit_property);
4682
4683 /* VGPRs */
4684 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4685 break;
4686 }
4687
4688 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4689 declare_vs_specific_input_sgprs(ctx, &fninfo);
4690 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4691 ac_array_in_const32_addr_space(ctx->v4i32));
4692
4693 if (shader->key.as_es) {
4694 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4695 } else if (shader->key.as_ls) {
4696 /* no extra parameters */
4697 } else {
4698 if (shader->is_gs_copy_shader) {
4699 fninfo.num_params = ctx->param_vs_state_bits + 1;
4700 fninfo.num_sgpr_params = fninfo.num_params;
4701 }
4702
4703 /* The locations of the other parameters are assigned dynamically. */
4704 declare_streamout_params(ctx, &shader->selector->so,
4705 &fninfo);
4706 }
4707
4708 /* VGPRs */
4709 declare_vs_input_vgprs(ctx, &fninfo, &num_prolog_vgprs);
4710
4711 /* Return values */
4712 if (shader->key.opt.vs_as_prim_discard_cs) {
4713 for (i = 0; i < 4; i++)
4714 returns[num_returns++] = ctx->f32; /* VGPRs */
4715 }
4716 break;
4717
4718 case PIPE_SHADER_TESS_CTRL: /* GFX6-GFX8 */
4719 declare_global_desc_pointers(ctx, &fninfo);
4720 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4721 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4722 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4723 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4724 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4725 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4726 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4727
4728 /* VGPRs */
4729 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4730 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4731
4732 /* param_tcs_offchip_offset and param_tcs_factor_offset are
4733 * placed after the user SGPRs.
4734 */
4735 for (i = 0; i < GFX6_TCS_NUM_USER_SGPR + 2; i++)
4736 returns[num_returns++] = ctx->i32; /* SGPRs */
4737 for (i = 0; i < 11; i++)
4738 returns[num_returns++] = ctx->f32; /* VGPRs */
4739 break;
4740
4741 case SI_SHADER_MERGED_VERTEX_TESSCTRL:
4742 /* Merged stages have 8 system SGPRs at the beginning. */
4743 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_HS */
4744 declare_per_stage_desc_pointers(ctx, &fninfo,
4745 ctx->type == PIPE_SHADER_TESS_CTRL);
4746 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4747 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4748 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4749 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4750 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4751 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused */
4752
4753 declare_global_desc_pointers(ctx, &fninfo);
4754 declare_per_stage_desc_pointers(ctx, &fninfo,
4755 ctx->type == PIPE_SHADER_VERTEX);
4756 declare_vs_specific_input_sgprs(ctx, &fninfo);
4757
4758 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4759 ctx->param_tcs_out_lds_offsets = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4760 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4761 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4762 ac_array_in_const32_addr_space(ctx->v4i32));
4763
4764 /* VGPRs (first TCS, then VS) */
4765 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_patch_id);
4766 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.tcs_rel_ids);
4767
4768 if (ctx->type == PIPE_SHADER_VERTEX) {
4769 declare_vs_input_vgprs(ctx, &fninfo,
4770 &num_prolog_vgprs);
4771
4772 /* LS return values are inputs to the TCS main shader part. */
4773 for (i = 0; i < 8 + GFX9_TCS_NUM_USER_SGPR; i++)
4774 returns[num_returns++] = ctx->i32; /* SGPRs */
4775 for (i = 0; i < 2; i++)
4776 returns[num_returns++] = ctx->f32; /* VGPRs */
4777 } else {
4778 /* TCS return values are inputs to the TCS epilog.
4779 *
4780 * param_tcs_offchip_offset, param_tcs_factor_offset,
4781 * param_tcs_offchip_layout, and param_rw_buffers
4782 * should be passed to the epilog.
4783 */
4784 for (i = 0; i <= 8 + GFX9_SGPR_TCS_OUT_LAYOUT; i++)
4785 returns[num_returns++] = ctx->i32; /* SGPRs */
4786 for (i = 0; i < 11; i++)
4787 returns[num_returns++] = ctx->f32; /* VGPRs */
4788 }
4789 break;
4790
4791 case SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY:
4792 /* Merged stages have 8 system SGPRs at the beginning. */
4793 /* SPI_SHADER_USER_DATA_ADDR_LO/HI_GS */
4794 declare_per_stage_desc_pointers(ctx, &fninfo,
4795 ctx->type == PIPE_SHADER_GEOMETRY);
4796
4797 if (ctx->shader->key.as_ngg)
4798 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->gs_tg_info);
4799 else
4800 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4801
4802 ctx->param_merged_wave_info = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4803 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4804 ctx->param_merged_scratch_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4805 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS << 8) */
4806 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* unused (SPI_SHADER_PGM_LO/HI_GS >> 24) */
4807
4808 declare_global_desc_pointers(ctx, &fninfo);
4809 if (ctx->type != PIPE_SHADER_VERTEX || !vs_blit_property) {
4810 declare_per_stage_desc_pointers(ctx, &fninfo,
4811 (ctx->type == PIPE_SHADER_VERTEX ||
4812 ctx->type == PIPE_SHADER_TESS_EVAL));
4813 }
4814
4815 if (ctx->type == PIPE_SHADER_VERTEX) {
4816 if (vs_blit_property)
4817 declare_vs_blit_inputs(ctx, &fninfo, vs_blit_property);
4818 else
4819 declare_vs_specific_input_sgprs(ctx, &fninfo);
4820 } else {
4821 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4822 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4823 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4824 /* Declare as many input SGPRs as the VS has. */
4825 }
4826
4827 if (ctx->type == PIPE_SHADER_VERTEX) {
4828 ctx->param_vertex_buffers = add_arg(&fninfo, ARG_SGPR,
4829 ac_array_in_const32_addr_space(ctx->v4i32));
4830 }
4831
4832 /* VGPRs (first GS, then VS/TES) */
4833 ctx->param_gs_vtx01_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4834 ctx->param_gs_vtx23_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4835 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4836 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4837 ctx->param_gs_vtx45_offset = add_arg(&fninfo, ARG_VGPR, ctx->i32);
4838
4839 if (ctx->type == PIPE_SHADER_VERTEX) {
4840 declare_vs_input_vgprs(ctx, &fninfo,
4841 &num_prolog_vgprs);
4842 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
4843 declare_tes_input_vgprs(ctx, &fninfo);
4844 }
4845
4846 if (ctx->shader->key.as_es &&
4847 (ctx->type == PIPE_SHADER_VERTEX ||
4848 ctx->type == PIPE_SHADER_TESS_EVAL)) {
4849 unsigned num_user_sgprs;
4850
4851 if (ctx->type == PIPE_SHADER_VERTEX)
4852 num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
4853 else
4854 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
4855
4856 /* ES return values are inputs to GS. */
4857 for (i = 0; i < 8 + num_user_sgprs; i++)
4858 returns[num_returns++] = ctx->i32; /* SGPRs */
4859 for (i = 0; i < 5; i++)
4860 returns[num_returns++] = ctx->f32; /* VGPRs */
4861 }
4862 break;
4863
4864 case PIPE_SHADER_TESS_EVAL:
4865 declare_global_desc_pointers(ctx, &fninfo);
4866 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4867 ctx->param_vs_state_bits = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4868 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4869 ctx->param_tes_offchip_addr = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4870
4871 if (shader->key.as_es) {
4872 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4873 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4874 ctx->param_es2gs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4875 } else {
4876 add_arg(&fninfo, ARG_SGPR, ctx->i32);
4877 declare_streamout_params(ctx, &shader->selector->so,
4878 &fninfo);
4879 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4880 }
4881
4882 /* VGPRs */
4883 declare_tes_input_vgprs(ctx, &fninfo);
4884 break;
4885
4886 case PIPE_SHADER_GEOMETRY:
4887 declare_global_desc_pointers(ctx, &fninfo);
4888 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4889 ctx->param_gs2vs_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4890 ctx->param_gs_wave_id = add_arg(&fninfo, ARG_SGPR, ctx->i32);
4891
4892 /* VGPRs */
4893 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[0]);
4894 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[1]);
4895 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_prim_id);
4896 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[2]);
4897 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[3]);
4898 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[4]);
4899 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->gs_vtx_offset[5]);
4900 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &ctx->abi.gs_invocation_id);
4901 break;
4902
4903 case PIPE_SHADER_FRAGMENT:
4904 declare_global_desc_pointers(ctx, &fninfo);
4905 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4906 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
4907 add_arg_assign_checked(&fninfo, ARG_SGPR, ctx->i32,
4908 &ctx->abi.prim_mask, SI_PARAM_PRIM_MASK);
4909
4910 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->v2i32,
4911 &ctx->abi.persp_sample, SI_PARAM_PERSP_SAMPLE);
4912 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->v2i32,
4913 &ctx->abi.persp_center, SI_PARAM_PERSP_CENTER);
4914 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->v2i32,
4915 &ctx->abi.persp_centroid, SI_PARAM_PERSP_CENTROID);
4916 add_arg_checked(&fninfo, ARG_VGPR, v3i32, SI_PARAM_PERSP_PULL_MODEL);
4917 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->v2i32,
4918 &ctx->abi.linear_sample, SI_PARAM_LINEAR_SAMPLE);
4919 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->v2i32,
4920 &ctx->abi.linear_center, SI_PARAM_LINEAR_CENTER);
4921 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->v2i32,
4922 &ctx->abi.linear_centroid, SI_PARAM_LINEAR_CENTROID);
4923 add_arg_checked(&fninfo, ARG_VGPR, ctx->f32, SI_PARAM_LINE_STIPPLE_TEX);
4924 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4925 &ctx->abi.frag_pos[0], SI_PARAM_POS_X_FLOAT);
4926 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4927 &ctx->abi.frag_pos[1], SI_PARAM_POS_Y_FLOAT);
4928 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4929 &ctx->abi.frag_pos[2], SI_PARAM_POS_Z_FLOAT);
4930 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4931 &ctx->abi.frag_pos[3], SI_PARAM_POS_W_FLOAT);
4932 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4933 &ctx->abi.front_face, SI_PARAM_FRONT_FACE);
4934 shader->info.face_vgpr_index = 20;
4935 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->i32,
4936 &ctx->abi.ancillary, SI_PARAM_ANCILLARY);
4937 shader->info.ancillary_vgpr_index = 21;
4938 add_arg_assign_checked(&fninfo, ARG_VGPR, ctx->f32,
4939 &ctx->abi.sample_coverage, SI_PARAM_SAMPLE_COVERAGE);
4940 add_arg_checked(&fninfo, ARG_VGPR, ctx->i32, SI_PARAM_POS_FIXED_PT);
4941
4942 /* Color inputs from the prolog. */
4943 if (shader->selector->info.colors_read) {
4944 unsigned num_color_elements =
4945 util_bitcount(shader->selector->info.colors_read);
4946
4947 assert(fninfo.num_params + num_color_elements <= ARRAY_SIZE(fninfo.types));
4948 for (i = 0; i < num_color_elements; i++)
4949 add_arg(&fninfo, ARG_VGPR, ctx->f32);
4950
4951 num_prolog_vgprs += num_color_elements;
4952 }
4953
4954 /* Outputs for the epilog. */
4955 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
4956 num_returns =
4957 num_return_sgprs +
4958 util_bitcount(shader->selector->info.colors_written) * 4 +
4959 shader->selector->info.writes_z +
4960 shader->selector->info.writes_stencil +
4961 shader->selector->info.writes_samplemask +
4962 1 /* SampleMaskIn */;
4963
4964 num_returns = MAX2(num_returns,
4965 num_return_sgprs +
4966 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
4967
4968 for (i = 0; i < num_return_sgprs; i++)
4969 returns[i] = ctx->i32;
4970 for (; i < num_returns; i++)
4971 returns[i] = ctx->f32;
4972 break;
4973
4974 case PIPE_SHADER_COMPUTE:
4975 declare_global_desc_pointers(ctx, &fninfo);
4976 declare_per_stage_desc_pointers(ctx, &fninfo, true);
4977 if (shader->selector->info.uses_grid_size)
4978 add_arg_assign(&fninfo, ARG_SGPR, v3i32, &ctx->abi.num_work_groups);
4979 if (shader->selector->info.uses_block_size &&
4980 shader->selector->info.properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
4981 ctx->param_block_size = add_arg(&fninfo, ARG_SGPR, v3i32);
4982
4983 unsigned cs_user_data_dwords =
4984 shader->selector->info.properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD];
4985 if (cs_user_data_dwords) {
4986 ctx->param_cs_user_data = add_arg(&fninfo, ARG_SGPR,
4987 LLVMVectorType(ctx->i32, cs_user_data_dwords));
4988 }
4989
4990 for (i = 0; i < 3; i++) {
4991 ctx->abi.workgroup_ids[i] = NULL;
4992 if (shader->selector->info.uses_block_id[i])
4993 add_arg_assign(&fninfo, ARG_SGPR, ctx->i32, &ctx->abi.workgroup_ids[i]);
4994 }
4995
4996 add_arg_assign(&fninfo, ARG_VGPR, v3i32, &ctx->abi.local_invocation_ids);
4997 break;
4998 default:
4999 assert(0 && "unimplemented shader");
5000 return;
5001 }
5002
5003 si_create_function(ctx, "main", returns, num_returns, &fninfo,
5004 si_get_max_workgroup_size(shader));
5005
5006 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5007 if (ctx->type == PIPE_SHADER_FRAGMENT && !ctx->shader->is_monolithic) {
5008 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
5009 "InitialPSInputAddr",
5010 S_0286D0_PERSP_SAMPLE_ENA(1) |
5011 S_0286D0_PERSP_CENTER_ENA(1) |
5012 S_0286D0_PERSP_CENTROID_ENA(1) |
5013 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5014 S_0286D0_LINEAR_CENTER_ENA(1) |
5015 S_0286D0_LINEAR_CENTROID_ENA(1) |
5016 S_0286D0_FRONT_FACE_ENA(1) |
5017 S_0286D0_ANCILLARY_ENA(1) |
5018 S_0286D0_POS_FIXED_PT_ENA(1));
5019 }
5020
5021 shader->info.num_input_sgprs = 0;
5022 shader->info.num_input_vgprs = 0;
5023
5024 for (i = 0; i < fninfo.num_sgpr_params; ++i)
5025 shader->info.num_input_sgprs += ac_get_type_size(fninfo.types[i]) / 4;
5026
5027 for (; i < fninfo.num_params; ++i)
5028 shader->info.num_input_vgprs += ac_get_type_size(fninfo.types[i]) / 4;
5029
5030 assert(shader->info.num_input_vgprs >= num_prolog_vgprs);
5031 shader->info.num_input_vgprs -= num_prolog_vgprs;
5032
5033 if (shader->key.as_ls || ctx->type == PIPE_SHADER_TESS_CTRL) {
5034 if (USE_LDS_SYMBOLS && LLVM_VERSION_MAJOR >= 9) {
5035 /* The LSHS size is not known until draw time, so we append it
5036 * at the end of whatever LDS use there may be in the rest of
5037 * the shader (currently none, unless LLVM decides to do its
5038 * own LDS-based lowering).
5039 */
5040 ctx->ac.lds = LLVMAddGlobalInAddressSpace(
5041 ctx->ac.module, LLVMArrayType(ctx->i32, 0),
5042 "__lds_end", AC_ADDR_SPACE_LDS);
5043 LLVMSetAlignment(ctx->ac.lds, 256);
5044 } else {
5045 ac_declare_lds_as_pointer(&ctx->ac);
5046 }
5047 }
5048 }
5049
5050 /* Ensure that the esgs ring is declared.
5051 *
5052 * We declare it with 64KB alignment as a hint that the
5053 * pointer value will always be 0.
5054 */
5055 static void declare_esgs_ring(struct si_shader_context *ctx)
5056 {
5057 if (ctx->esgs_ring)
5058 return;
5059
5060 assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
5061
5062 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
5063 ctx->ac.module, LLVMArrayType(ctx->i32, 0),
5064 "esgs_ring",
5065 AC_ADDR_SPACE_LDS);
5066 LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
5067 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
5068 }
5069
5070 /**
5071 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5072 * for later use.
5073 */
5074 static void preload_ring_buffers(struct si_shader_context *ctx)
5075 {
5076 LLVMBuilderRef builder = ctx->ac.builder;
5077
5078 LLVMValueRef buf_ptr = LLVMGetParam(ctx->main_fn,
5079 ctx->param_rw_buffers);
5080
5081 if (ctx->shader->key.as_es || ctx->type == PIPE_SHADER_GEOMETRY) {
5082 if (ctx->screen->info.chip_class <= GFX8) {
5083 unsigned ring =
5084 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5085 : SI_ES_RING_ESGS;
5086 LLVMValueRef offset = LLVMConstInt(ctx->i32, ring, 0);
5087
5088 ctx->esgs_ring =
5089 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5090 } else {
5091 if (USE_LDS_SYMBOLS && LLVM_VERSION_MAJOR >= 9) {
5092 /* Declare the ESGS ring as an explicit LDS symbol. */
5093 declare_esgs_ring(ctx);
5094 } else {
5095 ac_declare_lds_as_pointer(&ctx->ac);
5096 ctx->esgs_ring = ctx->ac.lds;
5097 }
5098 }
5099 }
5100
5101 if (ctx->shader->is_gs_copy_shader) {
5102 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5103
5104 ctx->gsvs_ring[0] =
5105 ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5106 } else if (ctx->type == PIPE_SHADER_GEOMETRY) {
5107 const struct si_shader_selector *sel = ctx->shader->selector;
5108 LLVMValueRef offset = LLVMConstInt(ctx->i32, SI_RING_GSVS, 0);
5109 LLVMValueRef base_ring;
5110
5111 base_ring = ac_build_load_to_sgpr(&ctx->ac, buf_ptr, offset);
5112
5113 /* The conceptual layout of the GSVS ring is
5114 * v0c0 .. vLv0 v0c1 .. vLc1 ..
5115 * but the real memory layout is swizzled across
5116 * threads:
5117 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
5118 * t16v0c0 ..
5119 * Override the buffer descriptor accordingly.
5120 */
5121 LLVMTypeRef v2i64 = LLVMVectorType(ctx->i64, 2);
5122 uint64_t stream_offset = 0;
5123
5124 for (unsigned stream = 0; stream < 4; ++stream) {
5125 unsigned num_components;
5126 unsigned stride;
5127 unsigned num_records;
5128 LLVMValueRef ring, tmp;
5129
5130 num_components = sel->info.num_stream_output_components[stream];
5131 if (!num_components)
5132 continue;
5133
5134 stride = 4 * num_components * sel->gs_max_out_vertices;
5135
5136 /* Limit on the stride field for <= GFX7. */
5137 assert(stride < (1 << 14));
5138
5139 num_records = ctx->ac.wave_size;
5140
5141 ring = LLVMBuildBitCast(builder, base_ring, v2i64, "");
5142 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_0, "");
5143 tmp = LLVMBuildAdd(builder, tmp,
5144 LLVMConstInt(ctx->i64,
5145 stream_offset, 0), "");
5146 stream_offset += stride * ctx->ac.wave_size;
5147
5148 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_0, "");
5149 ring = LLVMBuildBitCast(builder, ring, ctx->v4i32, "");
5150 tmp = LLVMBuildExtractElement(builder, ring, ctx->i32_1, "");
5151 tmp = LLVMBuildOr(builder, tmp,
5152 LLVMConstInt(ctx->i32,
5153 S_008F04_STRIDE(stride) |
5154 S_008F04_SWIZZLE_ENABLE(1), 0), "");
5155 ring = LLVMBuildInsertElement(builder, ring, tmp, ctx->i32_1, "");
5156 ring = LLVMBuildInsertElement(builder, ring,
5157 LLVMConstInt(ctx->i32, num_records, 0),
5158 LLVMConstInt(ctx->i32, 2, 0), "");
5159
5160 uint32_t rsrc3 =
5161 S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
5162 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
5163 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
5164 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
5165 S_008F0C_INDEX_STRIDE(1) | /* index_stride = 16 (elements) */
5166 S_008F0C_ADD_TID_ENABLE(1);
5167
5168 if (ctx->ac.chip_class >= GFX10) {
5169 rsrc3 |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
5170 S_008F0C_OOB_SELECT(2) |
5171 S_008F0C_RESOURCE_LEVEL(1);
5172 } else {
5173 rsrc3 |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
5174 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
5175 S_008F0C_ELEMENT_SIZE(1); /* element_size = 4 (bytes) */
5176 }
5177
5178 ring = LLVMBuildInsertElement(builder, ring,
5179 LLVMConstInt(ctx->i32, rsrc3, false),
5180 LLVMConstInt(ctx->i32, 3, 0), "");
5181
5182 ctx->gsvs_ring[stream] = ring;
5183 }
5184 } else if (ctx->type == PIPE_SHADER_TESS_EVAL) {
5185 ctx->tess_offchip_ring = get_tess_ring_descriptor(ctx, TESS_OFFCHIP_RING_TES);
5186 }
5187 }
5188
5189 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5190 LLVMValueRef param_rw_buffers,
5191 unsigned param_pos_fixed_pt)
5192 {
5193 LLVMBuilderRef builder = ctx->ac.builder;
5194 LLVMValueRef slot, desc, offset, row, bit, address[2];
5195
5196 /* Use the fixed-point gl_FragCoord input.
5197 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5198 * per coordinate to get the repeating effect.
5199 */
5200 address[0] = si_unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5201 address[1] = si_unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5202
5203 /* Load the buffer descriptor. */
5204 slot = LLVMConstInt(ctx->i32, SI_PS_CONST_POLY_STIPPLE, 0);
5205 desc = ac_build_load_to_sgpr(&ctx->ac, param_rw_buffers, slot);
5206
5207 /* The stipple pattern is 32x32, each row has 32 bits. */
5208 offset = LLVMBuildMul(builder, address[1],
5209 LLVMConstInt(ctx->i32, 4, 0), "");
5210 row = buffer_load_const(ctx, desc, offset);
5211 row = ac_to_integer(&ctx->ac, row);
5212 bit = LLVMBuildLShr(builder, row, address[0], "");
5213 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5214 ac_build_kill_if_false(&ctx->ac, bit);
5215 }
5216
5217 /* For the UMR disassembler. */
5218 #define DEBUGGER_END_OF_CODE_MARKER 0xbf9f0000 /* invalid instruction */
5219 #define DEBUGGER_NUM_MARKERS 5
5220
5221 static bool si_shader_binary_open(struct si_screen *screen,
5222 struct si_shader *shader,
5223 struct ac_rtld_binary *rtld)
5224 {
5225 const struct si_shader_selector *sel = shader->selector;
5226 const char *part_elfs[5];
5227 size_t part_sizes[5];
5228 unsigned num_parts = 0;
5229
5230 #define add_part(shader_or_part) \
5231 if (shader_or_part) { \
5232 part_elfs[num_parts] = (shader_or_part)->binary.elf_buffer; \
5233 part_sizes[num_parts] = (shader_or_part)->binary.elf_size; \
5234 num_parts++; \
5235 }
5236
5237 add_part(shader->prolog);
5238 add_part(shader->previous_stage);
5239 add_part(shader->prolog2);
5240 add_part(shader);
5241 add_part(shader->epilog);
5242
5243 #undef add_part
5244
5245 struct ac_rtld_symbol lds_symbols[2];
5246 unsigned num_lds_symbols = 0;
5247
5248 if (sel && screen->info.chip_class >= GFX9 && !shader->is_gs_copy_shader &&
5249 (sel->type == PIPE_SHADER_GEOMETRY || shader->key.as_ngg)) {
5250 /* We add this symbol even on LLVM <= 8 to ensure that
5251 * shader->config.lds_size is set correctly below.
5252 */
5253 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
5254 sym->name = "esgs_ring";
5255 sym->size = shader->gs_info.esgs_ring_size;
5256 sym->align = 64 * 1024;
5257 }
5258
5259 if (shader->key.as_ngg && sel->type == PIPE_SHADER_GEOMETRY) {
5260 struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
5261 sym->name = "ngg_emit";
5262 sym->size = shader->ngg.ngg_emit_size * 4;
5263 sym->align = 4;
5264 }
5265
5266 bool ok = ac_rtld_open(rtld, (struct ac_rtld_open_info){
5267 .info = &screen->info,
5268 .options = {
5269 .halt_at_entry = screen->options.halt_shaders,
5270 },
5271 .shader_type = tgsi_processor_to_shader_stage(sel->type),
5272 .wave_size = si_get_shader_wave_size(shader),
5273 .num_parts = num_parts,
5274 .elf_ptrs = part_elfs,
5275 .elf_sizes = part_sizes,
5276 .num_shared_lds_symbols = num_lds_symbols,
5277 .shared_lds_symbols = lds_symbols });
5278
5279 if (rtld->lds_size > 0) {
5280 unsigned alloc_granularity = screen->info.chip_class >= GFX7 ? 512 : 256;
5281 shader->config.lds_size =
5282 align(rtld->lds_size, alloc_granularity) / alloc_granularity;
5283 }
5284
5285 return ok;
5286 }
5287
5288 static unsigned si_get_shader_binary_size(struct si_screen *screen, struct si_shader *shader)
5289 {
5290 struct ac_rtld_binary rtld;
5291 si_shader_binary_open(screen, shader, &rtld);
5292 return rtld.exec_size;
5293 }
5294
5295 static bool si_get_external_symbol(void *data, const char *name, uint64_t *value)
5296 {
5297 uint64_t *scratch_va = data;
5298
5299 if (!strcmp(scratch_rsrc_dword0_symbol, name)) {
5300 *value = (uint32_t)*scratch_va;
5301 return true;
5302 }
5303 if (!strcmp(scratch_rsrc_dword1_symbol, name)) {
5304 /* Enable scratch coalescing. */
5305 *value = S_008F04_BASE_ADDRESS_HI(*scratch_va >> 32) |
5306 S_008F04_SWIZZLE_ENABLE(1);
5307 return true;
5308 }
5309
5310 return false;
5311 }
5312
5313 bool si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader,
5314 uint64_t scratch_va)
5315 {
5316 struct ac_rtld_binary binary;
5317 if (!si_shader_binary_open(sscreen, shader, &binary))
5318 return false;
5319
5320 si_resource_reference(&shader->bo, NULL);
5321 shader->bo = si_aligned_buffer_create(&sscreen->b,
5322 sscreen->info.cpdma_prefetch_writes_memory ?
5323 0 : SI_RESOURCE_FLAG_READ_ONLY,
5324 PIPE_USAGE_IMMUTABLE,
5325 align(binary.rx_size, SI_CPDMA_ALIGNMENT),
5326 256);
5327 if (!shader->bo)
5328 return false;
5329
5330 /* Upload. */
5331 struct ac_rtld_upload_info u = {};
5332 u.binary = &binary;
5333 u.get_external_symbol = si_get_external_symbol;
5334 u.cb_data = &scratch_va;
5335 u.rx_va = shader->bo->gpu_address;
5336 u.rx_ptr = sscreen->ws->buffer_map(shader->bo->buf, NULL,
5337 PIPE_TRANSFER_READ_WRITE |
5338 PIPE_TRANSFER_UNSYNCHRONIZED |
5339 RADEON_TRANSFER_TEMPORARY);
5340 if (!u.rx_ptr)
5341 return false;
5342
5343 bool ok = ac_rtld_upload(&u);
5344
5345 sscreen->ws->buffer_unmap(shader->bo->buf);
5346 ac_rtld_close(&binary);
5347
5348 return ok;
5349 }
5350
5351 static void si_shader_dump_disassembly(struct si_screen *screen,
5352 const struct si_shader_binary *binary,
5353 enum pipe_shader_type shader_type,
5354 unsigned wave_size,
5355 struct pipe_debug_callback *debug,
5356 const char *name, FILE *file)
5357 {
5358 struct ac_rtld_binary rtld_binary;
5359
5360 if (!ac_rtld_open(&rtld_binary, (struct ac_rtld_open_info){
5361 .info = &screen->info,
5362 .shader_type = tgsi_processor_to_shader_stage(shader_type),
5363 .wave_size = wave_size,
5364 .num_parts = 1,
5365 .elf_ptrs = &binary->elf_buffer,
5366 .elf_sizes = &binary->elf_size }))
5367 return;
5368
5369 const char *disasm;
5370 size_t nbytes;
5371
5372 if (!ac_rtld_get_section_by_name(&rtld_binary, ".AMDGPU.disasm", &disasm, &nbytes))
5373 goto out;
5374
5375 if (nbytes > INT_MAX)
5376 goto out;
5377
5378 if (debug && debug->debug_message) {
5379 /* Very long debug messages are cut off, so send the
5380 * disassembly one line at a time. This causes more
5381 * overhead, but on the plus side it simplifies
5382 * parsing of resulting logs.
5383 */
5384 pipe_debug_message(debug, SHADER_INFO,
5385 "Shader Disassembly Begin");
5386
5387 uint64_t line = 0;
5388 while (line < nbytes) {
5389 int count = nbytes - line;
5390 const char *nl = memchr(disasm + line, '\n', nbytes - line);
5391 if (nl)
5392 count = nl - (disasm + line);
5393
5394 if (count) {
5395 pipe_debug_message(debug, SHADER_INFO,
5396 "%.*s", count, disasm + line);
5397 }
5398
5399 line += count + 1;
5400 }
5401
5402 pipe_debug_message(debug, SHADER_INFO,
5403 "Shader Disassembly End");
5404 }
5405
5406 if (file) {
5407 fprintf(file, "Shader %s disassembly:\n", name);
5408 fprintf(file, "%*s", (int)nbytes, disasm);
5409 }
5410
5411 out:
5412 ac_rtld_close(&rtld_binary);
5413 }
5414
5415 static void si_calculate_max_simd_waves(struct si_shader *shader)
5416 {
5417 struct si_screen *sscreen = shader->selector->screen;
5418 struct ac_shader_config *conf = &shader->config;
5419 unsigned num_inputs = shader->selector->info.num_inputs;
5420 unsigned lds_increment = sscreen->info.chip_class >= GFX7 ? 512 : 256;
5421 unsigned lds_per_wave = 0;
5422 unsigned max_simd_waves;
5423
5424 max_simd_waves = sscreen->info.max_wave64_per_simd;
5425
5426 /* Compute LDS usage for PS. */
5427 switch (shader->selector->type) {
5428 case PIPE_SHADER_FRAGMENT:
5429 /* The minimum usage per wave is (num_inputs * 48). The maximum
5430 * usage is (num_inputs * 48 * 16).
5431 * We can get anything in between and it varies between waves.
5432 *
5433 * The 48 bytes per input for a single primitive is equal to
5434 * 4 bytes/component * 4 components/input * 3 points.
5435 *
5436 * Other stages don't know the size at compile time or don't
5437 * allocate LDS per wave, but instead they do it per thread group.
5438 */
5439 lds_per_wave = conf->lds_size * lds_increment +
5440 align(num_inputs * 48, lds_increment);
5441 break;
5442 case PIPE_SHADER_COMPUTE:
5443 if (shader->selector) {
5444 unsigned max_workgroup_size =
5445 si_get_max_workgroup_size(shader);
5446 lds_per_wave = (conf->lds_size * lds_increment) /
5447 DIV_ROUND_UP(max_workgroup_size,
5448 sscreen->compute_wave_size);
5449 }
5450 break;
5451 default:;
5452 }
5453
5454 /* Compute the per-SIMD wave counts. */
5455 if (conf->num_sgprs) {
5456 max_simd_waves =
5457 MIN2(max_simd_waves,
5458 sscreen->info.num_physical_sgprs_per_simd / conf->num_sgprs);
5459 }
5460
5461 if (conf->num_vgprs) {
5462 /* Always print wave limits as Wave64, so that we can compare
5463 * Wave32 and Wave64 with shader-db fairly. */
5464 unsigned max_vgprs = sscreen->info.num_physical_wave64_vgprs_per_simd;
5465 max_simd_waves = MIN2(max_simd_waves, max_vgprs / conf->num_vgprs);
5466 }
5467
5468 /* LDS is 64KB per CU (4 SIMDs) on GFX6-9, which is 16KB per SIMD (usage above
5469 * 16KB makes some SIMDs unoccupied).
5470 *
5471 * LDS is 128KB in WGP mode and 64KB in CU mode. Assume the WGP mode is used.
5472 */
5473 unsigned max_lds_size = sscreen->info.chip_class >= GFX10 ? 128*1024 : 64*1024;
5474 unsigned max_lds_per_simd = max_lds_size / 4;
5475 if (lds_per_wave)
5476 max_simd_waves = MIN2(max_simd_waves, max_lds_per_simd / lds_per_wave);
5477
5478 shader->info.max_simd_waves = max_simd_waves;
5479 }
5480
5481 void si_shader_dump_stats_for_shader_db(struct si_screen *screen,
5482 struct si_shader *shader,
5483 struct pipe_debug_callback *debug)
5484 {
5485 const struct ac_shader_config *conf = &shader->config;
5486
5487 if (screen->options.debug_disassembly)
5488 si_shader_dump_disassembly(screen, &shader->binary,
5489 shader->selector->type,
5490 si_get_shader_wave_size(shader),
5491 debug, "main", NULL);
5492
5493 pipe_debug_message(debug, SHADER_INFO,
5494 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
5495 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
5496 "Spilled VGPRs: %d PrivMem VGPRs: %d",
5497 conf->num_sgprs, conf->num_vgprs,
5498 si_get_shader_binary_size(screen, shader),
5499 conf->lds_size, conf->scratch_bytes_per_wave,
5500 shader->info.max_simd_waves, conf->spilled_sgprs,
5501 conf->spilled_vgprs, shader->info.private_mem_vgprs);
5502 }
5503
5504 static void si_shader_dump_stats(struct si_screen *sscreen,
5505 struct si_shader *shader,
5506 FILE *file,
5507 bool check_debug_option)
5508 {
5509 const struct ac_shader_config *conf = &shader->config;
5510
5511 if (!check_debug_option ||
5512 si_can_dump_shader(sscreen, shader->selector->type)) {
5513 if (shader->selector->type == PIPE_SHADER_FRAGMENT) {
5514 fprintf(file, "*** SHADER CONFIG ***\n"
5515 "SPI_PS_INPUT_ADDR = 0x%04x\n"
5516 "SPI_PS_INPUT_ENA = 0x%04x\n",
5517 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
5518 }
5519
5520 fprintf(file, "*** SHADER STATS ***\n"
5521 "SGPRS: %d\n"
5522 "VGPRS: %d\n"
5523 "Spilled SGPRs: %d\n"
5524 "Spilled VGPRs: %d\n"
5525 "Private memory VGPRs: %d\n"
5526 "Code Size: %d bytes\n"
5527 "LDS: %d blocks\n"
5528 "Scratch: %d bytes per wave\n"
5529 "Max Waves: %d\n"
5530 "********************\n\n\n",
5531 conf->num_sgprs, conf->num_vgprs,
5532 conf->spilled_sgprs, conf->spilled_vgprs,
5533 shader->info.private_mem_vgprs,
5534 si_get_shader_binary_size(sscreen, shader),
5535 conf->lds_size, conf->scratch_bytes_per_wave,
5536 shader->info.max_simd_waves);
5537 }
5538 }
5539
5540 const char *si_get_shader_name(const struct si_shader *shader)
5541 {
5542 switch (shader->selector->type) {
5543 case PIPE_SHADER_VERTEX:
5544 if (shader->key.as_es)
5545 return "Vertex Shader as ES";
5546 else if (shader->key.as_ls)
5547 return "Vertex Shader as LS";
5548 else if (shader->key.opt.vs_as_prim_discard_cs)
5549 return "Vertex Shader as Primitive Discard CS";
5550 else if (shader->key.as_ngg)
5551 return "Vertex Shader as ESGS";
5552 else
5553 return "Vertex Shader as VS";
5554 case PIPE_SHADER_TESS_CTRL:
5555 return "Tessellation Control Shader";
5556 case PIPE_SHADER_TESS_EVAL:
5557 if (shader->key.as_es)
5558 return "Tessellation Evaluation Shader as ES";
5559 else if (shader->key.as_ngg)
5560 return "Tessellation Evaluation Shader as ESGS";
5561 else
5562 return "Tessellation Evaluation Shader as VS";
5563 case PIPE_SHADER_GEOMETRY:
5564 if (shader->is_gs_copy_shader)
5565 return "GS Copy Shader as VS";
5566 else
5567 return "Geometry Shader";
5568 case PIPE_SHADER_FRAGMENT:
5569 return "Pixel Shader";
5570 case PIPE_SHADER_COMPUTE:
5571 return "Compute Shader";
5572 default:
5573 return "Unknown Shader";
5574 }
5575 }
5576
5577 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
5578 struct pipe_debug_callback *debug,
5579 FILE *file, bool check_debug_option)
5580 {
5581 enum pipe_shader_type shader_type = shader->selector->type;
5582
5583 if (!check_debug_option ||
5584 si_can_dump_shader(sscreen, shader_type))
5585 si_dump_shader_key(shader, file);
5586
5587 if (!check_debug_option && shader->binary.llvm_ir_string) {
5588 if (shader->previous_stage &&
5589 shader->previous_stage->binary.llvm_ir_string) {
5590 fprintf(file, "\n%s - previous stage - LLVM IR:\n\n",
5591 si_get_shader_name(shader));
5592 fprintf(file, "%s\n", shader->previous_stage->binary.llvm_ir_string);
5593 }
5594
5595 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
5596 si_get_shader_name(shader));
5597 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
5598 }
5599
5600 if (!check_debug_option ||
5601 (si_can_dump_shader(sscreen, shader_type) &&
5602 !(sscreen->debug_flags & DBG(NO_ASM)))) {
5603 unsigned wave_size = si_get_shader_wave_size(shader);
5604
5605 fprintf(file, "\n%s:\n", si_get_shader_name(shader));
5606
5607 if (shader->prolog)
5608 si_shader_dump_disassembly(sscreen, &shader->prolog->binary,
5609 shader_type, wave_size, debug, "prolog", file);
5610 if (shader->previous_stage)
5611 si_shader_dump_disassembly(sscreen, &shader->previous_stage->binary,
5612 shader_type, wave_size, debug, "previous stage", file);
5613 if (shader->prolog2)
5614 si_shader_dump_disassembly(sscreen, &shader->prolog2->binary,
5615 shader_type, wave_size, debug, "prolog2", file);
5616
5617 si_shader_dump_disassembly(sscreen, &shader->binary, shader_type,
5618 wave_size, debug, "main", file);
5619
5620 if (shader->epilog)
5621 si_shader_dump_disassembly(sscreen, &shader->epilog->binary,
5622 shader_type, wave_size, debug, "epilog", file);
5623 fprintf(file, "\n");
5624 }
5625
5626 si_shader_dump_stats(sscreen, shader, file, check_debug_option);
5627 }
5628
5629 static int si_compile_llvm(struct si_screen *sscreen,
5630 struct si_shader_binary *binary,
5631 struct ac_shader_config *conf,
5632 struct ac_llvm_compiler *compiler,
5633 LLVMModuleRef mod,
5634 struct pipe_debug_callback *debug,
5635 enum pipe_shader_type shader_type,
5636 unsigned wave_size,
5637 const char *name,
5638 bool less_optimized)
5639 {
5640 unsigned count = p_atomic_inc_return(&sscreen->num_compilations);
5641
5642 if (si_can_dump_shader(sscreen, shader_type)) {
5643 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
5644
5645 if (!(sscreen->debug_flags & (DBG(NO_IR) | DBG(PREOPT_IR)))) {
5646 fprintf(stderr, "%s LLVM IR:\n\n", name);
5647 ac_dump_module(mod);
5648 fprintf(stderr, "\n");
5649 }
5650 }
5651
5652 if (sscreen->record_llvm_ir) {
5653 char *ir = LLVMPrintModuleToString(mod);
5654 binary->llvm_ir_string = strdup(ir);
5655 LLVMDisposeMessage(ir);
5656 }
5657
5658 if (!si_replace_shader(count, binary)) {
5659 unsigned r = si_llvm_compile(mod, binary, compiler, debug,
5660 less_optimized, wave_size);
5661 if (r)
5662 return r;
5663 }
5664
5665 struct ac_rtld_binary rtld;
5666 if (!ac_rtld_open(&rtld, (struct ac_rtld_open_info){
5667 .info = &sscreen->info,
5668 .shader_type = tgsi_processor_to_shader_stage(shader_type),
5669 .wave_size = wave_size,
5670 .num_parts = 1,
5671 .elf_ptrs = &binary->elf_buffer,
5672 .elf_sizes = &binary->elf_size }))
5673 return -1;
5674
5675 bool ok = ac_rtld_read_config(&rtld, conf);
5676 ac_rtld_close(&rtld);
5677 if (!ok)
5678 return -1;
5679
5680 /* Enable 64-bit and 16-bit denormals, because there is no performance
5681 * cost.
5682 *
5683 * If denormals are enabled, all floating-point output modifiers are
5684 * ignored.
5685 *
5686 * Don't enable denormals for 32-bit floats, because:
5687 * - Floating-point output modifiers would be ignored by the hw.
5688 * - Some opcodes don't support denormals, such as v_mad_f32. We would
5689 * have to stop using those.
5690 * - GFX6 & GFX7 would be very slow.
5691 */
5692 conf->float_mode |= V_00B028_FP_64_DENORMS;
5693
5694 return 0;
5695 }
5696
5697 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
5698 {
5699 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
5700 LLVMBuildRetVoid(ctx->ac.builder);
5701 else
5702 LLVMBuildRet(ctx->ac.builder, ret);
5703 }
5704
5705 /* Generate code for the hardware VS shader stage to go with a geometry shader */
5706 struct si_shader *
5707 si_generate_gs_copy_shader(struct si_screen *sscreen,
5708 struct ac_llvm_compiler *compiler,
5709 struct si_shader_selector *gs_selector,
5710 struct pipe_debug_callback *debug)
5711 {
5712 struct si_shader_context ctx;
5713 struct si_shader *shader;
5714 LLVMBuilderRef builder;
5715 struct si_shader_output_values outputs[SI_MAX_VS_OUTPUTS];
5716 struct tgsi_shader_info *gsinfo = &gs_selector->info;
5717 int i;
5718
5719
5720 shader = CALLOC_STRUCT(si_shader);
5721 if (!shader)
5722 return NULL;
5723
5724 /* We can leave the fence as permanently signaled because the GS copy
5725 * shader only becomes visible globally after it has been compiled. */
5726 util_queue_fence_init(&shader->ready);
5727
5728 shader->selector = gs_selector;
5729 shader->is_gs_copy_shader = true;
5730
5731 si_init_shader_ctx(&ctx, sscreen, compiler,
5732 si_get_wave_size(sscreen, PIPE_SHADER_VERTEX, false, false),
5733 false);
5734 ctx.shader = shader;
5735 ctx.type = PIPE_SHADER_VERTEX;
5736
5737 builder = ctx.ac.builder;
5738
5739 create_function(&ctx);
5740 preload_ring_buffers(&ctx);
5741
5742 LLVMValueRef voffset =
5743 LLVMBuildMul(ctx.ac.builder, ctx.abi.vertex_id,
5744 LLVMConstInt(ctx.i32, 4, 0), "");
5745
5746 /* Fetch the vertex stream ID.*/
5747 LLVMValueRef stream_id;
5748
5749 if (!sscreen->use_ngg_streamout && gs_selector->so.num_outputs)
5750 stream_id = si_unpack_param(&ctx, ctx.param_streamout_config, 24, 2);
5751 else
5752 stream_id = ctx.i32_0;
5753
5754 /* Fill in output information. */
5755 for (i = 0; i < gsinfo->num_outputs; ++i) {
5756 outputs[i].semantic_name = gsinfo->output_semantic_name[i];
5757 outputs[i].semantic_index = gsinfo->output_semantic_index[i];
5758
5759 for (int chan = 0; chan < 4; chan++) {
5760 outputs[i].vertex_stream[chan] =
5761 (gsinfo->output_streams[i] >> (2 * chan)) & 3;
5762 }
5763 }
5764
5765 LLVMBasicBlockRef end_bb;
5766 LLVMValueRef switch_inst;
5767
5768 end_bb = LLVMAppendBasicBlockInContext(ctx.ac.context, ctx.main_fn, "end");
5769 switch_inst = LLVMBuildSwitch(builder, stream_id, end_bb, 4);
5770
5771 for (int stream = 0; stream < 4; stream++) {
5772 LLVMBasicBlockRef bb;
5773 unsigned offset;
5774
5775 if (!gsinfo->num_stream_output_components[stream])
5776 continue;
5777
5778 if (stream > 0 && !gs_selector->so.num_outputs)
5779 continue;
5780
5781 bb = LLVMInsertBasicBlockInContext(ctx.ac.context, end_bb, "out");
5782 LLVMAddCase(switch_inst, LLVMConstInt(ctx.i32, stream, 0), bb);
5783 LLVMPositionBuilderAtEnd(builder, bb);
5784
5785 /* Fetch vertex data from GSVS ring */
5786 offset = 0;
5787 for (i = 0; i < gsinfo->num_outputs; ++i) {
5788 for (unsigned chan = 0; chan < 4; chan++) {
5789 if (!(gsinfo->output_usagemask[i] & (1 << chan)) ||
5790 outputs[i].vertex_stream[chan] != stream) {
5791 outputs[i].values[chan] = LLVMGetUndef(ctx.f32);
5792 continue;
5793 }
5794
5795 LLVMValueRef soffset = LLVMConstInt(ctx.i32,
5796 offset * gs_selector->gs_max_out_vertices * 16 * 4, 0);
5797 offset++;
5798
5799 outputs[i].values[chan] =
5800 ac_build_buffer_load(&ctx.ac,
5801 ctx.gsvs_ring[0], 1,
5802 ctx.i32_0, voffset,
5803 soffset, 0, ac_glc | ac_slc,
5804 true, false);
5805 }
5806 }
5807
5808 /* Streamout and exports. */
5809 if (!sscreen->use_ngg_streamout && gs_selector->so.num_outputs) {
5810 si_llvm_emit_streamout(&ctx, outputs,
5811 gsinfo->num_outputs,
5812 stream);
5813 }
5814
5815 if (stream == 0)
5816 si_llvm_export_vs(&ctx, outputs, gsinfo->num_outputs);
5817
5818 LLVMBuildBr(builder, end_bb);
5819 }
5820
5821 LLVMPositionBuilderAtEnd(builder, end_bb);
5822
5823 LLVMBuildRetVoid(ctx.ac.builder);
5824
5825 ctx.type = PIPE_SHADER_GEOMETRY; /* override for shader dumping */
5826 si_llvm_optimize_module(&ctx);
5827
5828 bool ok = false;
5829 if (si_compile_llvm(sscreen, &ctx.shader->binary,
5830 &ctx.shader->config, ctx.compiler,
5831 ctx.ac.module,
5832 debug, PIPE_SHADER_GEOMETRY, ctx.ac.wave_size,
5833 "GS Copy Shader", false) == 0) {
5834 if (si_can_dump_shader(sscreen, PIPE_SHADER_GEOMETRY))
5835 fprintf(stderr, "GS Copy Shader:\n");
5836 si_shader_dump(sscreen, ctx.shader, debug, stderr, true);
5837
5838 if (!ctx.shader->config.scratch_bytes_per_wave)
5839 ok = si_shader_binary_upload(sscreen, ctx.shader, 0);
5840 else
5841 ok = true;
5842 }
5843
5844 si_llvm_dispose(&ctx);
5845
5846 if (!ok) {
5847 FREE(shader);
5848 shader = NULL;
5849 } else {
5850 si_fix_resource_usage(sscreen, shader);
5851 }
5852 return shader;
5853 }
5854
5855 static void si_dump_shader_key_vs(const struct si_shader_key *key,
5856 const struct si_vs_prolog_bits *prolog,
5857 const char *prefix, FILE *f)
5858 {
5859 fprintf(f, " %s.instance_divisor_is_one = %u\n",
5860 prefix, prolog->instance_divisor_is_one);
5861 fprintf(f, " %s.instance_divisor_is_fetched = %u\n",
5862 prefix, prolog->instance_divisor_is_fetched);
5863 fprintf(f, " %s.unpack_instance_id_from_vertex_id = %u\n",
5864 prefix, prolog->unpack_instance_id_from_vertex_id);
5865 fprintf(f, " %s.ls_vgpr_fix = %u\n",
5866 prefix, prolog->ls_vgpr_fix);
5867
5868 fprintf(f, " mono.vs.fetch_opencode = %x\n", key->mono.vs_fetch_opencode);
5869 fprintf(f, " mono.vs.fix_fetch = {");
5870 for (int i = 0; i < SI_MAX_ATTRIBS; i++) {
5871 union si_vs_fix_fetch fix = key->mono.vs_fix_fetch[i];
5872 if (i)
5873 fprintf(f, ", ");
5874 if (!fix.bits)
5875 fprintf(f, "0");
5876 else
5877 fprintf(f, "%u.%u.%u.%u", fix.u.reverse, fix.u.log_size,
5878 fix.u.num_channels_m1, fix.u.format);
5879 }
5880 fprintf(f, "}\n");
5881 }
5882
5883 static void si_dump_shader_key(const struct si_shader *shader, FILE *f)
5884 {
5885 const struct si_shader_key *key = &shader->key;
5886 enum pipe_shader_type shader_type = shader->selector->type;
5887
5888 fprintf(f, "SHADER KEY\n");
5889
5890 switch (shader_type) {
5891 case PIPE_SHADER_VERTEX:
5892 si_dump_shader_key_vs(key, &key->part.vs.prolog,
5893 "part.vs.prolog", f);
5894 fprintf(f, " as_es = %u\n", key->as_es);
5895 fprintf(f, " as_ls = %u\n", key->as_ls);
5896 fprintf(f, " as_ngg = %u\n", key->as_ngg);
5897 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5898 key->mono.u.vs_export_prim_id);
5899 fprintf(f, " opt.vs_as_prim_discard_cs = %u\n",
5900 key->opt.vs_as_prim_discard_cs);
5901 fprintf(f, " opt.cs_prim_type = %s\n",
5902 tgsi_primitive_names[key->opt.cs_prim_type]);
5903 fprintf(f, " opt.cs_indexed = %u\n",
5904 key->opt.cs_indexed);
5905 fprintf(f, " opt.cs_instancing = %u\n",
5906 key->opt.cs_instancing);
5907 fprintf(f, " opt.cs_primitive_restart = %u\n",
5908 key->opt.cs_primitive_restart);
5909 fprintf(f, " opt.cs_provoking_vertex_first = %u\n",
5910 key->opt.cs_provoking_vertex_first);
5911 fprintf(f, " opt.cs_need_correct_orientation = %u\n",
5912 key->opt.cs_need_correct_orientation);
5913 fprintf(f, " opt.cs_cull_front = %u\n",
5914 key->opt.cs_cull_front);
5915 fprintf(f, " opt.cs_cull_back = %u\n",
5916 key->opt.cs_cull_back);
5917 fprintf(f, " opt.cs_cull_z = %u\n",
5918 key->opt.cs_cull_z);
5919 fprintf(f, " opt.cs_halfz_clip_space = %u\n",
5920 key->opt.cs_halfz_clip_space);
5921 break;
5922
5923 case PIPE_SHADER_TESS_CTRL:
5924 if (shader->selector->screen->info.chip_class >= GFX9) {
5925 si_dump_shader_key_vs(key, &key->part.tcs.ls_prolog,
5926 "part.tcs.ls_prolog", f);
5927 }
5928 fprintf(f, " part.tcs.epilog.prim_mode = %u\n", key->part.tcs.epilog.prim_mode);
5929 fprintf(f, " mono.u.ff_tcs_inputs_to_copy = 0x%"PRIx64"\n", key->mono.u.ff_tcs_inputs_to_copy);
5930 break;
5931
5932 case PIPE_SHADER_TESS_EVAL:
5933 fprintf(f, " as_es = %u\n", key->as_es);
5934 fprintf(f, " as_ngg = %u\n", key->as_ngg);
5935 fprintf(f, " mono.u.vs_export_prim_id = %u\n",
5936 key->mono.u.vs_export_prim_id);
5937 break;
5938
5939 case PIPE_SHADER_GEOMETRY:
5940 if (shader->is_gs_copy_shader)
5941 break;
5942
5943 if (shader->selector->screen->info.chip_class >= GFX9 &&
5944 key->part.gs.es->type == PIPE_SHADER_VERTEX) {
5945 si_dump_shader_key_vs(key, &key->part.gs.vs_prolog,
5946 "part.gs.vs_prolog", f);
5947 }
5948 fprintf(f, " part.gs.prolog.tri_strip_adj_fix = %u\n", key->part.gs.prolog.tri_strip_adj_fix);
5949 fprintf(f, " part.gs.prolog.gfx9_prev_is_vs = %u\n", key->part.gs.prolog.gfx9_prev_is_vs);
5950 fprintf(f, " as_ngg = %u\n", key->as_ngg);
5951 break;
5952
5953 case PIPE_SHADER_COMPUTE:
5954 break;
5955
5956 case PIPE_SHADER_FRAGMENT:
5957 fprintf(f, " part.ps.prolog.color_two_side = %u\n", key->part.ps.prolog.color_two_side);
5958 fprintf(f, " part.ps.prolog.flatshade_colors = %u\n", key->part.ps.prolog.flatshade_colors);
5959 fprintf(f, " part.ps.prolog.poly_stipple = %u\n", key->part.ps.prolog.poly_stipple);
5960 fprintf(f, " part.ps.prolog.force_persp_sample_interp = %u\n", key->part.ps.prolog.force_persp_sample_interp);
5961 fprintf(f, " part.ps.prolog.force_linear_sample_interp = %u\n", key->part.ps.prolog.force_linear_sample_interp);
5962 fprintf(f, " part.ps.prolog.force_persp_center_interp = %u\n", key->part.ps.prolog.force_persp_center_interp);
5963 fprintf(f, " part.ps.prolog.force_linear_center_interp = %u\n", key->part.ps.prolog.force_linear_center_interp);
5964 fprintf(f, " part.ps.prolog.bc_optimize_for_persp = %u\n", key->part.ps.prolog.bc_optimize_for_persp);
5965 fprintf(f, " part.ps.prolog.bc_optimize_for_linear = %u\n", key->part.ps.prolog.bc_optimize_for_linear);
5966 fprintf(f, " part.ps.prolog.samplemask_log_ps_iter = %u\n", key->part.ps.prolog.samplemask_log_ps_iter);
5967 fprintf(f, " part.ps.epilog.spi_shader_col_format = 0x%x\n", key->part.ps.epilog.spi_shader_col_format);
5968 fprintf(f, " part.ps.epilog.color_is_int8 = 0x%X\n", key->part.ps.epilog.color_is_int8);
5969 fprintf(f, " part.ps.epilog.color_is_int10 = 0x%X\n", key->part.ps.epilog.color_is_int10);
5970 fprintf(f, " part.ps.epilog.last_cbuf = %u\n", key->part.ps.epilog.last_cbuf);
5971 fprintf(f, " part.ps.epilog.alpha_func = %u\n", key->part.ps.epilog.alpha_func);
5972 fprintf(f, " part.ps.epilog.alpha_to_one = %u\n", key->part.ps.epilog.alpha_to_one);
5973 fprintf(f, " part.ps.epilog.poly_line_smoothing = %u\n", key->part.ps.epilog.poly_line_smoothing);
5974 fprintf(f, " part.ps.epilog.clamp_color = %u\n", key->part.ps.epilog.clamp_color);
5975 fprintf(f, " mono.u.ps.interpolate_at_sample_force_center = %u\n", key->mono.u.ps.interpolate_at_sample_force_center);
5976 fprintf(f, " mono.u.ps.fbfetch_msaa = %u\n", key->mono.u.ps.fbfetch_msaa);
5977 fprintf(f, " mono.u.ps.fbfetch_is_1D = %u\n", key->mono.u.ps.fbfetch_is_1D);
5978 fprintf(f, " mono.u.ps.fbfetch_layered = %u\n", key->mono.u.ps.fbfetch_layered);
5979 break;
5980
5981 default:
5982 assert(0);
5983 }
5984
5985 if ((shader_type == PIPE_SHADER_GEOMETRY ||
5986 shader_type == PIPE_SHADER_TESS_EVAL ||
5987 shader_type == PIPE_SHADER_VERTEX) &&
5988 !key->as_es && !key->as_ls) {
5989 fprintf(f, " opt.kill_outputs = 0x%"PRIx64"\n", key->opt.kill_outputs);
5990 fprintf(f, " opt.clip_disable = %u\n", key->opt.clip_disable);
5991 }
5992 }
5993
5994 static void si_init_shader_ctx(struct si_shader_context *ctx,
5995 struct si_screen *sscreen,
5996 struct ac_llvm_compiler *compiler,
5997 unsigned wave_size,
5998 bool nir)
5999 {
6000 struct lp_build_tgsi_context *bld_base;
6001
6002 si_llvm_context_init(ctx, sscreen, compiler, wave_size,
6003 nir ? 64 : wave_size);
6004
6005 bld_base = &ctx->bld_base;
6006 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6007
6008 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID].emit = build_interp_intrinsic;
6009 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE].emit = build_interp_intrinsic;
6010 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET].emit = build_interp_intrinsic;
6011
6012 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6013
6014 bld_base->op_actions[TGSI_OPCODE_CLOCK].emit = clock_emit;
6015
6016 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6017 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6018 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6019 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6020
6021 bld_base->op_actions[TGSI_OPCODE_VOTE_ALL].emit = vote_all_emit;
6022 bld_base->op_actions[TGSI_OPCODE_VOTE_ANY].emit = vote_any_emit;
6023 bld_base->op_actions[TGSI_OPCODE_VOTE_EQ].emit = vote_eq_emit;
6024 bld_base->op_actions[TGSI_OPCODE_BALLOT].emit = ballot_emit;
6025 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].intr_name = "llvm.amdgcn.readfirstlane";
6026 bld_base->op_actions[TGSI_OPCODE_READ_FIRST].emit = read_lane_emit;
6027 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].intr_name = "llvm.amdgcn.readlane";
6028 bld_base->op_actions[TGSI_OPCODE_READ_INVOC].emit = read_lane_emit;
6029
6030 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_tgsi_emit_vertex;
6031 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_tgsi_emit_primitive;
6032 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6033 }
6034
6035 static void si_optimize_vs_outputs(struct si_shader_context *ctx)
6036 {
6037 struct si_shader *shader = ctx->shader;
6038 struct tgsi_shader_info *info = &shader->selector->info;
6039
6040 if ((ctx->type != PIPE_SHADER_VERTEX &&
6041 ctx->type != PIPE_SHADER_TESS_EVAL) ||
6042 shader->key.as_ls ||
6043 shader->key.as_es)
6044 return;
6045
6046 ac_optimize_vs_outputs(&ctx->ac,
6047 ctx->main_fn,
6048 shader->info.vs_output_param_offset,
6049 info->num_outputs,
6050 &shader->info.nr_param_exports);
6051 }
6052
6053 static void si_init_exec_from_input(struct si_shader_context *ctx,
6054 unsigned param, unsigned bitoffset)
6055 {
6056 LLVMValueRef args[] = {
6057 LLVMGetParam(ctx->main_fn, param),
6058 LLVMConstInt(ctx->i32, bitoffset, 0),
6059 };
6060 ac_build_intrinsic(&ctx->ac,
6061 "llvm.amdgcn.init.exec.from.input",
6062 ctx->voidt, args, 2, AC_FUNC_ATTR_CONVERGENT);
6063 }
6064
6065 static bool si_vs_needs_prolog(const struct si_shader_selector *sel,
6066 const struct si_vs_prolog_bits *key)
6067 {
6068 /* VGPR initialization fixup for Vega10 and Raven is always done in the
6069 * VS prolog. */
6070 return sel->vs_needs_prolog || key->ls_vgpr_fix;
6071 }
6072
6073 static bool si_compile_tgsi_main(struct si_shader_context *ctx,
6074 struct nir_shader *nir, bool free_nir)
6075 {
6076 struct si_shader *shader = ctx->shader;
6077 struct si_shader_selector *sel = shader->selector;
6078 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
6079
6080 // TODO clean all this up!
6081 switch (ctx->type) {
6082 case PIPE_SHADER_VERTEX:
6083 ctx->load_input = declare_input_vs;
6084 if (shader->key.as_ls)
6085 ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
6086 else if (shader->key.as_es)
6087 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6088 else if (shader->key.opt.vs_as_prim_discard_cs)
6089 ctx->abi.emit_outputs = si_llvm_emit_prim_discard_cs_epilogue;
6090 else if (shader->key.as_ngg)
6091 ctx->abi.emit_outputs = gfx10_emit_ngg_epilogue;
6092 else
6093 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6094 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6095 ctx->abi.load_base_vertex = get_base_vertex;
6096 break;
6097 case PIPE_SHADER_TESS_CTRL:
6098 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6099 ctx->abi.load_tess_varyings = si_nir_load_tcs_varyings;
6100 ctx->abi.load_tess_level = si_load_tess_level;
6101 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6102 bld_base->emit_store = store_output_tcs;
6103 ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
6104 ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
6105 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6106 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6107 break;
6108 case PIPE_SHADER_TESS_EVAL:
6109 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6110 ctx->abi.load_tess_varyings = si_nir_load_input_tes;
6111 ctx->abi.load_tess_coord = si_load_tess_coord;
6112 ctx->abi.load_tess_level = si_load_tess_level;
6113 ctx->abi.load_patch_vertices_in = si_load_patch_vertices_in;
6114 if (shader->key.as_es)
6115 ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
6116 else if (shader->key.as_ngg)
6117 ctx->abi.emit_outputs = gfx10_emit_ngg_epilogue;
6118 else
6119 ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
6120 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6121 break;
6122 case PIPE_SHADER_GEOMETRY:
6123 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6124 ctx->abi.load_inputs = si_nir_load_input_gs;
6125 ctx->abi.emit_vertex = si_llvm_emit_vertex;
6126 ctx->abi.emit_primitive = si_llvm_emit_primitive;
6127 ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
6128 bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
6129 break;
6130 case PIPE_SHADER_FRAGMENT:
6131 ctx->load_input = declare_input_fs;
6132 ctx->abi.emit_outputs = si_llvm_return_fs_outputs;
6133 bld_base->emit_epilogue = si_tgsi_emit_epilogue;
6134 ctx->abi.load_sample_position = load_sample_position;
6135 ctx->abi.load_sample_mask_in = load_sample_mask_in;
6136 ctx->abi.emit_fbfetch = si_nir_emit_fbfetch;
6137 ctx->abi.emit_kill = si_llvm_emit_kill;
6138 break;
6139 case PIPE_SHADER_COMPUTE:
6140 ctx->abi.load_local_group_size = get_block_size;
6141 break;
6142 default:
6143 assert(!"Unsupported shader type");
6144 return false;
6145 }
6146
6147 ctx->abi.load_ubo = load_ubo;
6148 ctx->abi.load_ssbo = load_ssbo;
6149
6150 create_function(ctx);
6151 preload_ring_buffers(ctx);
6152
6153 if (ctx->type == PIPE_SHADER_TESS_CTRL &&
6154 sel->tcs_info.tessfactors_are_def_in_all_invocs) {
6155 for (unsigned i = 0; i < 6; i++) {
6156 ctx->invoc0_tess_factors[i] =
6157 ac_build_alloca_undef(&ctx->ac, ctx->i32, "");
6158 }
6159 }
6160
6161 if (ctx->type == PIPE_SHADER_GEOMETRY) {
6162 for (unsigned i = 0; i < 4; i++) {
6163 ctx->gs_next_vertex[i] =
6164 ac_build_alloca(&ctx->ac, ctx->i32, "");
6165 }
6166 if (shader->key.as_ngg) {
6167 for (unsigned i = 0; i < 4; ++i) {
6168 ctx->gs_curprim_verts[i] =
6169 ac_build_alloca(&ctx->ac, ctx->ac.i32, "");
6170 ctx->gs_generated_prims[i] =
6171 ac_build_alloca(&ctx->ac, ctx->ac.i32, "");
6172 }
6173
6174 unsigned scratch_size = 8;
6175 if (sel->so.num_outputs)
6176 scratch_size = 44;
6177
6178 LLVMTypeRef ai32 = LLVMArrayType(ctx->i32, scratch_size);
6179 ctx->gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx->ac.module,
6180 ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
6181 LLVMSetInitializer(ctx->gs_ngg_scratch, LLVMGetUndef(ai32));
6182 LLVMSetAlignment(ctx->gs_ngg_scratch, 4);
6183
6184 ctx->gs_ngg_emit = LLVMAddGlobalInAddressSpace(ctx->ac.module,
6185 LLVMArrayType(ctx->i32, 0), "ngg_emit", AC_ADDR_SPACE_LDS);
6186 LLVMSetLinkage(ctx->gs_ngg_emit, LLVMExternalLinkage);
6187 LLVMSetAlignment(ctx->gs_ngg_emit, 4);
6188 }
6189 }
6190
6191 if (ctx->type != PIPE_SHADER_GEOMETRY &&
6192 (shader->key.as_ngg && !shader->key.as_es)) {
6193 /* Unconditionally declare scratch space base for streamout and
6194 * vertex compaction. Whether space is actually allocated is
6195 * determined during linking / PM4 creation.
6196 *
6197 * Add an extra dword per vertex to ensure an odd stride, which
6198 * avoids bank conflicts for SoA accesses.
6199 */
6200 declare_esgs_ring(ctx);
6201
6202 /* This is really only needed when streamout and / or vertex
6203 * compaction is enabled.
6204 */
6205 LLVMTypeRef asi32 = LLVMArrayType(ctx->i32, 8);
6206 ctx->gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx->ac.module,
6207 asi32, "ngg_scratch", AC_ADDR_SPACE_LDS);
6208 LLVMSetInitializer(ctx->gs_ngg_scratch, LLVMGetUndef(asi32));
6209 LLVMSetAlignment(ctx->gs_ngg_scratch, 4);
6210 }
6211
6212 /* For GFX9 merged shaders:
6213 * - Set EXEC for the first shader. If the prolog is present, set
6214 * EXEC there instead.
6215 * - Add a barrier before the second shader.
6216 * - In the second shader, reset EXEC to ~0 and wrap the main part in
6217 * an if-statement. This is required for correctness in geometry
6218 * shaders, to ensure that empty GS waves do not send GS_EMIT and
6219 * GS_CUT messages.
6220 *
6221 * For monolithic merged shaders, the first shader is wrapped in an
6222 * if-block together with its prolog in si_build_wrapper_function.
6223 *
6224 * NGG vertex and tess eval shaders running as the last
6225 * vertex/geometry stage handle execution explicitly using
6226 * if-statements.
6227 */
6228 if (ctx->screen->info.chip_class >= GFX9) {
6229 if (!shader->is_monolithic &&
6230 sel->info.num_instructions > 1 && /* not empty shader */
6231 (shader->key.as_es || shader->key.as_ls) &&
6232 (ctx->type == PIPE_SHADER_TESS_EVAL ||
6233 (ctx->type == PIPE_SHADER_VERTEX &&
6234 !si_vs_needs_prolog(sel, &shader->key.part.vs.prolog)))) {
6235 si_init_exec_from_input(ctx,
6236 ctx->param_merged_wave_info, 0);
6237 } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6238 ctx->type == PIPE_SHADER_GEOMETRY ||
6239 (shader->key.as_ngg && !shader->key.as_es)) {
6240 LLVMValueRef num_threads;
6241 bool nested_barrier;
6242
6243 if (!shader->is_monolithic ||
6244 (ctx->type == PIPE_SHADER_TESS_EVAL &&
6245 (shader->key.as_ngg && !shader->key.as_es)))
6246 ac_init_exec_full_mask(&ctx->ac);
6247
6248 if (ctx->type == PIPE_SHADER_TESS_CTRL ||
6249 ctx->type == PIPE_SHADER_GEOMETRY) {
6250 if (ctx->type == PIPE_SHADER_GEOMETRY && shader->key.as_ngg) {
6251 gfx10_ngg_gs_emit_prologue(ctx);
6252 nested_barrier = false;
6253 } else {
6254 nested_barrier = true;
6255 }
6256
6257 /* Number of patches / primitives */
6258 num_threads = si_unpack_param(ctx, ctx->param_merged_wave_info, 8, 8);
6259 } else {
6260 /* Number of vertices */
6261 num_threads = si_unpack_param(ctx, ctx->param_merged_wave_info, 0, 8);
6262 nested_barrier = false;
6263 }
6264
6265 LLVMValueRef ena =
6266 LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
6267 ac_get_thread_id(&ctx->ac), num_threads, "");
6268
6269 ctx->merged_wrap_if_entry_block = LLVMGetInsertBlock(ctx->ac.builder);
6270 ctx->merged_wrap_if_label = 11500;
6271 ac_build_ifcc(&ctx->ac, ena, ctx->merged_wrap_if_label);
6272
6273 if (nested_barrier) {
6274 /* Execute a barrier before the second shader in
6275 * a merged shader.
6276 *
6277 * Execute the barrier inside the conditional block,
6278 * so that empty waves can jump directly to s_endpgm,
6279 * which will also signal the barrier.
6280 *
6281 * This is possible in gfx9, because an empty wave
6282 * for the second shader does not participate in
6283 * the epilogue. With NGG, empty waves may still
6284 * be required to export data (e.g. GS output vertices),
6285 * so we cannot let them exit early.
6286 *
6287 * If the shader is TCS and the TCS epilog is present
6288 * and contains a barrier, it will wait there and then
6289 * reach s_endpgm.
6290 */
6291 si_llvm_emit_barrier(NULL, bld_base, NULL);
6292 }
6293 }
6294 }
6295
6296 if (sel->force_correct_derivs_after_kill) {
6297 ctx->postponed_kill = ac_build_alloca_undef(&ctx->ac, ctx->i1, "");
6298 /* true = don't kill. */
6299 LLVMBuildStore(ctx->ac.builder, ctx->i1true,
6300 ctx->postponed_kill);
6301 }
6302
6303 if (sel->tokens) {
6304 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6305 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6306 return false;
6307 }
6308 } else {
6309 bool success = si_nir_build_llvm(ctx, nir);
6310 if (free_nir)
6311 ralloc_free(nir);
6312 if (!success) {
6313 fprintf(stderr, "Failed to translate shader from NIR to LLVM\n");
6314 return false;
6315 }
6316 }
6317
6318 si_llvm_build_ret(ctx, ctx->return_value);
6319 return true;
6320 }
6321
6322 /**
6323 * Compute the VS prolog key, which contains all the information needed to
6324 * build the VS prolog function, and set shader->info bits where needed.
6325 *
6326 * \param info Shader info of the vertex shader.
6327 * \param num_input_sgprs Number of input SGPRs for the vertex shader.
6328 * \param prolog_key Key of the VS prolog
6329 * \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
6330 * \param key Output shader part key.
6331 */
6332 static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
6333 unsigned num_input_sgprs,
6334 const struct si_vs_prolog_bits *prolog_key,
6335 struct si_shader *shader_out,
6336 union si_shader_part_key *key)
6337 {
6338 memset(key, 0, sizeof(*key));
6339 key->vs_prolog.states = *prolog_key;
6340 key->vs_prolog.num_input_sgprs = num_input_sgprs;
6341 key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
6342 key->vs_prolog.as_ls = shader_out->key.as_ls;
6343 key->vs_prolog.as_es = shader_out->key.as_es;
6344 key->vs_prolog.as_ngg = shader_out->key.as_ngg;
6345
6346 if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
6347 key->vs_prolog.as_ls = 1;
6348 key->vs_prolog.num_merged_next_stage_vgprs = 2;
6349 } else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
6350 key->vs_prolog.as_es = 1;
6351 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6352 } else if (shader_out->key.as_ngg) {
6353 key->vs_prolog.num_merged_next_stage_vgprs = 5;
6354 }
6355
6356 /* Enable loading the InstanceID VGPR. */
6357 uint16_t input_mask = u_bit_consecutive(0, info->num_inputs);
6358
6359 if ((key->vs_prolog.states.instance_divisor_is_one |
6360 key->vs_prolog.states.instance_divisor_is_fetched) & input_mask)
6361 shader_out->info.uses_instanceid = true;
6362 }
6363
6364 /**
6365 * Compute the PS prolog key, which contains all the information needed to
6366 * build the PS prolog function, and set related bits in shader->config.
6367 */
6368 static void si_get_ps_prolog_key(struct si_shader *shader,
6369 union si_shader_part_key *key,
6370 bool separate_prolog)
6371 {
6372 struct tgsi_shader_info *info = &shader->selector->info;
6373
6374 memset(key, 0, sizeof(*key));
6375 key->ps_prolog.states = shader->key.part.ps.prolog;
6376 key->ps_prolog.colors_read = info->colors_read;
6377 key->ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
6378 key->ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
6379 key->ps_prolog.wqm = info->uses_derivatives &&
6380 (key->ps_prolog.colors_read ||
6381 key->ps_prolog.states.force_persp_sample_interp ||
6382 key->ps_prolog.states.force_linear_sample_interp ||
6383 key->ps_prolog.states.force_persp_center_interp ||
6384 key->ps_prolog.states.force_linear_center_interp ||
6385 key->ps_prolog.states.bc_optimize_for_persp ||
6386 key->ps_prolog.states.bc_optimize_for_linear);
6387 key->ps_prolog.ancillary_vgpr_index = shader->info.ancillary_vgpr_index;
6388
6389 if (info->colors_read) {
6390 unsigned *color = shader->selector->color_attr_index;
6391
6392 if (shader->key.part.ps.prolog.color_two_side) {
6393 /* BCOLORs are stored after the last input. */
6394 key->ps_prolog.num_interp_inputs = info->num_inputs;
6395 key->ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
6396 if (separate_prolog)
6397 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
6398 }
6399
6400 for (unsigned i = 0; i < 2; i++) {
6401 unsigned interp = info->input_interpolate[color[i]];
6402 unsigned location = info->input_interpolate_loc[color[i]];
6403
6404 if (!(info->colors_read & (0xf << i*4)))
6405 continue;
6406
6407 key->ps_prolog.color_attr_index[i] = color[i];
6408
6409 if (shader->key.part.ps.prolog.flatshade_colors &&
6410 interp == TGSI_INTERPOLATE_COLOR)
6411 interp = TGSI_INTERPOLATE_CONSTANT;
6412
6413 switch (interp) {
6414 case TGSI_INTERPOLATE_CONSTANT:
6415 key->ps_prolog.color_interp_vgpr_index[i] = -1;
6416 break;
6417 case TGSI_INTERPOLATE_PERSPECTIVE:
6418 case TGSI_INTERPOLATE_COLOR:
6419 /* Force the interpolation location for colors here. */
6420 if (shader->key.part.ps.prolog.force_persp_sample_interp)
6421 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6422 if (shader->key.part.ps.prolog.force_persp_center_interp)
6423 location = TGSI_INTERPOLATE_LOC_CENTER;
6424
6425 switch (location) {
6426 case TGSI_INTERPOLATE_LOC_SAMPLE:
6427 key->ps_prolog.color_interp_vgpr_index[i] = 0;
6428 if (separate_prolog) {
6429 shader->config.spi_ps_input_ena |=
6430 S_0286CC_PERSP_SAMPLE_ENA(1);
6431 }
6432 break;
6433 case TGSI_INTERPOLATE_LOC_CENTER:
6434 key->ps_prolog.color_interp_vgpr_index[i] = 2;
6435 if (separate_prolog) {
6436 shader->config.spi_ps_input_ena |=
6437 S_0286CC_PERSP_CENTER_ENA(1);
6438 }
6439 break;
6440 case TGSI_INTERPOLATE_LOC_CENTROID:
6441 key->ps_prolog.color_interp_vgpr_index[i] = 4;
6442 if (separate_prolog) {
6443 shader->config.spi_ps_input_ena |=
6444 S_0286CC_PERSP_CENTROID_ENA(1);
6445 }
6446 break;
6447 default:
6448 assert(0);
6449 }
6450 break;
6451 case TGSI_INTERPOLATE_LINEAR:
6452 /* Force the interpolation location for colors here. */
6453 if (shader->key.part.ps.prolog.force_linear_sample_interp)
6454 location = TGSI_INTERPOLATE_LOC_SAMPLE;
6455 if (shader->key.part.ps.prolog.force_linear_center_interp)
6456 location = TGSI_INTERPOLATE_LOC_CENTER;
6457
6458 /* The VGPR assignment for non-monolithic shaders
6459 * works because InitialPSInputAddr is set on the
6460 * main shader and PERSP_PULL_MODEL is never used.
6461 */
6462 switch (location) {
6463 case TGSI_INTERPOLATE_LOC_SAMPLE:
6464 key->ps_prolog.color_interp_vgpr_index[i] =
6465 separate_prolog ? 6 : 9;
6466 if (separate_prolog) {
6467 shader->config.spi_ps_input_ena |=
6468 S_0286CC_LINEAR_SAMPLE_ENA(1);
6469 }
6470 break;
6471 case TGSI_INTERPOLATE_LOC_CENTER:
6472 key->ps_prolog.color_interp_vgpr_index[i] =
6473 separate_prolog ? 8 : 11;
6474 if (separate_prolog) {
6475 shader->config.spi_ps_input_ena |=
6476 S_0286CC_LINEAR_CENTER_ENA(1);
6477 }
6478 break;
6479 case TGSI_INTERPOLATE_LOC_CENTROID:
6480 key->ps_prolog.color_interp_vgpr_index[i] =
6481 separate_prolog ? 10 : 13;
6482 if (separate_prolog) {
6483 shader->config.spi_ps_input_ena |=
6484 S_0286CC_LINEAR_CENTROID_ENA(1);
6485 }
6486 break;
6487 default:
6488 assert(0);
6489 }
6490 break;
6491 default:
6492 assert(0);
6493 }
6494 }
6495 }
6496 }
6497
6498 /**
6499 * Check whether a PS prolog is required based on the key.
6500 */
6501 static bool si_need_ps_prolog(const union si_shader_part_key *key)
6502 {
6503 return key->ps_prolog.colors_read ||
6504 key->ps_prolog.states.force_persp_sample_interp ||
6505 key->ps_prolog.states.force_linear_sample_interp ||
6506 key->ps_prolog.states.force_persp_center_interp ||
6507 key->ps_prolog.states.force_linear_center_interp ||
6508 key->ps_prolog.states.bc_optimize_for_persp ||
6509 key->ps_prolog.states.bc_optimize_for_linear ||
6510 key->ps_prolog.states.poly_stipple ||
6511 key->ps_prolog.states.samplemask_log_ps_iter;
6512 }
6513
6514 /**
6515 * Compute the PS epilog key, which contains all the information needed to
6516 * build the PS epilog function.
6517 */
6518 static void si_get_ps_epilog_key(struct si_shader *shader,
6519 union si_shader_part_key *key)
6520 {
6521 struct tgsi_shader_info *info = &shader->selector->info;
6522 memset(key, 0, sizeof(*key));
6523 key->ps_epilog.colors_written = info->colors_written;
6524 key->ps_epilog.writes_z = info->writes_z;
6525 key->ps_epilog.writes_stencil = info->writes_stencil;
6526 key->ps_epilog.writes_samplemask = info->writes_samplemask;
6527 key->ps_epilog.states = shader->key.part.ps.epilog;
6528 }
6529
6530 /**
6531 * Build the GS prolog function. Rotate the input vertices for triangle strips
6532 * with adjacency.
6533 */
6534 static void si_build_gs_prolog_function(struct si_shader_context *ctx,
6535 union si_shader_part_key *key)
6536 {
6537 unsigned num_sgprs, num_vgprs;
6538 struct si_function_info fninfo;
6539 LLVMBuilderRef builder = ctx->ac.builder;
6540 LLVMTypeRef returns[48];
6541 LLVMValueRef func, ret;
6542
6543 si_init_function_info(&fninfo);
6544
6545 if (ctx->screen->info.chip_class >= GFX9) {
6546 if (key->gs_prolog.states.gfx9_prev_is_vs)
6547 num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
6548 else
6549 num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
6550 num_vgprs = 5; /* ES inputs are not needed by GS */
6551 } else {
6552 num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
6553 num_vgprs = 8;
6554 }
6555
6556 for (unsigned i = 0; i < num_sgprs; ++i) {
6557 add_arg(&fninfo, ARG_SGPR, ctx->i32);
6558 returns[i] = ctx->i32;
6559 }
6560
6561 for (unsigned i = 0; i < num_vgprs; ++i) {
6562 add_arg(&fninfo, ARG_VGPR, ctx->i32);
6563 returns[num_sgprs + i] = ctx->f32;
6564 }
6565
6566 /* Create the function. */
6567 si_create_function(ctx, "gs_prolog", returns, num_sgprs + num_vgprs,
6568 &fninfo, 0);
6569 func = ctx->main_fn;
6570
6571 /* Set the full EXEC mask for the prolog, because we are only fiddling
6572 * with registers here. The main shader part will set the correct EXEC
6573 * mask.
6574 */
6575 if (ctx->screen->info.chip_class >= GFX9 && !key->gs_prolog.is_monolithic)
6576 ac_init_exec_full_mask(&ctx->ac);
6577
6578 /* Copy inputs to outputs. This should be no-op, as the registers match,
6579 * but it will prevent the compiler from overwriting them unintentionally.
6580 */
6581 ret = ctx->return_value;
6582 for (unsigned i = 0; i < num_sgprs; i++) {
6583 LLVMValueRef p = LLVMGetParam(func, i);
6584 ret = LLVMBuildInsertValue(builder, ret, p, i, "");
6585 }
6586 for (unsigned i = 0; i < num_vgprs; i++) {
6587 LLVMValueRef p = LLVMGetParam(func, num_sgprs + i);
6588 p = ac_to_float(&ctx->ac, p);
6589 ret = LLVMBuildInsertValue(builder, ret, p, num_sgprs + i, "");
6590 }
6591
6592 if (key->gs_prolog.states.tri_strip_adj_fix) {
6593 /* Remap the input vertices for every other primitive. */
6594 const unsigned gfx6_vtx_params[6] = {
6595 num_sgprs,
6596 num_sgprs + 1,
6597 num_sgprs + 3,
6598 num_sgprs + 4,
6599 num_sgprs + 5,
6600 num_sgprs + 6
6601 };
6602 const unsigned gfx9_vtx_params[3] = {
6603 num_sgprs,
6604 num_sgprs + 1,
6605 num_sgprs + 4,
6606 };
6607 LLVMValueRef vtx_in[6], vtx_out[6];
6608 LLVMValueRef prim_id, rotate;
6609
6610 if (ctx->screen->info.chip_class >= GFX9) {
6611 for (unsigned i = 0; i < 3; i++) {
6612 vtx_in[i*2] = si_unpack_param(ctx, gfx9_vtx_params[i], 0, 16);
6613 vtx_in[i*2+1] = si_unpack_param(ctx, gfx9_vtx_params[i], 16, 16);
6614 }
6615 } else {
6616 for (unsigned i = 0; i < 6; i++)
6617 vtx_in[i] = LLVMGetParam(func, gfx6_vtx_params[i]);
6618 }
6619
6620 prim_id = LLVMGetParam(func, num_sgprs + 2);
6621 rotate = LLVMBuildTrunc(builder, prim_id, ctx->i1, "");
6622
6623 for (unsigned i = 0; i < 6; ++i) {
6624 LLVMValueRef base, rotated;
6625 base = vtx_in[i];
6626 rotated = vtx_in[(i + 4) % 6];
6627 vtx_out[i] = LLVMBuildSelect(builder, rotate, rotated, base, "");
6628 }
6629
6630 if (ctx->screen->info.chip_class >= GFX9) {
6631 for (unsigned i = 0; i < 3; i++) {
6632 LLVMValueRef hi, out;
6633
6634 hi = LLVMBuildShl(builder, vtx_out[i*2+1],
6635 LLVMConstInt(ctx->i32, 16, 0), "");
6636 out = LLVMBuildOr(builder, vtx_out[i*2], hi, "");
6637 out = ac_to_float(&ctx->ac, out);
6638 ret = LLVMBuildInsertValue(builder, ret, out,
6639 gfx9_vtx_params[i], "");
6640 }
6641 } else {
6642 for (unsigned i = 0; i < 6; i++) {
6643 LLVMValueRef out;
6644
6645 out = ac_to_float(&ctx->ac, vtx_out[i]);
6646 ret = LLVMBuildInsertValue(builder, ret, out,
6647 gfx6_vtx_params[i], "");
6648 }
6649 }
6650 }
6651
6652 LLVMBuildRet(builder, ret);
6653 }
6654
6655 /**
6656 * Given a list of shader part functions, build a wrapper function that
6657 * runs them in sequence to form a monolithic shader.
6658 */
6659 static void si_build_wrapper_function(struct si_shader_context *ctx,
6660 LLVMValueRef *parts,
6661 unsigned num_parts,
6662 unsigned main_part,
6663 unsigned next_shader_first_part)
6664 {
6665 LLVMBuilderRef builder = ctx->ac.builder;
6666 /* PS epilog has one arg per color component; gfx9 merged shader
6667 * prologs need to forward 32 user SGPRs.
6668 */
6669 struct si_function_info fninfo;
6670 LLVMValueRef initial[64], out[64];
6671 LLVMTypeRef function_type;
6672 unsigned num_first_params;
6673 unsigned num_out, initial_num_out;
6674 ASSERTED unsigned num_out_sgpr; /* used in debug checks */
6675 ASSERTED unsigned initial_num_out_sgpr; /* used in debug checks */
6676 unsigned num_sgprs, num_vgprs;
6677 unsigned gprs;
6678
6679 si_init_function_info(&fninfo);
6680
6681 for (unsigned i = 0; i < num_parts; ++i) {
6682 ac_add_function_attr(ctx->ac.context, parts[i], -1,
6683 AC_FUNC_ATTR_ALWAYSINLINE);
6684 LLVMSetLinkage(parts[i], LLVMPrivateLinkage);
6685 }
6686
6687 /* The parameters of the wrapper function correspond to those of the
6688 * first part in terms of SGPRs and VGPRs, but we use the types of the
6689 * main part to get the right types. This is relevant for the
6690 * dereferenceable attribute on descriptor table pointers.
6691 */
6692 num_sgprs = 0;
6693 num_vgprs = 0;
6694
6695 function_type = LLVMGetElementType(LLVMTypeOf(parts[0]));
6696 num_first_params = LLVMCountParamTypes(function_type);
6697
6698 for (unsigned i = 0; i < num_first_params; ++i) {
6699 LLVMValueRef param = LLVMGetParam(parts[0], i);
6700
6701 if (ac_is_sgpr_param(param)) {
6702 assert(num_vgprs == 0);
6703 num_sgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6704 } else {
6705 num_vgprs += ac_get_type_size(LLVMTypeOf(param)) / 4;
6706 }
6707 }
6708
6709 gprs = 0;
6710 while (gprs < num_sgprs + num_vgprs) {
6711 LLVMValueRef param = LLVMGetParam(parts[main_part], fninfo.num_params);
6712 LLVMTypeRef type = LLVMTypeOf(param);
6713 unsigned size = ac_get_type_size(type) / 4;
6714
6715 add_arg(&fninfo, gprs < num_sgprs ? ARG_SGPR : ARG_VGPR, type);
6716
6717 assert(ac_is_sgpr_param(param) == (gprs < num_sgprs));
6718 assert(gprs + size <= num_sgprs + num_vgprs &&
6719 (gprs >= num_sgprs || gprs + size <= num_sgprs));
6720
6721 gprs += size;
6722 }
6723
6724 /* Prepare the return type. */
6725 unsigned num_returns = 0;
6726 LLVMTypeRef returns[32], last_func_type, return_type;
6727
6728 last_func_type = LLVMGetElementType(LLVMTypeOf(parts[num_parts - 1]));
6729 return_type = LLVMGetReturnType(last_func_type);
6730
6731 switch (LLVMGetTypeKind(return_type)) {
6732 case LLVMStructTypeKind:
6733 num_returns = LLVMCountStructElementTypes(return_type);
6734 assert(num_returns <= ARRAY_SIZE(returns));
6735 LLVMGetStructElementTypes(return_type, returns);
6736 break;
6737 case LLVMVoidTypeKind:
6738 break;
6739 default:
6740 unreachable("unexpected type");
6741 }
6742
6743 si_create_function(ctx, "wrapper", returns, num_returns, &fninfo,
6744 si_get_max_workgroup_size(ctx->shader));
6745
6746 if (is_merged_shader(ctx))
6747 ac_init_exec_full_mask(&ctx->ac);
6748
6749 /* Record the arguments of the function as if they were an output of
6750 * a previous part.
6751 */
6752 num_out = 0;
6753 num_out_sgpr = 0;
6754
6755 for (unsigned i = 0; i < fninfo.num_params; ++i) {
6756 LLVMValueRef param = LLVMGetParam(ctx->main_fn, i);
6757 LLVMTypeRef param_type = LLVMTypeOf(param);
6758 LLVMTypeRef out_type = i < fninfo.num_sgpr_params ? ctx->i32 : ctx->f32;
6759 unsigned size = ac_get_type_size(param_type) / 4;
6760
6761 if (size == 1) {
6762 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6763 param = LLVMBuildPtrToInt(builder, param, ctx->i32, "");
6764 param_type = ctx->i32;
6765 }
6766
6767 if (param_type != out_type)
6768 param = LLVMBuildBitCast(builder, param, out_type, "");
6769 out[num_out++] = param;
6770 } else {
6771 LLVMTypeRef vector_type = LLVMVectorType(out_type, size);
6772
6773 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6774 param = LLVMBuildPtrToInt(builder, param, ctx->i64, "");
6775 param_type = ctx->i64;
6776 }
6777
6778 if (param_type != vector_type)
6779 param = LLVMBuildBitCast(builder, param, vector_type, "");
6780
6781 for (unsigned j = 0; j < size; ++j)
6782 out[num_out++] = LLVMBuildExtractElement(
6783 builder, param, LLVMConstInt(ctx->i32, j, 0), "");
6784 }
6785
6786 if (i < fninfo.num_sgpr_params)
6787 num_out_sgpr = num_out;
6788 }
6789
6790 memcpy(initial, out, sizeof(out));
6791 initial_num_out = num_out;
6792 initial_num_out_sgpr = num_out_sgpr;
6793
6794 /* Now chain the parts. */
6795 LLVMValueRef ret = NULL;
6796 for (unsigned part = 0; part < num_parts; ++part) {
6797 LLVMValueRef in[48];
6798 LLVMTypeRef ret_type;
6799 unsigned out_idx = 0;
6800 unsigned num_params = LLVMCountParams(parts[part]);
6801
6802 /* Merged shaders are executed conditionally depending
6803 * on the number of enabled threads passed in the input SGPRs. */
6804 if (is_multi_part_shader(ctx) && part == 0) {
6805 LLVMValueRef ena, count = initial[3];
6806
6807 count = LLVMBuildAnd(builder, count,
6808 LLVMConstInt(ctx->i32, 0x7f, 0), "");
6809 ena = LLVMBuildICmp(builder, LLVMIntULT,
6810 ac_get_thread_id(&ctx->ac), count, "");
6811 ac_build_ifcc(&ctx->ac, ena, 6506);
6812 }
6813
6814 /* Derive arguments for the next part from outputs of the
6815 * previous one.
6816 */
6817 for (unsigned param_idx = 0; param_idx < num_params; ++param_idx) {
6818 LLVMValueRef param;
6819 LLVMTypeRef param_type;
6820 bool is_sgpr;
6821 unsigned param_size;
6822 LLVMValueRef arg = NULL;
6823
6824 param = LLVMGetParam(parts[part], param_idx);
6825 param_type = LLVMTypeOf(param);
6826 param_size = ac_get_type_size(param_type) / 4;
6827 is_sgpr = ac_is_sgpr_param(param);
6828
6829 if (is_sgpr) {
6830 ac_add_function_attr(ctx->ac.context, parts[part],
6831 param_idx + 1, AC_FUNC_ATTR_INREG);
6832 } else if (out_idx < num_out_sgpr) {
6833 /* Skip returned SGPRs the current part doesn't
6834 * declare on the input. */
6835 out_idx = num_out_sgpr;
6836 }
6837
6838 assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr : num_out));
6839
6840 if (param_size == 1)
6841 arg = out[out_idx];
6842 else
6843 arg = ac_build_gather_values(&ctx->ac, &out[out_idx], param_size);
6844
6845 if (LLVMTypeOf(arg) != param_type) {
6846 if (LLVMGetTypeKind(param_type) == LLVMPointerTypeKind) {
6847 if (LLVMGetPointerAddressSpace(param_type) ==
6848 AC_ADDR_SPACE_CONST_32BIT) {
6849 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
6850 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6851 } else {
6852 arg = LLVMBuildBitCast(builder, arg, ctx->i64, "");
6853 arg = LLVMBuildIntToPtr(builder, arg, param_type, "");
6854 }
6855 } else {
6856 arg = LLVMBuildBitCast(builder, arg, param_type, "");
6857 }
6858 }
6859
6860 in[param_idx] = arg;
6861 out_idx += param_size;
6862 }
6863
6864 ret = ac_build_call(&ctx->ac, parts[part], in, num_params);
6865
6866 if (is_multi_part_shader(ctx) &&
6867 part + 1 == next_shader_first_part) {
6868 ac_build_endif(&ctx->ac, 6506);
6869
6870 /* The second half of the merged shader should use
6871 * the inputs from the toplevel (wrapper) function,
6872 * not the return value from the last call.
6873 *
6874 * That's because the last call was executed condi-
6875 * tionally, so we can't consume it in the main
6876 * block.
6877 */
6878 memcpy(out, initial, sizeof(initial));
6879 num_out = initial_num_out;
6880 num_out_sgpr = initial_num_out_sgpr;
6881 continue;
6882 }
6883
6884 /* Extract the returned GPRs. */
6885 ret_type = LLVMTypeOf(ret);
6886 num_out = 0;
6887 num_out_sgpr = 0;
6888
6889 if (LLVMGetTypeKind(ret_type) != LLVMVoidTypeKind) {
6890 assert(LLVMGetTypeKind(ret_type) == LLVMStructTypeKind);
6891
6892 unsigned ret_size = LLVMCountStructElementTypes(ret_type);
6893
6894 for (unsigned i = 0; i < ret_size; ++i) {
6895 LLVMValueRef val =
6896 LLVMBuildExtractValue(builder, ret, i, "");
6897
6898 assert(num_out < ARRAY_SIZE(out));
6899 out[num_out++] = val;
6900
6901 if (LLVMTypeOf(val) == ctx->i32) {
6902 assert(num_out_sgpr + 1 == num_out);
6903 num_out_sgpr = num_out;
6904 }
6905 }
6906 }
6907 }
6908
6909 /* Return the value from the last part. */
6910 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6911 LLVMBuildRetVoid(builder);
6912 else
6913 LLVMBuildRet(builder, ret);
6914 }
6915
6916 static bool si_should_optimize_less(struct ac_llvm_compiler *compiler,
6917 struct si_shader_selector *sel)
6918 {
6919 if (!compiler->low_opt_passes)
6920 return false;
6921
6922 /* Assume a slow CPU. */
6923 assert(!sel->screen->info.has_dedicated_vram &&
6924 sel->screen->info.chip_class <= GFX8);
6925
6926 /* For a crazy dEQP test containing 2597 memory opcodes, mostly
6927 * buffer stores. */
6928 return sel->type == PIPE_SHADER_COMPUTE &&
6929 sel->info.num_memory_instructions > 1000;
6930 }
6931
6932 static struct nir_shader *get_nir_shader(struct si_shader_selector *sel,
6933 bool *free_nir)
6934 {
6935 *free_nir = false;
6936
6937 if (sel->nir) {
6938 return sel->nir;
6939 } else if (sel->nir_binary) {
6940 struct pipe_screen *screen = &sel->screen->b;
6941 const void *options =
6942 screen->get_compiler_options(screen, PIPE_SHADER_IR_NIR,
6943 sel->type);
6944
6945 struct blob_reader blob_reader;
6946 blob_reader_init(&blob_reader, sel->nir_binary, sel->nir_size);
6947 *free_nir = true;
6948 return nir_deserialize(NULL, options, &blob_reader);
6949 }
6950 return NULL;
6951 }
6952
6953 int si_compile_tgsi_shader(struct si_screen *sscreen,
6954 struct ac_llvm_compiler *compiler,
6955 struct si_shader *shader,
6956 struct pipe_debug_callback *debug)
6957 {
6958 struct si_shader_selector *sel = shader->selector;
6959 struct si_shader_context ctx;
6960 bool free_nir;
6961 struct nir_shader *nir = get_nir_shader(sel, &free_nir);
6962 int r = -1;
6963
6964 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6965 * conversion fails. */
6966 if (si_can_dump_shader(sscreen, sel->type) &&
6967 !(sscreen->debug_flags & DBG(NO_TGSI))) {
6968 if (sel->tokens)
6969 tgsi_dump(sel->tokens, 0);
6970 else
6971 nir_print_shader(nir, stderr);
6972 si_dump_streamout(&sel->so);
6973 }
6974
6975 si_init_shader_ctx(&ctx, sscreen, compiler, si_get_shader_wave_size(shader),
6976 nir != NULL);
6977 si_llvm_context_set_ir(&ctx, shader, nir);
6978
6979 memset(shader->info.vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
6980 sizeof(shader->info.vs_output_param_offset));
6981
6982 shader->info.uses_instanceid = sel->info.uses_instanceid;
6983
6984 if (!si_compile_tgsi_main(&ctx, nir, free_nir)) {
6985 si_llvm_dispose(&ctx);
6986 return -1;
6987 }
6988
6989 if (shader->is_monolithic && ctx.type == PIPE_SHADER_VERTEX) {
6990 LLVMValueRef parts[2];
6991 bool need_prolog = sel->vs_needs_prolog;
6992
6993 parts[1] = ctx.main_fn;
6994
6995 if (need_prolog) {
6996 union si_shader_part_key prolog_key;
6997 si_get_vs_prolog_key(&sel->info,
6998 shader->info.num_input_sgprs,
6999 &shader->key.part.vs.prolog,
7000 shader, &prolog_key);
7001 si_build_vs_prolog_function(&ctx, &prolog_key);
7002 parts[0] = ctx.main_fn;
7003 }
7004
7005 si_build_wrapper_function(&ctx, parts + !need_prolog,
7006 1 + need_prolog, need_prolog, 0);
7007
7008 if (ctx.shader->key.opt.vs_as_prim_discard_cs)
7009 si_build_prim_discard_compute_shader(&ctx);
7010 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_TESS_CTRL) {
7011 if (sscreen->info.chip_class >= GFX9) {
7012 struct si_shader_selector *ls = shader->key.part.tcs.ls;
7013 LLVMValueRef parts[4];
7014 bool vs_needs_prolog =
7015 si_vs_needs_prolog(ls, &shader->key.part.tcs.ls_prolog);
7016
7017 /* TCS main part */
7018 parts[2] = ctx.main_fn;
7019
7020 /* TCS epilog */
7021 union si_shader_part_key tcs_epilog_key;
7022 memset(&tcs_epilog_key, 0, sizeof(tcs_epilog_key));
7023 tcs_epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7024 si_build_tcs_epilog_function(&ctx, &tcs_epilog_key);
7025 parts[3] = ctx.main_fn;
7026
7027 /* VS as LS main part */
7028 nir = get_nir_shader(ls, &free_nir);
7029 struct si_shader shader_ls = {};
7030 shader_ls.selector = ls;
7031 shader_ls.key.as_ls = 1;
7032 shader_ls.key.mono = shader->key.mono;
7033 shader_ls.key.opt = shader->key.opt;
7034 shader_ls.is_monolithic = true;
7035 si_llvm_context_set_ir(&ctx, &shader_ls, nir);
7036
7037 if (!si_compile_tgsi_main(&ctx, nir, free_nir)) {
7038 si_llvm_dispose(&ctx);
7039 return -1;
7040 }
7041 shader->info.uses_instanceid |= ls->info.uses_instanceid;
7042 parts[1] = ctx.main_fn;
7043
7044 /* LS prolog */
7045 if (vs_needs_prolog) {
7046 union si_shader_part_key vs_prolog_key;
7047 si_get_vs_prolog_key(&ls->info,
7048 shader_ls.info.num_input_sgprs,
7049 &shader->key.part.tcs.ls_prolog,
7050 shader, &vs_prolog_key);
7051 vs_prolog_key.vs_prolog.is_monolithic = true;
7052 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
7053 parts[0] = ctx.main_fn;
7054 }
7055
7056 /* Reset the shader context. */
7057 ctx.shader = shader;
7058 ctx.type = PIPE_SHADER_TESS_CTRL;
7059
7060 si_build_wrapper_function(&ctx,
7061 parts + !vs_needs_prolog,
7062 4 - !vs_needs_prolog, vs_needs_prolog,
7063 vs_needs_prolog ? 2 : 1);
7064 } else {
7065 LLVMValueRef parts[2];
7066 union si_shader_part_key epilog_key;
7067
7068 parts[0] = ctx.main_fn;
7069
7070 memset(&epilog_key, 0, sizeof(epilog_key));
7071 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7072 si_build_tcs_epilog_function(&ctx, &epilog_key);
7073 parts[1] = ctx.main_fn;
7074
7075 si_build_wrapper_function(&ctx, parts, 2, 0, 0);
7076 }
7077 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_GEOMETRY) {
7078 if (ctx.screen->info.chip_class >= GFX9) {
7079 struct si_shader_selector *es = shader->key.part.gs.es;
7080 LLVMValueRef es_prolog = NULL;
7081 LLVMValueRef es_main = NULL;
7082 LLVMValueRef gs_prolog = NULL;
7083 LLVMValueRef gs_main = ctx.main_fn;
7084
7085 /* GS prolog */
7086 union si_shader_part_key gs_prolog_key;
7087 memset(&gs_prolog_key, 0, sizeof(gs_prolog_key));
7088 gs_prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7089 gs_prolog_key.gs_prolog.is_monolithic = true;
7090 gs_prolog_key.gs_prolog.as_ngg = shader->key.as_ngg;
7091 si_build_gs_prolog_function(&ctx, &gs_prolog_key);
7092 gs_prolog = ctx.main_fn;
7093
7094 /* ES main part */
7095 nir = get_nir_shader(es, &free_nir);
7096 struct si_shader shader_es = {};
7097 shader_es.selector = es;
7098 shader_es.key.as_es = 1;
7099 shader_es.key.as_ngg = shader->key.as_ngg;
7100 shader_es.key.mono = shader->key.mono;
7101 shader_es.key.opt = shader->key.opt;
7102 shader_es.is_monolithic = true;
7103 si_llvm_context_set_ir(&ctx, &shader_es, nir);
7104
7105 if (!si_compile_tgsi_main(&ctx, nir, free_nir)) {
7106 si_llvm_dispose(&ctx);
7107 return -1;
7108 }
7109 shader->info.uses_instanceid |= es->info.uses_instanceid;
7110 es_main = ctx.main_fn;
7111
7112 /* ES prolog */
7113 if (es->vs_needs_prolog) {
7114 union si_shader_part_key vs_prolog_key;
7115 si_get_vs_prolog_key(&es->info,
7116 shader_es.info.num_input_sgprs,
7117 &shader->key.part.gs.vs_prolog,
7118 shader, &vs_prolog_key);
7119 vs_prolog_key.vs_prolog.is_monolithic = true;
7120 si_build_vs_prolog_function(&ctx, &vs_prolog_key);
7121 es_prolog = ctx.main_fn;
7122 }
7123
7124 /* Reset the shader context. */
7125 ctx.shader = shader;
7126 ctx.type = PIPE_SHADER_GEOMETRY;
7127
7128 /* Prepare the array of shader parts. */
7129 LLVMValueRef parts[4];
7130 unsigned num_parts = 0, main_part, next_first_part;
7131
7132 if (es_prolog)
7133 parts[num_parts++] = es_prolog;
7134
7135 parts[main_part = num_parts++] = es_main;
7136 parts[next_first_part = num_parts++] = gs_prolog;
7137 parts[num_parts++] = gs_main;
7138
7139 si_build_wrapper_function(&ctx, parts, num_parts,
7140 main_part, next_first_part);
7141 } else {
7142 LLVMValueRef parts[2];
7143 union si_shader_part_key prolog_key;
7144
7145 parts[1] = ctx.main_fn;
7146
7147 memset(&prolog_key, 0, sizeof(prolog_key));
7148 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7149 si_build_gs_prolog_function(&ctx, &prolog_key);
7150 parts[0] = ctx.main_fn;
7151
7152 si_build_wrapper_function(&ctx, parts, 2, 1, 0);
7153 }
7154 } else if (shader->is_monolithic && ctx.type == PIPE_SHADER_FRAGMENT) {
7155 LLVMValueRef parts[3];
7156 union si_shader_part_key prolog_key;
7157 union si_shader_part_key epilog_key;
7158 bool need_prolog;
7159
7160 si_get_ps_prolog_key(shader, &prolog_key, false);
7161 need_prolog = si_need_ps_prolog(&prolog_key);
7162
7163 parts[need_prolog ? 1 : 0] = ctx.main_fn;
7164
7165 if (need_prolog) {
7166 si_build_ps_prolog_function(&ctx, &prolog_key);
7167 parts[0] = ctx.main_fn;
7168 }
7169
7170 si_get_ps_epilog_key(shader, &epilog_key);
7171 si_build_ps_epilog_function(&ctx, &epilog_key);
7172 parts[need_prolog ? 2 : 1] = ctx.main_fn;
7173
7174 si_build_wrapper_function(&ctx, parts, need_prolog ? 3 : 2,
7175 need_prolog ? 1 : 0, 0);
7176 }
7177
7178 si_llvm_optimize_module(&ctx);
7179
7180 /* Post-optimization transformations and analysis. */
7181 si_optimize_vs_outputs(&ctx);
7182
7183 if ((debug && debug->debug_message) ||
7184 si_can_dump_shader(sscreen, ctx.type)) {
7185 ctx.shader->info.private_mem_vgprs =
7186 ac_count_scratch_private_memory(ctx.main_fn);
7187 }
7188
7189 /* Make sure the input is a pointer and not integer followed by inttoptr. */
7190 assert(LLVMGetTypeKind(LLVMTypeOf(LLVMGetParam(ctx.main_fn, 0))) ==
7191 LLVMPointerTypeKind);
7192
7193 /* Compile to bytecode. */
7194 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, compiler,
7195 ctx.ac.module, debug, ctx.type, ctx.ac.wave_size,
7196 si_get_shader_name(shader),
7197 si_should_optimize_less(compiler, shader->selector));
7198 si_llvm_dispose(&ctx);
7199 if (r) {
7200 fprintf(stderr, "LLVM failed to compile shader\n");
7201 return r;
7202 }
7203
7204 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
7205 * LLVM 3.9svn has this bug.
7206 */
7207 if (sel->type == PIPE_SHADER_COMPUTE) {
7208 unsigned wave_size = sscreen->compute_wave_size;
7209 unsigned max_vgprs = sscreen->info.num_physical_wave64_vgprs_per_simd *
7210 (wave_size == 32 ? 2 : 1);
7211 unsigned max_sgprs = sscreen->info.num_physical_sgprs_per_simd;
7212 unsigned max_sgprs_per_wave = 128;
7213 unsigned simds_per_tg = 4; /* assuming WGP mode on gfx10 */
7214 unsigned threads_per_tg = si_get_max_workgroup_size(shader);
7215 unsigned waves_per_tg = DIV_ROUND_UP(threads_per_tg, wave_size);
7216 unsigned waves_per_simd = DIV_ROUND_UP(waves_per_tg, simds_per_tg);
7217
7218 max_vgprs = max_vgprs / waves_per_simd;
7219 max_sgprs = MIN2(max_sgprs / waves_per_simd, max_sgprs_per_wave);
7220
7221 if (shader->config.num_sgprs > max_sgprs ||
7222 shader->config.num_vgprs > max_vgprs) {
7223 fprintf(stderr, "LLVM failed to compile a shader correctly: "
7224 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
7225 shader->config.num_sgprs, shader->config.num_vgprs,
7226 max_sgprs, max_vgprs);
7227
7228 /* Just terminate the process, because dependent
7229 * shaders can hang due to bad input data, but use
7230 * the env var to allow shader-db to work.
7231 */
7232 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
7233 abort();
7234 }
7235 }
7236
7237 /* Add the scratch offset to input SGPRs. */
7238 if (shader->config.scratch_bytes_per_wave && !is_merged_shader(&ctx))
7239 shader->info.num_input_sgprs += 1; /* scratch byte offset */
7240
7241 /* Calculate the number of fragment input VGPRs. */
7242 if (ctx.type == PIPE_SHADER_FRAGMENT) {
7243 shader->info.num_input_vgprs = ac_get_fs_input_vgpr_cnt(&shader->config,
7244 &shader->info.face_vgpr_index,
7245 &shader->info.ancillary_vgpr_index);
7246 }
7247
7248 si_calculate_max_simd_waves(shader);
7249 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
7250 return 0;
7251 }
7252
7253 /**
7254 * Create, compile and return a shader part (prolog or epilog).
7255 *
7256 * \param sscreen screen
7257 * \param list list of shader parts of the same category
7258 * \param type shader type
7259 * \param key shader part key
7260 * \param prolog whether the part being requested is a prolog
7261 * \param tm LLVM target machine
7262 * \param debug debug callback
7263 * \param build the callback responsible for building the main function
7264 * \return non-NULL on success
7265 */
7266 static struct si_shader_part *
7267 si_get_shader_part(struct si_screen *sscreen,
7268 struct si_shader_part **list,
7269 enum pipe_shader_type type,
7270 bool prolog,
7271 union si_shader_part_key *key,
7272 struct ac_llvm_compiler *compiler,
7273 struct pipe_debug_callback *debug,
7274 void (*build)(struct si_shader_context *,
7275 union si_shader_part_key *),
7276 const char *name)
7277 {
7278 struct si_shader_part *result;
7279
7280 simple_mtx_lock(&sscreen->shader_parts_mutex);
7281
7282 /* Find existing. */
7283 for (result = *list; result; result = result->next) {
7284 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
7285 simple_mtx_unlock(&sscreen->shader_parts_mutex);
7286 return result;
7287 }
7288 }
7289
7290 /* Compile a new one. */
7291 result = CALLOC_STRUCT(si_shader_part);
7292 result->key = *key;
7293
7294 struct si_shader shader = {};
7295
7296 switch (type) {
7297 case PIPE_SHADER_VERTEX:
7298 shader.key.as_ls = key->vs_prolog.as_ls;
7299 shader.key.as_es = key->vs_prolog.as_es;
7300 shader.key.as_ngg = key->vs_prolog.as_ngg;
7301 break;
7302 case PIPE_SHADER_TESS_CTRL:
7303 assert(!prolog);
7304 shader.key.part.tcs.epilog = key->tcs_epilog.states;
7305 break;
7306 case PIPE_SHADER_GEOMETRY:
7307 assert(prolog);
7308 shader.key.as_ngg = key->gs_prolog.as_ngg;
7309 break;
7310 case PIPE_SHADER_FRAGMENT:
7311 if (prolog)
7312 shader.key.part.ps.prolog = key->ps_prolog.states;
7313 else
7314 shader.key.part.ps.epilog = key->ps_epilog.states;
7315 break;
7316 default:
7317 unreachable("bad shader part");
7318 }
7319
7320 struct si_shader_context ctx;
7321 si_init_shader_ctx(&ctx, sscreen, compiler,
7322 si_get_wave_size(sscreen, type, shader.key.as_ngg,
7323 shader.key.as_es),
7324 false);
7325 ctx.shader = &shader;
7326 ctx.type = type;
7327
7328 build(&ctx, key);
7329
7330 /* Compile. */
7331 si_llvm_optimize_module(&ctx);
7332
7333 if (si_compile_llvm(sscreen, &result->binary, &result->config, compiler,
7334 ctx.ac.module, debug, ctx.type, ctx.ac.wave_size,
7335 name, false)) {
7336 FREE(result);
7337 result = NULL;
7338 goto out;
7339 }
7340
7341 result->next = *list;
7342 *list = result;
7343
7344 out:
7345 si_llvm_dispose(&ctx);
7346 simple_mtx_unlock(&sscreen->shader_parts_mutex);
7347 return result;
7348 }
7349
7350 static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
7351 {
7352 LLVMValueRef ptr[2], list;
7353 bool merged_shader = is_merged_shader(ctx);
7354
7355 ptr[0] = LLVMGetParam(ctx->main_fn, (merged_shader ? 8 : 0) + SI_SGPR_RW_BUFFERS);
7356 list = LLVMBuildIntToPtr(ctx->ac.builder, ptr[0],
7357 ac_array_in_const32_addr_space(ctx->v4i32), "");
7358 return list;
7359 }
7360
7361 /**
7362 * Build the vertex shader prolog function.
7363 *
7364 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
7365 * All inputs are returned unmodified. The vertex load indices are
7366 * stored after them, which will be used by the API VS for fetching inputs.
7367 *
7368 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
7369 * input_v0,
7370 * input_v1,
7371 * input_v2,
7372 * input_v3,
7373 * (VertexID + BaseVertex),
7374 * (InstanceID + StartInstance),
7375 * (InstanceID / 2 + StartInstance)
7376 */
7377 static void si_build_vs_prolog_function(struct si_shader_context *ctx,
7378 union si_shader_part_key *key)
7379 {
7380 struct si_function_info fninfo;
7381 LLVMTypeRef *returns;
7382 LLVMValueRef ret, func;
7383 int num_returns, i;
7384 unsigned first_vs_vgpr = key->vs_prolog.num_merged_next_stage_vgprs;
7385 unsigned num_input_vgprs = key->vs_prolog.num_merged_next_stage_vgprs + 4;
7386 LLVMValueRef input_vgprs[9];
7387 unsigned num_all_input_regs = key->vs_prolog.num_input_sgprs +
7388 num_input_vgprs;
7389 unsigned user_sgpr_base = key->vs_prolog.num_merged_next_stage_vgprs ? 8 : 0;
7390
7391 si_init_function_info(&fninfo);
7392
7393 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
7394 returns = alloca((num_all_input_regs + key->vs_prolog.last_input + 1) *
7395 sizeof(LLVMTypeRef));
7396 num_returns = 0;
7397
7398 /* Declare input and output SGPRs. */
7399 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7400 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7401 returns[num_returns++] = ctx->i32;
7402 }
7403
7404 /* Preloaded VGPRs (outputs must be floats) */
7405 for (i = 0; i < num_input_vgprs; i++) {
7406 add_arg_assign(&fninfo, ARG_VGPR, ctx->i32, &input_vgprs[i]);
7407 returns[num_returns++] = ctx->f32;
7408 }
7409
7410 /* Vertex load indices. */
7411 for (i = 0; i <= key->vs_prolog.last_input; i++)
7412 returns[num_returns++] = ctx->f32;
7413
7414 /* Create the function. */
7415 si_create_function(ctx, "vs_prolog", returns, num_returns, &fninfo, 0);
7416 func = ctx->main_fn;
7417
7418 if (key->vs_prolog.num_merged_next_stage_vgprs) {
7419 if (!key->vs_prolog.is_monolithic)
7420 si_init_exec_from_input(ctx, 3, 0);
7421
7422 if (key->vs_prolog.as_ls &&
7423 ctx->screen->info.has_ls_vgpr_init_bug) {
7424 /* If there are no HS threads, SPI loads the LS VGPRs
7425 * starting at VGPR 0. Shift them back to where they
7426 * belong.
7427 */
7428 LLVMValueRef has_hs_threads =
7429 LLVMBuildICmp(ctx->ac.builder, LLVMIntNE,
7430 si_unpack_param(ctx, 3, 8, 8),
7431 ctx->i32_0, "");
7432
7433 for (i = 4; i > 0; --i) {
7434 input_vgprs[i + 1] =
7435 LLVMBuildSelect(ctx->ac.builder, has_hs_threads,
7436 input_vgprs[i + 1],
7437 input_vgprs[i - 1], "");
7438 }
7439 }
7440 }
7441
7442 unsigned vertex_id_vgpr = first_vs_vgpr;
7443 unsigned instance_id_vgpr =
7444 ctx->screen->info.chip_class >= GFX10 ?
7445 first_vs_vgpr + 3 :
7446 first_vs_vgpr + (key->vs_prolog.as_ls ? 2 : 1);
7447
7448 ctx->abi.vertex_id = input_vgprs[vertex_id_vgpr];
7449 ctx->abi.instance_id = input_vgprs[instance_id_vgpr];
7450
7451 /* InstanceID = VertexID >> 16;
7452 * VertexID = VertexID & 0xffff;
7453 */
7454 if (key->vs_prolog.states.unpack_instance_id_from_vertex_id) {
7455 ctx->abi.instance_id = LLVMBuildLShr(ctx->ac.builder, ctx->abi.vertex_id,
7456 LLVMConstInt(ctx->i32, 16, 0), "");
7457 ctx->abi.vertex_id = LLVMBuildAnd(ctx->ac.builder, ctx->abi.vertex_id,
7458 LLVMConstInt(ctx->i32, 0xffff, 0), "");
7459 }
7460
7461 /* Copy inputs to outputs. This should be no-op, as the registers match,
7462 * but it will prevent the compiler from overwriting them unintentionally.
7463 */
7464 ret = ctx->return_value;
7465 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
7466 LLVMValueRef p = LLVMGetParam(func, i);
7467 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7468 }
7469 for (i = 0; i < num_input_vgprs; i++) {
7470 LLVMValueRef p = input_vgprs[i];
7471
7472 if (i == vertex_id_vgpr)
7473 p = ctx->abi.vertex_id;
7474 else if (i == instance_id_vgpr)
7475 p = ctx->abi.instance_id;
7476
7477 p = ac_to_float(&ctx->ac, p);
7478 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p,
7479 key->vs_prolog.num_input_sgprs + i, "");
7480 }
7481
7482 LLVMValueRef original_ret = ret;
7483 bool wrapped = false;
7484 LLVMBasicBlockRef if_entry_block = NULL;
7485
7486 if (key->vs_prolog.is_monolithic && key->vs_prolog.as_ngg) {
7487 LLVMValueRef num_threads;
7488 LLVMValueRef ena;
7489
7490 num_threads = si_unpack_param(ctx, 3, 0, 8);
7491 ena = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
7492 ac_get_thread_id(&ctx->ac), num_threads, "");
7493 if_entry_block = LLVMGetInsertBlock(ctx->ac.builder);
7494 ac_build_ifcc(&ctx->ac, ena, 11501);
7495 wrapped = true;
7496 }
7497
7498 /* Compute vertex load indices from instance divisors. */
7499 LLVMValueRef instance_divisor_constbuf = NULL;
7500
7501 if (key->vs_prolog.states.instance_divisor_is_fetched) {
7502 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7503 LLVMValueRef buf_index =
7504 LLVMConstInt(ctx->i32, SI_VS_CONST_INSTANCE_DIVISORS, 0);
7505 instance_divisor_constbuf =
7506 ac_build_load_to_sgpr(&ctx->ac, list, buf_index);
7507 }
7508
7509 for (i = 0; i <= key->vs_prolog.last_input; i++) {
7510 bool divisor_is_one =
7511 key->vs_prolog.states.instance_divisor_is_one & (1u << i);
7512 bool divisor_is_fetched =
7513 key->vs_prolog.states.instance_divisor_is_fetched & (1u << i);
7514 LLVMValueRef index = NULL;
7515
7516 if (divisor_is_one) {
7517 index = ctx->abi.instance_id;
7518 } else if (divisor_is_fetched) {
7519 LLVMValueRef udiv_factors[4];
7520
7521 for (unsigned j = 0; j < 4; j++) {
7522 udiv_factors[j] =
7523 buffer_load_const(ctx, instance_divisor_constbuf,
7524 LLVMConstInt(ctx->i32, i*16 + j*4, 0));
7525 udiv_factors[j] = ac_to_integer(&ctx->ac, udiv_factors[j]);
7526 }
7527 /* The faster NUW version doesn't work when InstanceID == UINT_MAX.
7528 * Such InstanceID might not be achievable in a reasonable time though.
7529 */
7530 index = ac_build_fast_udiv_nuw(&ctx->ac, ctx->abi.instance_id,
7531 udiv_factors[0], udiv_factors[1],
7532 udiv_factors[2], udiv_factors[3]);
7533 }
7534
7535 if (divisor_is_one || divisor_is_fetched) {
7536 /* Add StartInstance. */
7537 index = LLVMBuildAdd(ctx->ac.builder, index,
7538 LLVMGetParam(ctx->main_fn, user_sgpr_base +
7539 SI_SGPR_START_INSTANCE), "");
7540 } else {
7541 /* VertexID + BaseVertex */
7542 index = LLVMBuildAdd(ctx->ac.builder,
7543 ctx->abi.vertex_id,
7544 LLVMGetParam(func, user_sgpr_base +
7545 SI_SGPR_BASE_VERTEX), "");
7546 }
7547
7548 index = ac_to_float(&ctx->ac, index);
7549 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, index,
7550 fninfo.num_params + i, "");
7551 }
7552
7553 if (wrapped) {
7554 LLVMBasicBlockRef bbs[2] = {
7555 LLVMGetInsertBlock(ctx->ac.builder),
7556 if_entry_block,
7557 };
7558 ac_build_endif(&ctx->ac, 11501);
7559
7560 LLVMValueRef values[2] = {
7561 ret,
7562 original_ret
7563 };
7564 ret = ac_build_phi(&ctx->ac, LLVMTypeOf(ret), 2, values, bbs);
7565 }
7566
7567 si_llvm_build_ret(ctx, ret);
7568 }
7569
7570 static bool si_get_vs_prolog(struct si_screen *sscreen,
7571 struct ac_llvm_compiler *compiler,
7572 struct si_shader *shader,
7573 struct pipe_debug_callback *debug,
7574 struct si_shader *main_part,
7575 const struct si_vs_prolog_bits *key)
7576 {
7577 struct si_shader_selector *vs = main_part->selector;
7578
7579 if (!si_vs_needs_prolog(vs, key))
7580 return true;
7581
7582 /* Get the prolog. */
7583 union si_shader_part_key prolog_key;
7584 si_get_vs_prolog_key(&vs->info, main_part->info.num_input_sgprs,
7585 key, shader, &prolog_key);
7586
7587 shader->prolog =
7588 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7589 PIPE_SHADER_VERTEX, true, &prolog_key, compiler,
7590 debug, si_build_vs_prolog_function,
7591 "Vertex Shader Prolog");
7592 return shader->prolog != NULL;
7593 }
7594
7595 /**
7596 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7597 */
7598 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7599 struct ac_llvm_compiler *compiler,
7600 struct si_shader *shader,
7601 struct pipe_debug_callback *debug)
7602 {
7603 return si_get_vs_prolog(sscreen, compiler, shader, debug, shader,
7604 &shader->key.part.vs.prolog);
7605 }
7606
7607 /**
7608 * Compile the TCS epilog function. This writes tesselation factors to memory
7609 * based on the output primitive type of the tesselator (determined by TES).
7610 */
7611 static void si_build_tcs_epilog_function(struct si_shader_context *ctx,
7612 union si_shader_part_key *key)
7613 {
7614 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
7615 struct si_function_info fninfo;
7616 LLVMValueRef func;
7617
7618 si_init_function_info(&fninfo);
7619
7620 if (ctx->screen->info.chip_class >= GFX9) {
7621 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7622 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7623 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7624 add_arg(&fninfo, ARG_SGPR, ctx->i32); /* wave info */
7625 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7626 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7627 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7628 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7629 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7630 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7631 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7632 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7633 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7634 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7635 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7636 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7637 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7638 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7639 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7640 } else {
7641 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7642 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7643 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7644 add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
7645 ctx->param_tcs_offchip_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7646 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7647 ctx->param_tcs_out_lds_layout = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7648 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7649 ctx->param_tcs_offchip_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7650 ctx->param_tcs_factor_offset = add_arg(&fninfo, ARG_SGPR, ctx->i32);
7651 }
7652
7653 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7654 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* VGPR gap */
7655 unsigned tess_factors_idx =
7656 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* patch index within the wave (REL_PATCH_ID) */
7657 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* invocation ID within the patch */
7658 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* LDS offset where tess factors should be loaded from */
7659
7660 for (unsigned i = 0; i < 6; i++)
7661 add_arg(&fninfo, ARG_VGPR, ctx->i32); /* tess factors */
7662
7663 /* Create the function. */
7664 si_create_function(ctx, "tcs_epilog", NULL, 0, &fninfo,
7665 ctx->screen->info.chip_class >= GFX7 ? 128 : 0);
7666 ac_declare_lds_as_pointer(&ctx->ac);
7667 func = ctx->main_fn;
7668
7669 LLVMValueRef invoc0_tess_factors[6];
7670 for (unsigned i = 0; i < 6; i++)
7671 invoc0_tess_factors[i] = LLVMGetParam(func, tess_factors_idx + 3 + i);
7672
7673 si_write_tess_factors(bld_base,
7674 LLVMGetParam(func, tess_factors_idx),
7675 LLVMGetParam(func, tess_factors_idx + 1),
7676 LLVMGetParam(func, tess_factors_idx + 2),
7677 invoc0_tess_factors, invoc0_tess_factors + 4);
7678
7679 LLVMBuildRetVoid(ctx->ac.builder);
7680 }
7681
7682 /**
7683 * Select and compile (or reuse) TCS parts (epilog).
7684 */
7685 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7686 struct ac_llvm_compiler *compiler,
7687 struct si_shader *shader,
7688 struct pipe_debug_callback *debug)
7689 {
7690 if (sscreen->info.chip_class >= GFX9) {
7691 struct si_shader *ls_main_part =
7692 shader->key.part.tcs.ls->main_shader_part_ls;
7693
7694 if (!si_get_vs_prolog(sscreen, compiler, shader, debug, ls_main_part,
7695 &shader->key.part.tcs.ls_prolog))
7696 return false;
7697
7698 shader->previous_stage = ls_main_part;
7699 }
7700
7701 /* Get the epilog. */
7702 union si_shader_part_key epilog_key;
7703 memset(&epilog_key, 0, sizeof(epilog_key));
7704 epilog_key.tcs_epilog.states = shader->key.part.tcs.epilog;
7705
7706 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7707 PIPE_SHADER_TESS_CTRL, false,
7708 &epilog_key, compiler, debug,
7709 si_build_tcs_epilog_function,
7710 "Tessellation Control Shader Epilog");
7711 return shader->epilog != NULL;
7712 }
7713
7714 /**
7715 * Select and compile (or reuse) GS parts (prolog).
7716 */
7717 static bool si_shader_select_gs_parts(struct si_screen *sscreen,
7718 struct ac_llvm_compiler *compiler,
7719 struct si_shader *shader,
7720 struct pipe_debug_callback *debug)
7721 {
7722 if (sscreen->info.chip_class >= GFX9) {
7723 struct si_shader *es_main_part;
7724 enum pipe_shader_type es_type = shader->key.part.gs.es->type;
7725
7726 if (shader->key.as_ngg)
7727 es_main_part = shader->key.part.gs.es->main_shader_part_ngg_es;
7728 else
7729 es_main_part = shader->key.part.gs.es->main_shader_part_es;
7730
7731 if (es_type == PIPE_SHADER_VERTEX &&
7732 !si_get_vs_prolog(sscreen, compiler, shader, debug, es_main_part,
7733 &shader->key.part.gs.vs_prolog))
7734 return false;
7735
7736 shader->previous_stage = es_main_part;
7737 }
7738
7739 if (!shader->key.part.gs.prolog.tri_strip_adj_fix)
7740 return true;
7741
7742 union si_shader_part_key prolog_key;
7743 memset(&prolog_key, 0, sizeof(prolog_key));
7744 prolog_key.gs_prolog.states = shader->key.part.gs.prolog;
7745 prolog_key.gs_prolog.as_ngg = shader->key.as_ngg;
7746
7747 shader->prolog2 = si_get_shader_part(sscreen, &sscreen->gs_prologs,
7748 PIPE_SHADER_GEOMETRY, true,
7749 &prolog_key, compiler, debug,
7750 si_build_gs_prolog_function,
7751 "Geometry Shader Prolog");
7752 return shader->prolog2 != NULL;
7753 }
7754
7755 /**
7756 * Build the pixel shader prolog function. This handles:
7757 * - two-side color selection and interpolation
7758 * - overriding interpolation parameters for the API PS
7759 * - polygon stippling
7760 *
7761 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7762 * overriden by other states. (e.g. per-sample interpolation)
7763 * Interpolated colors are stored after the preloaded VGPRs.
7764 */
7765 static void si_build_ps_prolog_function(struct si_shader_context *ctx,
7766 union si_shader_part_key *key)
7767 {
7768 struct si_function_info fninfo;
7769 LLVMValueRef ret, func;
7770 int num_returns, i, num_color_channels;
7771
7772 assert(si_need_ps_prolog(key));
7773
7774 si_init_function_info(&fninfo);
7775
7776 /* Declare inputs. */
7777 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7778 add_arg(&fninfo, ARG_SGPR, ctx->i32);
7779
7780 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7781 add_arg(&fninfo, ARG_VGPR, ctx->f32);
7782
7783 /* Declare outputs (same as inputs + add colors if needed) */
7784 num_returns = fninfo.num_params;
7785 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7786 for (i = 0; i < num_color_channels; i++)
7787 fninfo.types[num_returns++] = ctx->f32;
7788
7789 /* Create the function. */
7790 si_create_function(ctx, "ps_prolog", fninfo.types, num_returns,
7791 &fninfo, 0);
7792 func = ctx->main_fn;
7793
7794 /* Copy inputs to outputs. This should be no-op, as the registers match,
7795 * but it will prevent the compiler from overwriting them unintentionally.
7796 */
7797 ret = ctx->return_value;
7798 for (i = 0; i < fninfo.num_params; i++) {
7799 LLVMValueRef p = LLVMGetParam(func, i);
7800 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, p, i, "");
7801 }
7802
7803 /* Polygon stippling. */
7804 if (key->ps_prolog.states.poly_stipple) {
7805 /* POS_FIXED_PT is always last. */
7806 unsigned pos = key->ps_prolog.num_input_sgprs +
7807 key->ps_prolog.num_input_vgprs - 1;
7808 LLVMValueRef list = si_prolog_get_rw_buffers(ctx);
7809
7810 si_llvm_emit_polygon_stipple(ctx, list, pos);
7811 }
7812
7813 if (key->ps_prolog.states.bc_optimize_for_persp ||
7814 key->ps_prolog.states.bc_optimize_for_linear) {
7815 unsigned i, base = key->ps_prolog.num_input_sgprs;
7816 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7817
7818 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7819 * The hw doesn't compute CENTROID if the whole wave only
7820 * contains fully-covered quads.
7821 *
7822 * PRIM_MASK is after user SGPRs.
7823 */
7824 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7825 bc_optimize = LLVMBuildLShr(ctx->ac.builder, bc_optimize,
7826 LLVMConstInt(ctx->i32, 31, 0), "");
7827 bc_optimize = LLVMBuildTrunc(ctx->ac.builder, bc_optimize,
7828 ctx->i1, "");
7829
7830 if (key->ps_prolog.states.bc_optimize_for_persp) {
7831 /* Read PERSP_CENTER. */
7832 for (i = 0; i < 2; i++)
7833 center[i] = LLVMGetParam(func, base + 2 + i);
7834 /* Read PERSP_CENTROID. */
7835 for (i = 0; i < 2; i++)
7836 centroid[i] = LLVMGetParam(func, base + 4 + i);
7837 /* Select PERSP_CENTROID. */
7838 for (i = 0; i < 2; i++) {
7839 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7840 center[i], centroid[i], "");
7841 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7842 tmp, base + 4 + i, "");
7843 }
7844 }
7845 if (key->ps_prolog.states.bc_optimize_for_linear) {
7846 /* Read LINEAR_CENTER. */
7847 for (i = 0; i < 2; i++)
7848 center[i] = LLVMGetParam(func, base + 8 + i);
7849 /* Read LINEAR_CENTROID. */
7850 for (i = 0; i < 2; i++)
7851 centroid[i] = LLVMGetParam(func, base + 10 + i);
7852 /* Select LINEAR_CENTROID. */
7853 for (i = 0; i < 2; i++) {
7854 tmp = LLVMBuildSelect(ctx->ac.builder, bc_optimize,
7855 center[i], centroid[i], "");
7856 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7857 tmp, base + 10 + i, "");
7858 }
7859 }
7860 }
7861
7862 /* Force per-sample interpolation. */
7863 if (key->ps_prolog.states.force_persp_sample_interp) {
7864 unsigned i, base = key->ps_prolog.num_input_sgprs;
7865 LLVMValueRef persp_sample[2];
7866
7867 /* Read PERSP_SAMPLE. */
7868 for (i = 0; i < 2; i++)
7869 persp_sample[i] = LLVMGetParam(func, base + i);
7870 /* Overwrite PERSP_CENTER. */
7871 for (i = 0; i < 2; i++)
7872 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7873 persp_sample[i], base + 2 + i, "");
7874 /* Overwrite PERSP_CENTROID. */
7875 for (i = 0; i < 2; i++)
7876 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7877 persp_sample[i], base + 4 + i, "");
7878 }
7879 if (key->ps_prolog.states.force_linear_sample_interp) {
7880 unsigned i, base = key->ps_prolog.num_input_sgprs;
7881 LLVMValueRef linear_sample[2];
7882
7883 /* Read LINEAR_SAMPLE. */
7884 for (i = 0; i < 2; i++)
7885 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7886 /* Overwrite LINEAR_CENTER. */
7887 for (i = 0; i < 2; i++)
7888 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7889 linear_sample[i], base + 8 + i, "");
7890 /* Overwrite LINEAR_CENTROID. */
7891 for (i = 0; i < 2; i++)
7892 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7893 linear_sample[i], base + 10 + i, "");
7894 }
7895
7896 /* Force center interpolation. */
7897 if (key->ps_prolog.states.force_persp_center_interp) {
7898 unsigned i, base = key->ps_prolog.num_input_sgprs;
7899 LLVMValueRef persp_center[2];
7900
7901 /* Read PERSP_CENTER. */
7902 for (i = 0; i < 2; i++)
7903 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7904 /* Overwrite PERSP_SAMPLE. */
7905 for (i = 0; i < 2; i++)
7906 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7907 persp_center[i], base + i, "");
7908 /* Overwrite PERSP_CENTROID. */
7909 for (i = 0; i < 2; i++)
7910 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7911 persp_center[i], base + 4 + i, "");
7912 }
7913 if (key->ps_prolog.states.force_linear_center_interp) {
7914 unsigned i, base = key->ps_prolog.num_input_sgprs;
7915 LLVMValueRef linear_center[2];
7916
7917 /* Read LINEAR_CENTER. */
7918 for (i = 0; i < 2; i++)
7919 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7920 /* Overwrite LINEAR_SAMPLE. */
7921 for (i = 0; i < 2; i++)
7922 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7923 linear_center[i], base + 6 + i, "");
7924 /* Overwrite LINEAR_CENTROID. */
7925 for (i = 0; i < 2; i++)
7926 ret = LLVMBuildInsertValue(ctx->ac.builder, ret,
7927 linear_center[i], base + 10 + i, "");
7928 }
7929
7930 /* Interpolate colors. */
7931 unsigned color_out_idx = 0;
7932 for (i = 0; i < 2; i++) {
7933 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7934 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7935 key->ps_prolog.face_vgpr_index;
7936 LLVMValueRef interp[2], color[4];
7937 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7938
7939 if (!writemask)
7940 continue;
7941
7942 /* If the interpolation qualifier is not CONSTANT (-1). */
7943 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7944 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7945 key->ps_prolog.color_interp_vgpr_index[i];
7946
7947 /* Get the (i,j) updated by bc_optimize handling. */
7948 interp[0] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7949 interp_vgpr, "");
7950 interp[1] = LLVMBuildExtractValue(ctx->ac.builder, ret,
7951 interp_vgpr + 1, "");
7952 interp_ij = ac_build_gather_values(&ctx->ac, interp, 2);
7953 }
7954
7955 /* Use the absolute location of the input. */
7956 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7957
7958 if (key->ps_prolog.states.color_two_side) {
7959 face = LLVMGetParam(func, face_vgpr);
7960 face = ac_to_integer(&ctx->ac, face);
7961 }
7962
7963 interp_fs_input(ctx,
7964 key->ps_prolog.color_attr_index[i],
7965 TGSI_SEMANTIC_COLOR, i,
7966 key->ps_prolog.num_interp_inputs,
7967 key->ps_prolog.colors_read, interp_ij,
7968 prim_mask, face, color);
7969
7970 while (writemask) {
7971 unsigned chan = u_bit_scan(&writemask);
7972 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, color[chan],
7973 fninfo.num_params + color_out_idx++, "");
7974 }
7975 }
7976
7977 /* Section 15.2.2 (Shader Inputs) of the OpenGL 4.5 (Core Profile) spec
7978 * says:
7979 *
7980 * "When per-sample shading is active due to the use of a fragment
7981 * input qualified by sample or due to the use of the gl_SampleID
7982 * or gl_SamplePosition variables, only the bit for the current
7983 * sample is set in gl_SampleMaskIn. When state specifies multiple
7984 * fragment shader invocations for a given fragment, the sample
7985 * mask for any single fragment shader invocation may specify a
7986 * subset of the covered samples for the fragment. In this case,
7987 * the bit corresponding to each covered sample will be set in
7988 * exactly one fragment shader invocation."
7989 *
7990 * The samplemask loaded by hardware is always the coverage of the
7991 * entire pixel/fragment, so mask bits out based on the sample ID.
7992 */
7993 if (key->ps_prolog.states.samplemask_log_ps_iter) {
7994 /* The bit pattern matches that used by fixed function fragment
7995 * processing. */
7996 static const uint16_t ps_iter_masks[] = {
7997 0xffff, /* not used */
7998 0x5555,
7999 0x1111,
8000 0x0101,
8001 0x0001,
8002 };
8003 assert(key->ps_prolog.states.samplemask_log_ps_iter < ARRAY_SIZE(ps_iter_masks));
8004
8005 uint32_t ps_iter_mask = ps_iter_masks[key->ps_prolog.states.samplemask_log_ps_iter];
8006 unsigned ancillary_vgpr = key->ps_prolog.num_input_sgprs +
8007 key->ps_prolog.ancillary_vgpr_index;
8008 LLVMValueRef sampleid = si_unpack_param(ctx, ancillary_vgpr, 8, 4);
8009 LLVMValueRef samplemask = LLVMGetParam(func, ancillary_vgpr + 1);
8010
8011 samplemask = ac_to_integer(&ctx->ac, samplemask);
8012 samplemask = LLVMBuildAnd(
8013 ctx->ac.builder,
8014 samplemask,
8015 LLVMBuildShl(ctx->ac.builder,
8016 LLVMConstInt(ctx->i32, ps_iter_mask, false),
8017 sampleid, ""),
8018 "");
8019 samplemask = ac_to_float(&ctx->ac, samplemask);
8020
8021 ret = LLVMBuildInsertValue(ctx->ac.builder, ret, samplemask,
8022 ancillary_vgpr + 1, "");
8023 }
8024
8025 /* Tell LLVM to insert WQM instruction sequence when needed. */
8026 if (key->ps_prolog.wqm) {
8027 LLVMAddTargetDependentFunctionAttr(func,
8028 "amdgpu-ps-wqm-outputs", "");
8029 }
8030
8031 si_llvm_build_ret(ctx, ret);
8032 }
8033
8034 /**
8035 * Build the pixel shader epilog function. This handles everything that must be
8036 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
8037 */
8038 static void si_build_ps_epilog_function(struct si_shader_context *ctx,
8039 union si_shader_part_key *key)
8040 {
8041 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
8042 struct si_function_info fninfo;
8043 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
8044 int i;
8045 struct si_ps_exports exp = {};
8046
8047 si_init_function_info(&fninfo);
8048
8049 /* Declare input SGPRs. */
8050 ctx->param_rw_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
8051 ctx->param_bindless_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
8052 ctx->param_const_and_shader_buffers = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
8053 ctx->param_samplers_and_images = add_arg(&fninfo, ARG_SGPR, ctx->ac.intptr);
8054 add_arg_checked(&fninfo, ARG_SGPR, ctx->f32, SI_PARAM_ALPHA_REF);
8055
8056 /* Declare input VGPRs. */
8057 unsigned required_num_params =
8058 fninfo.num_sgpr_params +
8059 util_bitcount(key->ps_epilog.colors_written) * 4 +
8060 key->ps_epilog.writes_z +
8061 key->ps_epilog.writes_stencil +
8062 key->ps_epilog.writes_samplemask;
8063
8064 required_num_params = MAX2(required_num_params,
8065 fninfo.num_sgpr_params + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
8066
8067 while (fninfo.num_params < required_num_params)
8068 add_arg(&fninfo, ARG_VGPR, ctx->f32);
8069
8070 /* Create the function. */
8071 si_create_function(ctx, "ps_epilog", NULL, 0, &fninfo, 0);
8072 /* Disable elimination of unused inputs. */
8073 ac_llvm_add_target_dep_function_attr(ctx->main_fn,
8074 "InitialPSInputAddr", 0xffffff);
8075
8076 /* Process colors. */
8077 unsigned vgpr = fninfo.num_sgpr_params;
8078 unsigned colors_written = key->ps_epilog.colors_written;
8079 int last_color_export = -1;
8080
8081 /* Find the last color export. */
8082 if (!key->ps_epilog.writes_z &&
8083 !key->ps_epilog.writes_stencil &&
8084 !key->ps_epilog.writes_samplemask) {
8085 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
8086
8087 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
8088 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
8089 /* Just set this if any of the colorbuffers are enabled. */
8090 if (spi_format &
8091 ((1ull << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
8092 last_color_export = 0;
8093 } else {
8094 for (i = 0; i < 8; i++)
8095 if (colors_written & (1 << i) &&
8096 (spi_format >> (i * 4)) & 0xf)
8097 last_color_export = i;
8098 }
8099 }
8100
8101 while (colors_written) {
8102 LLVMValueRef color[4];
8103 int mrt = u_bit_scan(&colors_written);
8104
8105 for (i = 0; i < 4; i++)
8106 color[i] = LLVMGetParam(ctx->main_fn, vgpr++);
8107
8108 si_export_mrt_color(bld_base, color, mrt,
8109 fninfo.num_params - 1,
8110 mrt == last_color_export, &exp);
8111 }
8112
8113 /* Process depth, stencil, samplemask. */
8114 if (key->ps_epilog.writes_z)
8115 depth = LLVMGetParam(ctx->main_fn, vgpr++);
8116 if (key->ps_epilog.writes_stencil)
8117 stencil = LLVMGetParam(ctx->main_fn, vgpr++);
8118 if (key->ps_epilog.writes_samplemask)
8119 samplemask = LLVMGetParam(ctx->main_fn, vgpr++);
8120
8121 if (depth || stencil || samplemask)
8122 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
8123 else if (last_color_export == -1)
8124 ac_build_export_null(&ctx->ac);
8125
8126 if (exp.num)
8127 si_emit_ps_exports(ctx, &exp);
8128
8129 /* Compile. */
8130 LLVMBuildRetVoid(ctx->ac.builder);
8131 }
8132
8133 /**
8134 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
8135 */
8136 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
8137 struct ac_llvm_compiler *compiler,
8138 struct si_shader *shader,
8139 struct pipe_debug_callback *debug)
8140 {
8141 union si_shader_part_key prolog_key;
8142 union si_shader_part_key epilog_key;
8143
8144 /* Get the prolog. */
8145 si_get_ps_prolog_key(shader, &prolog_key, true);
8146
8147 /* The prolog is a no-op if these aren't set. */
8148 if (si_need_ps_prolog(&prolog_key)) {
8149 shader->prolog =
8150 si_get_shader_part(sscreen, &sscreen->ps_prologs,
8151 PIPE_SHADER_FRAGMENT, true,
8152 &prolog_key, compiler, debug,
8153 si_build_ps_prolog_function,
8154 "Fragment Shader Prolog");
8155 if (!shader->prolog)
8156 return false;
8157 }
8158
8159 /* Get the epilog. */
8160 si_get_ps_epilog_key(shader, &epilog_key);
8161
8162 shader->epilog =
8163 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
8164 PIPE_SHADER_FRAGMENT, false,
8165 &epilog_key, compiler, debug,
8166 si_build_ps_epilog_function,
8167 "Fragment Shader Epilog");
8168 if (!shader->epilog)
8169 return false;
8170
8171 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
8172 if (shader->key.part.ps.prolog.poly_stipple) {
8173 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
8174 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
8175 }
8176
8177 /* Set up the enable bits for per-sample shading if needed. */
8178 if (shader->key.part.ps.prolog.force_persp_sample_interp &&
8179 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8180 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8181 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
8182 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8183 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
8184 }
8185 if (shader->key.part.ps.prolog.force_linear_sample_interp &&
8186 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
8187 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8188 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
8189 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8190 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
8191 }
8192 if (shader->key.part.ps.prolog.force_persp_center_interp &&
8193 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8194 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8195 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
8196 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
8197 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8198 }
8199 if (shader->key.part.ps.prolog.force_linear_center_interp &&
8200 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
8201 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
8202 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
8203 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
8204 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8205 }
8206
8207 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
8208 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
8209 !(shader->config.spi_ps_input_ena & 0xf)) {
8210 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
8211 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
8212 }
8213
8214 /* At least one pair of interpolation weights must be enabled. */
8215 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
8216 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
8217 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
8218 }
8219
8220 /* Samplemask fixup requires the sample ID. */
8221 if (shader->key.part.ps.prolog.samplemask_log_ps_iter) {
8222 shader->config.spi_ps_input_ena |= S_0286CC_ANCILLARY_ENA(1);
8223 assert(G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr));
8224 }
8225
8226 /* The sample mask input is always enabled, because the API shader always
8227 * passes it through to the epilog. Disable it here if it's unused.
8228 */
8229 if (!shader->key.part.ps.epilog.poly_line_smoothing &&
8230 !shader->selector->info.reads_samplemask)
8231 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
8232
8233 return true;
8234 }
8235
8236 void si_multiwave_lds_size_workaround(struct si_screen *sscreen,
8237 unsigned *lds_size)
8238 {
8239 /* If tessellation is all offchip and on-chip GS isn't used, this
8240 * workaround is not needed.
8241 */
8242 return;
8243
8244 /* SPI barrier management bug:
8245 * Make sure we have at least 4k of LDS in use to avoid the bug.
8246 * It applies to workgroup sizes of more than one wavefront.
8247 */
8248 if (sscreen->info.family == CHIP_BONAIRE ||
8249 sscreen->info.family == CHIP_KABINI)
8250 *lds_size = MAX2(*lds_size, 8);
8251 }
8252
8253 static void si_fix_resource_usage(struct si_screen *sscreen,
8254 struct si_shader *shader)
8255 {
8256 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
8257
8258 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
8259
8260 if (shader->selector->type == PIPE_SHADER_COMPUTE &&
8261 si_get_max_workgroup_size(shader) > sscreen->compute_wave_size) {
8262 si_multiwave_lds_size_workaround(sscreen,
8263 &shader->config.lds_size);
8264 }
8265 }
8266
8267 bool si_shader_create(struct si_screen *sscreen, struct ac_llvm_compiler *compiler,
8268 struct si_shader *shader,
8269 struct pipe_debug_callback *debug)
8270 {
8271 struct si_shader_selector *sel = shader->selector;
8272 struct si_shader *mainp = *si_get_main_shader_part(sel, &shader->key);
8273 int r;
8274
8275 /* LS, ES, VS are compiled on demand if the main part hasn't been
8276 * compiled for that stage.
8277 *
8278 * GS are compiled on demand if the main part hasn't been compiled
8279 * for the chosen NGG-ness.
8280 *
8281 * Vertex shaders are compiled on demand when a vertex fetch
8282 * workaround must be applied.
8283 */
8284 if (shader->is_monolithic) {
8285 /* Monolithic shader (compiled as a whole, has many variants,
8286 * may take a long time to compile).
8287 */
8288 r = si_compile_tgsi_shader(sscreen, compiler, shader, debug);
8289 if (r)
8290 return false;
8291 } else {
8292 /* The shader consists of several parts:
8293 *
8294 * - the middle part is the user shader, it has 1 variant only
8295 * and it was compiled during the creation of the shader
8296 * selector
8297 * - the prolog part is inserted at the beginning
8298 * - the epilog part is inserted at the end
8299 *
8300 * The prolog and epilog have many (but simple) variants.
8301 *
8302 * Starting with gfx9, geometry and tessellation control
8303 * shaders also contain the prolog and user shader parts of
8304 * the previous shader stage.
8305 */
8306
8307 if (!mainp)
8308 return false;
8309
8310 /* Copy the compiled TGSI shader data over. */
8311 shader->is_binary_shared = true;
8312 shader->binary = mainp->binary;
8313 shader->config = mainp->config;
8314 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
8315 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
8316 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
8317 shader->info.ancillary_vgpr_index = mainp->info.ancillary_vgpr_index;
8318 memcpy(shader->info.vs_output_param_offset,
8319 mainp->info.vs_output_param_offset,
8320 sizeof(mainp->info.vs_output_param_offset));
8321 shader->info.uses_instanceid = mainp->info.uses_instanceid;
8322 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
8323 shader->info.nr_param_exports = mainp->info.nr_param_exports;
8324
8325 /* Select prologs and/or epilogs. */
8326 switch (sel->type) {
8327 case PIPE_SHADER_VERTEX:
8328 if (!si_shader_select_vs_parts(sscreen, compiler, shader, debug))
8329 return false;
8330 break;
8331 case PIPE_SHADER_TESS_CTRL:
8332 if (!si_shader_select_tcs_parts(sscreen, compiler, shader, debug))
8333 return false;
8334 break;
8335 case PIPE_SHADER_TESS_EVAL:
8336 break;
8337 case PIPE_SHADER_GEOMETRY:
8338 if (!si_shader_select_gs_parts(sscreen, compiler, shader, debug))
8339 return false;
8340 break;
8341 case PIPE_SHADER_FRAGMENT:
8342 if (!si_shader_select_ps_parts(sscreen, compiler, shader, debug))
8343 return false;
8344
8345 /* Make sure we have at least as many VGPRs as there
8346 * are allocated inputs.
8347 */
8348 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8349 shader->info.num_input_vgprs);
8350 break;
8351 default:;
8352 }
8353
8354 /* Update SGPR and VGPR counts. */
8355 if (shader->prolog) {
8356 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8357 shader->prolog->config.num_sgprs);
8358 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8359 shader->prolog->config.num_vgprs);
8360 }
8361 if (shader->previous_stage) {
8362 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8363 shader->previous_stage->config.num_sgprs);
8364 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8365 shader->previous_stage->config.num_vgprs);
8366 shader->config.spilled_sgprs =
8367 MAX2(shader->config.spilled_sgprs,
8368 shader->previous_stage->config.spilled_sgprs);
8369 shader->config.spilled_vgprs =
8370 MAX2(shader->config.spilled_vgprs,
8371 shader->previous_stage->config.spilled_vgprs);
8372 shader->info.private_mem_vgprs =
8373 MAX2(shader->info.private_mem_vgprs,
8374 shader->previous_stage->info.private_mem_vgprs);
8375 shader->config.scratch_bytes_per_wave =
8376 MAX2(shader->config.scratch_bytes_per_wave,
8377 shader->previous_stage->config.scratch_bytes_per_wave);
8378 shader->info.uses_instanceid |=
8379 shader->previous_stage->info.uses_instanceid;
8380 }
8381 if (shader->prolog2) {
8382 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8383 shader->prolog2->config.num_sgprs);
8384 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8385 shader->prolog2->config.num_vgprs);
8386 }
8387 if (shader->epilog) {
8388 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
8389 shader->epilog->config.num_sgprs);
8390 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
8391 shader->epilog->config.num_vgprs);
8392 }
8393 si_calculate_max_simd_waves(shader);
8394 }
8395
8396 if (shader->key.as_ngg) {
8397 assert(!shader->key.as_es && !shader->key.as_ls);
8398 gfx10_ngg_calculate_subgroup_info(shader);
8399 } else if (sscreen->info.chip_class >= GFX9 && sel->type == PIPE_SHADER_GEOMETRY) {
8400 gfx9_get_gs_info(shader->previous_stage_sel, sel, &shader->gs_info);
8401 }
8402
8403 si_fix_resource_usage(sscreen, shader);
8404 si_shader_dump(sscreen, shader, debug, stderr, true);
8405
8406 /* Upload. */
8407 if (!si_shader_binary_upload(sscreen, shader, 0)) {
8408 fprintf(stderr, "LLVM failed to upload shader\n");
8409 return false;
8410 }
8411
8412 return true;
8413 }
8414
8415 void si_shader_destroy(struct si_shader *shader)
8416 {
8417 if (shader->scratch_bo)
8418 si_resource_reference(&shader->scratch_bo, NULL);
8419
8420 si_resource_reference(&shader->bo, NULL);
8421
8422 if (!shader->is_binary_shared)
8423 si_shader_binary_clean(&shader->binary);
8424
8425 free(shader->shader_log);
8426 }