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radeonsi: fix indirect loads of 64 bit constants
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_flow.h"
35 #include "gallivm/lp_bld_misc.h"
36 #include "radeon/radeon_llvm.h"
37 #include "radeon/radeon_elf_util.h"
38 #include "radeon/radeon_llvm_emit.h"
39 #include "util/u_memory.h"
40 #include "util/u_string.h"
41 #include "tgsi/tgsi_build.h"
42 #include "tgsi/tgsi_util.h"
43 #include "tgsi/tgsi_dump.h"
44
45 #include "si_pipe.h"
46 #include "sid.h"
47
48
49 static const char *scratch_rsrc_dword0_symbol =
50 "SCRATCH_RSRC_DWORD0";
51
52 static const char *scratch_rsrc_dword1_symbol =
53 "SCRATCH_RSRC_DWORD1";
54
55 struct si_shader_output_values
56 {
57 LLVMValueRef values[4];
58 unsigned name;
59 unsigned sid;
60 };
61
62 struct si_shader_context
63 {
64 struct radeon_llvm_context radeon_bld;
65 struct si_shader *shader;
66 struct si_screen *screen;
67
68 unsigned type; /* PIPE_SHADER_* specifies the type of shader. */
69 bool is_gs_copy_shader;
70
71 /* Whether to generate the optimized shader variant compiled as a whole
72 * (without a prolog and epilog)
73 */
74 bool is_monolithic;
75
76 int param_streamout_config;
77 int param_streamout_write_index;
78 int param_streamout_offset[4];
79 int param_vertex_id;
80 int param_rel_auto_id;
81 int param_vs_prim_id;
82 int param_instance_id;
83 int param_vertex_index0;
84 int param_tes_u;
85 int param_tes_v;
86 int param_tes_rel_patch_id;
87 int param_tes_patch_id;
88 int param_es2gs_offset;
89 int param_oc_lds;
90
91 /* Sets a bit if the dynamic HS control word was 0x80000000. The bit is
92 * 0x800000 for VS, 0x1 for ES.
93 */
94 int param_tess_offchip;
95
96 LLVMTargetMachineRef tm;
97
98 unsigned invariant_load_md_kind;
99 unsigned range_md_kind;
100 unsigned uniform_md_kind;
101 LLVMValueRef empty_md;
102
103 /* Preloaded descriptors. */
104 LLVMValueRef esgs_ring;
105 LLVMValueRef gsvs_ring[4];
106
107 LLVMValueRef lds;
108 LLVMValueRef gs_next_vertex[4];
109 LLVMValueRef return_value;
110
111 LLVMTypeRef voidt;
112 LLVMTypeRef i1;
113 LLVMTypeRef i8;
114 LLVMTypeRef i32;
115 LLVMTypeRef i64;
116 LLVMTypeRef i128;
117 LLVMTypeRef f32;
118 LLVMTypeRef v16i8;
119 LLVMTypeRef v2i32;
120 LLVMTypeRef v4i32;
121 LLVMTypeRef v4f32;
122 LLVMTypeRef v8i32;
123
124 LLVMValueRef shared_memory;
125 };
126
127 static struct si_shader_context *si_shader_context(
128 struct lp_build_tgsi_context *bld_base)
129 {
130 return (struct si_shader_context *)bld_base;
131 }
132
133 static void si_init_shader_ctx(struct si_shader_context *ctx,
134 struct si_screen *sscreen,
135 struct si_shader *shader,
136 LLVMTargetMachineRef tm);
137
138 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
139 struct lp_build_tgsi_context *bld_base,
140 struct lp_build_emit_data *emit_data);
141
142 static void si_dump_shader_key(unsigned shader, union si_shader_key *key,
143 FILE *f);
144
145 /* Ideally pass the sample mask input to the PS epilog as v13, which
146 * is its usual location, so that the shader doesn't have to add v_mov.
147 */
148 #define PS_EPILOG_SAMPLEMASK_MIN_LOC 13
149
150 /* The VS location of the PrimitiveID input is the same in the epilog,
151 * so that the main shader part doesn't have to move it.
152 */
153 #define VS_EPILOG_PRIMID_LOC 2
154
155 enum {
156 CONST_ADDR_SPACE = 2,
157 LOCAL_ADDR_SPACE = 3,
158 };
159
160 #define SENDMSG_GS 2
161 #define SENDMSG_GS_DONE 3
162
163 #define SENDMSG_GS_OP_NOP (0 << 4)
164 #define SENDMSG_GS_OP_CUT (1 << 4)
165 #define SENDMSG_GS_OP_EMIT (2 << 4)
166 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
167
168 /**
169 * Returns a unique index for a semantic name and index. The index must be
170 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
171 * calculated.
172 */
173 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
174 {
175 switch (semantic_name) {
176 case TGSI_SEMANTIC_POSITION:
177 return 0;
178 case TGSI_SEMANTIC_PSIZE:
179 return 1;
180 case TGSI_SEMANTIC_CLIPDIST:
181 assert(index <= 1);
182 return 2 + index;
183 case TGSI_SEMANTIC_GENERIC:
184 if (index <= 63-4)
185 return 4 + index;
186 else
187 /* same explanation as in the default statement,
188 * the only user hitting this is st/nine.
189 */
190 return 0;
191
192 /* patch indices are completely separate and thus start from 0 */
193 case TGSI_SEMANTIC_TESSOUTER:
194 return 0;
195 case TGSI_SEMANTIC_TESSINNER:
196 return 1;
197 case TGSI_SEMANTIC_PATCH:
198 return 2 + index;
199
200 default:
201 /* Don't fail here. The result of this function is only used
202 * for LS, TCS, TES, and GS, where legacy GL semantics can't
203 * occur, but this function is called for all vertex shaders
204 * before it's known whether LS will be compiled or not.
205 */
206 return 0;
207 }
208 }
209
210 /**
211 * Get the value of a shader input parameter and extract a bitfield.
212 */
213 static LLVMValueRef unpack_param(struct si_shader_context *ctx,
214 unsigned param, unsigned rshift,
215 unsigned bitwidth)
216 {
217 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
218 LLVMValueRef value = LLVMGetParam(ctx->radeon_bld.main_fn,
219 param);
220
221 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
222 value = bitcast(&ctx->radeon_bld.soa.bld_base,
223 TGSI_TYPE_UNSIGNED, value);
224
225 if (rshift)
226 value = LLVMBuildLShr(gallivm->builder, value,
227 lp_build_const_int32(gallivm, rshift), "");
228
229 if (rshift + bitwidth < 32) {
230 unsigned mask = (1 << bitwidth) - 1;
231 value = LLVMBuildAnd(gallivm->builder, value,
232 lp_build_const_int32(gallivm, mask), "");
233 }
234
235 return value;
236 }
237
238 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
239 {
240 switch (ctx->type) {
241 case PIPE_SHADER_TESS_CTRL:
242 return unpack_param(ctx, SI_PARAM_REL_IDS, 0, 8);
243
244 case PIPE_SHADER_TESS_EVAL:
245 return LLVMGetParam(ctx->radeon_bld.main_fn,
246 ctx->param_tes_rel_patch_id);
247
248 default:
249 assert(0);
250 return NULL;
251 }
252 }
253
254 /* Tessellation shaders pass outputs to the next shader using LDS.
255 *
256 * LS outputs = TCS inputs
257 * TCS outputs = TES inputs
258 *
259 * The LDS layout is:
260 * - TCS inputs for patch 0
261 * - TCS inputs for patch 1
262 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
263 * - ...
264 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
265 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
266 * - TCS outputs for patch 1
267 * - Per-patch TCS outputs for patch 1
268 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
269 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
270 * - ...
271 *
272 * All three shaders VS(LS), TCS, TES share the same LDS space.
273 */
274
275 static LLVMValueRef
276 get_tcs_in_patch_stride(struct si_shader_context *ctx)
277 {
278 if (ctx->type == PIPE_SHADER_VERTEX)
279 return unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
280 else if (ctx->type == PIPE_SHADER_TESS_CTRL)
281 return unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
282 else {
283 assert(0);
284 return NULL;
285 }
286 }
287
288 static LLVMValueRef
289 get_tcs_out_patch_stride(struct si_shader_context *ctx)
290 {
291 return unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
292 }
293
294 static LLVMValueRef
295 get_tcs_out_patch0_offset(struct si_shader_context *ctx)
296 {
297 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
298 unpack_param(ctx,
299 SI_PARAM_TCS_OUT_OFFSETS,
300 0, 16),
301 4);
302 }
303
304 static LLVMValueRef
305 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *ctx)
306 {
307 return lp_build_mul_imm(&ctx->radeon_bld.soa.bld_base.uint_bld,
308 unpack_param(ctx,
309 SI_PARAM_TCS_OUT_OFFSETS,
310 16, 16),
311 4);
312 }
313
314 static LLVMValueRef
315 get_tcs_in_current_patch_offset(struct si_shader_context *ctx)
316 {
317 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
318 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
319 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
320
321 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
322 }
323
324 static LLVMValueRef
325 get_tcs_out_current_patch_offset(struct si_shader_context *ctx)
326 {
327 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
328 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
329 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
330 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
331
332 return LLVMBuildAdd(gallivm->builder, patch0_offset,
333 LLVMBuildMul(gallivm->builder, patch_stride,
334 rel_patch_id, ""),
335 "");
336 }
337
338 static LLVMValueRef
339 get_tcs_out_current_patch_data_offset(struct si_shader_context *ctx)
340 {
341 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
342 LLVMValueRef patch0_patch_data_offset =
343 get_tcs_out_patch0_patch_data_offset(ctx);
344 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
345 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
346
347 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
348 LLVMBuildMul(gallivm->builder, patch_stride,
349 rel_patch_id, ""),
350 "");
351 }
352
353 static LLVMValueRef build_gep0(struct si_shader_context *ctx,
354 LLVMValueRef base_ptr, LLVMValueRef index)
355 {
356 LLVMValueRef indices[2] = {
357 LLVMConstInt(ctx->i32, 0, 0),
358 index,
359 };
360 return LLVMBuildGEP(ctx->radeon_bld.gallivm.builder, base_ptr,
361 indices, 2, "");
362 }
363
364 static void build_indexed_store(struct si_shader_context *ctx,
365 LLVMValueRef base_ptr, LLVMValueRef index,
366 LLVMValueRef value)
367 {
368 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
369 struct gallivm_state *gallivm = bld_base->base.gallivm;
370
371 LLVMBuildStore(gallivm->builder, value,
372 build_gep0(ctx, base_ptr, index));
373 }
374
375 /**
376 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
377 * It's equivalent to doing a load from &base_ptr[index].
378 *
379 * \param base_ptr Where the array starts.
380 * \param index The element index into the array.
381 * \param uniform Whether the base_ptr and index can be assumed to be
382 * dynamically uniform
383 */
384 static LLVMValueRef build_indexed_load(struct si_shader_context *ctx,
385 LLVMValueRef base_ptr, LLVMValueRef index,
386 bool uniform)
387 {
388 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
389 struct gallivm_state *gallivm = bld_base->base.gallivm;
390 LLVMValueRef pointer;
391
392 pointer = build_gep0(ctx, base_ptr, index);
393 if (uniform)
394 LLVMSetMetadata(pointer, ctx->uniform_md_kind, ctx->empty_md);
395 return LLVMBuildLoad(gallivm->builder, pointer, "");
396 }
397
398 /**
399 * Do a load from &base_ptr[index], but also add a flag that it's loading
400 * a constant from a dynamically uniform index.
401 */
402 static LLVMValueRef build_indexed_load_const(
403 struct si_shader_context *ctx,
404 LLVMValueRef base_ptr, LLVMValueRef index)
405 {
406 LLVMValueRef result = build_indexed_load(ctx, base_ptr, index, true);
407 LLVMSetMetadata(result, ctx->invariant_load_md_kind, ctx->empty_md);
408 return result;
409 }
410
411 static LLVMValueRef get_instance_index_for_fetch(
412 struct radeon_llvm_context *radeon_bld,
413 unsigned param_start_instance, unsigned divisor)
414 {
415 struct si_shader_context *ctx =
416 si_shader_context(&radeon_bld->soa.bld_base);
417 struct gallivm_state *gallivm = radeon_bld->soa.bld_base.base.gallivm;
418
419 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
420 ctx->param_instance_id);
421
422 /* The division must be done before START_INSTANCE is added. */
423 if (divisor > 1)
424 result = LLVMBuildUDiv(gallivm->builder, result,
425 lp_build_const_int32(gallivm, divisor), "");
426
427 return LLVMBuildAdd(gallivm->builder, result,
428 LLVMGetParam(radeon_bld->main_fn, param_start_instance), "");
429 }
430
431 static void declare_input_vs(
432 struct radeon_llvm_context *radeon_bld,
433 unsigned input_index,
434 const struct tgsi_full_declaration *decl,
435 LLVMValueRef out[4])
436 {
437 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
438 struct gallivm_state *gallivm = base->gallivm;
439 struct si_shader_context *ctx =
440 si_shader_context(&radeon_bld->soa.bld_base);
441 unsigned divisor =
442 ctx->shader->key.vs.prolog.instance_divisors[input_index];
443
444 unsigned chan;
445
446 LLVMValueRef t_list_ptr;
447 LLVMValueRef t_offset;
448 LLVMValueRef t_list;
449 LLVMValueRef attribute_offset;
450 LLVMValueRef buffer_index;
451 LLVMValueRef args[3];
452 LLVMValueRef input;
453
454 /* Load the T list */
455 t_list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
456
457 t_offset = lp_build_const_int32(gallivm, input_index);
458
459 t_list = build_indexed_load_const(ctx, t_list_ptr, t_offset);
460
461 /* Build the attribute offset */
462 attribute_offset = lp_build_const_int32(gallivm, 0);
463
464 if (!ctx->is_monolithic) {
465 buffer_index = LLVMGetParam(radeon_bld->main_fn,
466 ctx->param_vertex_index0 +
467 input_index);
468 } else if (divisor) {
469 /* Build index from instance ID, start instance and divisor */
470 ctx->shader->info.uses_instanceid = true;
471 buffer_index = get_instance_index_for_fetch(&ctx->radeon_bld,
472 SI_PARAM_START_INSTANCE,
473 divisor);
474 } else {
475 /* Load the buffer index for vertices. */
476 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
477 ctx->param_vertex_id);
478 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
479 SI_PARAM_BASE_VERTEX);
480 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
481 }
482
483 args[0] = t_list;
484 args[1] = attribute_offset;
485 args[2] = buffer_index;
486 input = lp_build_intrinsic(gallivm->builder,
487 "llvm.SI.vs.load.input", ctx->v4f32, args, 3,
488 LLVMReadNoneAttribute);
489
490 /* Break up the vec4 into individual components */
491 for (chan = 0; chan < 4; chan++) {
492 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
493 out[chan] = LLVMBuildExtractElement(gallivm->builder,
494 input, llvm_chan, "");
495 }
496 }
497
498 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
499 unsigned swizzle)
500 {
501 struct si_shader_context *ctx = si_shader_context(bld_base);
502
503 if (swizzle > 0)
504 return bld_base->uint_bld.zero;
505
506 switch (ctx->type) {
507 case PIPE_SHADER_VERTEX:
508 return LLVMGetParam(ctx->radeon_bld.main_fn,
509 ctx->param_vs_prim_id);
510 case PIPE_SHADER_TESS_CTRL:
511 return LLVMGetParam(ctx->radeon_bld.main_fn,
512 SI_PARAM_PATCH_ID);
513 case PIPE_SHADER_TESS_EVAL:
514 return LLVMGetParam(ctx->radeon_bld.main_fn,
515 ctx->param_tes_patch_id);
516 case PIPE_SHADER_GEOMETRY:
517 return LLVMGetParam(ctx->radeon_bld.main_fn,
518 SI_PARAM_PRIMITIVE_ID);
519 default:
520 assert(0);
521 return bld_base->uint_bld.zero;
522 }
523 }
524
525 /**
526 * Return the value of tgsi_ind_register for indexing.
527 * This is the indirect index with the constant offset added to it.
528 */
529 static LLVMValueRef get_indirect_index(struct si_shader_context *ctx,
530 const struct tgsi_ind_register *ind,
531 int rel_index)
532 {
533 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
534 LLVMValueRef result;
535
536 result = ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
537 result = LLVMBuildLoad(gallivm->builder, result, "");
538 result = LLVMBuildAdd(gallivm->builder, result,
539 lp_build_const_int32(gallivm, rel_index), "");
540 return result;
541 }
542
543 /**
544 * Like get_indirect_index, but restricts the return value to a (possibly
545 * undefined) value inside [0..num).
546 */
547 static LLVMValueRef get_bounded_indirect_index(struct si_shader_context *ctx,
548 const struct tgsi_ind_register *ind,
549 int rel_index, unsigned num)
550 {
551 LLVMValueRef result = get_indirect_index(ctx, ind, rel_index);
552
553 /* LLVM 3.8: If indirect resource indexing is used:
554 * - SI & CIK hang
555 * - VI crashes
556 */
557 if (HAVE_LLVM <= 0x0308)
558 return LLVMGetUndef(ctx->i32);
559
560 return radeon_llvm_bound_index(&ctx->radeon_bld, result, num);
561 }
562
563
564 /**
565 * Calculate a dword address given an input or output register and a stride.
566 */
567 static LLVMValueRef get_dw_address(struct si_shader_context *ctx,
568 const struct tgsi_full_dst_register *dst,
569 const struct tgsi_full_src_register *src,
570 LLVMValueRef vertex_dw_stride,
571 LLVMValueRef base_addr)
572 {
573 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
574 struct tgsi_shader_info *info = &ctx->shader->selector->info;
575 ubyte *name, *index, *array_first;
576 int first, param;
577 struct tgsi_full_dst_register reg;
578
579 /* Set the register description. The address computation is the same
580 * for sources and destinations. */
581 if (src) {
582 reg.Register.File = src->Register.File;
583 reg.Register.Index = src->Register.Index;
584 reg.Register.Indirect = src->Register.Indirect;
585 reg.Register.Dimension = src->Register.Dimension;
586 reg.Indirect = src->Indirect;
587 reg.Dimension = src->Dimension;
588 reg.DimIndirect = src->DimIndirect;
589 } else
590 reg = *dst;
591
592 /* If the register is 2-dimensional (e.g. an array of vertices
593 * in a primitive), calculate the base address of the vertex. */
594 if (reg.Register.Dimension) {
595 LLVMValueRef index;
596
597 if (reg.Dimension.Indirect)
598 index = get_indirect_index(ctx, &reg.DimIndirect,
599 reg.Dimension.Index);
600 else
601 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
602
603 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
604 LLVMBuildMul(gallivm->builder, index,
605 vertex_dw_stride, ""), "");
606 }
607
608 /* Get information about the register. */
609 if (reg.Register.File == TGSI_FILE_INPUT) {
610 name = info->input_semantic_name;
611 index = info->input_semantic_index;
612 array_first = info->input_array_first;
613 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
614 name = info->output_semantic_name;
615 index = info->output_semantic_index;
616 array_first = info->output_array_first;
617 } else {
618 assert(0);
619 return NULL;
620 }
621
622 if (reg.Register.Indirect) {
623 /* Add the relative address of the element. */
624 LLVMValueRef ind_index;
625
626 if (reg.Indirect.ArrayID)
627 first = array_first[reg.Indirect.ArrayID];
628 else
629 first = reg.Register.Index;
630
631 ind_index = get_indirect_index(ctx, &reg.Indirect,
632 reg.Register.Index - first);
633
634 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
635 LLVMBuildMul(gallivm->builder, ind_index,
636 lp_build_const_int32(gallivm, 4), ""), "");
637
638 param = si_shader_io_get_unique_index(name[first], index[first]);
639 } else {
640 param = si_shader_io_get_unique_index(name[reg.Register.Index],
641 index[reg.Register.Index]);
642 }
643
644 /* Add the base address of the element. */
645 return LLVMBuildAdd(gallivm->builder, base_addr,
646 lp_build_const_int32(gallivm, param * 4), "");
647 }
648
649 /* The offchip buffer layout for TCS->TES is
650 *
651 * - attribute 0 of patch 0 vertex 0
652 * - attribute 0 of patch 0 vertex 1
653 * - attribute 0 of patch 0 vertex 2
654 * ...
655 * - attribute 0 of patch 1 vertex 0
656 * - attribute 0 of patch 1 vertex 1
657 * ...
658 * - attribute 1 of patch 0 vertex 0
659 * - attribute 1 of patch 0 vertex 1
660 * ...
661 * - per patch attribute 0 of patch 0
662 * - per patch attribute 0 of patch 1
663 * ...
664 *
665 * Note that every attribute has 4 components.
666 */
667 static LLVMValueRef get_tcs_tes_buffer_address(struct si_shader_context *ctx,
668 LLVMValueRef vertex_index,
669 LLVMValueRef param_index)
670 {
671 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
672 LLVMValueRef base_addr, vertices_per_patch, num_patches, total_vertices;
673 LLVMValueRef param_stride, constant16;
674
675 vertices_per_patch = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 6);
676 num_patches = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 0, 9);
677 total_vertices = LLVMBuildMul(gallivm->builder, vertices_per_patch,
678 num_patches, "");
679
680 constant16 = lp_build_const_int32(gallivm, 16);
681 if (vertex_index) {
682 base_addr = LLVMBuildMul(gallivm->builder, get_rel_patch_id(ctx),
683 vertices_per_patch, "");
684
685 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
686 vertex_index, "");
687
688 param_stride = total_vertices;
689 } else {
690 base_addr = get_rel_patch_id(ctx);
691 param_stride = num_patches;
692 }
693
694 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
695 LLVMBuildMul(gallivm->builder, param_index,
696 param_stride, ""), "");
697
698 base_addr = LLVMBuildMul(gallivm->builder, base_addr, constant16, "");
699
700 if (!vertex_index) {
701 LLVMValueRef patch_data_offset =
702 unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 16, 16);
703
704 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
705 patch_data_offset, "");
706 }
707 return base_addr;
708 }
709
710 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
711 struct si_shader_context *ctx,
712 const struct tgsi_full_dst_register *dst,
713 const struct tgsi_full_src_register *src)
714 {
715 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
716 struct tgsi_shader_info *info = &ctx->shader->selector->info;
717 ubyte *name, *index, *array_first;
718 struct tgsi_full_src_register reg;
719 LLVMValueRef vertex_index = NULL;
720 LLVMValueRef param_index = NULL;
721 unsigned param_index_base, param_base;
722
723 reg = src ? *src : tgsi_full_src_register_from_dst(dst);
724
725 if (reg.Register.Dimension) {
726
727 if (reg.Dimension.Indirect)
728 vertex_index = get_indirect_index(ctx, &reg.DimIndirect,
729 reg.Dimension.Index);
730 else
731 vertex_index = lp_build_const_int32(gallivm,
732 reg.Dimension.Index);
733 }
734
735 /* Get information about the register. */
736 if (reg.Register.File == TGSI_FILE_INPUT) {
737 name = info->input_semantic_name;
738 index = info->input_semantic_index;
739 array_first = info->input_array_first;
740 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
741 name = info->output_semantic_name;
742 index = info->output_semantic_index;
743 array_first = info->output_array_first;
744 } else {
745 assert(0);
746 return NULL;
747 }
748
749 if (reg.Register.Indirect) {
750 if (reg.Indirect.ArrayID)
751 param_base = array_first[reg.Indirect.ArrayID];
752 else
753 param_base = reg.Register.Index;
754
755 param_index = get_indirect_index(ctx, &reg.Indirect,
756 reg.Register.Index - param_base);
757
758 } else {
759 param_base = reg.Register.Index;
760 param_index = lp_build_const_int32(gallivm, 0);
761 }
762
763 param_index_base = si_shader_io_get_unique_index(name[param_base],
764 index[param_base]);
765
766 param_index = LLVMBuildAdd(gallivm->builder, param_index,
767 lp_build_const_int32(gallivm, param_index_base),
768 "");
769
770 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
771 }
772
773 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
774 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
775 * or v4i32 (num_channels=3,4). */
776 static void build_tbuffer_store(struct si_shader_context *ctx,
777 LLVMValueRef rsrc,
778 LLVMValueRef vdata,
779 unsigned num_channels,
780 LLVMValueRef vaddr,
781 LLVMValueRef soffset,
782 unsigned inst_offset,
783 unsigned dfmt,
784 unsigned nfmt,
785 unsigned offen,
786 unsigned idxen,
787 unsigned glc,
788 unsigned slc,
789 unsigned tfe)
790 {
791 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
792 LLVMValueRef args[] = {
793 rsrc,
794 vdata,
795 LLVMConstInt(ctx->i32, num_channels, 0),
796 vaddr,
797 soffset,
798 LLVMConstInt(ctx->i32, inst_offset, 0),
799 LLVMConstInt(ctx->i32, dfmt, 0),
800 LLVMConstInt(ctx->i32, nfmt, 0),
801 LLVMConstInt(ctx->i32, offen, 0),
802 LLVMConstInt(ctx->i32, idxen, 0),
803 LLVMConstInt(ctx->i32, glc, 0),
804 LLVMConstInt(ctx->i32, slc, 0),
805 LLVMConstInt(ctx->i32, tfe, 0)
806 };
807
808 /* The instruction offset field has 12 bits */
809 assert(offen || inst_offset < (1 << 12));
810
811 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
812 unsigned func = CLAMP(num_channels, 1, 3) - 1;
813 const char *types[] = {"i32", "v2i32", "v4i32"};
814 char name[256];
815 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
816
817 lp_build_intrinsic(gallivm->builder, name, ctx->voidt,
818 args, ARRAY_SIZE(args), 0);
819 }
820
821 static void build_tbuffer_store_dwords(struct si_shader_context *ctx,
822 LLVMValueRef rsrc,
823 LLVMValueRef vdata,
824 unsigned num_channels,
825 LLVMValueRef vaddr,
826 LLVMValueRef soffset,
827 unsigned inst_offset)
828 {
829 static unsigned dfmt[] = {
830 V_008F0C_BUF_DATA_FORMAT_32,
831 V_008F0C_BUF_DATA_FORMAT_32_32,
832 V_008F0C_BUF_DATA_FORMAT_32_32_32,
833 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
834 };
835 assert(num_channels >= 1 && num_channels <= 4);
836
837 build_tbuffer_store(ctx, rsrc, vdata, num_channels, vaddr, soffset,
838 inst_offset, dfmt[num_channels-1],
839 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
840 }
841
842 static LLVMValueRef build_buffer_load(struct si_shader_context *ctx,
843 LLVMValueRef rsrc,
844 int num_channels,
845 LLVMValueRef vindex,
846 LLVMValueRef voffset,
847 LLVMValueRef soffset,
848 unsigned inst_offset,
849 unsigned glc,
850 unsigned slc)
851 {
852 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
853 unsigned func = CLAMP(num_channels, 1, 3) - 1;
854
855 if (HAVE_LLVM >= 0x309) {
856 LLVMValueRef args[] = {
857 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, ""),
858 vindex ? vindex : LLVMConstInt(ctx->i32, 0, 0),
859 LLVMConstInt(ctx->i32, inst_offset, 0),
860 LLVMConstInt(ctx->i1, glc, 0),
861 LLVMConstInt(ctx->i1, slc, 0)
862 };
863
864 LLVMTypeRef types[] = {ctx->f32, LLVMVectorType(ctx->f32, 2),
865 ctx->v4f32};
866 const char *type_names[] = {"f32", "v2f32", "v4f32"};
867 char name[256];
868
869 if (voffset) {
870 args[2] = LLVMBuildAdd(gallivm->builder, args[2], voffset,
871 "");
872 }
873
874 if (soffset) {
875 args[2] = LLVMBuildAdd(gallivm->builder, args[2], soffset,
876 "");
877 }
878
879 snprintf(name, sizeof(name), "llvm.amdgcn.buffer.load.%s",
880 type_names[func]);
881
882 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
883 ARRAY_SIZE(args), LLVMReadOnlyAttribute);
884 } else {
885 LLVMValueRef args[] = {
886 LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v16i8, ""),
887 voffset ? voffset : vindex,
888 soffset,
889 LLVMConstInt(ctx->i32, inst_offset, 0),
890 LLVMConstInt(ctx->i32, voffset ? 1 : 0, 0), // offen
891 LLVMConstInt(ctx->i32, vindex ? 1 : 0, 0), //idxen
892 LLVMConstInt(ctx->i32, glc, 0),
893 LLVMConstInt(ctx->i32, slc, 0),
894 LLVMConstInt(ctx->i32, 0, 0), // TFE
895 };
896
897 LLVMTypeRef types[] = {ctx->i32, LLVMVectorType(ctx->i32, 2),
898 ctx->v4i32};
899 const char *type_names[] = {"i32", "v2i32", "v4i32"};
900 const char *arg_type = "i32";
901 char name[256];
902
903 if (voffset && vindex) {
904 LLVMValueRef vaddr[] = {vindex, voffset};
905
906 arg_type = "v2i32";
907 args[1] = lp_build_gather_values(gallivm, vaddr, 2);
908 }
909
910 snprintf(name, sizeof(name), "llvm.SI.buffer.load.dword.%s.%s",
911 type_names[func], arg_type);
912
913 return lp_build_intrinsic(gallivm->builder, name, types[func], args,
914 ARRAY_SIZE(args), LLVMReadOnlyAttribute);
915 }
916 }
917
918 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
919 enum tgsi_opcode_type type, unsigned swizzle,
920 LLVMValueRef buffer, LLVMValueRef offset,
921 LLVMValueRef base)
922 {
923 struct si_shader_context *ctx = si_shader_context(bld_base);
924 struct gallivm_state *gallivm = bld_base->base.gallivm;
925 LLVMValueRef value, value2;
926 LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
927 LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
928
929 if (swizzle == ~0) {
930 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
931 0, 1, 0);
932
933 return LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
934 }
935
936 if (!tgsi_type_is_64bit(type)) {
937 value = build_buffer_load(ctx, buffer, 4, NULL, base, offset,
938 0, 1, 0);
939
940 value = LLVMBuildBitCast(gallivm->builder, value, vec_type, "");
941 return LLVMBuildExtractElement(gallivm->builder, value,
942 lp_build_const_int32(gallivm, swizzle), "");
943 }
944
945 value = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
946 swizzle * 4, 1, 0);
947
948 value2 = build_buffer_load(ctx, buffer, 1, NULL, base, offset,
949 swizzle * 4 + 4, 1, 0);
950
951 return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
952 }
953
954 /**
955 * Load from LDS.
956 *
957 * \param type output value type
958 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
959 * \param dw_addr address in dwords
960 */
961 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
962 enum tgsi_opcode_type type, unsigned swizzle,
963 LLVMValueRef dw_addr)
964 {
965 struct si_shader_context *ctx = si_shader_context(bld_base);
966 struct gallivm_state *gallivm = bld_base->base.gallivm;
967 LLVMValueRef value;
968
969 if (swizzle == ~0) {
970 LLVMValueRef values[TGSI_NUM_CHANNELS];
971
972 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
973 values[chan] = lds_load(bld_base, type, chan, dw_addr);
974
975 return lp_build_gather_values(bld_base->base.gallivm, values,
976 TGSI_NUM_CHANNELS);
977 }
978
979 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
980 lp_build_const_int32(gallivm, swizzle));
981
982 value = build_indexed_load(ctx, ctx->lds, dw_addr, false);
983 if (tgsi_type_is_64bit(type)) {
984 LLVMValueRef value2;
985 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
986 lp_build_const_int32(gallivm, swizzle + 1));
987 value2 = build_indexed_load(ctx, ctx->lds, dw_addr, false);
988 return radeon_llvm_emit_fetch_64bit(bld_base, type, value, value2);
989 }
990
991 return LLVMBuildBitCast(gallivm->builder, value,
992 tgsi2llvmtype(bld_base, type), "");
993 }
994
995 /**
996 * Store to LDS.
997 *
998 * \param swizzle offset (typically 0..3)
999 * \param dw_addr address in dwords
1000 * \param value value to store
1001 */
1002 static void lds_store(struct lp_build_tgsi_context *bld_base,
1003 unsigned swizzle, LLVMValueRef dw_addr,
1004 LLVMValueRef value)
1005 {
1006 struct si_shader_context *ctx = si_shader_context(bld_base);
1007 struct gallivm_state *gallivm = bld_base->base.gallivm;
1008
1009 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
1010 lp_build_const_int32(gallivm, swizzle));
1011
1012 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1013 build_indexed_store(ctx, ctx->lds,
1014 dw_addr, value);
1015 }
1016
1017 static LLVMValueRef fetch_input_tcs(
1018 struct lp_build_tgsi_context *bld_base,
1019 const struct tgsi_full_src_register *reg,
1020 enum tgsi_opcode_type type, unsigned swizzle)
1021 {
1022 struct si_shader_context *ctx = si_shader_context(bld_base);
1023 LLVMValueRef dw_addr, stride;
1024
1025 stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
1026 dw_addr = get_tcs_in_current_patch_offset(ctx);
1027 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1028
1029 return lds_load(bld_base, type, swizzle, dw_addr);
1030 }
1031
1032 static LLVMValueRef fetch_output_tcs(
1033 struct lp_build_tgsi_context *bld_base,
1034 const struct tgsi_full_src_register *reg,
1035 enum tgsi_opcode_type type, unsigned swizzle)
1036 {
1037 struct si_shader_context *ctx = si_shader_context(bld_base);
1038 LLVMValueRef dw_addr, stride;
1039
1040 if (reg->Register.Dimension) {
1041 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1042 dw_addr = get_tcs_out_current_patch_offset(ctx);
1043 dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
1044 } else {
1045 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1046 dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
1047 }
1048
1049 return lds_load(bld_base, type, swizzle, dw_addr);
1050 }
1051
1052 static LLVMValueRef fetch_input_tes(
1053 struct lp_build_tgsi_context *bld_base,
1054 const struct tgsi_full_src_register *reg,
1055 enum tgsi_opcode_type type, unsigned swizzle)
1056 {
1057 struct si_shader_context *ctx = si_shader_context(bld_base);
1058 struct gallivm_state *gallivm = bld_base->base.gallivm;
1059 LLVMValueRef rw_buffers, buffer, base, addr;
1060
1061 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1062 SI_PARAM_RW_BUFFERS);
1063 buffer = build_indexed_load_const(ctx, rw_buffers,
1064 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1065
1066 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1067 addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
1068
1069 return buffer_load(bld_base, type, swizzle, buffer, base, addr);
1070 }
1071
1072 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
1073 const struct tgsi_full_instruction *inst,
1074 const struct tgsi_opcode_info *info,
1075 LLVMValueRef dst[4])
1076 {
1077 struct si_shader_context *ctx = si_shader_context(bld_base);
1078 struct gallivm_state *gallivm = bld_base->base.gallivm;
1079 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
1080 unsigned chan_index;
1081 LLVMValueRef dw_addr, stride;
1082 LLVMValueRef rw_buffers, buffer, base, buf_addr;
1083 LLVMValueRef values[4];
1084
1085 /* Only handle per-patch and per-vertex outputs here.
1086 * Vectors will be lowered to scalars and this function will be called again.
1087 */
1088 if (reg->Register.File != TGSI_FILE_OUTPUT ||
1089 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
1090 radeon_llvm_emit_store(bld_base, inst, info, dst);
1091 return;
1092 }
1093
1094 if (reg->Register.Dimension) {
1095 stride = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
1096 dw_addr = get_tcs_out_current_patch_offset(ctx);
1097 dw_addr = get_dw_address(ctx, reg, NULL, stride, dw_addr);
1098 } else {
1099 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1100 dw_addr = get_dw_address(ctx, reg, NULL, NULL, dw_addr);
1101 }
1102
1103 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1104 SI_PARAM_RW_BUFFERS);
1105 buffer = build_indexed_load_const(ctx, rw_buffers,
1106 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1107
1108 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1109 buf_addr = get_tcs_tes_buffer_address_from_reg(ctx, reg, NULL);
1110
1111
1112 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
1113 LLVMValueRef value = dst[chan_index];
1114
1115 if (inst->Instruction.Saturate)
1116 value = radeon_llvm_saturate(bld_base, value);
1117
1118 lds_store(bld_base, chan_index, dw_addr, value);
1119
1120 value = LLVMBuildBitCast(gallivm->builder, value, ctx->i32, "");
1121 values[chan_index] = value;
1122
1123 if (inst->Dst[0].Register.WriteMask != 0xF) {
1124 build_tbuffer_store_dwords(ctx, buffer, value, 1,
1125 buf_addr, base,
1126 4 * chan_index);
1127 }
1128 }
1129
1130 if (inst->Dst[0].Register.WriteMask == 0xF) {
1131 LLVMValueRef value = lp_build_gather_values(bld_base->base.gallivm,
1132 values, 4);
1133 build_tbuffer_store_dwords(ctx, buffer, value, 4, buf_addr,
1134 base, 0);
1135 }
1136 }
1137
1138 static LLVMValueRef fetch_input_gs(
1139 struct lp_build_tgsi_context *bld_base,
1140 const struct tgsi_full_src_register *reg,
1141 enum tgsi_opcode_type type,
1142 unsigned swizzle)
1143 {
1144 struct lp_build_context *base = &bld_base->base;
1145 struct si_shader_context *ctx = si_shader_context(bld_base);
1146 struct si_shader *shader = ctx->shader;
1147 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1148 struct gallivm_state *gallivm = base->gallivm;
1149 LLVMValueRef vtx_offset;
1150 LLVMValueRef args[9];
1151 unsigned vtx_offset_param;
1152 struct tgsi_shader_info *info = &shader->selector->info;
1153 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
1154 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
1155 unsigned param;
1156 LLVMValueRef value;
1157
1158 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
1159 return get_primitive_id(bld_base, swizzle);
1160
1161 if (!reg->Register.Dimension)
1162 return NULL;
1163
1164 if (swizzle == ~0) {
1165 LLVMValueRef values[TGSI_NUM_CHANNELS];
1166 unsigned chan;
1167 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1168 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
1169 }
1170 return lp_build_gather_values(bld_base->base.gallivm, values,
1171 TGSI_NUM_CHANNELS);
1172 }
1173
1174 /* Get the vertex offset parameter */
1175 vtx_offset_param = reg->Dimension.Index;
1176 if (vtx_offset_param < 2) {
1177 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
1178 } else {
1179 assert(vtx_offset_param < 6);
1180 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
1181 }
1182 vtx_offset = lp_build_mul_imm(uint,
1183 LLVMGetParam(ctx->radeon_bld.main_fn,
1184 vtx_offset_param),
1185 4);
1186
1187 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
1188 args[0] = ctx->esgs_ring;
1189 args[1] = vtx_offset;
1190 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
1191 args[3] = uint->zero;
1192 args[4] = uint->one; /* OFFEN */
1193 args[5] = uint->zero; /* IDXEN */
1194 args[6] = uint->one; /* GLC */
1195 args[7] = uint->zero; /* SLC */
1196 args[8] = uint->zero; /* TFE */
1197
1198 value = lp_build_intrinsic(gallivm->builder,
1199 "llvm.SI.buffer.load.dword.i32.i32",
1200 ctx->i32, args, 9,
1201 LLVMReadOnlyAttribute);
1202 if (tgsi_type_is_64bit(type)) {
1203 LLVMValueRef value2;
1204 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
1205 value2 = lp_build_intrinsic(gallivm->builder,
1206 "llvm.SI.buffer.load.dword.i32.i32",
1207 ctx->i32, args, 9,
1208 LLVMReadOnlyAttribute);
1209 return radeon_llvm_emit_fetch_64bit(bld_base, type,
1210 value, value2);
1211 }
1212 return LLVMBuildBitCast(gallivm->builder,
1213 value,
1214 tgsi2llvmtype(bld_base, type), "");
1215 }
1216
1217 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
1218 {
1219 switch (interpolate) {
1220 case TGSI_INTERPOLATE_CONSTANT:
1221 return 0;
1222
1223 case TGSI_INTERPOLATE_LINEAR:
1224 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1225 return SI_PARAM_LINEAR_SAMPLE;
1226 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1227 return SI_PARAM_LINEAR_CENTROID;
1228 else
1229 return SI_PARAM_LINEAR_CENTER;
1230 break;
1231 case TGSI_INTERPOLATE_COLOR:
1232 case TGSI_INTERPOLATE_PERSPECTIVE:
1233 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
1234 return SI_PARAM_PERSP_SAMPLE;
1235 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
1236 return SI_PARAM_PERSP_CENTROID;
1237 else
1238 return SI_PARAM_PERSP_CENTER;
1239 break;
1240 default:
1241 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
1242 return -1;
1243 }
1244 }
1245
1246 /* This shouldn't be used by explicit INTERP opcodes. */
1247 static unsigned select_interp_param(struct si_shader_context *ctx,
1248 unsigned param)
1249 {
1250 if (!ctx->is_monolithic)
1251 return param;
1252
1253 if (ctx->shader->key.ps.prolog.force_persp_sample_interp) {
1254 switch (param) {
1255 case SI_PARAM_PERSP_CENTROID:
1256 case SI_PARAM_PERSP_CENTER:
1257 return SI_PARAM_PERSP_SAMPLE;
1258 }
1259 }
1260 if (ctx->shader->key.ps.prolog.force_linear_sample_interp) {
1261 switch (param) {
1262 case SI_PARAM_LINEAR_CENTROID:
1263 case SI_PARAM_LINEAR_CENTER:
1264 return SI_PARAM_LINEAR_SAMPLE;
1265 }
1266 }
1267 if (ctx->shader->key.ps.prolog.force_persp_center_interp) {
1268 switch (param) {
1269 case SI_PARAM_PERSP_CENTROID:
1270 case SI_PARAM_PERSP_SAMPLE:
1271 return SI_PARAM_PERSP_CENTER;
1272 }
1273 }
1274 if (ctx->shader->key.ps.prolog.force_linear_center_interp) {
1275 switch (param) {
1276 case SI_PARAM_LINEAR_CENTROID:
1277 case SI_PARAM_LINEAR_SAMPLE:
1278 return SI_PARAM_LINEAR_CENTER;
1279 }
1280 }
1281
1282 return param;
1283 }
1284
1285 /**
1286 * Interpolate a fragment shader input.
1287 *
1288 * @param ctx context
1289 * @param input_index index of the input in hardware
1290 * @param semantic_name TGSI_SEMANTIC_*
1291 * @param semantic_index semantic index
1292 * @param num_interp_inputs number of all interpolated inputs (= BCOLOR offset)
1293 * @param colors_read_mask color components read (4 bits for each color, 8 bits in total)
1294 * @param interp_param interpolation weights (i,j)
1295 * @param prim_mask SI_PARAM_PRIM_MASK
1296 * @param face SI_PARAM_FRONT_FACE
1297 * @param result the return value (4 components)
1298 */
1299 static void interp_fs_input(struct si_shader_context *ctx,
1300 unsigned input_index,
1301 unsigned semantic_name,
1302 unsigned semantic_index,
1303 unsigned num_interp_inputs,
1304 unsigned colors_read_mask,
1305 LLVMValueRef interp_param,
1306 LLVMValueRef prim_mask,
1307 LLVMValueRef face,
1308 LLVMValueRef result[4])
1309 {
1310 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
1311 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
1312 struct gallivm_state *gallivm = base->gallivm;
1313 const char *intr_name;
1314 LLVMValueRef attr_number;
1315
1316 unsigned chan;
1317
1318 attr_number = lp_build_const_int32(gallivm, input_index);
1319
1320 /* fs.constant returns the param from the middle vertex, so it's not
1321 * really useful for flat shading. It's meant to be used for custom
1322 * interpolation (but the intrinsic can't fetch from the other two
1323 * vertices).
1324 *
1325 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
1326 * to do the right thing. The only reason we use fs.constant is that
1327 * fs.interp cannot be used on integers, because they can be equal
1328 * to NaN.
1329 */
1330 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
1331
1332 if (semantic_name == TGSI_SEMANTIC_COLOR &&
1333 ctx->shader->key.ps.prolog.color_two_side) {
1334 LLVMValueRef args[4];
1335 LLVMValueRef is_face_positive;
1336 LLVMValueRef back_attr_number;
1337
1338 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
1339 * otherwise it's at offset "num_inputs".
1340 */
1341 unsigned back_attr_offset = num_interp_inputs;
1342 if (semantic_index == 1 && colors_read_mask & 0xf)
1343 back_attr_offset += 1;
1344
1345 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
1346
1347 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
1348 face, uint->zero, "");
1349
1350 args[2] = prim_mask;
1351 args[3] = interp_param;
1352 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1353 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1354 LLVMValueRef front, back;
1355
1356 args[0] = llvm_chan;
1357 args[1] = attr_number;
1358 front = lp_build_intrinsic(gallivm->builder, intr_name,
1359 ctx->f32, args, args[3] ? 4 : 3,
1360 LLVMReadNoneAttribute);
1361
1362 args[1] = back_attr_number;
1363 back = lp_build_intrinsic(gallivm->builder, intr_name,
1364 ctx->f32, args, args[3] ? 4 : 3,
1365 LLVMReadNoneAttribute);
1366
1367 result[chan] = LLVMBuildSelect(gallivm->builder,
1368 is_face_positive,
1369 front,
1370 back,
1371 "");
1372 }
1373 } else if (semantic_name == TGSI_SEMANTIC_FOG) {
1374 LLVMValueRef args[4];
1375
1376 args[0] = uint->zero;
1377 args[1] = attr_number;
1378 args[2] = prim_mask;
1379 args[3] = interp_param;
1380 result[0] = lp_build_intrinsic(gallivm->builder, intr_name,
1381 ctx->f32, args, args[3] ? 4 : 3,
1382 LLVMReadNoneAttribute);
1383 result[1] =
1384 result[2] = lp_build_const_float(gallivm, 0.0f);
1385 result[3] = lp_build_const_float(gallivm, 1.0f);
1386 } else {
1387 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1388 LLVMValueRef args[4];
1389 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1390
1391 args[0] = llvm_chan;
1392 args[1] = attr_number;
1393 args[2] = prim_mask;
1394 args[3] = interp_param;
1395 result[chan] = lp_build_intrinsic(gallivm->builder, intr_name,
1396 ctx->f32, args, args[3] ? 4 : 3,
1397 LLVMReadNoneAttribute);
1398 }
1399 }
1400 }
1401
1402 /* LLVMGetParam with bc_optimize resolved. */
1403 static LLVMValueRef get_interp_param(struct si_shader_context *ctx,
1404 int interp_param_idx)
1405 {
1406 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
1407 LLVMValueRef main_fn = ctx->radeon_bld.main_fn;
1408 LLVMValueRef param = NULL;
1409
1410 /* Handle PRIM_MASK[31] (bc_optimize). */
1411 if (ctx->is_monolithic &&
1412 ((ctx->shader->key.ps.prolog.bc_optimize_for_persp &&
1413 interp_param_idx == SI_PARAM_PERSP_CENTROID) ||
1414 (ctx->shader->key.ps.prolog.bc_optimize_for_linear &&
1415 interp_param_idx == SI_PARAM_LINEAR_CENTROID))) {
1416 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
1417 * The hw doesn't compute CENTROID if the whole wave only
1418 * contains fully-covered quads.
1419 */
1420 LLVMValueRef bc_optimize =
1421 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
1422 bc_optimize = LLVMBuildLShr(builder,
1423 bc_optimize,
1424 LLVMConstInt(ctx->i32, 31, 0), "");
1425 bc_optimize = LLVMBuildTrunc(builder, bc_optimize, ctx->i1, "");
1426
1427 if (ctx->shader->key.ps.prolog.bc_optimize_for_persp &&
1428 interp_param_idx == SI_PARAM_PERSP_CENTROID) {
1429 param = LLVMBuildSelect(builder, bc_optimize,
1430 LLVMGetParam(main_fn,
1431 SI_PARAM_PERSP_CENTER),
1432 LLVMGetParam(main_fn,
1433 SI_PARAM_PERSP_CENTROID),
1434 "");
1435 }
1436 if (ctx->shader->key.ps.prolog.bc_optimize_for_linear &&
1437 interp_param_idx == SI_PARAM_LINEAR_CENTROID) {
1438 param = LLVMBuildSelect(builder, bc_optimize,
1439 LLVMGetParam(main_fn,
1440 SI_PARAM_LINEAR_CENTER),
1441 LLVMGetParam(main_fn,
1442 SI_PARAM_LINEAR_CENTROID),
1443 "");
1444 }
1445 }
1446
1447 if (!param)
1448 param = LLVMGetParam(main_fn, interp_param_idx);
1449 return param;
1450 }
1451
1452 static void declare_input_fs(
1453 struct radeon_llvm_context *radeon_bld,
1454 unsigned input_index,
1455 const struct tgsi_full_declaration *decl,
1456 LLVMValueRef out[4])
1457 {
1458 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
1459 struct si_shader_context *ctx =
1460 si_shader_context(&radeon_bld->soa.bld_base);
1461 struct si_shader *shader = ctx->shader;
1462 LLVMValueRef main_fn = radeon_bld->main_fn;
1463 LLVMValueRef interp_param = NULL;
1464 int interp_param_idx;
1465
1466 /* Get colors from input VGPRs (set by the prolog). */
1467 if (!ctx->is_monolithic &&
1468 decl->Semantic.Name == TGSI_SEMANTIC_COLOR) {
1469 unsigned i = decl->Semantic.Index;
1470 unsigned colors_read = shader->selector->info.colors_read;
1471 unsigned mask = colors_read >> (i * 4);
1472 unsigned offset = SI_PARAM_POS_FIXED_PT + 1 +
1473 (i ? util_bitcount(colors_read & 0xf) : 0);
1474
1475 out[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : base->undef;
1476 out[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : base->undef;
1477 out[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : base->undef;
1478 out[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : base->undef;
1479 return;
1480 }
1481
1482 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
1483 decl->Interp.Location);
1484 if (interp_param_idx == -1)
1485 return;
1486 else if (interp_param_idx) {
1487 interp_param_idx = select_interp_param(ctx,
1488 interp_param_idx);
1489 interp_param = get_interp_param(ctx, interp_param_idx);
1490 }
1491
1492 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
1493 decl->Interp.Interpolate == TGSI_INTERPOLATE_COLOR &&
1494 ctx->shader->key.ps.prolog.flatshade_colors)
1495 interp_param = NULL; /* load the constant color */
1496
1497 interp_fs_input(ctx, input_index, decl->Semantic.Name,
1498 decl->Semantic.Index, shader->selector->info.num_inputs,
1499 shader->selector->info.colors_read, interp_param,
1500 LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK),
1501 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE),
1502 &out[0]);
1503 }
1504
1505 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1506 {
1507 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1508 SI_PARAM_ANCILLARY, 8, 4);
1509 }
1510
1511 /**
1512 * Set range metadata on an instruction. This can only be used on load and
1513 * call instructions. If you know an instruction can only produce the values
1514 * 0, 1, 2, you would do set_range_metadata(value, 0, 3);
1515 * \p lo is the minimum value inclusive.
1516 * \p hi is the maximum value exclusive.
1517 */
1518 static void set_range_metadata(struct si_shader_context *ctx,
1519 LLVMValueRef value, unsigned lo, unsigned hi)
1520 {
1521 LLVMValueRef range_md, md_args[2];
1522 LLVMTypeRef type = LLVMTypeOf(value);
1523 LLVMContextRef context = LLVMGetTypeContext(type);
1524
1525 md_args[0] = LLVMConstInt(type, lo, false);
1526 md_args[1] = LLVMConstInt(type, hi, false);
1527 range_md = LLVMMDNodeInContext(context, md_args, 2);
1528 LLVMSetMetadata(value, ctx->range_md_kind, range_md);
1529 }
1530
1531 static LLVMValueRef get_thread_id(struct si_shader_context *ctx)
1532 {
1533 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
1534 LLVMValueRef tid;
1535
1536 if (HAVE_LLVM < 0x0308) {
1537 tid = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid",
1538 ctx->i32, NULL, 0, LLVMReadNoneAttribute);
1539 } else {
1540 LLVMValueRef tid_args[2];
1541 tid_args[0] = lp_build_const_int32(gallivm, 0xffffffff);
1542 tid_args[1] = lp_build_const_int32(gallivm, 0);
1543 tid_args[1] = lp_build_intrinsic(gallivm->builder,
1544 "llvm.amdgcn.mbcnt.lo", ctx->i32,
1545 tid_args, 2, LLVMReadNoneAttribute);
1546
1547 tid = lp_build_intrinsic(gallivm->builder,
1548 "llvm.amdgcn.mbcnt.hi", ctx->i32,
1549 tid_args, 2, LLVMReadNoneAttribute);
1550 }
1551 set_range_metadata(ctx, tid, 0, 64);
1552 return tid;
1553 }
1554
1555 /**
1556 * Load a dword from a constant buffer.
1557 */
1558 static LLVMValueRef buffer_load_const(struct si_shader_context *ctx,
1559 LLVMValueRef resource,
1560 LLVMValueRef offset)
1561 {
1562 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
1563 LLVMValueRef args[2] = {resource, offset};
1564
1565 return lp_build_intrinsic(builder, "llvm.SI.load.const", ctx->f32, args, 2,
1566 LLVMReadNoneAttribute);
1567 }
1568
1569 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1570 {
1571 struct si_shader_context *ctx =
1572 si_shader_context(&radeon_bld->soa.bld_base);
1573 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1574 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1575 LLVMBuilderRef builder = gallivm->builder;
1576 LLVMValueRef desc = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1577 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_PS_CONST_SAMPLE_POSITIONS);
1578 LLVMValueRef resource = build_indexed_load_const(ctx, desc, buf_index);
1579
1580 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1581 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1582 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1583
1584 LLVMValueRef pos[4] = {
1585 buffer_load_const(ctx, resource, offset0),
1586 buffer_load_const(ctx, resource, offset1),
1587 lp_build_const_float(gallivm, 0),
1588 lp_build_const_float(gallivm, 0)
1589 };
1590
1591 return lp_build_gather_values(gallivm, pos, 4);
1592 }
1593
1594 static void declare_system_value(
1595 struct radeon_llvm_context *radeon_bld,
1596 unsigned index,
1597 const struct tgsi_full_declaration *decl)
1598 {
1599 struct si_shader_context *ctx =
1600 si_shader_context(&radeon_bld->soa.bld_base);
1601 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1602 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1603 LLVMValueRef value = 0;
1604
1605 switch (decl->Semantic.Name) {
1606 case TGSI_SEMANTIC_INSTANCEID:
1607 value = LLVMGetParam(radeon_bld->main_fn,
1608 ctx->param_instance_id);
1609 break;
1610
1611 case TGSI_SEMANTIC_VERTEXID:
1612 value = LLVMBuildAdd(gallivm->builder,
1613 LLVMGetParam(radeon_bld->main_fn,
1614 ctx->param_vertex_id),
1615 LLVMGetParam(radeon_bld->main_fn,
1616 SI_PARAM_BASE_VERTEX), "");
1617 break;
1618
1619 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1620 value = LLVMGetParam(radeon_bld->main_fn,
1621 ctx->param_vertex_id);
1622 break;
1623
1624 case TGSI_SEMANTIC_BASEVERTEX:
1625 value = LLVMGetParam(radeon_bld->main_fn,
1626 SI_PARAM_BASE_VERTEX);
1627 break;
1628
1629 case TGSI_SEMANTIC_BASEINSTANCE:
1630 value = LLVMGetParam(radeon_bld->main_fn,
1631 SI_PARAM_START_INSTANCE);
1632 break;
1633
1634 case TGSI_SEMANTIC_DRAWID:
1635 value = LLVMGetParam(radeon_bld->main_fn,
1636 SI_PARAM_DRAWID);
1637 break;
1638
1639 case TGSI_SEMANTIC_INVOCATIONID:
1640 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1641 value = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
1642 else if (ctx->type == PIPE_SHADER_GEOMETRY)
1643 value = LLVMGetParam(radeon_bld->main_fn,
1644 SI_PARAM_GS_INSTANCE_ID);
1645 else
1646 assert(!"INVOCATIONID not implemented");
1647 break;
1648
1649 case TGSI_SEMANTIC_POSITION:
1650 {
1651 LLVMValueRef pos[4] = {
1652 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1653 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1654 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1655 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1656 LLVMGetParam(radeon_bld->main_fn,
1657 SI_PARAM_POS_W_FLOAT)),
1658 };
1659 value = lp_build_gather_values(gallivm, pos, 4);
1660 break;
1661 }
1662
1663 case TGSI_SEMANTIC_FACE:
1664 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1665 break;
1666
1667 case TGSI_SEMANTIC_SAMPLEID:
1668 value = get_sample_id(radeon_bld);
1669 break;
1670
1671 case TGSI_SEMANTIC_SAMPLEPOS: {
1672 LLVMValueRef pos[4] = {
1673 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1674 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1675 lp_build_const_float(gallivm, 0),
1676 lp_build_const_float(gallivm, 0)
1677 };
1678 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1679 TGSI_OPCODE_FRC, pos[0]);
1680 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1681 TGSI_OPCODE_FRC, pos[1]);
1682 value = lp_build_gather_values(gallivm, pos, 4);
1683 break;
1684 }
1685
1686 case TGSI_SEMANTIC_SAMPLEMASK:
1687 /* This can only occur with the OpenGL Core profile, which
1688 * doesn't support smoothing.
1689 */
1690 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1691 break;
1692
1693 case TGSI_SEMANTIC_TESSCOORD:
1694 {
1695 LLVMValueRef coord[4] = {
1696 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_u),
1697 LLVMGetParam(radeon_bld->main_fn, ctx->param_tes_v),
1698 bld->zero,
1699 bld->zero
1700 };
1701
1702 /* For triangles, the vector should be (u, v, 1-u-v). */
1703 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1704 PIPE_PRIM_TRIANGLES)
1705 coord[2] = lp_build_sub(bld, bld->one,
1706 lp_build_add(bld, coord[0], coord[1]));
1707
1708 value = lp_build_gather_values(gallivm, coord, 4);
1709 break;
1710 }
1711
1712 case TGSI_SEMANTIC_VERTICESIN:
1713 if (ctx->type == PIPE_SHADER_TESS_CTRL)
1714 value = unpack_param(ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1715 else if (ctx->type == PIPE_SHADER_TESS_EVAL)
1716 value = unpack_param(ctx, SI_PARAM_TCS_OFFCHIP_LAYOUT, 9, 7);
1717 else
1718 assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
1719 break;
1720
1721 case TGSI_SEMANTIC_TESSINNER:
1722 case TGSI_SEMANTIC_TESSOUTER:
1723 {
1724 LLVMValueRef rw_buffers, buffer, base, addr;
1725 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1726
1727 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
1728 SI_PARAM_RW_BUFFERS);
1729 buffer = build_indexed_load_const(ctx, rw_buffers,
1730 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
1731
1732 base = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
1733 addr = get_tcs_tes_buffer_address(ctx, NULL,
1734 lp_build_const_int32(gallivm, param));
1735
1736 value = buffer_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1737 ~0, buffer, base, addr);
1738
1739 break;
1740 }
1741
1742 case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
1743 case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:
1744 {
1745 LLVMValueRef buf, slot, val[4];
1746 int i, offset;
1747
1748 slot = lp_build_const_int32(gallivm, SI_HS_CONST_DEFAULT_TESS_LEVELS);
1749 buf = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
1750 buf = build_indexed_load_const(ctx, buf, slot);
1751 offset = decl->Semantic.Name == TGSI_SEMANTIC_DEFAULT_TESSINNER_SI ? 4 : 0;
1752
1753 for (i = 0; i < 4; i++)
1754 val[i] = buffer_load_const(ctx, buf,
1755 lp_build_const_int32(gallivm, (offset + i) * 4));
1756 value = lp_build_gather_values(gallivm, val, 4);
1757 break;
1758 }
1759
1760 case TGSI_SEMANTIC_PRIMID:
1761 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1762 break;
1763
1764 case TGSI_SEMANTIC_GRID_SIZE:
1765 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_GRID_SIZE);
1766 break;
1767
1768 case TGSI_SEMANTIC_BLOCK_SIZE:
1769 {
1770 LLVMValueRef values[3];
1771 unsigned i;
1772 unsigned *properties = ctx->shader->selector->info.properties;
1773
1774 if (properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] != 0) {
1775 unsigned sizes[3] = {
1776 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH],
1777 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT],
1778 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH]
1779 };
1780
1781 for (i = 0; i < 3; ++i)
1782 values[i] = lp_build_const_int32(gallivm, sizes[i]);
1783
1784 value = lp_build_gather_values(gallivm, values, 3);
1785 } else {
1786 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_SIZE);
1787 }
1788 break;
1789 }
1790
1791 case TGSI_SEMANTIC_BLOCK_ID:
1792 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_BLOCK_ID);
1793 break;
1794
1795 case TGSI_SEMANTIC_THREAD_ID:
1796 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_THREAD_ID);
1797 break;
1798
1799 #if HAVE_LLVM >= 0x0309
1800 case TGSI_SEMANTIC_HELPER_INVOCATION:
1801 value = lp_build_intrinsic(gallivm->builder,
1802 "llvm.amdgcn.ps.live",
1803 ctx->i1, NULL, 0,
1804 LLVMReadNoneAttribute);
1805 value = LLVMBuildNot(gallivm->builder, value, "");
1806 value = LLVMBuildSExt(gallivm->builder, value, ctx->i32, "");
1807 break;
1808 #endif
1809
1810 default:
1811 assert(!"unknown system value");
1812 return;
1813 }
1814
1815 radeon_bld->system_values[index] = value;
1816 }
1817
1818 static void declare_compute_memory(struct radeon_llvm_context *radeon_bld,
1819 const struct tgsi_full_declaration *decl)
1820 {
1821 struct si_shader_context *ctx =
1822 si_shader_context(&radeon_bld->soa.bld_base);
1823 struct si_shader_selector *sel = ctx->shader->selector;
1824 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1825
1826 LLVMTypeRef i8p = LLVMPointerType(ctx->i8, LOCAL_ADDR_SPACE);
1827 LLVMValueRef var;
1828
1829 assert(decl->Declaration.MemType == TGSI_MEMORY_TYPE_SHARED);
1830 assert(decl->Range.First == decl->Range.Last);
1831 assert(!ctx->shared_memory);
1832
1833 var = LLVMAddGlobalInAddressSpace(gallivm->module,
1834 LLVMArrayType(ctx->i8, sel->local_size),
1835 "compute_lds",
1836 LOCAL_ADDR_SPACE);
1837 LLVMSetAlignment(var, 4);
1838
1839 ctx->shared_memory = LLVMBuildBitCast(gallivm->builder, var, i8p, "");
1840 }
1841
1842 static LLVMValueRef load_const_buffer_desc(struct si_shader_context *ctx, int i)
1843 {
1844 LLVMValueRef list_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
1845 SI_PARAM_CONST_BUFFERS);
1846
1847 return build_indexed_load_const(ctx, list_ptr,
1848 LLVMConstInt(ctx->i32, i, 0));
1849 }
1850
1851 static LLVMValueRef fetch_constant(
1852 struct lp_build_tgsi_context *bld_base,
1853 const struct tgsi_full_src_register *reg,
1854 enum tgsi_opcode_type type,
1855 unsigned swizzle)
1856 {
1857 struct si_shader_context *ctx = si_shader_context(bld_base);
1858 struct lp_build_context *base = &bld_base->base;
1859 const struct tgsi_ind_register *ireg = &reg->Indirect;
1860 unsigned buf, idx;
1861
1862 LLVMValueRef addr, bufp;
1863 LLVMValueRef result;
1864
1865 if (swizzle == LP_CHAN_ALL) {
1866 unsigned chan;
1867 LLVMValueRef values[4];
1868 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1869 values[chan] = fetch_constant(bld_base, reg, type, chan);
1870
1871 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1872 }
1873
1874 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1875 idx = reg->Register.Index * 4 + swizzle;
1876
1877 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1878 LLVMValueRef c0, c1, desc;
1879
1880 desc = load_const_buffer_desc(ctx, buf);
1881 c0 = buffer_load_const(ctx, desc,
1882 LLVMConstInt(ctx->i32, idx * 4, 0));
1883
1884 if (!tgsi_type_is_64bit(type))
1885 return bitcast(bld_base, type, c0);
1886 else {
1887 c1 = buffer_load_const(ctx, desc,
1888 LLVMConstInt(ctx->i32,
1889 (idx + 1) * 4, 0));
1890 return radeon_llvm_emit_fetch_64bit(bld_base, type,
1891 c0, c1);
1892 }
1893 }
1894
1895 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1896 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1897 LLVMValueRef index;
1898 index = get_bounded_indirect_index(ctx, &reg->DimIndirect,
1899 reg->Dimension.Index,
1900 SI_NUM_CONST_BUFFERS);
1901 bufp = build_indexed_load_const(ctx, ptr, index);
1902 } else
1903 bufp = load_const_buffer_desc(ctx, buf);
1904
1905 addr = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1906 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1907 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1908 addr = lp_build_add(&bld_base->uint_bld, addr,
1909 lp_build_const_int32(base->gallivm, idx * 4));
1910
1911 result = buffer_load_const(ctx, bufp, addr);
1912
1913 if (!tgsi_type_is_64bit(type))
1914 result = bitcast(bld_base, type, result);
1915 else {
1916 LLVMValueRef addr2, result2;
1917 addr2 = ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1918 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1919 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1920 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1921 lp_build_const_int32(base->gallivm, (idx + 1) * 4));
1922
1923 result2 = buffer_load_const(ctx, bufp, addr2);
1924
1925 result = radeon_llvm_emit_fetch_64bit(bld_base, type,
1926 result, result2);
1927 }
1928 return result;
1929 }
1930
1931 /* Upper 16 bits must be zero. */
1932 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1933 LLVMValueRef val[2])
1934 {
1935 return LLVMBuildOr(gallivm->builder, val[0],
1936 LLVMBuildShl(gallivm->builder, val[1],
1937 lp_build_const_int32(gallivm, 16),
1938 ""), "");
1939 }
1940
1941 /* Upper 16 bits are ignored and will be dropped. */
1942 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1943 LLVMValueRef val[2])
1944 {
1945 LLVMValueRef v[2] = {
1946 LLVMBuildAnd(gallivm->builder, val[0],
1947 lp_build_const_int32(gallivm, 0xffff), ""),
1948 val[1],
1949 };
1950 return si_llvm_pack_two_int16(gallivm, v);
1951 }
1952
1953 /* Initialize arguments for the shader export intrinsic */
1954 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1955 LLVMValueRef *values,
1956 unsigned target,
1957 LLVMValueRef *args)
1958 {
1959 struct si_shader_context *ctx = si_shader_context(bld_base);
1960 struct lp_build_context *uint =
1961 &ctx->radeon_bld.soa.bld_base.uint_bld;
1962 struct lp_build_context *base = &bld_base->base;
1963 struct gallivm_state *gallivm = base->gallivm;
1964 LLVMBuilderRef builder = base->gallivm->builder;
1965 LLVMValueRef val[4];
1966 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1967 unsigned chan;
1968 bool is_int8;
1969
1970 /* Default is 0xf. Adjusted below depending on the format. */
1971 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1972
1973 /* Specify whether the EXEC mask represents the valid mask */
1974 args[1] = uint->zero;
1975
1976 /* Specify whether this is the last export */
1977 args[2] = uint->zero;
1978
1979 /* Specify the target we are exporting */
1980 args[3] = lp_build_const_int32(base->gallivm, target);
1981
1982 if (ctx->type == PIPE_SHADER_FRAGMENT) {
1983 const union si_shader_key *key = &ctx->shader->key;
1984 unsigned col_formats = key->ps.epilog.spi_shader_col_format;
1985 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1986
1987 assert(cbuf >= 0 && cbuf < 8);
1988 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1989 is_int8 = (key->ps.epilog.color_is_int8 >> cbuf) & 0x1;
1990 }
1991
1992 args[4] = uint->zero; /* COMPR flag */
1993 args[5] = base->undef;
1994 args[6] = base->undef;
1995 args[7] = base->undef;
1996 args[8] = base->undef;
1997
1998 switch (spi_shader_col_format) {
1999 case V_028714_SPI_SHADER_ZERO:
2000 args[0] = uint->zero; /* writemask */
2001 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2002 break;
2003
2004 case V_028714_SPI_SHADER_32_R:
2005 args[0] = uint->one; /* writemask */
2006 args[5] = values[0];
2007 break;
2008
2009 case V_028714_SPI_SHADER_32_GR:
2010 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
2011 args[5] = values[0];
2012 args[6] = values[1];
2013 break;
2014
2015 case V_028714_SPI_SHADER_32_AR:
2016 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
2017 args[5] = values[0];
2018 args[8] = values[3];
2019 break;
2020
2021 case V_028714_SPI_SHADER_FP16_ABGR:
2022 args[4] = uint->one; /* COMPR flag */
2023
2024 for (chan = 0; chan < 2; chan++) {
2025 LLVMValueRef pack_args[2] = {
2026 values[2 * chan],
2027 values[2 * chan + 1]
2028 };
2029 LLVMValueRef packed;
2030
2031 packed = lp_build_intrinsic(base->gallivm->builder,
2032 "llvm.SI.packf16",
2033 ctx->i32, pack_args, 2,
2034 LLVMReadNoneAttribute);
2035 args[chan + 5] =
2036 LLVMBuildBitCast(base->gallivm->builder,
2037 packed, ctx->f32, "");
2038 }
2039 break;
2040
2041 case V_028714_SPI_SHADER_UNORM16_ABGR:
2042 for (chan = 0; chan < 4; chan++) {
2043 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
2044 val[chan] = LLVMBuildFMul(builder, val[chan],
2045 lp_build_const_float(gallivm, 65535), "");
2046 val[chan] = LLVMBuildFAdd(builder, val[chan],
2047 lp_build_const_float(gallivm, 0.5), "");
2048 val[chan] = LLVMBuildFPToUI(builder, val[chan],
2049 ctx->i32, "");
2050 }
2051
2052 args[4] = uint->one; /* COMPR flag */
2053 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2054 si_llvm_pack_two_int16(gallivm, val));
2055 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2056 si_llvm_pack_two_int16(gallivm, val+2));
2057 break;
2058
2059 case V_028714_SPI_SHADER_SNORM16_ABGR:
2060 for (chan = 0; chan < 4; chan++) {
2061 /* Clamp between [-1, 1]. */
2062 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
2063 values[chan],
2064 lp_build_const_float(gallivm, 1));
2065 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
2066 val[chan],
2067 lp_build_const_float(gallivm, -1));
2068 /* Convert to a signed integer in [-32767, 32767]. */
2069 val[chan] = LLVMBuildFMul(builder, val[chan],
2070 lp_build_const_float(gallivm, 32767), "");
2071 /* If positive, add 0.5, else add -0.5. */
2072 val[chan] = LLVMBuildFAdd(builder, val[chan],
2073 LLVMBuildSelect(builder,
2074 LLVMBuildFCmp(builder, LLVMRealOGE,
2075 val[chan], base->zero, ""),
2076 lp_build_const_float(gallivm, 0.5),
2077 lp_build_const_float(gallivm, -0.5), ""), "");
2078 val[chan] = LLVMBuildFPToSI(builder, val[chan], ctx->i32, "");
2079 }
2080
2081 args[4] = uint->one; /* COMPR flag */
2082 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2083 si_llvm_pack_two_int32_as_int16(gallivm, val));
2084 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2085 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2086 break;
2087
2088 case V_028714_SPI_SHADER_UINT16_ABGR: {
2089 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2090 255 : 65535);
2091 /* Clamp. */
2092 for (chan = 0; chan < 4; chan++) {
2093 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2094 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
2095 val[chan], max);
2096 }
2097
2098 args[4] = uint->one; /* COMPR flag */
2099 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2100 si_llvm_pack_two_int16(gallivm, val));
2101 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2102 si_llvm_pack_two_int16(gallivm, val+2));
2103 break;
2104 }
2105
2106 case V_028714_SPI_SHADER_SINT16_ABGR: {
2107 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
2108 127 : 32767);
2109 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
2110 -128 : -32768);
2111 /* Clamp. */
2112 for (chan = 0; chan < 4; chan++) {
2113 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
2114 val[chan] = lp_build_emit_llvm_binary(bld_base,
2115 TGSI_OPCODE_IMIN,
2116 val[chan], max);
2117 val[chan] = lp_build_emit_llvm_binary(bld_base,
2118 TGSI_OPCODE_IMAX,
2119 val[chan], min);
2120 }
2121
2122 args[4] = uint->one; /* COMPR flag */
2123 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2124 si_llvm_pack_two_int32_as_int16(gallivm, val));
2125 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2126 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
2127 break;
2128 }
2129
2130 case V_028714_SPI_SHADER_32_ABGR:
2131 memcpy(&args[5], values, sizeof(values[0]) * 4);
2132 break;
2133 }
2134 }
2135
2136 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
2137 LLVMValueRef alpha)
2138 {
2139 struct si_shader_context *ctx = si_shader_context(bld_base);
2140 struct gallivm_state *gallivm = bld_base->base.gallivm;
2141
2142 if (ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER) {
2143 LLVMValueRef alpha_ref = LLVMGetParam(ctx->radeon_bld.main_fn,
2144 SI_PARAM_ALPHA_REF);
2145
2146 LLVMValueRef alpha_pass =
2147 lp_build_cmp(&bld_base->base,
2148 ctx->shader->key.ps.epilog.alpha_func,
2149 alpha, alpha_ref);
2150 LLVMValueRef arg =
2151 lp_build_select(&bld_base->base,
2152 alpha_pass,
2153 lp_build_const_float(gallivm, 1.0f),
2154 lp_build_const_float(gallivm, -1.0f));
2155
2156 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
2157 ctx->voidt, &arg, 1, 0);
2158 } else {
2159 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kilp",
2160 ctx->voidt, NULL, 0, 0);
2161 }
2162 }
2163
2164 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
2165 LLVMValueRef alpha,
2166 unsigned samplemask_param)
2167 {
2168 struct si_shader_context *ctx = si_shader_context(bld_base);
2169 struct gallivm_state *gallivm = bld_base->base.gallivm;
2170 LLVMValueRef coverage;
2171
2172 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
2173 coverage = LLVMGetParam(ctx->radeon_bld.main_fn,
2174 samplemask_param);
2175 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
2176
2177 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
2178 ctx->i32,
2179 &coverage, 1, LLVMReadNoneAttribute);
2180
2181 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
2182 ctx->f32, "");
2183
2184 coverage = LLVMBuildFMul(gallivm->builder, coverage,
2185 lp_build_const_float(gallivm,
2186 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
2187
2188 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
2189 }
2190
2191 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
2192 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
2193 {
2194 struct si_shader_context *ctx = si_shader_context(bld_base);
2195 struct lp_build_context *base = &bld_base->base;
2196 struct lp_build_context *uint = &ctx->radeon_bld.soa.bld_base.uint_bld;
2197 unsigned reg_index;
2198 unsigned chan;
2199 unsigned const_chan;
2200 LLVMValueRef base_elt;
2201 LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
2202 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm,
2203 SI_VS_CONST_CLIP_PLANES);
2204 LLVMValueRef const_resource = build_indexed_load_const(ctx, ptr, constbuf_index);
2205
2206 for (reg_index = 0; reg_index < 2; reg_index ++) {
2207 LLVMValueRef *args = pos[2 + reg_index];
2208
2209 args[5] =
2210 args[6] =
2211 args[7] =
2212 args[8] = lp_build_const_float(base->gallivm, 0.0f);
2213
2214 /* Compute dot products of position and user clip plane vectors */
2215 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
2216 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
2217 args[1] = lp_build_const_int32(base->gallivm,
2218 ((reg_index * 4 + chan) * 4 +
2219 const_chan) * 4);
2220 base_elt = buffer_load_const(ctx, const_resource,
2221 args[1]);
2222 args[5 + chan] =
2223 lp_build_add(base, args[5 + chan],
2224 lp_build_mul(base, base_elt,
2225 out_elts[const_chan]));
2226 }
2227 }
2228
2229 args[0] = lp_build_const_int32(base->gallivm, 0xf);
2230 args[1] = uint->zero;
2231 args[2] = uint->zero;
2232 args[3] = lp_build_const_int32(base->gallivm,
2233 V_008DFC_SQ_EXP_POS + 2 + reg_index);
2234 args[4] = uint->zero;
2235 }
2236 }
2237
2238 static void si_dump_streamout(struct pipe_stream_output_info *so)
2239 {
2240 unsigned i;
2241
2242 if (so->num_outputs)
2243 fprintf(stderr, "STREAMOUT\n");
2244
2245 for (i = 0; i < so->num_outputs; i++) {
2246 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
2247 so->output[i].start_component;
2248 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
2249 i, so->output[i].output_buffer,
2250 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
2251 so->output[i].register_index,
2252 mask & 1 ? "x" : "",
2253 mask & 2 ? "y" : "",
2254 mask & 4 ? "z" : "",
2255 mask & 8 ? "w" : "");
2256 }
2257 }
2258
2259 /* On SI, the vertex shader is responsible for writing streamout data
2260 * to buffers. */
2261 static void si_llvm_emit_streamout(struct si_shader_context *ctx,
2262 struct si_shader_output_values *outputs,
2263 unsigned noutput)
2264 {
2265 struct pipe_stream_output_info *so = &ctx->shader->selector->so;
2266 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
2267 LLVMBuilderRef builder = gallivm->builder;
2268 int i, j;
2269 struct lp_build_if_state if_ctx;
2270 LLVMValueRef so_buffers[4];
2271 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
2272 SI_PARAM_RW_BUFFERS);
2273
2274 /* Load the descriptors. */
2275 for (i = 0; i < 4; ++i) {
2276 if (ctx->shader->selector->so.stride[i]) {
2277 LLVMValueRef offset = lp_build_const_int32(gallivm,
2278 SI_VS_STREAMOUT_BUF0 + i);
2279
2280 so_buffers[i] = build_indexed_load_const(ctx, buf_ptr, offset);
2281 }
2282 }
2283
2284 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2285 LLVMValueRef so_vtx_count =
2286 unpack_param(ctx, ctx->param_streamout_config, 16, 7);
2287
2288 LLVMValueRef tid = get_thread_id(ctx);
2289
2290 /* can_emit = tid < so_vtx_count; */
2291 LLVMValueRef can_emit =
2292 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
2293
2294 LLVMValueRef stream_id =
2295 unpack_param(ctx, ctx->param_streamout_config, 24, 2);
2296
2297 /* Emit the streamout code conditionally. This actually avoids
2298 * out-of-bounds buffer access. The hw tells us via the SGPR
2299 * (so_vtx_count) which threads are allowed to emit streamout data. */
2300 lp_build_if(&if_ctx, gallivm, can_emit);
2301 {
2302 /* The buffer offset is computed as follows:
2303 * ByteOffset = streamout_offset[buffer_id]*4 +
2304 * (streamout_write_index + thread_id)*stride[buffer_id] +
2305 * attrib_offset
2306 */
2307
2308 LLVMValueRef so_write_index =
2309 LLVMGetParam(ctx->radeon_bld.main_fn,
2310 ctx->param_streamout_write_index);
2311
2312 /* Compute (streamout_write_index + thread_id). */
2313 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
2314
2315 /* Compute the write offset for each enabled buffer. */
2316 LLVMValueRef so_write_offset[4] = {};
2317 for (i = 0; i < 4; i++) {
2318 if (!so->stride[i])
2319 continue;
2320
2321 LLVMValueRef so_offset = LLVMGetParam(ctx->radeon_bld.main_fn,
2322 ctx->param_streamout_offset[i]);
2323 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(ctx->i32, 4, 0), "");
2324
2325 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
2326 LLVMConstInt(ctx->i32, so->stride[i]*4, 0), "");
2327 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
2328 }
2329
2330 /* Write streamout data. */
2331 for (i = 0; i < so->num_outputs; i++) {
2332 unsigned buf_idx = so->output[i].output_buffer;
2333 unsigned reg = so->output[i].register_index;
2334 unsigned start = so->output[i].start_component;
2335 unsigned num_comps = so->output[i].num_components;
2336 unsigned stream = so->output[i].stream;
2337 LLVMValueRef out[4];
2338 struct lp_build_if_state if_ctx_stream;
2339
2340 assert(num_comps && num_comps <= 4);
2341 if (!num_comps || num_comps > 4)
2342 continue;
2343
2344 if (reg >= noutput)
2345 continue;
2346
2347 /* Load the output as int. */
2348 for (j = 0; j < num_comps; j++) {
2349 out[j] = LLVMBuildBitCast(builder,
2350 outputs[reg].values[start+j],
2351 ctx->i32, "");
2352 }
2353
2354 /* Pack the output. */
2355 LLVMValueRef vdata = NULL;
2356
2357 switch (num_comps) {
2358 case 1: /* as i32 */
2359 vdata = out[0];
2360 break;
2361 case 2: /* as v2i32 */
2362 case 3: /* as v4i32 (aligned to 4) */
2363 case 4: /* as v4i32 */
2364 vdata = LLVMGetUndef(LLVMVectorType(ctx->i32, util_next_power_of_two(num_comps)));
2365 for (j = 0; j < num_comps; j++) {
2366 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
2367 LLVMConstInt(ctx->i32, j, 0), "");
2368 }
2369 break;
2370 }
2371
2372 LLVMValueRef can_emit_stream =
2373 LLVMBuildICmp(builder, LLVMIntEQ,
2374 stream_id,
2375 lp_build_const_int32(gallivm, stream), "");
2376
2377 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
2378 build_tbuffer_store_dwords(ctx, so_buffers[buf_idx],
2379 vdata, num_comps,
2380 so_write_offset[buf_idx],
2381 LLVMConstInt(ctx->i32, 0, 0),
2382 so->output[i].dst_offset*4);
2383 lp_build_endif(&if_ctx_stream);
2384 }
2385 }
2386 lp_build_endif(&if_ctx);
2387 }
2388
2389
2390 /* Generate export instructions for hardware VS shader stage */
2391 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
2392 struct si_shader_output_values *outputs,
2393 unsigned noutput)
2394 {
2395 struct si_shader_context *ctx = si_shader_context(bld_base);
2396 struct si_shader *shader = ctx->shader;
2397 struct lp_build_context *base = &bld_base->base;
2398 struct lp_build_context *uint =
2399 &ctx->radeon_bld.soa.bld_base.uint_bld;
2400 LLVMValueRef args[9];
2401 LLVMValueRef pos_args[4][9] = { { 0 } };
2402 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
2403 unsigned semantic_name, semantic_index;
2404 unsigned target;
2405 unsigned param_count = 0;
2406 unsigned pos_idx;
2407 int i;
2408
2409 if (outputs && ctx->shader->selector->so.num_outputs) {
2410 si_llvm_emit_streamout(ctx, outputs, noutput);
2411 }
2412
2413 for (i = 0; i < noutput; i++) {
2414 semantic_name = outputs[i].name;
2415 semantic_index = outputs[i].sid;
2416
2417 handle_semantic:
2418 /* Select the correct target */
2419 switch(semantic_name) {
2420 case TGSI_SEMANTIC_PSIZE:
2421 psize_value = outputs[i].values[0];
2422 continue;
2423 case TGSI_SEMANTIC_EDGEFLAG:
2424 edgeflag_value = outputs[i].values[0];
2425 continue;
2426 case TGSI_SEMANTIC_LAYER:
2427 layer_value = outputs[i].values[0];
2428 semantic_name = TGSI_SEMANTIC_GENERIC;
2429 goto handle_semantic;
2430 case TGSI_SEMANTIC_VIEWPORT_INDEX:
2431 viewport_index_value = outputs[i].values[0];
2432 semantic_name = TGSI_SEMANTIC_GENERIC;
2433 goto handle_semantic;
2434 case TGSI_SEMANTIC_POSITION:
2435 target = V_008DFC_SQ_EXP_POS;
2436 break;
2437 case TGSI_SEMANTIC_COLOR:
2438 case TGSI_SEMANTIC_BCOLOR:
2439 target = V_008DFC_SQ_EXP_PARAM + param_count;
2440 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2441 shader->info.vs_output_param_offset[i] = param_count;
2442 param_count++;
2443 break;
2444 case TGSI_SEMANTIC_CLIPDIST:
2445 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
2446 break;
2447 case TGSI_SEMANTIC_CLIPVERTEX:
2448 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
2449 continue;
2450 case TGSI_SEMANTIC_PRIMID:
2451 case TGSI_SEMANTIC_FOG:
2452 case TGSI_SEMANTIC_TEXCOORD:
2453 case TGSI_SEMANTIC_GENERIC:
2454 target = V_008DFC_SQ_EXP_PARAM + param_count;
2455 assert(i < ARRAY_SIZE(shader->info.vs_output_param_offset));
2456 shader->info.vs_output_param_offset[i] = param_count;
2457 param_count++;
2458 break;
2459 default:
2460 target = 0;
2461 fprintf(stderr,
2462 "Warning: SI unhandled vs output type:%d\n",
2463 semantic_name);
2464 }
2465
2466 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
2467
2468 if (target >= V_008DFC_SQ_EXP_POS &&
2469 target <= (V_008DFC_SQ_EXP_POS + 3)) {
2470 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
2471 args, sizeof(args));
2472 } else {
2473 lp_build_intrinsic(base->gallivm->builder,
2474 "llvm.SI.export", ctx->voidt,
2475 args, 9, 0);
2476 }
2477
2478 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
2479 semantic_name = TGSI_SEMANTIC_GENERIC;
2480 goto handle_semantic;
2481 }
2482 }
2483
2484 shader->info.nr_param_exports = param_count;
2485
2486 /* We need to add the position output manually if it's missing. */
2487 if (!pos_args[0][0]) {
2488 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
2489 pos_args[0][1] = uint->zero; /* EXEC mask */
2490 pos_args[0][2] = uint->zero; /* last export? */
2491 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
2492 pos_args[0][4] = uint->zero; /* COMPR flag */
2493 pos_args[0][5] = base->zero; /* X */
2494 pos_args[0][6] = base->zero; /* Y */
2495 pos_args[0][7] = base->zero; /* Z */
2496 pos_args[0][8] = base->one; /* W */
2497 }
2498
2499 /* Write the misc vector (point size, edgeflag, layer, viewport). */
2500 if (shader->selector->info.writes_psize ||
2501 shader->selector->info.writes_edgeflag ||
2502 shader->selector->info.writes_viewport_index ||
2503 shader->selector->info.writes_layer) {
2504 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
2505 shader->selector->info.writes_psize |
2506 (shader->selector->info.writes_edgeflag << 1) |
2507 (shader->selector->info.writes_layer << 2) |
2508 (shader->selector->info.writes_viewport_index << 3));
2509 pos_args[1][1] = uint->zero; /* EXEC mask */
2510 pos_args[1][2] = uint->zero; /* last export? */
2511 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
2512 pos_args[1][4] = uint->zero; /* COMPR flag */
2513 pos_args[1][5] = base->zero; /* X */
2514 pos_args[1][6] = base->zero; /* Y */
2515 pos_args[1][7] = base->zero; /* Z */
2516 pos_args[1][8] = base->zero; /* W */
2517
2518 if (shader->selector->info.writes_psize)
2519 pos_args[1][5] = psize_value;
2520
2521 if (shader->selector->info.writes_edgeflag) {
2522 /* The output is a float, but the hw expects an integer
2523 * with the first bit containing the edge flag. */
2524 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
2525 edgeflag_value,
2526 ctx->i32, "");
2527 edgeflag_value = lp_build_min(&bld_base->int_bld,
2528 edgeflag_value,
2529 bld_base->int_bld.one);
2530
2531 /* The LLVM intrinsic expects a float. */
2532 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
2533 edgeflag_value,
2534 ctx->f32, "");
2535 }
2536
2537 if (shader->selector->info.writes_layer)
2538 pos_args[1][7] = layer_value;
2539
2540 if (shader->selector->info.writes_viewport_index)
2541 pos_args[1][8] = viewport_index_value;
2542 }
2543
2544 for (i = 0; i < 4; i++)
2545 if (pos_args[i][0])
2546 shader->info.nr_pos_exports++;
2547
2548 pos_idx = 0;
2549 for (i = 0; i < 4; i++) {
2550 if (!pos_args[i][0])
2551 continue;
2552
2553 /* Specify the target we are exporting */
2554 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
2555
2556 if (pos_idx == shader->info.nr_pos_exports)
2557 /* Specify that this is the last export */
2558 pos_args[i][2] = uint->one;
2559
2560 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2561 ctx->voidt, pos_args[i], 9, 0);
2562 }
2563 }
2564
2565 static void si_copy_tcs_inputs(struct lp_build_tgsi_context *bld_base)
2566 {
2567 struct si_shader_context *ctx = si_shader_context(bld_base);
2568 struct gallivm_state *gallivm = bld_base->base.gallivm;
2569 LLVMValueRef invocation_id, rw_buffers, buffer, buffer_offset;
2570 LLVMValueRef lds_vertex_stride, lds_vertex_offset, lds_base;
2571 uint64_t inputs;
2572
2573 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2574
2575 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_RW_BUFFERS);
2576 buffer = build_indexed_load_const(ctx, rw_buffers,
2577 lp_build_const_int32(gallivm, SI_HS_RING_TESS_OFFCHIP));
2578
2579 buffer_offset = LLVMGetParam(ctx->radeon_bld.main_fn, ctx->param_oc_lds);
2580
2581 lds_vertex_stride = unpack_param(ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
2582 lds_vertex_offset = LLVMBuildMul(gallivm->builder, invocation_id,
2583 lds_vertex_stride, "");
2584 lds_base = get_tcs_in_current_patch_offset(ctx);
2585 lds_base = LLVMBuildAdd(gallivm->builder, lds_base, lds_vertex_offset, "");
2586
2587 inputs = ctx->shader->key.tcs.epilog.inputs_to_copy;
2588 while (inputs) {
2589 unsigned i = u_bit_scan64(&inputs);
2590
2591 LLVMValueRef lds_ptr = LLVMBuildAdd(gallivm->builder, lds_base,
2592 lp_build_const_int32(gallivm, 4 * i),
2593 "");
2594
2595 LLVMValueRef buffer_addr = get_tcs_tes_buffer_address(ctx,
2596 invocation_id,
2597 lp_build_const_int32(gallivm, i));
2598
2599 LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
2600 lds_ptr);
2601
2602 build_tbuffer_store_dwords(ctx, buffer, value, 4, buffer_addr,
2603 buffer_offset, 0);
2604 }
2605 }
2606
2607 static void si_write_tess_factors(struct lp_build_tgsi_context *bld_base,
2608 LLVMValueRef rel_patch_id,
2609 LLVMValueRef invocation_id,
2610 LLVMValueRef tcs_out_current_patch_data_offset)
2611 {
2612 struct si_shader_context *ctx = si_shader_context(bld_base);
2613 struct gallivm_state *gallivm = bld_base->base.gallivm;
2614 struct si_shader *shader = ctx->shader;
2615 unsigned tess_inner_index, tess_outer_index;
2616 LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
2617 LLVMValueRef out[6], vec0, vec1, rw_buffers, tf_base;
2618 unsigned stride, outer_comps, inner_comps, i;
2619 struct lp_build_if_state if_ctx, inner_if_ctx;
2620
2621 si_llvm_emit_barrier(NULL, bld_base, NULL);
2622
2623 /* Do this only for invocation 0, because the tess levels are per-patch,
2624 * not per-vertex.
2625 *
2626 * This can't jump, because invocation 0 executes this. It should
2627 * at least mask out the loads and stores for other invocations.
2628 */
2629 lp_build_if(&if_ctx, gallivm,
2630 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2631 invocation_id, bld_base->uint_bld.zero, ""));
2632
2633 /* Determine the layout of one tess factor element in the buffer. */
2634 switch (shader->key.tcs.epilog.prim_mode) {
2635 case PIPE_PRIM_LINES:
2636 stride = 2; /* 2 dwords, 1 vec2 store */
2637 outer_comps = 2;
2638 inner_comps = 0;
2639 break;
2640 case PIPE_PRIM_TRIANGLES:
2641 stride = 4; /* 4 dwords, 1 vec4 store */
2642 outer_comps = 3;
2643 inner_comps = 1;
2644 break;
2645 case PIPE_PRIM_QUADS:
2646 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2647 outer_comps = 4;
2648 inner_comps = 2;
2649 break;
2650 default:
2651 assert(0);
2652 return;
2653 }
2654
2655 /* Load tess_inner and tess_outer from LDS.
2656 * Any invocation can write them, so we can't get them from a temporary.
2657 */
2658 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2659 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2660
2661 lds_base = tcs_out_current_patch_data_offset;
2662 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2663 lp_build_const_int32(gallivm,
2664 tess_inner_index * 4), "");
2665 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2666 lp_build_const_int32(gallivm,
2667 tess_outer_index * 4), "");
2668
2669 for (i = 0; i < outer_comps; i++)
2670 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2671 for (i = 0; i < inner_comps; i++)
2672 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2673
2674 /* Convert the outputs to vectors for stores. */
2675 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2676 vec1 = NULL;
2677
2678 if (stride > 4)
2679 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2680
2681 /* Get the buffer. */
2682 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2683 SI_PARAM_RW_BUFFERS);
2684 buffer = build_indexed_load_const(ctx, rw_buffers,
2685 lp_build_const_int32(gallivm, SI_HS_RING_TESS_FACTOR));
2686
2687 /* Get the offset. */
2688 tf_base = LLVMGetParam(ctx->radeon_bld.main_fn,
2689 SI_PARAM_TESS_FACTOR_OFFSET);
2690 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2691 lp_build_const_int32(gallivm, 4 * stride), "");
2692
2693 lp_build_if(&inner_if_ctx, gallivm,
2694 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
2695 rel_patch_id, bld_base->uint_bld.zero, ""));
2696
2697 /* Store the dynamic HS control word. */
2698 build_tbuffer_store_dwords(ctx, buffer,
2699 lp_build_const_int32(gallivm, 0x80000000),
2700 1, lp_build_const_int32(gallivm, 0), tf_base, 0);
2701
2702 lp_build_endif(&inner_if_ctx);
2703
2704 /* Store the tessellation factors. */
2705 build_tbuffer_store_dwords(ctx, buffer, vec0,
2706 MIN2(stride, 4), byteoffset, tf_base, 4);
2707 if (vec1)
2708 build_tbuffer_store_dwords(ctx, buffer, vec1,
2709 stride - 4, byteoffset, tf_base, 20);
2710 lp_build_endif(&if_ctx);
2711 }
2712
2713 /* This only writes the tessellation factor levels. */
2714 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
2715 {
2716 struct si_shader_context *ctx = si_shader_context(bld_base);
2717 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
2718
2719 rel_patch_id = get_rel_patch_id(ctx);
2720 invocation_id = unpack_param(ctx, SI_PARAM_REL_IDS, 8, 5);
2721 tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
2722
2723 if (!ctx->is_monolithic) {
2724 /* Return epilog parameters from this function. */
2725 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2726 LLVMValueRef ret = ctx->return_value;
2727 LLVMValueRef rw_buffers, rw0, rw1, tf_soffset;
2728 unsigned vgpr;
2729
2730 /* RW_BUFFERS pointer */
2731 rw_buffers = LLVMGetParam(ctx->radeon_bld.main_fn,
2732 SI_PARAM_RW_BUFFERS);
2733 rw_buffers = LLVMBuildPtrToInt(builder, rw_buffers, ctx->i64, "");
2734 rw_buffers = LLVMBuildBitCast(builder, rw_buffers, ctx->v2i32, "");
2735 rw0 = LLVMBuildExtractElement(builder, rw_buffers,
2736 bld_base->uint_bld.zero, "");
2737 rw1 = LLVMBuildExtractElement(builder, rw_buffers,
2738 bld_base->uint_bld.one, "");
2739 ret = LLVMBuildInsertValue(builder, ret, rw0, 0, "");
2740 ret = LLVMBuildInsertValue(builder, ret, rw1, 1, "");
2741
2742 /* Tess factor buffer soffset is after user SGPRs. */
2743 tf_soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2744 SI_PARAM_TESS_FACTOR_OFFSET);
2745 ret = LLVMBuildInsertValue(builder, ret, tf_soffset,
2746 SI_TCS_NUM_USER_SGPR + 1, "");
2747
2748 /* VGPRs */
2749 rel_patch_id = bitcast(bld_base, TGSI_TYPE_FLOAT, rel_patch_id);
2750 invocation_id = bitcast(bld_base, TGSI_TYPE_FLOAT, invocation_id);
2751 tf_lds_offset = bitcast(bld_base, TGSI_TYPE_FLOAT, tf_lds_offset);
2752
2753 vgpr = SI_TCS_NUM_USER_SGPR + 2;
2754 ret = LLVMBuildInsertValue(builder, ret, rel_patch_id, vgpr++, "");
2755 ret = LLVMBuildInsertValue(builder, ret, invocation_id, vgpr++, "");
2756 ret = LLVMBuildInsertValue(builder, ret, tf_lds_offset, vgpr++, "");
2757 ctx->return_value = ret;
2758 return;
2759 }
2760
2761 si_copy_tcs_inputs(bld_base);
2762 si_write_tess_factors(bld_base, rel_patch_id, invocation_id, tf_lds_offset);
2763 }
2764
2765 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
2766 {
2767 struct si_shader_context *ctx = si_shader_context(bld_base);
2768 struct si_shader *shader = ctx->shader;
2769 struct tgsi_shader_info *info = &shader->selector->info;
2770 struct gallivm_state *gallivm = bld_base->base.gallivm;
2771 unsigned i, chan;
2772 LLVMValueRef vertex_id = LLVMGetParam(ctx->radeon_bld.main_fn,
2773 ctx->param_rel_auto_id);
2774 LLVMValueRef vertex_dw_stride =
2775 unpack_param(ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2776 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2777 vertex_dw_stride, "");
2778
2779 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2780 * its inputs from it. */
2781 for (i = 0; i < info->num_outputs; i++) {
2782 LLVMValueRef *out_ptr = ctx->radeon_bld.soa.outputs[i];
2783 unsigned name = info->output_semantic_name[i];
2784 unsigned index = info->output_semantic_index[i];
2785 int param = si_shader_io_get_unique_index(name, index);
2786 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2787 lp_build_const_int32(gallivm, param * 4), "");
2788
2789 for (chan = 0; chan < 4; chan++) {
2790 lds_store(bld_base, chan, dw_addr,
2791 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2792 }
2793 }
2794 }
2795
2796 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
2797 {
2798 struct si_shader_context *ctx = si_shader_context(bld_base);
2799 struct gallivm_state *gallivm = bld_base->base.gallivm;
2800 struct si_shader *es = ctx->shader;
2801 struct tgsi_shader_info *info = &es->selector->info;
2802 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
2803 ctx->param_es2gs_offset);
2804 unsigned chan;
2805 int i;
2806
2807 for (i = 0; i < info->num_outputs; i++) {
2808 LLVMValueRef *out_ptr =
2809 ctx->radeon_bld.soa.outputs[i];
2810 int param_index;
2811
2812 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2813 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2814 continue;
2815
2816 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2817 info->output_semantic_index[i]);
2818
2819 for (chan = 0; chan < 4; chan++) {
2820 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2821 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
2822
2823 build_tbuffer_store(ctx,
2824 ctx->esgs_ring,
2825 out_val, 1,
2826 LLVMGetUndef(ctx->i32), soffset,
2827 (4 * param_index + chan) * 4,
2828 V_008F0C_BUF_DATA_FORMAT_32,
2829 V_008F0C_BUF_NUM_FORMAT_UINT,
2830 0, 0, 1, 1, 0);
2831 }
2832 }
2833 }
2834
2835 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2836 {
2837 struct si_shader_context *ctx = si_shader_context(bld_base);
2838 struct gallivm_state *gallivm = bld_base->base.gallivm;
2839 LLVMValueRef args[2];
2840
2841 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2842 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2843 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2844 ctx->voidt, args, 2, 0);
2845 }
2846
2847 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
2848 {
2849 struct si_shader_context *ctx = si_shader_context(bld_base);
2850 struct gallivm_state *gallivm = bld_base->base.gallivm;
2851 struct tgsi_shader_info *info = &ctx->shader->selector->info;
2852 struct si_shader_output_values *outputs = NULL;
2853 int i,j;
2854
2855 assert(!ctx->is_gs_copy_shader);
2856
2857 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2858
2859 /* Vertex color clamping.
2860 *
2861 * This uses a state constant loaded in a user data SGPR and
2862 * an IF statement is added that clamps all colors if the constant
2863 * is true.
2864 */
2865 if (ctx->type == PIPE_SHADER_VERTEX) {
2866 struct lp_build_if_state if_ctx;
2867 LLVMValueRef cond = NULL;
2868 LLVMValueRef addr, val;
2869
2870 for (i = 0; i < info->num_outputs; i++) {
2871 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2872 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2873 continue;
2874
2875 /* We've found a color. */
2876 if (!cond) {
2877 /* The state is in the first bit of the user SGPR. */
2878 cond = LLVMGetParam(ctx->radeon_bld.main_fn,
2879 SI_PARAM_VS_STATE_BITS);
2880 cond = LLVMBuildTrunc(gallivm->builder, cond,
2881 ctx->i1, "");
2882 lp_build_if(&if_ctx, gallivm, cond);
2883 }
2884
2885 for (j = 0; j < 4; j++) {
2886 addr = ctx->radeon_bld.soa.outputs[i][j];
2887 val = LLVMBuildLoad(gallivm->builder, addr, "");
2888 val = radeon_llvm_saturate(bld_base, val);
2889 LLVMBuildStore(gallivm->builder, val, addr);
2890 }
2891 }
2892
2893 if (cond)
2894 lp_build_endif(&if_ctx);
2895 }
2896
2897 for (i = 0; i < info->num_outputs; i++) {
2898 outputs[i].name = info->output_semantic_name[i];
2899 outputs[i].sid = info->output_semantic_index[i];
2900
2901 for (j = 0; j < 4; j++)
2902 outputs[i].values[j] =
2903 LLVMBuildLoad(gallivm->builder,
2904 ctx->radeon_bld.soa.outputs[i][j],
2905 "");
2906 }
2907
2908 if (ctx->is_monolithic) {
2909 /* Export PrimitiveID when PS needs it. */
2910 if (si_vs_exports_prim_id(ctx->shader)) {
2911 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2912 outputs[i].sid = 0;
2913 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2914 get_primitive_id(bld_base, 0));
2915 outputs[i].values[1] = bld_base->base.undef;
2916 outputs[i].values[2] = bld_base->base.undef;
2917 outputs[i].values[3] = bld_base->base.undef;
2918 i++;
2919 }
2920 } else {
2921 /* Return the primitive ID from the LLVM function. */
2922 ctx->return_value =
2923 LLVMBuildInsertValue(gallivm->builder,
2924 ctx->return_value,
2925 bitcast(bld_base, TGSI_TYPE_FLOAT,
2926 get_primitive_id(bld_base, 0)),
2927 VS_EPILOG_PRIMID_LOC, "");
2928 }
2929
2930 si_llvm_export_vs(bld_base, outputs, i);
2931 FREE(outputs);
2932 }
2933
2934 struct si_ps_exports {
2935 unsigned num;
2936 LLVMValueRef args[10][9];
2937 };
2938
2939 unsigned si_get_spi_shader_z_format(bool writes_z, bool writes_stencil,
2940 bool writes_samplemask)
2941 {
2942 if (writes_z) {
2943 /* Z needs 32 bits. */
2944 if (writes_samplemask)
2945 return V_028710_SPI_SHADER_32_ABGR;
2946 else if (writes_stencil)
2947 return V_028710_SPI_SHADER_32_GR;
2948 else
2949 return V_028710_SPI_SHADER_32_R;
2950 } else if (writes_stencil || writes_samplemask) {
2951 /* Both stencil and sample mask need only 16 bits. */
2952 return V_028710_SPI_SHADER_UINT16_ABGR;
2953 } else {
2954 return V_028710_SPI_SHADER_ZERO;
2955 }
2956 }
2957
2958 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2959 LLVMValueRef depth, LLVMValueRef stencil,
2960 LLVMValueRef samplemask, struct si_ps_exports *exp)
2961 {
2962 struct si_shader_context *ctx = si_shader_context(bld_base);
2963 struct lp_build_context *base = &bld_base->base;
2964 struct lp_build_context *uint = &bld_base->uint_bld;
2965 LLVMValueRef args[9];
2966 unsigned mask = 0;
2967 unsigned format = si_get_spi_shader_z_format(depth != NULL,
2968 stencil != NULL,
2969 samplemask != NULL);
2970
2971 assert(depth || stencil || samplemask);
2972
2973 args[1] = uint->one; /* whether the EXEC mask is valid */
2974 args[2] = uint->one; /* DONE bit */
2975
2976 /* Specify the target we are exporting */
2977 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2978
2979 args[4] = uint->zero; /* COMP flag */
2980 args[5] = base->undef; /* R, depth */
2981 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2982 args[7] = base->undef; /* B, sample mask */
2983 args[8] = base->undef; /* A, alpha to mask */
2984
2985 if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
2986 assert(!depth);
2987 args[4] = uint->one; /* COMPR flag */
2988
2989 if (stencil) {
2990 /* Stencil should be in X[23:16]. */
2991 stencil = bitcast(bld_base, TGSI_TYPE_UNSIGNED, stencil);
2992 stencil = LLVMBuildShl(base->gallivm->builder, stencil,
2993 LLVMConstInt(ctx->i32, 16, 0), "");
2994 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT, stencil);
2995 mask |= 0x3;
2996 }
2997 if (samplemask) {
2998 /* SampleMask should be in Y[15:0]. */
2999 args[6] = samplemask;
3000 mask |= 0xc;
3001 }
3002 } else {
3003 if (depth) {
3004 args[5] = depth;
3005 mask |= 0x1;
3006 }
3007 if (stencil) {
3008 args[6] = stencil;
3009 mask |= 0x2;
3010 }
3011 if (samplemask) {
3012 args[7] = samplemask;
3013 mask |= 0x4;
3014 }
3015 }
3016
3017 /* SI (except OLAND) has a bug that it only looks
3018 * at the X writemask component. */
3019 if (ctx->screen->b.chip_class == SI &&
3020 ctx->screen->b.family != CHIP_OLAND)
3021 mask |= 0x1;
3022
3023 /* Specify which components to enable */
3024 args[0] = lp_build_const_int32(base->gallivm, mask);
3025
3026 memcpy(exp->args[exp->num++], args, sizeof(args));
3027 }
3028
3029 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
3030 LLVMValueRef *color, unsigned index,
3031 unsigned samplemask_param,
3032 bool is_last, struct si_ps_exports *exp)
3033 {
3034 struct si_shader_context *ctx = si_shader_context(bld_base);
3035 struct lp_build_context *base = &bld_base->base;
3036 int i;
3037
3038 /* Clamp color */
3039 if (ctx->shader->key.ps.epilog.clamp_color)
3040 for (i = 0; i < 4; i++)
3041 color[i] = radeon_llvm_saturate(bld_base, color[i]);
3042
3043 /* Alpha to one */
3044 if (ctx->shader->key.ps.epilog.alpha_to_one)
3045 color[3] = base->one;
3046
3047 /* Alpha test */
3048 if (index == 0 &&
3049 ctx->shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS)
3050 si_alpha_test(bld_base, color[3]);
3051
3052 /* Line & polygon smoothing */
3053 if (ctx->shader->key.ps.epilog.poly_line_smoothing)
3054 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3],
3055 samplemask_param);
3056
3057 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3058 if (ctx->shader->key.ps.epilog.last_cbuf > 0) {
3059 LLVMValueRef args[8][9];
3060 int c, last = -1;
3061
3062 /* Get the export arguments, also find out what the last one is. */
3063 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
3064 si_llvm_init_export_args(bld_base, color,
3065 V_008DFC_SQ_EXP_MRT + c, args[c]);
3066 if (args[c][0] != bld_base->uint_bld.zero)
3067 last = c;
3068 }
3069
3070 /* Emit all exports. */
3071 for (c = 0; c <= ctx->shader->key.ps.epilog.last_cbuf; c++) {
3072 if (is_last && last == c) {
3073 args[c][1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3074 args[c][2] = bld_base->uint_bld.one; /* DONE bit */
3075 } else if (args[c][0] == bld_base->uint_bld.zero)
3076 continue; /* unnecessary NULL export */
3077
3078 memcpy(exp->args[exp->num++], args[c], sizeof(args[c]));
3079 }
3080 } else {
3081 LLVMValueRef args[9];
3082
3083 /* Export */
3084 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
3085 args);
3086 if (is_last) {
3087 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
3088 args[2] = bld_base->uint_bld.one; /* DONE bit */
3089 } else if (args[0] == bld_base->uint_bld.zero)
3090 return; /* unnecessary NULL export */
3091
3092 memcpy(exp->args[exp->num++], args, sizeof(args));
3093 }
3094 }
3095
3096 static void si_emit_ps_exports(struct si_shader_context *ctx,
3097 struct si_ps_exports *exp)
3098 {
3099 for (unsigned i = 0; i < exp->num; i++)
3100 lp_build_intrinsic(ctx->radeon_bld.gallivm.builder,
3101 "llvm.SI.export", ctx->voidt,
3102 exp->args[i], 9, 0);
3103 }
3104
3105 static void si_export_null(struct lp_build_tgsi_context *bld_base)
3106 {
3107 struct si_shader_context *ctx = si_shader_context(bld_base);
3108 struct lp_build_context *base = &bld_base->base;
3109 struct lp_build_context *uint = &bld_base->uint_bld;
3110 LLVMValueRef args[9];
3111
3112 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
3113 args[1] = uint->one; /* whether the EXEC mask is valid */
3114 args[2] = uint->one; /* DONE bit */
3115 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
3116 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
3117 args[5] = base->undef; /* R */
3118 args[6] = base->undef; /* G */
3119 args[7] = base->undef; /* B */
3120 args[8] = base->undef; /* A */
3121
3122 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
3123 ctx->voidt, args, 9, 0);
3124 }
3125
3126 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context *bld_base)
3127 {
3128 struct si_shader_context *ctx = si_shader_context(bld_base);
3129 struct si_shader *shader = ctx->shader;
3130 struct lp_build_context *base = &bld_base->base;
3131 struct tgsi_shader_info *info = &shader->selector->info;
3132 LLVMBuilderRef builder = base->gallivm->builder;
3133 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3134 int last_color_export = -1;
3135 int i;
3136 struct si_ps_exports exp = {};
3137
3138 /* Determine the last export. If MRTZ is present, it's always last.
3139 * Otherwise, find the last color export.
3140 */
3141 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask) {
3142 unsigned spi_format = shader->key.ps.epilog.spi_shader_col_format;
3143
3144 /* Don't export NULL and return if alpha-test is enabled. */
3145 if (shader->key.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS &&
3146 shader->key.ps.epilog.alpha_func != PIPE_FUNC_NEVER &&
3147 (spi_format & 0xf) == 0)
3148 spi_format |= V_028714_SPI_SHADER_32_AR;
3149
3150 for (i = 0; i < info->num_outputs; i++) {
3151 unsigned index = info->output_semantic_index[i];
3152
3153 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR)
3154 continue;
3155
3156 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
3157 if (shader->key.ps.epilog.last_cbuf > 0) {
3158 /* Just set this if any of the colorbuffers are enabled. */
3159 if (spi_format &
3160 ((1llu << (4 * (shader->key.ps.epilog.last_cbuf + 1))) - 1))
3161 last_color_export = i;
3162 continue;
3163 }
3164
3165 if ((spi_format >> (index * 4)) & 0xf)
3166 last_color_export = i;
3167 }
3168
3169 /* If there are no outputs, export NULL. */
3170 if (last_color_export == -1) {
3171 si_export_null(bld_base);
3172 return;
3173 }
3174 }
3175
3176 for (i = 0; i < info->num_outputs; i++) {
3177 unsigned semantic_name = info->output_semantic_name[i];
3178 unsigned semantic_index = info->output_semantic_index[i];
3179 unsigned j;
3180 LLVMValueRef color[4] = {};
3181
3182 /* Select the correct target */
3183 switch (semantic_name) {
3184 case TGSI_SEMANTIC_POSITION:
3185 depth = LLVMBuildLoad(builder,
3186 ctx->radeon_bld.soa.outputs[i][2], "");
3187 break;
3188 case TGSI_SEMANTIC_STENCIL:
3189 stencil = LLVMBuildLoad(builder,
3190 ctx->radeon_bld.soa.outputs[i][1], "");
3191 break;
3192 case TGSI_SEMANTIC_SAMPLEMASK:
3193 samplemask = LLVMBuildLoad(builder,
3194 ctx->radeon_bld.soa.outputs[i][0], "");
3195 break;
3196 case TGSI_SEMANTIC_COLOR:
3197 for (j = 0; j < 4; j++)
3198 color[j] = LLVMBuildLoad(builder,
3199 ctx->radeon_bld.soa.outputs[i][j], "");
3200
3201 si_export_mrt_color(bld_base, color, semantic_index,
3202 SI_PARAM_SAMPLE_COVERAGE,
3203 last_color_export == i, &exp);
3204 break;
3205 default:
3206 fprintf(stderr,
3207 "Warning: SI unhandled fs output type:%d\n",
3208 semantic_name);
3209 }
3210 }
3211
3212 if (depth || stencil || samplemask)
3213 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
3214
3215 si_emit_ps_exports(ctx, &exp);
3216 }
3217
3218 /**
3219 * Return PS outputs in this order:
3220 *
3221 * v[0:3] = color0.xyzw
3222 * v[4:7] = color1.xyzw
3223 * ...
3224 * vN+0 = Depth
3225 * vN+1 = Stencil
3226 * vN+2 = SampleMask
3227 * vN+3 = SampleMaskIn (used for OpenGL smoothing)
3228 *
3229 * The alpha-ref SGPR is returned via its original location.
3230 */
3231 static void si_llvm_return_fs_outputs(struct lp_build_tgsi_context *bld_base)
3232 {
3233 struct si_shader_context *ctx = si_shader_context(bld_base);
3234 struct si_shader *shader = ctx->shader;
3235 struct lp_build_context *base = &bld_base->base;
3236 struct tgsi_shader_info *info = &shader->selector->info;
3237 LLVMBuilderRef builder = base->gallivm->builder;
3238 unsigned i, j, first_vgpr, vgpr;
3239
3240 LLVMValueRef color[8][4] = {};
3241 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3242 LLVMValueRef ret;
3243
3244 /* Read the output values. */
3245 for (i = 0; i < info->num_outputs; i++) {
3246 unsigned semantic_name = info->output_semantic_name[i];
3247 unsigned semantic_index = info->output_semantic_index[i];
3248
3249 switch (semantic_name) {
3250 case TGSI_SEMANTIC_COLOR:
3251 assert(semantic_index < 8);
3252 for (j = 0; j < 4; j++) {
3253 LLVMValueRef ptr = ctx->radeon_bld.soa.outputs[i][j];
3254 LLVMValueRef result = LLVMBuildLoad(builder, ptr, "");
3255 color[semantic_index][j] = result;
3256 }
3257 break;
3258 case TGSI_SEMANTIC_POSITION:
3259 depth = LLVMBuildLoad(builder,
3260 ctx->radeon_bld.soa.outputs[i][2], "");
3261 break;
3262 case TGSI_SEMANTIC_STENCIL:
3263 stencil = LLVMBuildLoad(builder,
3264 ctx->radeon_bld.soa.outputs[i][1], "");
3265 break;
3266 case TGSI_SEMANTIC_SAMPLEMASK:
3267 samplemask = LLVMBuildLoad(builder,
3268 ctx->radeon_bld.soa.outputs[i][0], "");
3269 break;
3270 default:
3271 fprintf(stderr, "Warning: SI unhandled fs output type:%d\n",
3272 semantic_name);
3273 }
3274 }
3275
3276 /* Fill the return structure. */
3277 ret = ctx->return_value;
3278
3279 /* Set SGPRs. */
3280 ret = LLVMBuildInsertValue(builder, ret,
3281 bitcast(bld_base, TGSI_TYPE_SIGNED,
3282 LLVMGetParam(ctx->radeon_bld.main_fn,
3283 SI_PARAM_ALPHA_REF)),
3284 SI_SGPR_ALPHA_REF, "");
3285
3286 /* Set VGPRs */
3287 first_vgpr = vgpr = SI_SGPR_ALPHA_REF + 1;
3288 for (i = 0; i < ARRAY_SIZE(color); i++) {
3289 if (!color[i][0])
3290 continue;
3291
3292 for (j = 0; j < 4; j++)
3293 ret = LLVMBuildInsertValue(builder, ret, color[i][j], vgpr++, "");
3294 }
3295 if (depth)
3296 ret = LLVMBuildInsertValue(builder, ret, depth, vgpr++, "");
3297 if (stencil)
3298 ret = LLVMBuildInsertValue(builder, ret, stencil, vgpr++, "");
3299 if (samplemask)
3300 ret = LLVMBuildInsertValue(builder, ret, samplemask, vgpr++, "");
3301
3302 /* Add the input sample mask for smoothing at the end. */
3303 if (vgpr < first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC)
3304 vgpr = first_vgpr + PS_EPILOG_SAMPLEMASK_MIN_LOC;
3305 ret = LLVMBuildInsertValue(builder, ret,
3306 LLVMGetParam(ctx->radeon_bld.main_fn,
3307 SI_PARAM_SAMPLE_COVERAGE), vgpr++, "");
3308
3309 ctx->return_value = ret;
3310 }
3311
3312 /**
3313 * Given a v8i32 resource descriptor for a buffer, extract the size of the
3314 * buffer in number of elements and return it as an i32.
3315 */
3316 static LLVMValueRef get_buffer_size(
3317 struct lp_build_tgsi_context *bld_base,
3318 LLVMValueRef descriptor)
3319 {
3320 struct si_shader_context *ctx = si_shader_context(bld_base);
3321 struct gallivm_state *gallivm = bld_base->base.gallivm;
3322 LLVMBuilderRef builder = gallivm->builder;
3323 LLVMValueRef size =
3324 LLVMBuildExtractElement(builder, descriptor,
3325 lp_build_const_int32(gallivm, 6), "");
3326
3327 if (ctx->screen->b.chip_class >= VI) {
3328 /* On VI, the descriptor contains the size in bytes,
3329 * but TXQ must return the size in elements.
3330 * The stride is always non-zero for resources using TXQ.
3331 */
3332 LLVMValueRef stride =
3333 LLVMBuildExtractElement(builder, descriptor,
3334 lp_build_const_int32(gallivm, 5), "");
3335 stride = LLVMBuildLShr(builder, stride,
3336 lp_build_const_int32(gallivm, 16), "");
3337 stride = LLVMBuildAnd(builder, stride,
3338 lp_build_const_int32(gallivm, 0x3FFF), "");
3339
3340 size = LLVMBuildUDiv(builder, size, stride, "");
3341 }
3342
3343 return size;
3344 }
3345
3346 /**
3347 * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
3348 * intrinsic names).
3349 */
3350 static void build_type_name_for_intr(
3351 LLVMTypeRef type,
3352 char *buf, unsigned bufsize)
3353 {
3354 LLVMTypeRef elem_type = type;
3355
3356 assert(bufsize >= 8);
3357
3358 if (LLVMGetTypeKind(type) == LLVMVectorTypeKind) {
3359 int ret = snprintf(buf, bufsize, "v%u",
3360 LLVMGetVectorSize(type));
3361 if (ret < 0) {
3362 char *type_name = LLVMPrintTypeToString(type);
3363 fprintf(stderr, "Error building type name for: %s\n",
3364 type_name);
3365 return;
3366 }
3367 elem_type = LLVMGetElementType(type);
3368 buf += ret;
3369 bufsize -= ret;
3370 }
3371 switch (LLVMGetTypeKind(elem_type)) {
3372 default: break;
3373 case LLVMIntegerTypeKind:
3374 snprintf(buf, bufsize, "i%d", LLVMGetIntTypeWidth(elem_type));
3375 break;
3376 case LLVMFloatTypeKind:
3377 snprintf(buf, bufsize, "f32");
3378 break;
3379 case LLVMDoubleTypeKind:
3380 snprintf(buf, bufsize, "f64");
3381 break;
3382 }
3383 }
3384
3385 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
3386 struct lp_build_tgsi_context *bld_base,
3387 struct lp_build_emit_data *emit_data);
3388
3389 /* Prevent optimizations (at least of memory accesses) across the current
3390 * point in the program by emitting empty inline assembly that is marked as
3391 * having side effects.
3392 */
3393 static void emit_optimization_barrier(struct si_shader_context *ctx)
3394 {
3395 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3396 LLVMTypeRef ftype = LLVMFunctionType(ctx->voidt, NULL, 0, false);
3397 LLVMValueRef inlineasm = LLVMConstInlineAsm(ftype, "", "", true, false);
3398 LLVMBuildCall(builder, inlineasm, NULL, 0, "");
3399 }
3400
3401 static void emit_waitcnt(struct si_shader_context *ctx)
3402 {
3403 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3404 LLVMBuilderRef builder = gallivm->builder;
3405 LLVMValueRef args[1] = {
3406 lp_build_const_int32(gallivm, 0xf70)
3407 };
3408 lp_build_intrinsic(builder, "llvm.amdgcn.s.waitcnt",
3409 ctx->voidt, args, 1, 0);
3410 }
3411
3412 static void membar_emit(
3413 const struct lp_build_tgsi_action *action,
3414 struct lp_build_tgsi_context *bld_base,
3415 struct lp_build_emit_data *emit_data)
3416 {
3417 struct si_shader_context *ctx = si_shader_context(bld_base);
3418
3419 emit_waitcnt(ctx);
3420 }
3421
3422 static LLVMValueRef
3423 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
3424 const struct tgsi_full_src_register *reg)
3425 {
3426 LLVMValueRef index;
3427 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
3428 SI_PARAM_SHADER_BUFFERS);
3429
3430 if (!reg->Register.Indirect)
3431 index = LLVMConstInt(ctx->i32, reg->Register.Index, 0);
3432 else
3433 index = get_bounded_indirect_index(ctx, &reg->Indirect,
3434 reg->Register.Index,
3435 SI_NUM_SHADER_BUFFERS);
3436
3437 return build_indexed_load_const(ctx, rsrc_ptr, index);
3438 }
3439
3440 static bool tgsi_is_array_sampler(unsigned target)
3441 {
3442 return target == TGSI_TEXTURE_1D_ARRAY ||
3443 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
3444 target == TGSI_TEXTURE_2D_ARRAY ||
3445 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
3446 target == TGSI_TEXTURE_CUBE_ARRAY ||
3447 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
3448 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3449 }
3450
3451 static bool tgsi_is_array_image(unsigned target)
3452 {
3453 return target == TGSI_TEXTURE_3D ||
3454 target == TGSI_TEXTURE_CUBE ||
3455 target == TGSI_TEXTURE_1D_ARRAY ||
3456 target == TGSI_TEXTURE_2D_ARRAY ||
3457 target == TGSI_TEXTURE_CUBE_ARRAY ||
3458 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
3459 }
3460
3461 /**
3462 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
3463 *
3464 * At least on Tonga, executing image stores on images with DCC enabled and
3465 * non-trivial can eventually lead to lockups. This can occur when an
3466 * application binds an image as read-only but then uses a shader that writes
3467 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
3468 * program termination) in this case, but it doesn't cost much to be a bit
3469 * nicer: disabling DCC in the shader still leads to undefined results but
3470 * avoids the lockup.
3471 */
3472 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
3473 LLVMValueRef rsrc)
3474 {
3475 if (ctx->screen->b.chip_class <= CIK) {
3476 return rsrc;
3477 } else {
3478 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
3479 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
3480 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
3481 LLVMValueRef tmp;
3482
3483 tmp = LLVMBuildExtractElement(builder, rsrc, i32_6, "");
3484 tmp = LLVMBuildAnd(builder, tmp, i32_C, "");
3485 return LLVMBuildInsertElement(builder, rsrc, tmp, i32_6, "");
3486 }
3487 }
3488
3489 /**
3490 * Load the resource descriptor for \p image.
3491 */
3492 static void
3493 image_fetch_rsrc(
3494 struct lp_build_tgsi_context *bld_base,
3495 const struct tgsi_full_src_register *image,
3496 bool dcc_off,
3497 LLVMValueRef *rsrc)
3498 {
3499 struct si_shader_context *ctx = si_shader_context(bld_base);
3500 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
3501 SI_PARAM_IMAGES);
3502 LLVMValueRef index, tmp;
3503
3504 assert(image->Register.File == TGSI_FILE_IMAGE);
3505
3506 if (!image->Register.Indirect) {
3507 const struct tgsi_shader_info *info = bld_base->info;
3508
3509 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
3510
3511 if (info->images_writemask & (1 << image->Register.Index) &&
3512 !(info->images_buffers & (1 << image->Register.Index)))
3513 dcc_off = true;
3514 } else {
3515 /* From the GL_ARB_shader_image_load_store extension spec:
3516 *
3517 * If a shader performs an image load, store, or atomic
3518 * operation using an image variable declared as an array,
3519 * and if the index used to select an individual element is
3520 * negative or greater than or equal to the size of the
3521 * array, the results of the operation are undefined but may
3522 * not lead to termination.
3523 */
3524 index = get_bounded_indirect_index(ctx, &image->Indirect,
3525 image->Register.Index,
3526 SI_NUM_IMAGES);
3527 }
3528
3529 tmp = build_indexed_load_const(ctx, rsrc_ptr, index);
3530 if (dcc_off)
3531 tmp = force_dcc_off(ctx, tmp);
3532 *rsrc = tmp;
3533 }
3534
3535 static LLVMValueRef image_fetch_coords(
3536 struct lp_build_tgsi_context *bld_base,
3537 const struct tgsi_full_instruction *inst,
3538 unsigned src)
3539 {
3540 struct gallivm_state *gallivm = bld_base->base.gallivm;
3541 LLVMBuilderRef builder = gallivm->builder;
3542 unsigned target = inst->Memory.Texture;
3543 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
3544 LLVMValueRef coords[4];
3545 LLVMValueRef tmp;
3546 int chan;
3547
3548 for (chan = 0; chan < num_coords; ++chan) {
3549 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
3550 tmp = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3551 coords[chan] = tmp;
3552 }
3553
3554 if (num_coords == 1)
3555 return coords[0];
3556
3557 if (num_coords == 3) {
3558 /* LLVM has difficulties lowering 3-element vectors. */
3559 coords[3] = bld_base->uint_bld.undef;
3560 num_coords = 4;
3561 }
3562
3563 return lp_build_gather_values(gallivm, coords, num_coords);
3564 }
3565
3566 /**
3567 * Append the extra mode bits that are used by image load and store.
3568 */
3569 static void image_append_args(
3570 struct si_shader_context *ctx,
3571 struct lp_build_emit_data * emit_data,
3572 unsigned target,
3573 bool atomic)
3574 {
3575 const struct tgsi_full_instruction *inst = emit_data->inst;
3576 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3577 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3578 LLVMValueRef r128 = i1false;
3579 LLVMValueRef da = tgsi_is_array_image(target) ? i1true : i1false;
3580 LLVMValueRef glc =
3581 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3582 i1true : i1false;
3583 LLVMValueRef slc = i1false;
3584 LLVMValueRef lwe = i1false;
3585
3586 if (atomic || (HAVE_LLVM <= 0x0309)) {
3587 emit_data->args[emit_data->arg_count++] = r128;
3588 emit_data->args[emit_data->arg_count++] = da;
3589 if (!atomic) {
3590 emit_data->args[emit_data->arg_count++] = glc;
3591 }
3592 emit_data->args[emit_data->arg_count++] = slc;
3593 return;
3594 }
3595
3596 /* HAVE_LLVM >= 0x0400 */
3597 emit_data->args[emit_data->arg_count++] = glc;
3598 emit_data->args[emit_data->arg_count++] = slc;
3599 emit_data->args[emit_data->arg_count++] = lwe;
3600 emit_data->args[emit_data->arg_count++] = da;
3601 }
3602
3603 /**
3604 * Given a 256 bit resource, extract the top half (which stores the buffer
3605 * resource in the case of textures and images).
3606 */
3607 static LLVMValueRef extract_rsrc_top_half(
3608 struct si_shader_context *ctx,
3609 LLVMValueRef rsrc)
3610 {
3611 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3612 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
3613 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
3614
3615 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, v2i128, "");
3616 rsrc = LLVMBuildExtractElement(gallivm->builder, rsrc, bld_base->uint_bld.one, "");
3617 rsrc = LLVMBuildBitCast(gallivm->builder, rsrc, ctx->v4i32, "");
3618
3619 return rsrc;
3620 }
3621
3622 /**
3623 * Append the resource and indexing arguments for buffer intrinsics.
3624 *
3625 * \param rsrc the v4i32 buffer resource
3626 * \param index index into the buffer (stride-based)
3627 * \param offset byte offset into the buffer
3628 */
3629 static void buffer_append_args(
3630 struct si_shader_context *ctx,
3631 struct lp_build_emit_data *emit_data,
3632 LLVMValueRef rsrc,
3633 LLVMValueRef index,
3634 LLVMValueRef offset,
3635 bool atomic)
3636 {
3637 const struct tgsi_full_instruction *inst = emit_data->inst;
3638 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
3639 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
3640
3641 emit_data->args[emit_data->arg_count++] = rsrc;
3642 emit_data->args[emit_data->arg_count++] = index; /* vindex */
3643 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
3644 if (!atomic) {
3645 emit_data->args[emit_data->arg_count++] =
3646 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
3647 i1true : i1false; /* glc */
3648 }
3649 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
3650 }
3651
3652 static void load_fetch_args(
3653 struct lp_build_tgsi_context * bld_base,
3654 struct lp_build_emit_data * emit_data)
3655 {
3656 struct si_shader_context *ctx = si_shader_context(bld_base);
3657 struct gallivm_state *gallivm = bld_base->base.gallivm;
3658 const struct tgsi_full_instruction * inst = emit_data->inst;
3659 unsigned target = inst->Memory.Texture;
3660 LLVMValueRef rsrc;
3661
3662 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
3663
3664 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3665 LLVMBuilderRef builder = gallivm->builder;
3666 LLVMValueRef offset;
3667 LLVMValueRef tmp;
3668
3669 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
3670
3671 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
3672 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3673
3674 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3675 offset, false);
3676 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
3677 LLVMValueRef coords;
3678
3679 image_fetch_rsrc(bld_base, &inst->Src[0], false, &rsrc);
3680 coords = image_fetch_coords(bld_base, inst, 1);
3681
3682 if (target == TGSI_TEXTURE_BUFFER) {
3683 rsrc = extract_rsrc_top_half(ctx, rsrc);
3684 buffer_append_args(ctx, emit_data, rsrc, coords,
3685 bld_base->uint_bld.zero, false);
3686 } else {
3687 emit_data->args[0] = coords;
3688 emit_data->args[1] = rsrc;
3689 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
3690 emit_data->arg_count = 3;
3691
3692 image_append_args(ctx, emit_data, target, false);
3693 }
3694 }
3695 }
3696
3697 static void load_emit_buffer(struct si_shader_context *ctx,
3698 struct lp_build_emit_data *emit_data)
3699 {
3700 const struct tgsi_full_instruction *inst = emit_data->inst;
3701 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3702 LLVMBuilderRef builder = gallivm->builder;
3703 uint writemask = inst->Dst[0].Register.WriteMask;
3704 uint count = util_last_bit(writemask);
3705 const char *intrinsic_name;
3706 LLVMTypeRef dst_type;
3707
3708 switch (count) {
3709 case 1:
3710 intrinsic_name = "llvm.amdgcn.buffer.load.f32";
3711 dst_type = ctx->f32;
3712 break;
3713 case 2:
3714 intrinsic_name = "llvm.amdgcn.buffer.load.v2f32";
3715 dst_type = LLVMVectorType(ctx->f32, 2);
3716 break;
3717 default: // 3 & 4
3718 intrinsic_name = "llvm.amdgcn.buffer.load.v4f32";
3719 dst_type = ctx->v4f32;
3720 count = 4;
3721 }
3722
3723 emit_data->output[emit_data->chan] = lp_build_intrinsic(
3724 builder, intrinsic_name, dst_type,
3725 emit_data->args, emit_data->arg_count,
3726 LLVMReadOnlyAttribute);
3727 }
3728
3729 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
3730 const struct tgsi_full_instruction *inst,
3731 LLVMTypeRef type, int arg)
3732 {
3733 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3734 LLVMBuilderRef builder = gallivm->builder;
3735 LLVMValueRef offset, ptr;
3736 int addr_space;
3737
3738 offset = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, arg, 0);
3739 offset = LLVMBuildBitCast(builder, offset, ctx->i32, "");
3740
3741 ptr = ctx->shared_memory;
3742 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
3743 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
3744 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
3745
3746 return ptr;
3747 }
3748
3749 static void load_emit_memory(
3750 struct si_shader_context *ctx,
3751 struct lp_build_emit_data *emit_data)
3752 {
3753 const struct tgsi_full_instruction *inst = emit_data->inst;
3754 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3755 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3756 LLVMBuilderRef builder = gallivm->builder;
3757 unsigned writemask = inst->Dst[0].Register.WriteMask;
3758 LLVMValueRef channels[4], ptr, derived_ptr, index;
3759 int chan;
3760
3761 ptr = get_memory_ptr(ctx, inst, base->elem_type, 1);
3762
3763 for (chan = 0; chan < 4; ++chan) {
3764 if (!(writemask & (1 << chan))) {
3765 channels[chan] = LLVMGetUndef(base->elem_type);
3766 continue;
3767 }
3768
3769 index = lp_build_const_int32(gallivm, chan);
3770 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3771 channels[chan] = LLVMBuildLoad(builder, derived_ptr, "");
3772 }
3773 emit_data->output[emit_data->chan] = lp_build_gather_values(gallivm, channels, 4);
3774 }
3775
3776 static void get_image_intr_name(const char *base_name,
3777 LLVMTypeRef data_type,
3778 LLVMTypeRef coords_type,
3779 LLVMTypeRef rsrc_type,
3780 char *out_name, unsigned out_len)
3781 {
3782 char coords_type_name[8];
3783
3784 build_type_name_for_intr(coords_type, coords_type_name,
3785 sizeof(coords_type_name));
3786
3787 if (HAVE_LLVM <= 0x0309) {
3788 snprintf(out_name, out_len, "%s.%s", base_name, coords_type_name);
3789 } else {
3790 char data_type_name[8];
3791 char rsrc_type_name[8];
3792
3793 build_type_name_for_intr(data_type, data_type_name,
3794 sizeof(data_type_name));
3795 build_type_name_for_intr(rsrc_type, rsrc_type_name,
3796 sizeof(rsrc_type_name));
3797 snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
3798 data_type_name, coords_type_name, rsrc_type_name);
3799 }
3800 }
3801
3802 static void load_emit(
3803 const struct lp_build_tgsi_action *action,
3804 struct lp_build_tgsi_context *bld_base,
3805 struct lp_build_emit_data *emit_data)
3806 {
3807 struct si_shader_context *ctx = si_shader_context(bld_base);
3808 struct gallivm_state *gallivm = bld_base->base.gallivm;
3809 LLVMBuilderRef builder = gallivm->builder;
3810 const struct tgsi_full_instruction * inst = emit_data->inst;
3811 char intrinsic_name[64];
3812
3813 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
3814 load_emit_memory(ctx, emit_data);
3815 return;
3816 }
3817
3818 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
3819 emit_waitcnt(ctx);
3820
3821 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
3822 load_emit_buffer(ctx, emit_data);
3823 return;
3824 }
3825
3826 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
3827 emit_data->output[emit_data->chan] =
3828 lp_build_intrinsic(
3829 builder, "llvm.amdgcn.buffer.load.format.v4f32", emit_data->dst_type,
3830 emit_data->args, emit_data->arg_count,
3831 LLVMReadOnlyAttribute);
3832 } else {
3833 get_image_intr_name("llvm.amdgcn.image.load",
3834 emit_data->dst_type, /* vdata */
3835 LLVMTypeOf(emit_data->args[0]), /* coords */
3836 LLVMTypeOf(emit_data->args[1]), /* rsrc */
3837 intrinsic_name, sizeof(intrinsic_name));
3838
3839 emit_data->output[emit_data->chan] =
3840 lp_build_intrinsic(
3841 builder, intrinsic_name, emit_data->dst_type,
3842 emit_data->args, emit_data->arg_count,
3843 LLVMReadOnlyAttribute);
3844 }
3845 }
3846
3847 static void store_fetch_args(
3848 struct lp_build_tgsi_context * bld_base,
3849 struct lp_build_emit_data * emit_data)
3850 {
3851 struct si_shader_context *ctx = si_shader_context(bld_base);
3852 struct gallivm_state *gallivm = bld_base->base.gallivm;
3853 LLVMBuilderRef builder = gallivm->builder;
3854 const struct tgsi_full_instruction * inst = emit_data->inst;
3855 struct tgsi_full_src_register memory;
3856 LLVMValueRef chans[4];
3857 LLVMValueRef data;
3858 LLVMValueRef rsrc;
3859 unsigned chan;
3860
3861 emit_data->dst_type = LLVMVoidTypeInContext(gallivm->context);
3862
3863 for (chan = 0; chan < 4; ++chan) {
3864 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
3865 }
3866 data = lp_build_gather_values(gallivm, chans, 4);
3867
3868 emit_data->args[emit_data->arg_count++] = data;
3869
3870 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
3871
3872 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
3873 LLVMValueRef offset;
3874 LLVMValueRef tmp;
3875
3876 rsrc = shader_buffer_fetch_rsrc(ctx, &memory);
3877
3878 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
3879 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
3880
3881 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
3882 offset, false);
3883 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE) {
3884 unsigned target = inst->Memory.Texture;
3885 LLVMValueRef coords;
3886
3887 coords = image_fetch_coords(bld_base, inst, 0);
3888
3889 if (target == TGSI_TEXTURE_BUFFER) {
3890 image_fetch_rsrc(bld_base, &memory, false, &rsrc);
3891
3892 rsrc = extract_rsrc_top_half(ctx, rsrc);
3893 buffer_append_args(ctx, emit_data, rsrc, coords,
3894 bld_base->uint_bld.zero, false);
3895 } else {
3896 emit_data->args[1] = coords;
3897 image_fetch_rsrc(bld_base, &memory, true, &emit_data->args[2]);
3898 emit_data->args[3] = lp_build_const_int32(gallivm, 15); /* dmask */
3899 emit_data->arg_count = 4;
3900
3901 image_append_args(ctx, emit_data, target, false);
3902 }
3903 }
3904 }
3905
3906 static void store_emit_buffer(
3907 struct si_shader_context *ctx,
3908 struct lp_build_emit_data *emit_data)
3909 {
3910 const struct tgsi_full_instruction *inst = emit_data->inst;
3911 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3912 LLVMBuilderRef builder = gallivm->builder;
3913 struct lp_build_context *uint_bld = &ctx->radeon_bld.soa.bld_base.uint_bld;
3914 LLVMValueRef base_data = emit_data->args[0];
3915 LLVMValueRef base_offset = emit_data->args[3];
3916 unsigned writemask = inst->Dst[0].Register.WriteMask;
3917
3918 while (writemask) {
3919 int start, count;
3920 const char *intrinsic_name;
3921 LLVMValueRef data;
3922 LLVMValueRef offset;
3923 LLVMValueRef tmp;
3924
3925 u_bit_scan_consecutive_range(&writemask, &start, &count);
3926
3927 /* Due to an LLVM limitation, split 3-element writes
3928 * into a 2-element and a 1-element write. */
3929 if (count == 3) {
3930 writemask |= 1 << (start + 2);
3931 count = 2;
3932 }
3933
3934 if (count == 4) {
3935 data = base_data;
3936 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
3937 } else if (count == 2) {
3938 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
3939
3940 tmp = LLVMBuildExtractElement(
3941 builder, base_data,
3942 lp_build_const_int32(gallivm, start), "");
3943 data = LLVMBuildInsertElement(
3944 builder, LLVMGetUndef(v2f32), tmp,
3945 uint_bld->zero, "");
3946
3947 tmp = LLVMBuildExtractElement(
3948 builder, base_data,
3949 lp_build_const_int32(gallivm, start + 1), "");
3950 data = LLVMBuildInsertElement(
3951 builder, data, tmp, uint_bld->one, "");
3952
3953 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
3954 } else {
3955 assert(count == 1);
3956 data = LLVMBuildExtractElement(
3957 builder, base_data,
3958 lp_build_const_int32(gallivm, start), "");
3959 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
3960 }
3961
3962 offset = base_offset;
3963 if (start != 0) {
3964 offset = LLVMBuildAdd(
3965 builder, offset,
3966 lp_build_const_int32(gallivm, start * 4), "");
3967 }
3968
3969 emit_data->args[0] = data;
3970 emit_data->args[3] = offset;
3971
3972 lp_build_intrinsic(
3973 builder, intrinsic_name, emit_data->dst_type,
3974 emit_data->args, emit_data->arg_count, 0);
3975 }
3976 }
3977
3978 static void store_emit_memory(
3979 struct si_shader_context *ctx,
3980 struct lp_build_emit_data *emit_data)
3981 {
3982 const struct tgsi_full_instruction *inst = emit_data->inst;
3983 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
3984 struct lp_build_context *base = &ctx->radeon_bld.soa.bld_base.base;
3985 LLVMBuilderRef builder = gallivm->builder;
3986 unsigned writemask = inst->Dst[0].Register.WriteMask;
3987 LLVMValueRef ptr, derived_ptr, data, index;
3988 int chan;
3989
3990 ptr = get_memory_ptr(ctx, inst, base->elem_type, 0);
3991
3992 for (chan = 0; chan < 4; ++chan) {
3993 if (!(writemask & (1 << chan))) {
3994 continue;
3995 }
3996 data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 1, chan);
3997 index = lp_build_const_int32(gallivm, chan);
3998 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
3999 LLVMBuildStore(builder, data, derived_ptr);
4000 }
4001 }
4002
4003 static void store_emit(
4004 const struct lp_build_tgsi_action *action,
4005 struct lp_build_tgsi_context *bld_base,
4006 struct lp_build_emit_data *emit_data)
4007 {
4008 struct si_shader_context *ctx = si_shader_context(bld_base);
4009 struct gallivm_state *gallivm = bld_base->base.gallivm;
4010 LLVMBuilderRef builder = gallivm->builder;
4011 const struct tgsi_full_instruction * inst = emit_data->inst;
4012 unsigned target = inst->Memory.Texture;
4013 char intrinsic_name[64];
4014
4015 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
4016 store_emit_memory(ctx, emit_data);
4017 return;
4018 }
4019
4020 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
4021 emit_waitcnt(ctx);
4022
4023 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
4024 store_emit_buffer(ctx, emit_data);
4025 return;
4026 }
4027
4028 if (target == TGSI_TEXTURE_BUFFER) {
4029 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4030 builder, "llvm.amdgcn.buffer.store.format.v4f32",
4031 emit_data->dst_type, emit_data->args,
4032 emit_data->arg_count, 0);
4033 } else {
4034 get_image_intr_name("llvm.amdgcn.image.store",
4035 LLVMTypeOf(emit_data->args[0]), /* vdata */
4036 LLVMTypeOf(emit_data->args[1]), /* coords */
4037 LLVMTypeOf(emit_data->args[2]), /* rsrc */
4038 intrinsic_name, sizeof(intrinsic_name));
4039
4040 emit_data->output[emit_data->chan] =
4041 lp_build_intrinsic(
4042 builder, intrinsic_name, emit_data->dst_type,
4043 emit_data->args, emit_data->arg_count, 0);
4044 }
4045 }
4046
4047 static void atomic_fetch_args(
4048 struct lp_build_tgsi_context * bld_base,
4049 struct lp_build_emit_data * emit_data)
4050 {
4051 struct si_shader_context *ctx = si_shader_context(bld_base);
4052 struct gallivm_state *gallivm = bld_base->base.gallivm;
4053 LLVMBuilderRef builder = gallivm->builder;
4054 const struct tgsi_full_instruction * inst = emit_data->inst;
4055 LLVMValueRef data1, data2;
4056 LLVMValueRef rsrc;
4057 LLVMValueRef tmp;
4058
4059 emit_data->dst_type = bld_base->base.elem_type;
4060
4061 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
4062 data1 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4063
4064 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4065 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
4066 data2 = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4067 }
4068
4069 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
4070 * of arguments, which is reversed relative to TGSI (and GLSL)
4071 */
4072 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4073 emit_data->args[emit_data->arg_count++] = data2;
4074 emit_data->args[emit_data->arg_count++] = data1;
4075
4076 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4077 LLVMValueRef offset;
4078
4079 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0]);
4080
4081 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
4082 offset = LLVMBuildBitCast(builder, tmp, bld_base->uint_bld.elem_type, "");
4083
4084 buffer_append_args(ctx, emit_data, rsrc, bld_base->uint_bld.zero,
4085 offset, true);
4086 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE) {
4087 unsigned target = inst->Memory.Texture;
4088 LLVMValueRef coords;
4089
4090 image_fetch_rsrc(bld_base, &inst->Src[0],
4091 target != TGSI_TEXTURE_BUFFER, &rsrc);
4092 coords = image_fetch_coords(bld_base, inst, 1);
4093
4094 if (target == TGSI_TEXTURE_BUFFER) {
4095 rsrc = extract_rsrc_top_half(ctx, rsrc);
4096 buffer_append_args(ctx, emit_data, rsrc, coords,
4097 bld_base->uint_bld.zero, true);
4098 } else {
4099 emit_data->args[emit_data->arg_count++] = coords;
4100 emit_data->args[emit_data->arg_count++] = rsrc;
4101
4102 image_append_args(ctx, emit_data, target, true);
4103 }
4104 }
4105 }
4106
4107 static void atomic_emit_memory(struct si_shader_context *ctx,
4108 struct lp_build_emit_data *emit_data) {
4109 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4110 LLVMBuilderRef builder = gallivm->builder;
4111 const struct tgsi_full_instruction * inst = emit_data->inst;
4112 LLVMValueRef ptr, result, arg;
4113
4114 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
4115
4116 arg = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base, inst, 2, 0);
4117 arg = LLVMBuildBitCast(builder, arg, ctx->i32, "");
4118
4119 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
4120 LLVMValueRef new_data;
4121 new_data = lp_build_emit_fetch(&ctx->radeon_bld.soa.bld_base,
4122 inst, 3, 0);
4123
4124 new_data = LLVMBuildBitCast(builder, new_data, ctx->i32, "");
4125
4126 #if HAVE_LLVM >= 0x309
4127 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
4128 LLVMAtomicOrderingSequentiallyConsistent,
4129 LLVMAtomicOrderingSequentiallyConsistent,
4130 false);
4131 #endif
4132
4133 result = LLVMBuildExtractValue(builder, result, 0, "");
4134 } else {
4135 LLVMAtomicRMWBinOp op;
4136
4137 switch(inst->Instruction.Opcode) {
4138 case TGSI_OPCODE_ATOMUADD:
4139 op = LLVMAtomicRMWBinOpAdd;
4140 break;
4141 case TGSI_OPCODE_ATOMXCHG:
4142 op = LLVMAtomicRMWBinOpXchg;
4143 break;
4144 case TGSI_OPCODE_ATOMAND:
4145 op = LLVMAtomicRMWBinOpAnd;
4146 break;
4147 case TGSI_OPCODE_ATOMOR:
4148 op = LLVMAtomicRMWBinOpOr;
4149 break;
4150 case TGSI_OPCODE_ATOMXOR:
4151 op = LLVMAtomicRMWBinOpXor;
4152 break;
4153 case TGSI_OPCODE_ATOMUMIN:
4154 op = LLVMAtomicRMWBinOpUMin;
4155 break;
4156 case TGSI_OPCODE_ATOMUMAX:
4157 op = LLVMAtomicRMWBinOpUMax;
4158 break;
4159 case TGSI_OPCODE_ATOMIMIN:
4160 op = LLVMAtomicRMWBinOpMin;
4161 break;
4162 case TGSI_OPCODE_ATOMIMAX:
4163 op = LLVMAtomicRMWBinOpMax;
4164 break;
4165 default:
4166 unreachable("unknown atomic opcode");
4167 }
4168
4169 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
4170 LLVMAtomicOrderingSequentiallyConsistent,
4171 false);
4172 }
4173 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
4174 }
4175
4176 static void atomic_emit(
4177 const struct lp_build_tgsi_action *action,
4178 struct lp_build_tgsi_context *bld_base,
4179 struct lp_build_emit_data *emit_data)
4180 {
4181 struct si_shader_context *ctx = si_shader_context(bld_base);
4182 struct gallivm_state *gallivm = bld_base->base.gallivm;
4183 LLVMBuilderRef builder = gallivm->builder;
4184 const struct tgsi_full_instruction * inst = emit_data->inst;
4185 char intrinsic_name[40];
4186 LLVMValueRef tmp;
4187
4188 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
4189 atomic_emit_memory(ctx, emit_data);
4190 return;
4191 }
4192
4193 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
4194 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4195 snprintf(intrinsic_name, sizeof(intrinsic_name),
4196 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
4197 } else {
4198 LLVMValueRef coords;
4199 char coords_type[8];
4200
4201 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
4202 coords = emit_data->args[2];
4203 else
4204 coords = emit_data->args[1];
4205
4206 build_type_name_for_intr(LLVMTypeOf(coords), coords_type, sizeof(coords_type));
4207 snprintf(intrinsic_name, sizeof(intrinsic_name),
4208 "llvm.amdgcn.image.atomic.%s.%s",
4209 action->intr_name, coords_type);
4210 }
4211
4212 tmp = lp_build_intrinsic(
4213 builder, intrinsic_name, bld_base->uint_bld.elem_type,
4214 emit_data->args, emit_data->arg_count, 0);
4215 emit_data->output[emit_data->chan] =
4216 LLVMBuildBitCast(builder, tmp, bld_base->base.elem_type, "");
4217 }
4218
4219 static void resq_fetch_args(
4220 struct lp_build_tgsi_context * bld_base,
4221 struct lp_build_emit_data * emit_data)
4222 {
4223 struct si_shader_context *ctx = si_shader_context(bld_base);
4224 struct gallivm_state *gallivm = bld_base->base.gallivm;
4225 const struct tgsi_full_instruction *inst = emit_data->inst;
4226 const struct tgsi_full_src_register *reg = &inst->Src[0];
4227
4228 emit_data->dst_type = ctx->v4i32;
4229
4230 if (reg->Register.File == TGSI_FILE_BUFFER) {
4231 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg);
4232 emit_data->arg_count = 1;
4233 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4234 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[0]);
4235 emit_data->arg_count = 1;
4236 } else {
4237 emit_data->args[0] = bld_base->uint_bld.zero; /* mip level */
4238 image_fetch_rsrc(bld_base, reg, false, &emit_data->args[1]);
4239 emit_data->args[2] = lp_build_const_int32(gallivm, 15); /* dmask */
4240 emit_data->args[3] = bld_base->uint_bld.zero; /* unorm */
4241 emit_data->args[4] = bld_base->uint_bld.zero; /* r128 */
4242 emit_data->args[5] = tgsi_is_array_image(inst->Memory.Texture) ?
4243 bld_base->uint_bld.one : bld_base->uint_bld.zero; /* da */
4244 emit_data->args[6] = bld_base->uint_bld.zero; /* glc */
4245 emit_data->args[7] = bld_base->uint_bld.zero; /* slc */
4246 emit_data->args[8] = bld_base->uint_bld.zero; /* tfe */
4247 emit_data->args[9] = bld_base->uint_bld.zero; /* lwe */
4248 emit_data->arg_count = 10;
4249 }
4250 }
4251
4252 static void resq_emit(
4253 const struct lp_build_tgsi_action *action,
4254 struct lp_build_tgsi_context *bld_base,
4255 struct lp_build_emit_data *emit_data)
4256 {
4257 struct gallivm_state *gallivm = bld_base->base.gallivm;
4258 LLVMBuilderRef builder = gallivm->builder;
4259 const struct tgsi_full_instruction *inst = emit_data->inst;
4260 LLVMValueRef out;
4261
4262 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
4263 out = LLVMBuildExtractElement(builder, emit_data->args[0],
4264 lp_build_const_int32(gallivm, 2), "");
4265 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
4266 out = get_buffer_size(bld_base, emit_data->args[0]);
4267 } else {
4268 out = lp_build_intrinsic(
4269 builder, "llvm.SI.getresinfo.i32", emit_data->dst_type,
4270 emit_data->args, emit_data->arg_count,
4271 LLVMReadNoneAttribute);
4272
4273 /* Divide the number of layers by 6 to get the number of cubes. */
4274 if (inst->Memory.Texture == TGSI_TEXTURE_CUBE_ARRAY) {
4275 LLVMValueRef imm2 = lp_build_const_int32(gallivm, 2);
4276 LLVMValueRef imm6 = lp_build_const_int32(gallivm, 6);
4277
4278 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
4279 z = LLVMBuildSDiv(builder, z, imm6, "");
4280 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
4281 }
4282 }
4283
4284 emit_data->output[emit_data->chan] = out;
4285 }
4286
4287 static void set_tex_fetch_args(struct si_shader_context *ctx,
4288 struct lp_build_emit_data *emit_data,
4289 unsigned opcode, unsigned target,
4290 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
4291 LLVMValueRef *param, unsigned count,
4292 unsigned dmask)
4293 {
4294 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4295 unsigned num_args;
4296 unsigned is_rect = target == TGSI_TEXTURE_RECT;
4297
4298 /* Pad to power of two vector */
4299 while (count < util_next_power_of_two(count))
4300 param[count++] = LLVMGetUndef(ctx->i32);
4301
4302 /* Texture coordinates. */
4303 if (count > 1)
4304 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
4305 else
4306 emit_data->args[0] = param[0];
4307
4308 /* Resource. */
4309 emit_data->args[1] = res_ptr;
4310 num_args = 2;
4311
4312 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
4313 emit_data->dst_type = ctx->v4i32;
4314 else {
4315 emit_data->dst_type = ctx->v4f32;
4316
4317 emit_data->args[num_args++] = samp_ptr;
4318 }
4319
4320 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
4321 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
4322 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
4323 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
4324 tgsi_is_array_sampler(target)); /* da */
4325 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
4326 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
4327 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
4328 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
4329
4330 emit_data->arg_count = num_args;
4331 }
4332
4333 static const struct lp_build_tgsi_action tex_action;
4334
4335 enum desc_type {
4336 DESC_IMAGE,
4337 DESC_FMASK,
4338 DESC_SAMPLER
4339 };
4340
4341 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
4342 {
4343 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
4344 CONST_ADDR_SPACE);
4345 }
4346
4347 /**
4348 * Load an image view, fmask view. or sampler state descriptor.
4349 */
4350 static LLVMValueRef load_sampler_desc_custom(struct si_shader_context *ctx,
4351 LLVMValueRef list, LLVMValueRef index,
4352 enum desc_type type)
4353 {
4354 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
4355 LLVMBuilderRef builder = gallivm->builder;
4356
4357 switch (type) {
4358 case DESC_IMAGE:
4359 /* The image is at [0:7]. */
4360 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4361 break;
4362 case DESC_FMASK:
4363 /* The FMASK is at [8:15]. */
4364 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
4365 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 1, 0), "");
4366 break;
4367 case DESC_SAMPLER:
4368 /* The sampler state is at [12:15]. */
4369 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
4370 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
4371 list = LLVMBuildPointerCast(builder, list,
4372 const_array(ctx->v4i32, 0), "");
4373 break;
4374 }
4375
4376 return build_indexed_load_const(ctx, list, index);
4377 }
4378
4379 static LLVMValueRef load_sampler_desc(struct si_shader_context *ctx,
4380 LLVMValueRef index, enum desc_type type)
4381 {
4382 LLVMValueRef list = LLVMGetParam(ctx->radeon_bld.main_fn,
4383 SI_PARAM_SAMPLERS);
4384
4385 return load_sampler_desc_custom(ctx, list, index, type);
4386 }
4387
4388 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
4389 *
4390 * SI-CI:
4391 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
4392 * filtering manually. The driver sets img7 to a mask clearing
4393 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
4394 * s_and_b32 samp0, samp0, img7
4395 *
4396 * VI:
4397 * The ANISO_OVERRIDE sampler field enables this fix in TA.
4398 */
4399 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
4400 LLVMValueRef res, LLVMValueRef samp)
4401 {
4402 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
4403 LLVMValueRef img7, samp0;
4404
4405 if (ctx->screen->b.chip_class >= VI)
4406 return samp;
4407
4408 img7 = LLVMBuildExtractElement(builder, res,
4409 LLVMConstInt(ctx->i32, 7, 0), "");
4410 samp0 = LLVMBuildExtractElement(builder, samp,
4411 LLVMConstInt(ctx->i32, 0, 0), "");
4412 samp0 = LLVMBuildAnd(builder, samp0, img7, "");
4413 return LLVMBuildInsertElement(builder, samp, samp0,
4414 LLVMConstInt(ctx->i32, 0, 0), "");
4415 }
4416
4417 static void tex_fetch_ptrs(
4418 struct lp_build_tgsi_context *bld_base,
4419 struct lp_build_emit_data *emit_data,
4420 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
4421 {
4422 struct si_shader_context *ctx = si_shader_context(bld_base);
4423 const struct tgsi_full_instruction *inst = emit_data->inst;
4424 unsigned target = inst->Texture.Texture;
4425 unsigned sampler_src;
4426 unsigned sampler_index;
4427 LLVMValueRef index;
4428
4429 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
4430 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
4431
4432 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
4433 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
4434
4435 index = get_bounded_indirect_index(ctx,
4436 &reg->Indirect,
4437 reg->Register.Index,
4438 SI_NUM_SAMPLERS);
4439 } else {
4440 index = LLVMConstInt(ctx->i32, sampler_index, 0);
4441 }
4442
4443 *res_ptr = load_sampler_desc(ctx, index, DESC_IMAGE);
4444
4445 if (target == TGSI_TEXTURE_2D_MSAA ||
4446 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4447 if (samp_ptr)
4448 *samp_ptr = NULL;
4449 if (fmask_ptr)
4450 *fmask_ptr = load_sampler_desc(ctx, index, DESC_FMASK);
4451 } else {
4452 if (samp_ptr) {
4453 *samp_ptr = load_sampler_desc(ctx, index, DESC_SAMPLER);
4454 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
4455 }
4456 if (fmask_ptr)
4457 *fmask_ptr = NULL;
4458 }
4459 }
4460
4461 static void txq_fetch_args(
4462 struct lp_build_tgsi_context *bld_base,
4463 struct lp_build_emit_data *emit_data)
4464 {
4465 struct si_shader_context *ctx = si_shader_context(bld_base);
4466 struct gallivm_state *gallivm = bld_base->base.gallivm;
4467 LLVMBuilderRef builder = gallivm->builder;
4468 const struct tgsi_full_instruction *inst = emit_data->inst;
4469 unsigned target = inst->Texture.Texture;
4470 LLVMValueRef res_ptr;
4471 LLVMValueRef address;
4472
4473 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, NULL, NULL);
4474
4475 if (target == TGSI_TEXTURE_BUFFER) {
4476 /* Read the size from the buffer descriptor directly. */
4477 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
4478 emit_data->args[0] = get_buffer_size(bld_base, res);
4479 return;
4480 }
4481
4482 /* Textures - set the mip level. */
4483 address = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
4484
4485 set_tex_fetch_args(ctx, emit_data, TGSI_OPCODE_TXQ, target, res_ptr,
4486 NULL, &address, 1, 0xf);
4487 }
4488
4489 static void txq_emit(const struct lp_build_tgsi_action *action,
4490 struct lp_build_tgsi_context *bld_base,
4491 struct lp_build_emit_data *emit_data)
4492 {
4493 struct lp_build_context *base = &bld_base->base;
4494 unsigned target = emit_data->inst->Texture.Texture;
4495
4496 if (target == TGSI_TEXTURE_BUFFER) {
4497 /* Just return the buffer size. */
4498 emit_data->output[emit_data->chan] = emit_data->args[0];
4499 return;
4500 }
4501
4502 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4503 base->gallivm->builder, "llvm.SI.getresinfo.i32",
4504 emit_data->dst_type, emit_data->args, emit_data->arg_count,
4505 LLVMReadNoneAttribute);
4506
4507 /* Divide the number of layers by 6 to get the number of cubes. */
4508 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
4509 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4510 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
4511 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
4512 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
4513
4514 LLVMValueRef v4 = emit_data->output[emit_data->chan];
4515 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
4516 z = LLVMBuildSDiv(builder, z, six, "");
4517
4518 emit_data->output[emit_data->chan] =
4519 LLVMBuildInsertElement(builder, v4, z, two, "");
4520 }
4521 }
4522
4523 static void tex_fetch_args(
4524 struct lp_build_tgsi_context *bld_base,
4525 struct lp_build_emit_data *emit_data)
4526 {
4527 struct si_shader_context *ctx = si_shader_context(bld_base);
4528 struct gallivm_state *gallivm = bld_base->base.gallivm;
4529 const struct tgsi_full_instruction *inst = emit_data->inst;
4530 unsigned opcode = inst->Instruction.Opcode;
4531 unsigned target = inst->Texture.Texture;
4532 LLVMValueRef coords[5], derivs[6];
4533 LLVMValueRef address[16];
4534 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
4535 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
4536 unsigned count = 0;
4537 unsigned chan;
4538 unsigned num_deriv_channels = 0;
4539 bool has_offset = inst->Texture.NumOffsets > 0;
4540 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
4541 unsigned dmask = 0xf;
4542
4543 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
4544
4545 if (target == TGSI_TEXTURE_BUFFER) {
4546 LLVMTypeRef v2i128 = LLVMVectorType(ctx->i128, 2);
4547
4548 /* Bitcast and truncate v8i32 to v16i8. */
4549 LLVMValueRef res = res_ptr;
4550 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
4551 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
4552 res = LLVMBuildBitCast(gallivm->builder, res, ctx->v16i8, "");
4553
4554 emit_data->dst_type = ctx->v4f32;
4555 emit_data->args[0] = res;
4556 emit_data->args[1] = bld_base->uint_bld.zero;
4557 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
4558 emit_data->arg_count = 3;
4559 return;
4560 }
4561
4562 /* Fetch and project texture coordinates */
4563 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
4564 for (chan = 0; chan < 3; chan++ ) {
4565 coords[chan] = lp_build_emit_fetch(bld_base,
4566 emit_data->inst, 0,
4567 chan);
4568 if (opcode == TGSI_OPCODE_TXP)
4569 coords[chan] = lp_build_emit_llvm_binary(bld_base,
4570 TGSI_OPCODE_DIV,
4571 coords[chan],
4572 coords[3]);
4573 }
4574
4575 if (opcode == TGSI_OPCODE_TXP)
4576 coords[3] = bld_base->base.one;
4577
4578 /* Pack offsets. */
4579 if (has_offset && opcode != TGSI_OPCODE_TXF) {
4580 /* The offsets are six-bit signed integers packed like this:
4581 * X=[5:0], Y=[13:8], and Z=[21:16].
4582 */
4583 LLVMValueRef offset[3], pack;
4584
4585 assert(inst->Texture.NumOffsets == 1);
4586
4587 for (chan = 0; chan < 3; chan++) {
4588 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
4589 emit_data->inst, 0, chan);
4590 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
4591 lp_build_const_int32(gallivm, 0x3f), "");
4592 if (chan)
4593 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
4594 lp_build_const_int32(gallivm, chan*8), "");
4595 }
4596
4597 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
4598 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
4599 address[count++] = pack;
4600 }
4601
4602 /* Pack LOD bias value */
4603 if (opcode == TGSI_OPCODE_TXB)
4604 address[count++] = coords[3];
4605 if (opcode == TGSI_OPCODE_TXB2)
4606 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4607
4608 /* Pack depth comparison value */
4609 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
4610 LLVMValueRef z;
4611
4612 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
4613 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4614 } else {
4615 assert(ref_pos >= 0);
4616 z = coords[ref_pos];
4617 }
4618
4619 /* TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
4620 * so the depth comparison value isn't clamped for Z16 and
4621 * Z24 anymore. Do it manually here.
4622 *
4623 * It's unnecessary if the original texture format was
4624 * Z32_FLOAT, but we don't know that here.
4625 */
4626 if (ctx->screen->b.chip_class == VI)
4627 z = radeon_llvm_saturate(bld_base, z);
4628
4629 address[count++] = z;
4630 }
4631
4632 /* Pack user derivatives */
4633 if (opcode == TGSI_OPCODE_TXD) {
4634 int param, num_src_deriv_channels;
4635
4636 switch (target) {
4637 case TGSI_TEXTURE_3D:
4638 num_src_deriv_channels = 3;
4639 num_deriv_channels = 3;
4640 break;
4641 case TGSI_TEXTURE_2D:
4642 case TGSI_TEXTURE_SHADOW2D:
4643 case TGSI_TEXTURE_RECT:
4644 case TGSI_TEXTURE_SHADOWRECT:
4645 case TGSI_TEXTURE_2D_ARRAY:
4646 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4647 num_src_deriv_channels = 2;
4648 num_deriv_channels = 2;
4649 break;
4650 case TGSI_TEXTURE_CUBE:
4651 case TGSI_TEXTURE_SHADOWCUBE:
4652 case TGSI_TEXTURE_CUBE_ARRAY:
4653 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
4654 /* Cube derivatives will be converted to 2D. */
4655 num_src_deriv_channels = 3;
4656 num_deriv_channels = 2;
4657 break;
4658 case TGSI_TEXTURE_1D:
4659 case TGSI_TEXTURE_SHADOW1D:
4660 case TGSI_TEXTURE_1D_ARRAY:
4661 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4662 num_src_deriv_channels = 1;
4663 num_deriv_channels = 1;
4664 break;
4665 default:
4666 unreachable("invalid target");
4667 }
4668
4669 for (param = 0; param < 2; param++)
4670 for (chan = 0; chan < num_src_deriv_channels; chan++)
4671 derivs[param * num_src_deriv_channels + chan] =
4672 lp_build_emit_fetch(bld_base, inst, param+1, chan);
4673 }
4674
4675 if (target == TGSI_TEXTURE_CUBE ||
4676 target == TGSI_TEXTURE_CUBE_ARRAY ||
4677 target == TGSI_TEXTURE_SHADOWCUBE ||
4678 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
4679 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
4680
4681 if (opcode == TGSI_OPCODE_TXD)
4682 for (int i = 0; i < num_deriv_channels * 2; i++)
4683 address[count++] = derivs[i];
4684
4685 /* Pack texture coordinates */
4686 address[count++] = coords[0];
4687 if (num_coords > 1)
4688 address[count++] = coords[1];
4689 if (num_coords > 2)
4690 address[count++] = coords[2];
4691
4692 /* Pack LOD or sample index */
4693 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
4694 address[count++] = coords[3];
4695 else if (opcode == TGSI_OPCODE_TXL2)
4696 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
4697
4698 if (count > 16) {
4699 assert(!"Cannot handle more than 16 texture address parameters");
4700 count = 16;
4701 }
4702
4703 for (chan = 0; chan < count; chan++ ) {
4704 address[chan] = LLVMBuildBitCast(gallivm->builder,
4705 address[chan], ctx->i32, "");
4706 }
4707
4708 /* Adjust the sample index according to FMASK.
4709 *
4710 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
4711 * which is the identity mapping. Each nibble says which physical sample
4712 * should be fetched to get that sample.
4713 *
4714 * For example, 0x11111100 means there are only 2 samples stored and
4715 * the second sample covers 3/4 of the pixel. When reading samples 0
4716 * and 1, return physical sample 0 (determined by the first two 0s
4717 * in FMASK), otherwise return physical sample 1.
4718 *
4719 * The sample index should be adjusted as follows:
4720 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
4721 */
4722 if (target == TGSI_TEXTURE_2D_MSAA ||
4723 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
4724 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4725 struct lp_build_emit_data txf_emit_data = *emit_data;
4726 LLVMValueRef txf_address[4];
4727 unsigned txf_count = count;
4728 struct tgsi_full_instruction inst = {};
4729
4730 memcpy(txf_address, address, sizeof(txf_address));
4731
4732 if (target == TGSI_TEXTURE_2D_MSAA) {
4733 txf_address[2] = bld_base->uint_bld.zero;
4734 }
4735 txf_address[3] = bld_base->uint_bld.zero;
4736
4737 /* Read FMASK using TXF. */
4738 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
4739 inst.Texture.Texture = target;
4740 txf_emit_data.inst = &inst;
4741 txf_emit_data.chan = 0;
4742 set_tex_fetch_args(ctx, &txf_emit_data, TGSI_OPCODE_TXF,
4743 target, fmask_ptr, NULL,
4744 txf_address, txf_count, 0xf);
4745 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
4746
4747 /* Initialize some constants. */
4748 LLVMValueRef four = LLVMConstInt(ctx->i32, 4, 0);
4749 LLVMValueRef F = LLVMConstInt(ctx->i32, 0xF, 0);
4750
4751 /* Apply the formula. */
4752 LLVMValueRef fmask =
4753 LLVMBuildExtractElement(gallivm->builder,
4754 txf_emit_data.output[0],
4755 uint_bld->zero, "");
4756
4757 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
4758
4759 LLVMValueRef sample_index4 =
4760 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
4761
4762 LLVMValueRef shifted_fmask =
4763 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
4764
4765 LLVMValueRef final_sample =
4766 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
4767
4768 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
4769 * resource descriptor is 0 (invalid),
4770 */
4771 LLVMValueRef fmask_desc =
4772 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
4773 ctx->v8i32, "");
4774
4775 LLVMValueRef fmask_word1 =
4776 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
4777 uint_bld->one, "");
4778
4779 LLVMValueRef word1_is_nonzero =
4780 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
4781 fmask_word1, uint_bld->zero, "");
4782
4783 /* Replace the MSAA sample index. */
4784 address[sample_chan] =
4785 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
4786 final_sample, address[sample_chan], "");
4787 }
4788
4789 if (opcode == TGSI_OPCODE_TXF) {
4790 /* add tex offsets */
4791 if (inst->Texture.NumOffsets) {
4792 struct lp_build_context *uint_bld = &bld_base->uint_bld;
4793 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
4794 const struct tgsi_texture_offset *off = inst->TexOffsets;
4795
4796 assert(inst->Texture.NumOffsets == 1);
4797
4798 switch (target) {
4799 case TGSI_TEXTURE_3D:
4800 address[2] = lp_build_add(uint_bld, address[2],
4801 bld->immediates[off->Index][off->SwizzleZ]);
4802 /* fall through */
4803 case TGSI_TEXTURE_2D:
4804 case TGSI_TEXTURE_SHADOW2D:
4805 case TGSI_TEXTURE_RECT:
4806 case TGSI_TEXTURE_SHADOWRECT:
4807 case TGSI_TEXTURE_2D_ARRAY:
4808 case TGSI_TEXTURE_SHADOW2D_ARRAY:
4809 address[1] =
4810 lp_build_add(uint_bld, address[1],
4811 bld->immediates[off->Index][off->SwizzleY]);
4812 /* fall through */
4813 case TGSI_TEXTURE_1D:
4814 case TGSI_TEXTURE_SHADOW1D:
4815 case TGSI_TEXTURE_1D_ARRAY:
4816 case TGSI_TEXTURE_SHADOW1D_ARRAY:
4817 address[0] =
4818 lp_build_add(uint_bld, address[0],
4819 bld->immediates[off->Index][off->SwizzleX]);
4820 break;
4821 /* texture offsets do not apply to other texture targets */
4822 }
4823 }
4824 }
4825
4826 if (opcode == TGSI_OPCODE_TG4) {
4827 unsigned gather_comp = 0;
4828
4829 /* DMASK was repurposed for GATHER4. 4 components are always
4830 * returned and DMASK works like a swizzle - it selects
4831 * the component to fetch. The only valid DMASK values are
4832 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
4833 * (red,red,red,red) etc.) The ISA document doesn't mention
4834 * this.
4835 */
4836
4837 /* Get the component index from src1.x for Gather4. */
4838 if (!tgsi_is_shadow_target(target)) {
4839 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
4840 LLVMValueRef comp_imm;
4841 struct tgsi_src_register src1 = inst->Src[1].Register;
4842
4843 assert(src1.File == TGSI_FILE_IMMEDIATE);
4844
4845 comp_imm = imms[src1.Index][src1.SwizzleX];
4846 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
4847 gather_comp = CLAMP(gather_comp, 0, 3);
4848 }
4849
4850 dmask = 1 << gather_comp;
4851 }
4852
4853 set_tex_fetch_args(ctx, emit_data, opcode, target, res_ptr,
4854 samp_ptr, address, count, dmask);
4855 }
4856
4857 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
4858 * incorrectly forces nearest filtering if the texture format is integer.
4859 * The only effect it has on Gather4, which always returns 4 texels for
4860 * bilinear filtering, is that the final coordinates are off by 0.5 of
4861 * the texel size.
4862 *
4863 * The workaround is to subtract 0.5 from the unnormalized coordinates,
4864 * or (0.5 / size) from the normalized coordinates.
4865 */
4866 static void si_lower_gather4_integer(struct si_shader_context *ctx,
4867 struct lp_build_emit_data *emit_data,
4868 const char *intr_name,
4869 unsigned coord_vgpr_index)
4870 {
4871 LLVMBuilderRef builder = ctx->radeon_bld.gallivm.builder;
4872 LLVMValueRef coord = emit_data->args[0];
4873 LLVMValueRef half_texel[2];
4874 int c;
4875
4876 if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_RECT ||
4877 emit_data->inst->Texture.Texture == TGSI_TEXTURE_SHADOWRECT) {
4878 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
4879 } else {
4880 struct tgsi_full_instruction txq_inst = {};
4881 struct lp_build_emit_data txq_emit_data = {};
4882
4883 /* Query the texture size. */
4884 txq_inst.Texture.Texture = emit_data->inst->Texture.Texture;
4885 txq_emit_data.inst = &txq_inst;
4886 txq_emit_data.dst_type = ctx->v4i32;
4887 set_tex_fetch_args(ctx, &txq_emit_data, TGSI_OPCODE_TXQ,
4888 txq_inst.Texture.Texture,
4889 emit_data->args[1], NULL,
4890 &ctx->radeon_bld.soa.bld_base.uint_bld.zero,
4891 1, 0xf);
4892 txq_emit(NULL, &ctx->radeon_bld.soa.bld_base, &txq_emit_data);
4893
4894 /* Compute -0.5 / size. */
4895 for (c = 0; c < 2; c++) {
4896 half_texel[c] =
4897 LLVMBuildExtractElement(builder, txq_emit_data.output[0],
4898 LLVMConstInt(ctx->i32, c, 0), "");
4899 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
4900 half_texel[c] =
4901 lp_build_emit_llvm_unary(&ctx->radeon_bld.soa.bld_base,
4902 TGSI_OPCODE_RCP, half_texel[c]);
4903 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
4904 LLVMConstReal(ctx->f32, -0.5), "");
4905 }
4906 }
4907
4908 for (c = 0; c < 2; c++) {
4909 LLVMValueRef tmp;
4910 LLVMValueRef index = LLVMConstInt(ctx->i32, coord_vgpr_index + c, 0);
4911
4912 tmp = LLVMBuildExtractElement(builder, coord, index, "");
4913 tmp = LLVMBuildBitCast(builder, tmp, ctx->f32, "");
4914 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
4915 tmp = LLVMBuildBitCast(builder, tmp, ctx->i32, "");
4916 coord = LLVMBuildInsertElement(builder, coord, tmp, index, "");
4917 }
4918
4919 emit_data->args[0] = coord;
4920 emit_data->output[emit_data->chan] =
4921 lp_build_intrinsic(builder, intr_name, emit_data->dst_type,
4922 emit_data->args, emit_data->arg_count,
4923 LLVMReadNoneAttribute);
4924 }
4925
4926 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
4927 struct lp_build_tgsi_context *bld_base,
4928 struct lp_build_emit_data *emit_data)
4929 {
4930 struct si_shader_context *ctx = si_shader_context(bld_base);
4931 struct lp_build_context *base = &bld_base->base;
4932 const struct tgsi_full_instruction *inst = emit_data->inst;
4933 unsigned opcode = inst->Instruction.Opcode;
4934 unsigned target = inst->Texture.Texture;
4935 char intr_name[127];
4936 bool has_offset = inst->Texture.NumOffsets > 0;
4937 bool is_shadow = tgsi_is_shadow_target(target);
4938 char type[64];
4939 const char *name = "llvm.SI.image.sample";
4940 const char *infix = "";
4941
4942 if (target == TGSI_TEXTURE_BUFFER) {
4943 emit_data->output[emit_data->chan] = lp_build_intrinsic(
4944 base->gallivm->builder,
4945 "llvm.SI.vs.load.input", emit_data->dst_type,
4946 emit_data->args, emit_data->arg_count,
4947 LLVMReadNoneAttribute);
4948 return;
4949 }
4950
4951 switch (opcode) {
4952 case TGSI_OPCODE_TXF:
4953 name = target == TGSI_TEXTURE_2D_MSAA ||
4954 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
4955 "llvm.SI.image.load" :
4956 "llvm.SI.image.load.mip";
4957 is_shadow = false;
4958 has_offset = false;
4959 break;
4960 case TGSI_OPCODE_LODQ:
4961 name = "llvm.SI.getlod";
4962 is_shadow = false;
4963 has_offset = false;
4964 break;
4965 case TGSI_OPCODE_TEX:
4966 case TGSI_OPCODE_TEX2:
4967 case TGSI_OPCODE_TXP:
4968 if (ctx->type != PIPE_SHADER_FRAGMENT)
4969 infix = ".lz";
4970 break;
4971 case TGSI_OPCODE_TXB:
4972 case TGSI_OPCODE_TXB2:
4973 assert(ctx->type == PIPE_SHADER_FRAGMENT);
4974 infix = ".b";
4975 break;
4976 case TGSI_OPCODE_TXL:
4977 case TGSI_OPCODE_TXL2:
4978 infix = ".l";
4979 break;
4980 case TGSI_OPCODE_TXD:
4981 infix = ".d";
4982 break;
4983 case TGSI_OPCODE_TG4:
4984 name = "llvm.SI.gather4";
4985 infix = ".lz";
4986 break;
4987 default:
4988 assert(0);
4989 return;
4990 }
4991
4992 /* Add the type and suffixes .c, .o if needed. */
4993 build_type_name_for_intr(LLVMTypeOf(emit_data->args[0]), type, sizeof(type));
4994 sprintf(intr_name, "%s%s%s%s.%s",
4995 name, is_shadow ? ".c" : "", infix,
4996 has_offset ? ".o" : "", type);
4997
4998 /* The hardware needs special lowering for Gather4 with integer formats. */
4999 if (opcode == TGSI_OPCODE_TG4) {
5000 struct tgsi_shader_info *info = &ctx->shader->selector->info;
5001 /* This will also work with non-constant indexing because of how
5002 * glsl_to_tgsi works and we intent to preserve that behavior.
5003 */
5004 const unsigned src_idx = 2;
5005 unsigned sampler = inst->Src[src_idx].Register.Index;
5006
5007 assert(inst->Src[src_idx].Register.File == TGSI_FILE_SAMPLER);
5008
5009 if (info->sampler_type[sampler] == TGSI_RETURN_TYPE_SINT ||
5010 info->sampler_type[sampler] == TGSI_RETURN_TYPE_UINT) {
5011 /* Texture coordinates start after:
5012 * {offset, bias, z-compare, derivatives}
5013 * Only the offset and z-compare can occur here.
5014 */
5015 si_lower_gather4_integer(ctx, emit_data, intr_name,
5016 (int)has_offset + (int)is_shadow);
5017 return;
5018 }
5019 }
5020
5021 emit_data->output[emit_data->chan] = lp_build_intrinsic(
5022 base->gallivm->builder, intr_name, emit_data->dst_type,
5023 emit_data->args, emit_data->arg_count,
5024 LLVMReadNoneAttribute);
5025 }
5026
5027 static void si_llvm_emit_txqs(
5028 const struct lp_build_tgsi_action *action,
5029 struct lp_build_tgsi_context *bld_base,
5030 struct lp_build_emit_data *emit_data)
5031 {
5032 struct si_shader_context *ctx = si_shader_context(bld_base);
5033 struct gallivm_state *gallivm = bld_base->base.gallivm;
5034 LLVMBuilderRef builder = gallivm->builder;
5035 LLVMValueRef res, samples;
5036 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
5037
5038 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
5039
5040
5041 /* Read the samples from the descriptor directly. */
5042 res = LLVMBuildBitCast(builder, res_ptr, ctx->v8i32, "");
5043 samples = LLVMBuildExtractElement(
5044 builder, res,
5045 lp_build_const_int32(gallivm, 3), "");
5046 samples = LLVMBuildLShr(builder, samples,
5047 lp_build_const_int32(gallivm, 16), "");
5048 samples = LLVMBuildAnd(builder, samples,
5049 lp_build_const_int32(gallivm, 0xf), "");
5050 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
5051 samples, "");
5052
5053 emit_data->output[emit_data->chan] = samples;
5054 }
5055
5056 /*
5057 * SI implements derivatives using the local data store (LDS)
5058 * All writes to the LDS happen in all executing threads at
5059 * the same time. TID is the Thread ID for the current
5060 * thread and is a value between 0 and 63, representing
5061 * the thread's position in the wavefront.
5062 *
5063 * For the pixel shader threads are grouped into quads of four pixels.
5064 * The TIDs of the pixels of a quad are:
5065 *
5066 * +------+------+
5067 * |4n + 0|4n + 1|
5068 * +------+------+
5069 * |4n + 2|4n + 3|
5070 * +------+------+
5071 *
5072 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
5073 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
5074 * the current pixel's column, and masking with 0xfffffffe yields the TID
5075 * of the left pixel of the current pixel's row.
5076 *
5077 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
5078 * adding 2 yields the TID of the pixel below the top pixel.
5079 */
5080 /* masks for thread ID. */
5081 #define TID_MASK_TOP_LEFT 0xfffffffc
5082 #define TID_MASK_TOP 0xfffffffd
5083 #define TID_MASK_LEFT 0xfffffffe
5084
5085 static void si_llvm_emit_ddxy(
5086 const struct lp_build_tgsi_action *action,
5087 struct lp_build_tgsi_context *bld_base,
5088 struct lp_build_emit_data *emit_data)
5089 {
5090 struct si_shader_context *ctx = si_shader_context(bld_base);
5091 struct gallivm_state *gallivm = bld_base->base.gallivm;
5092 unsigned opcode = emit_data->info->opcode;
5093 LLVMValueRef thread_id, tl, trbl, tl_tid, trbl_tid, val, args[2];
5094 int idx;
5095 unsigned mask;
5096
5097 thread_id = get_thread_id(ctx);
5098
5099 if (opcode == TGSI_OPCODE_DDX_FINE)
5100 mask = TID_MASK_LEFT;
5101 else if (opcode == TGSI_OPCODE_DDY_FINE)
5102 mask = TID_MASK_TOP;
5103 else
5104 mask = TID_MASK_TOP_LEFT;
5105
5106 tl_tid = LLVMBuildAnd(gallivm->builder, thread_id,
5107 lp_build_const_int32(gallivm, mask), "");
5108
5109 /* for DDX we want to next X pixel, DDY next Y pixel. */
5110 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
5111 trbl_tid = LLVMBuildAdd(gallivm->builder, tl_tid,
5112 lp_build_const_int32(gallivm, idx), "");
5113
5114 val = LLVMBuildBitCast(gallivm->builder, emit_data->args[0], ctx->i32, "");
5115
5116 if (ctx->screen->has_ds_bpermute) {
5117 args[0] = LLVMBuildMul(gallivm->builder, tl_tid,
5118 lp_build_const_int32(gallivm, 4), "");
5119 args[1] = val;
5120 tl = lp_build_intrinsic(gallivm->builder,
5121 "llvm.amdgcn.ds.bpermute", ctx->i32,
5122 args, 2, LLVMReadNoneAttribute);
5123
5124 args[0] = LLVMBuildMul(gallivm->builder, trbl_tid,
5125 lp_build_const_int32(gallivm, 4), "");
5126 trbl = lp_build_intrinsic(gallivm->builder,
5127 "llvm.amdgcn.ds.bpermute", ctx->i32,
5128 args, 2, LLVMReadNoneAttribute);
5129 } else {
5130 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
5131
5132 store_ptr = build_gep0(ctx, ctx->lds, thread_id);
5133 load_ptr0 = build_gep0(ctx, ctx->lds, tl_tid);
5134 load_ptr1 = build_gep0(ctx, ctx->lds, trbl_tid);
5135
5136 LLVMBuildStore(gallivm->builder, val, store_ptr);
5137 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
5138 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
5139 }
5140
5141 tl = LLVMBuildBitCast(gallivm->builder, tl, ctx->f32, "");
5142 trbl = LLVMBuildBitCast(gallivm->builder, trbl, ctx->f32, "");
5143
5144 emit_data->output[emit_data->chan] =
5145 LLVMBuildFSub(gallivm->builder, trbl, tl, "");
5146 }
5147
5148 /*
5149 * this takes an I,J coordinate pair,
5150 * and works out the X and Y derivatives.
5151 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
5152 */
5153 static LLVMValueRef si_llvm_emit_ddxy_interp(
5154 struct lp_build_tgsi_context *bld_base,
5155 LLVMValueRef interp_ij)
5156 {
5157 struct si_shader_context *ctx = si_shader_context(bld_base);
5158 struct gallivm_state *gallivm = bld_base->base.gallivm;
5159 LLVMValueRef result[4], a;
5160 unsigned i;
5161
5162 for (i = 0; i < 2; i++) {
5163 a = LLVMBuildExtractElement(gallivm->builder, interp_ij,
5164 LLVMConstInt(ctx->i32, i, 0), "");
5165 result[i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDX, a);
5166 result[2+i] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_DDY, a);
5167 }
5168
5169 return lp_build_gather_values(gallivm, result, 4);
5170 }
5171
5172 static void interp_fetch_args(
5173 struct lp_build_tgsi_context *bld_base,
5174 struct lp_build_emit_data *emit_data)
5175 {
5176 struct si_shader_context *ctx = si_shader_context(bld_base);
5177 struct gallivm_state *gallivm = bld_base->base.gallivm;
5178 const struct tgsi_full_instruction *inst = emit_data->inst;
5179
5180 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
5181 /* offset is in second src, first two channels */
5182 emit_data->args[0] = lp_build_emit_fetch(bld_base,
5183 emit_data->inst, 1,
5184 TGSI_CHAN_X);
5185 emit_data->args[1] = lp_build_emit_fetch(bld_base,
5186 emit_data->inst, 1,
5187 TGSI_CHAN_Y);
5188 emit_data->arg_count = 2;
5189 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5190 LLVMValueRef sample_position;
5191 LLVMValueRef sample_id;
5192 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
5193
5194 /* fetch sample ID, then fetch its sample position,
5195 * and place into first two channels.
5196 */
5197 sample_id = lp_build_emit_fetch(bld_base,
5198 emit_data->inst, 1, TGSI_CHAN_X);
5199 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
5200 ctx->i32, "");
5201 sample_position = load_sample_position(&ctx->radeon_bld, sample_id);
5202
5203 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
5204 sample_position,
5205 lp_build_const_int32(gallivm, 0), "");
5206
5207 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
5208 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
5209 sample_position,
5210 lp_build_const_int32(gallivm, 1), "");
5211 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
5212 emit_data->arg_count = 2;
5213 }
5214 }
5215
5216 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
5217 struct lp_build_tgsi_context *bld_base,
5218 struct lp_build_emit_data *emit_data)
5219 {
5220 struct si_shader_context *ctx = si_shader_context(bld_base);
5221 struct si_shader *shader = ctx->shader;
5222 struct gallivm_state *gallivm = bld_base->base.gallivm;
5223 LLVMValueRef interp_param;
5224 const struct tgsi_full_instruction *inst = emit_data->inst;
5225 const char *intr_name;
5226 int input_index = inst->Src[0].Register.Index;
5227 int chan;
5228 int i;
5229 LLVMValueRef attr_number;
5230 LLVMValueRef params = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
5231 int interp_param_idx;
5232 unsigned interp = shader->selector->info.input_interpolate[input_index];
5233 unsigned location;
5234
5235 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
5236
5237 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5238 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
5239 location = TGSI_INTERPOLATE_LOC_CENTER;
5240 else
5241 location = TGSI_INTERPOLATE_LOC_CENTROID;
5242
5243 interp_param_idx = lookup_interp_param_index(interp, location);
5244 if (interp_param_idx == -1)
5245 return;
5246 else if (interp_param_idx)
5247 interp_param = get_interp_param(ctx, interp_param_idx);
5248 else
5249 interp_param = NULL;
5250
5251 attr_number = lp_build_const_int32(gallivm, input_index);
5252
5253 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
5254 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
5255 LLVMValueRef ij_out[2];
5256 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
5257
5258 /*
5259 * take the I then J parameters, and the DDX/Y for it, and
5260 * calculate the IJ inputs for the interpolator.
5261 * temp1 = ddx * offset/sample.x + I;
5262 * interp_param.I = ddy * offset/sample.y + temp1;
5263 * temp1 = ddx * offset/sample.x + J;
5264 * interp_param.J = ddy * offset/sample.y + temp1;
5265 */
5266 for (i = 0; i < 2; i++) {
5267 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
5268 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
5269 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
5270 ddxy_out, ix_ll, "");
5271 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
5272 ddxy_out, iy_ll, "");
5273 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
5274 interp_param, ix_ll, "");
5275 LLVMValueRef temp1, temp2;
5276
5277 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
5278 ctx->f32, "");
5279
5280 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
5281
5282 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
5283
5284 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
5285
5286 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
5287
5288 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
5289 temp2, ctx->i32, "");
5290 }
5291 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
5292 }
5293
5294 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
5295 for (chan = 0; chan < 4; chan++) {
5296 LLVMValueRef args[4];
5297 LLVMValueRef llvm_chan;
5298 unsigned schan;
5299
5300 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
5301 llvm_chan = lp_build_const_int32(gallivm, schan);
5302
5303 args[0] = llvm_chan;
5304 args[1] = attr_number;
5305 args[2] = params;
5306 args[3] = interp_param;
5307
5308 emit_data->output[chan] =
5309 lp_build_intrinsic(gallivm->builder, intr_name,
5310 ctx->f32, args, args[3] ? 4 : 3,
5311 LLVMReadNoneAttribute);
5312 }
5313 }
5314
5315 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
5316 struct lp_build_emit_data *emit_data)
5317 {
5318 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
5319 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
5320 unsigned stream;
5321
5322 assert(src0.File == TGSI_FILE_IMMEDIATE);
5323
5324 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
5325 return stream;
5326 }
5327
5328 /* Emit one vertex from the geometry shader */
5329 static void si_llvm_emit_vertex(
5330 const struct lp_build_tgsi_action *action,
5331 struct lp_build_tgsi_context *bld_base,
5332 struct lp_build_emit_data *emit_data)
5333 {
5334 struct si_shader_context *ctx = si_shader_context(bld_base);
5335 struct lp_build_context *uint = &bld_base->uint_bld;
5336 struct si_shader *shader = ctx->shader;
5337 struct tgsi_shader_info *info = &shader->selector->info;
5338 struct gallivm_state *gallivm = bld_base->base.gallivm;
5339 LLVMValueRef soffset = LLVMGetParam(ctx->radeon_bld.main_fn,
5340 SI_PARAM_GS2VS_OFFSET);
5341 LLVMValueRef gs_next_vertex;
5342 LLVMValueRef can_emit, kill;
5343 LLVMValueRef args[2];
5344 unsigned chan;
5345 int i;
5346 unsigned stream;
5347
5348 stream = si_llvm_get_stream(bld_base, emit_data);
5349
5350 /* Write vertex attribute values to GSVS ring */
5351 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
5352 ctx->gs_next_vertex[stream],
5353 "");
5354
5355 /* If this thread has already emitted the declared maximum number of
5356 * vertices, kill it: excessive vertex emissions are not supposed to
5357 * have any effect, and GS threads have no externally observable
5358 * effects other than emitting vertices.
5359 */
5360 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
5361 lp_build_const_int32(gallivm,
5362 shader->selector->gs_max_out_vertices), "");
5363 kill = lp_build_select(&bld_base->base, can_emit,
5364 lp_build_const_float(gallivm, 1.0f),
5365 lp_build_const_float(gallivm, -1.0f));
5366
5367 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
5368 ctx->voidt, &kill, 1, 0);
5369
5370 for (i = 0; i < info->num_outputs; i++) {
5371 LLVMValueRef *out_ptr =
5372 ctx->radeon_bld.soa.outputs[i];
5373
5374 for (chan = 0; chan < 4; chan++) {
5375 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
5376 LLVMValueRef voffset =
5377 lp_build_const_int32(gallivm, (i * 4 + chan) *
5378 shader->selector->gs_max_out_vertices);
5379
5380 voffset = lp_build_add(uint, voffset, gs_next_vertex);
5381 voffset = lp_build_mul_imm(uint, voffset, 4);
5382
5383 out_val = LLVMBuildBitCast(gallivm->builder, out_val, ctx->i32, "");
5384
5385 build_tbuffer_store(ctx,
5386 ctx->gsvs_ring[stream],
5387 out_val, 1,
5388 voffset, soffset, 0,
5389 V_008F0C_BUF_DATA_FORMAT_32,
5390 V_008F0C_BUF_NUM_FORMAT_UINT,
5391 1, 0, 1, 1, 0);
5392 }
5393 }
5394 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
5395 lp_build_const_int32(gallivm, 1));
5396
5397 LLVMBuildStore(gallivm->builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
5398
5399 /* Signal vertex emission */
5400 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
5401 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
5402 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5403 ctx->voidt, args, 2, 0);
5404 }
5405
5406 /* Cut one primitive from the geometry shader */
5407 static void si_llvm_emit_primitive(
5408 const struct lp_build_tgsi_action *action,
5409 struct lp_build_tgsi_context *bld_base,
5410 struct lp_build_emit_data *emit_data)
5411 {
5412 struct si_shader_context *ctx = si_shader_context(bld_base);
5413 struct gallivm_state *gallivm = bld_base->base.gallivm;
5414 LLVMValueRef args[2];
5415 unsigned stream;
5416
5417 /* Signal primitive cut */
5418 stream = si_llvm_get_stream(bld_base, emit_data);
5419 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
5420 args[1] = LLVMGetParam(ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
5421 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
5422 ctx->voidt, args, 2, 0);
5423 }
5424
5425 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
5426 struct lp_build_tgsi_context *bld_base,
5427 struct lp_build_emit_data *emit_data)
5428 {
5429 struct si_shader_context *ctx = si_shader_context(bld_base);
5430 struct gallivm_state *gallivm = bld_base->base.gallivm;
5431
5432 /* The real barrier instruction isn’t needed, because an entire patch
5433 * always fits into a single wave.
5434 */
5435 if (ctx->type == PIPE_SHADER_TESS_CTRL) {
5436 emit_optimization_barrier(ctx);
5437 return;
5438 }
5439
5440 lp_build_intrinsic(gallivm->builder,
5441 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
5442 : "llvm.AMDGPU.barrier.local",
5443 ctx->voidt, NULL, 0, 0);
5444 }
5445
5446 static const struct lp_build_tgsi_action tex_action = {
5447 .fetch_args = tex_fetch_args,
5448 .emit = build_tex_intrinsic,
5449 };
5450
5451 static const struct lp_build_tgsi_action interp_action = {
5452 .fetch_args = interp_fetch_args,
5453 .emit = build_interp_intrinsic,
5454 };
5455
5456 static void si_create_function(struct si_shader_context *ctx,
5457 LLVMTypeRef *returns, unsigned num_returns,
5458 LLVMTypeRef *params, unsigned num_params,
5459 int last_sgpr)
5460 {
5461 int i;
5462
5463 radeon_llvm_create_func(&ctx->radeon_bld, returns, num_returns,
5464 params, num_params);
5465 radeon_llvm_shader_type(ctx->radeon_bld.main_fn, ctx->type);
5466 ctx->return_value = LLVMGetUndef(ctx->radeon_bld.return_type);
5467
5468 for (i = 0; i <= last_sgpr; ++i) {
5469 LLVMValueRef P = LLVMGetParam(ctx->radeon_bld.main_fn, i);
5470
5471 /* The combination of:
5472 * - ByVal
5473 * - dereferenceable
5474 * - invariant.load
5475 * allows the optimization passes to move loads and reduces
5476 * SGPR spilling significantly.
5477 */
5478 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
5479 LLVMAddAttribute(P, LLVMByValAttribute);
5480 lp_add_attr_dereferenceable(P, UINT64_MAX);
5481 } else
5482 LLVMAddAttribute(P, LLVMInRegAttribute);
5483 }
5484
5485 if (ctx->screen->b.debug_flags & DBG_UNSAFE_MATH) {
5486 /* These were copied from some LLVM test. */
5487 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5488 "less-precise-fpmad",
5489 "true");
5490 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5491 "no-infs-fp-math",
5492 "true");
5493 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5494 "no-nans-fp-math",
5495 "true");
5496 LLVMAddTargetDependentFunctionAttr(ctx->radeon_bld.main_fn,
5497 "unsafe-fp-math",
5498 "true");
5499 }
5500 }
5501
5502 static void create_meta_data(struct si_shader_context *ctx)
5503 {
5504 struct gallivm_state *gallivm = ctx->radeon_bld.soa.bld_base.base.gallivm;
5505
5506 ctx->invariant_load_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5507 "invariant.load", 14);
5508 ctx->range_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5509 "range", 5);
5510 ctx->uniform_md_kind = LLVMGetMDKindIDInContext(gallivm->context,
5511 "amdgpu.uniform", 14);
5512
5513 ctx->empty_md = LLVMMDNodeInContext(gallivm->context, NULL, 0);
5514 }
5515
5516 static void declare_streamout_params(struct si_shader_context *ctx,
5517 struct pipe_stream_output_info *so,
5518 LLVMTypeRef *params, LLVMTypeRef i32,
5519 unsigned *num_params)
5520 {
5521 int i;
5522
5523 /* Streamout SGPRs. */
5524 if (so->num_outputs) {
5525 if (ctx->type != PIPE_SHADER_TESS_EVAL)
5526 params[ctx->param_streamout_config = (*num_params)++] = i32;
5527 else
5528 ctx->param_streamout_config = ctx->param_tess_offchip;
5529
5530 params[ctx->param_streamout_write_index = (*num_params)++] = i32;
5531 }
5532 /* A streamout buffer offset is loaded if the stride is non-zero. */
5533 for (i = 0; i < 4; i++) {
5534 if (!so->stride[i])
5535 continue;
5536
5537 params[ctx->param_streamout_offset[i] = (*num_params)++] = i32;
5538 }
5539 }
5540
5541 static unsigned llvm_get_type_size(LLVMTypeRef type)
5542 {
5543 LLVMTypeKind kind = LLVMGetTypeKind(type);
5544
5545 switch (kind) {
5546 case LLVMIntegerTypeKind:
5547 return LLVMGetIntTypeWidth(type) / 8;
5548 case LLVMFloatTypeKind:
5549 return 4;
5550 case LLVMPointerTypeKind:
5551 return 8;
5552 case LLVMVectorTypeKind:
5553 return LLVMGetVectorSize(type) *
5554 llvm_get_type_size(LLVMGetElementType(type));
5555 default:
5556 assert(0);
5557 return 0;
5558 }
5559 }
5560
5561 static void declare_tess_lds(struct si_shader_context *ctx)
5562 {
5563 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
5564 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5565 struct lp_build_context *uint = &bld_base->uint_bld;
5566
5567 unsigned lds_size = ctx->screen->b.chip_class >= CIK ? 65536 : 32768;
5568 ctx->lds = LLVMBuildIntToPtr(gallivm->builder, uint->zero,
5569 LLVMPointerType(LLVMArrayType(ctx->i32, lds_size / 4), LOCAL_ADDR_SPACE),
5570 "tess_lds");
5571 }
5572
5573 static void create_function(struct si_shader_context *ctx)
5574 {
5575 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
5576 struct gallivm_state *gallivm = bld_base->base.gallivm;
5577 struct si_shader *shader = ctx->shader;
5578 LLVMTypeRef params[SI_NUM_PARAMS + SI_NUM_VERTEX_BUFFERS], v3i32;
5579 LLVMTypeRef returns[16+32*4];
5580 unsigned i, last_sgpr, num_params, num_return_sgprs;
5581 unsigned num_returns = 0;
5582
5583 v3i32 = LLVMVectorType(ctx->i32, 3);
5584
5585 params[SI_PARAM_RW_BUFFERS] = const_array(ctx->v16i8, SI_NUM_RW_BUFFERS);
5586 params[SI_PARAM_CONST_BUFFERS] = const_array(ctx->v16i8, SI_NUM_CONST_BUFFERS);
5587 params[SI_PARAM_SAMPLERS] = const_array(ctx->v8i32, SI_NUM_SAMPLERS);
5588 params[SI_PARAM_IMAGES] = const_array(ctx->v8i32, SI_NUM_IMAGES);
5589 params[SI_PARAM_SHADER_BUFFERS] = const_array(ctx->v4i32, SI_NUM_SHADER_BUFFERS);
5590
5591 switch (ctx->type) {
5592 case PIPE_SHADER_VERTEX:
5593 params[SI_PARAM_VERTEX_BUFFERS] = const_array(ctx->v16i8, SI_NUM_VERTEX_BUFFERS);
5594 params[SI_PARAM_BASE_VERTEX] = ctx->i32;
5595 params[SI_PARAM_START_INSTANCE] = ctx->i32;
5596 params[SI_PARAM_DRAWID] = ctx->i32;
5597 num_params = SI_PARAM_DRAWID+1;
5598
5599 if (shader->key.vs.as_es) {
5600 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5601 } else if (shader->key.vs.as_ls) {
5602 params[SI_PARAM_LS_OUT_LAYOUT] = ctx->i32;
5603 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
5604 } else {
5605 if (ctx->is_gs_copy_shader) {
5606 num_params = SI_PARAM_RW_BUFFERS+1;
5607 } else {
5608 params[SI_PARAM_VS_STATE_BITS] = ctx->i32;
5609 num_params = SI_PARAM_VS_STATE_BITS+1;
5610 }
5611
5612 /* The locations of the other parameters are assigned dynamically. */
5613 declare_streamout_params(ctx, &shader->selector->so,
5614 params, ctx->i32, &num_params);
5615 }
5616
5617 last_sgpr = num_params-1;
5618
5619 /* VGPRs */
5620 params[ctx->param_vertex_id = num_params++] = ctx->i32;
5621 params[ctx->param_rel_auto_id = num_params++] = ctx->i32;
5622 params[ctx->param_vs_prim_id = num_params++] = ctx->i32;
5623 params[ctx->param_instance_id = num_params++] = ctx->i32;
5624
5625 if (!ctx->is_monolithic &&
5626 !ctx->is_gs_copy_shader) {
5627 /* Vertex load indices. */
5628 ctx->param_vertex_index0 = num_params;
5629
5630 for (i = 0; i < shader->selector->info.num_inputs; i++)
5631 params[num_params++] = ctx->i32;
5632
5633 /* PrimitiveID output. */
5634 if (!shader->key.vs.as_es && !shader->key.vs.as_ls)
5635 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5636 returns[num_returns++] = ctx->f32;
5637 }
5638 break;
5639
5640 case PIPE_SHADER_TESS_CTRL:
5641 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5642 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx->i32;
5643 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx->i32;
5644 params[SI_PARAM_TCS_IN_LAYOUT] = ctx->i32;
5645 params[ctx->param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx->i32;
5646 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx->i32;
5647 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
5648
5649 /* VGPRs */
5650 params[SI_PARAM_PATCH_ID] = ctx->i32;
5651 params[SI_PARAM_REL_IDS] = ctx->i32;
5652 num_params = SI_PARAM_REL_IDS+1;
5653
5654 if (!ctx->is_monolithic) {
5655 /* SI_PARAM_TCS_OC_LDS and PARAM_TESS_FACTOR_OFFSET are
5656 * placed after the user SGPRs.
5657 */
5658 for (i = 0; i < SI_TCS_NUM_USER_SGPR + 2; i++)
5659 returns[num_returns++] = ctx->i32; /* SGPRs */
5660
5661 for (i = 0; i < 3; i++)
5662 returns[num_returns++] = ctx->f32; /* VGPRs */
5663 }
5664 break;
5665
5666 case PIPE_SHADER_TESS_EVAL:
5667 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx->i32;
5668 num_params = SI_PARAM_TCS_OFFCHIP_LAYOUT+1;
5669
5670 if (shader->key.tes.as_es) {
5671 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5672 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5673 params[ctx->param_es2gs_offset = num_params++] = ctx->i32;
5674 } else {
5675 params[ctx->param_tess_offchip = num_params++] = ctx->i32;
5676 declare_streamout_params(ctx, &shader->selector->so,
5677 params, ctx->i32, &num_params);
5678 params[ctx->param_oc_lds = num_params++] = ctx->i32;
5679 }
5680 last_sgpr = num_params - 1;
5681
5682 /* VGPRs */
5683 params[ctx->param_tes_u = num_params++] = ctx->f32;
5684 params[ctx->param_tes_v = num_params++] = ctx->f32;
5685 params[ctx->param_tes_rel_patch_id = num_params++] = ctx->i32;
5686 params[ctx->param_tes_patch_id = num_params++] = ctx->i32;
5687
5688 /* PrimitiveID output. */
5689 if (!ctx->is_monolithic && !shader->key.tes.as_es)
5690 for (i = 0; i <= VS_EPILOG_PRIMID_LOC; i++)
5691 returns[num_returns++] = ctx->f32;
5692 break;
5693
5694 case PIPE_SHADER_GEOMETRY:
5695 params[SI_PARAM_GS2VS_OFFSET] = ctx->i32;
5696 params[SI_PARAM_GS_WAVE_ID] = ctx->i32;
5697 last_sgpr = SI_PARAM_GS_WAVE_ID;
5698
5699 /* VGPRs */
5700 params[SI_PARAM_VTX0_OFFSET] = ctx->i32;
5701 params[SI_PARAM_VTX1_OFFSET] = ctx->i32;
5702 params[SI_PARAM_PRIMITIVE_ID] = ctx->i32;
5703 params[SI_PARAM_VTX2_OFFSET] = ctx->i32;
5704 params[SI_PARAM_VTX3_OFFSET] = ctx->i32;
5705 params[SI_PARAM_VTX4_OFFSET] = ctx->i32;
5706 params[SI_PARAM_VTX5_OFFSET] = ctx->i32;
5707 params[SI_PARAM_GS_INSTANCE_ID] = ctx->i32;
5708 num_params = SI_PARAM_GS_INSTANCE_ID+1;
5709 break;
5710
5711 case PIPE_SHADER_FRAGMENT:
5712 params[SI_PARAM_ALPHA_REF] = ctx->f32;
5713 params[SI_PARAM_PRIM_MASK] = ctx->i32;
5714 last_sgpr = SI_PARAM_PRIM_MASK;
5715 params[SI_PARAM_PERSP_SAMPLE] = ctx->v2i32;
5716 params[SI_PARAM_PERSP_CENTER] = ctx->v2i32;
5717 params[SI_PARAM_PERSP_CENTROID] = ctx->v2i32;
5718 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
5719 params[SI_PARAM_LINEAR_SAMPLE] = ctx->v2i32;
5720 params[SI_PARAM_LINEAR_CENTER] = ctx->v2i32;
5721 params[SI_PARAM_LINEAR_CENTROID] = ctx->v2i32;
5722 params[SI_PARAM_LINE_STIPPLE_TEX] = ctx->f32;
5723 params[SI_PARAM_POS_X_FLOAT] = ctx->f32;
5724 params[SI_PARAM_POS_Y_FLOAT] = ctx->f32;
5725 params[SI_PARAM_POS_Z_FLOAT] = ctx->f32;
5726 params[SI_PARAM_POS_W_FLOAT] = ctx->f32;
5727 params[SI_PARAM_FRONT_FACE] = ctx->i32;
5728 params[SI_PARAM_ANCILLARY] = ctx->i32;
5729 params[SI_PARAM_SAMPLE_COVERAGE] = ctx->f32;
5730 params[SI_PARAM_POS_FIXED_PT] = ctx->i32;
5731 num_params = SI_PARAM_POS_FIXED_PT+1;
5732
5733 if (!ctx->is_monolithic) {
5734 /* Color inputs from the prolog. */
5735 if (shader->selector->info.colors_read) {
5736 unsigned num_color_elements =
5737 util_bitcount(shader->selector->info.colors_read);
5738
5739 assert(num_params + num_color_elements <= ARRAY_SIZE(params));
5740 for (i = 0; i < num_color_elements; i++)
5741 params[num_params++] = ctx->f32;
5742 }
5743
5744 /* Outputs for the epilog. */
5745 num_return_sgprs = SI_SGPR_ALPHA_REF + 1;
5746 num_returns =
5747 num_return_sgprs +
5748 util_bitcount(shader->selector->info.colors_written) * 4 +
5749 shader->selector->info.writes_z +
5750 shader->selector->info.writes_stencil +
5751 shader->selector->info.writes_samplemask +
5752 1 /* SampleMaskIn */;
5753
5754 num_returns = MAX2(num_returns,
5755 num_return_sgprs +
5756 PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
5757
5758 for (i = 0; i < num_return_sgprs; i++)
5759 returns[i] = ctx->i32;
5760 for (; i < num_returns; i++)
5761 returns[i] = ctx->f32;
5762 }
5763 break;
5764
5765 case PIPE_SHADER_COMPUTE:
5766 params[SI_PARAM_GRID_SIZE] = v3i32;
5767 params[SI_PARAM_BLOCK_SIZE] = v3i32;
5768 params[SI_PARAM_BLOCK_ID] = v3i32;
5769 last_sgpr = SI_PARAM_BLOCK_ID;
5770
5771 params[SI_PARAM_THREAD_ID] = v3i32;
5772 num_params = SI_PARAM_THREAD_ID + 1;
5773 break;
5774 default:
5775 assert(0 && "unimplemented shader");
5776 return;
5777 }
5778
5779 assert(num_params <= ARRAY_SIZE(params));
5780
5781 si_create_function(ctx, returns, num_returns, params,
5782 num_params, last_sgpr);
5783
5784 /* Reserve register locations for VGPR inputs the PS prolog may need. */
5785 if (ctx->type == PIPE_SHADER_FRAGMENT &&
5786 !ctx->is_monolithic) {
5787 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5788 "InitialPSInputAddr",
5789 S_0286D0_PERSP_SAMPLE_ENA(1) |
5790 S_0286D0_PERSP_CENTER_ENA(1) |
5791 S_0286D0_PERSP_CENTROID_ENA(1) |
5792 S_0286D0_LINEAR_SAMPLE_ENA(1) |
5793 S_0286D0_LINEAR_CENTER_ENA(1) |
5794 S_0286D0_LINEAR_CENTROID_ENA(1) |
5795 S_0286D0_FRONT_FACE_ENA(1) |
5796 S_0286D0_POS_FIXED_PT_ENA(1));
5797 } else if (ctx->type == PIPE_SHADER_COMPUTE) {
5798 const unsigned *properties = shader->selector->info.properties;
5799 unsigned max_work_group_size =
5800 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
5801 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
5802 properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
5803
5804 if (!max_work_group_size) {
5805 /* This is a variable group size compute shader,
5806 * compile it for the maximum possible group size.
5807 */
5808 max_work_group_size = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
5809 }
5810
5811 radeon_llvm_add_attribute(ctx->radeon_bld.main_fn,
5812 "amdgpu-max-work-group-size",
5813 max_work_group_size);
5814 }
5815
5816 shader->info.num_input_sgprs = 0;
5817 shader->info.num_input_vgprs = 0;
5818
5819 for (i = 0; i <= last_sgpr; ++i)
5820 shader->info.num_input_sgprs += llvm_get_type_size(params[i]) / 4;
5821
5822 /* Unused fragment shader inputs are eliminated by the compiler,
5823 * so we don't know yet how many there will be.
5824 */
5825 if (ctx->type != PIPE_SHADER_FRAGMENT)
5826 for (; i < num_params; ++i)
5827 shader->info.num_input_vgprs += llvm_get_type_size(params[i]) / 4;
5828
5829 if (!ctx->screen->has_ds_bpermute &&
5830 bld_base->info &&
5831 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
5832 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
5833 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
5834 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
5835 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
5836 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
5837 ctx->lds =
5838 LLVMAddGlobalInAddressSpace(gallivm->module,
5839 LLVMArrayType(ctx->i32, 64),
5840 "ddxy_lds",
5841 LOCAL_ADDR_SPACE);
5842
5843 if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.vs.as_ls) ||
5844 ctx->type == PIPE_SHADER_TESS_CTRL ||
5845 ctx->type == PIPE_SHADER_TESS_EVAL)
5846 declare_tess_lds(ctx);
5847 }
5848
5849 /**
5850 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
5851 * for later use.
5852 */
5853 static void preload_ring_buffers(struct si_shader_context *ctx)
5854 {
5855 struct gallivm_state *gallivm =
5856 ctx->radeon_bld.soa.bld_base.base.gallivm;
5857
5858 LLVMValueRef buf_ptr = LLVMGetParam(ctx->radeon_bld.main_fn,
5859 SI_PARAM_RW_BUFFERS);
5860
5861 if ((ctx->type == PIPE_SHADER_VERTEX &&
5862 ctx->shader->key.vs.as_es) ||
5863 (ctx->type == PIPE_SHADER_TESS_EVAL &&
5864 ctx->shader->key.tes.as_es) ||
5865 ctx->type == PIPE_SHADER_GEOMETRY) {
5866 unsigned ring =
5867 ctx->type == PIPE_SHADER_GEOMETRY ? SI_GS_RING_ESGS
5868 : SI_ES_RING_ESGS;
5869 LLVMValueRef offset = lp_build_const_int32(gallivm, ring);
5870
5871 ctx->esgs_ring =
5872 build_indexed_load_const(ctx, buf_ptr, offset);
5873 }
5874
5875 if (ctx->is_gs_copy_shader) {
5876 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_VS_RING_GSVS);
5877
5878 ctx->gsvs_ring[0] =
5879 build_indexed_load_const(ctx, buf_ptr, offset);
5880 }
5881 if (ctx->type == PIPE_SHADER_GEOMETRY) {
5882 int i;
5883 for (i = 0; i < 4; i++) {
5884 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_GS_RING_GSVS0 + i);
5885
5886 ctx->gsvs_ring[i] =
5887 build_indexed_load_const(ctx, buf_ptr, offset);
5888 }
5889 }
5890 }
5891
5892 static void si_llvm_emit_polygon_stipple(struct si_shader_context *ctx,
5893 LLVMValueRef param_rw_buffers,
5894 unsigned param_pos_fixed_pt)
5895 {
5896 struct lp_build_tgsi_context *bld_base =
5897 &ctx->radeon_bld.soa.bld_base;
5898 struct gallivm_state *gallivm = bld_base->base.gallivm;
5899 LLVMBuilderRef builder = gallivm->builder;
5900 LLVMValueRef slot, desc, offset, row, bit, address[2];
5901
5902 /* Use the fixed-point gl_FragCoord input.
5903 * Since the stipple pattern is 32x32 and it repeats, just get 5 bits
5904 * per coordinate to get the repeating effect.
5905 */
5906 address[0] = unpack_param(ctx, param_pos_fixed_pt, 0, 5);
5907 address[1] = unpack_param(ctx, param_pos_fixed_pt, 16, 5);
5908
5909 /* Load the buffer descriptor. */
5910 slot = lp_build_const_int32(gallivm, SI_PS_CONST_POLY_STIPPLE);
5911 desc = build_indexed_load_const(ctx, param_rw_buffers, slot);
5912
5913 /* The stipple pattern is 32x32, each row has 32 bits. */
5914 offset = LLVMBuildMul(builder, address[1],
5915 LLVMConstInt(ctx->i32, 4, 0), "");
5916 row = buffer_load_const(ctx, desc, offset);
5917 row = LLVMBuildBitCast(builder, row, ctx->i32, "");
5918 bit = LLVMBuildLShr(builder, row, address[0], "");
5919 bit = LLVMBuildTrunc(builder, bit, ctx->i1, "");
5920
5921 /* The intrinsic kills the thread if arg < 0. */
5922 bit = LLVMBuildSelect(builder, bit, LLVMConstReal(ctx->f32, 0),
5923 LLVMConstReal(ctx->f32, -1), "");
5924 lp_build_intrinsic(builder, "llvm.AMDGPU.kill", ctx->voidt, &bit, 1, 0);
5925 }
5926
5927 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
5928 struct si_shader_config *conf,
5929 unsigned symbol_offset)
5930 {
5931 unsigned i;
5932 const unsigned char *config =
5933 radeon_shader_binary_config_start(binary, symbol_offset);
5934 bool really_needs_scratch = false;
5935
5936 /* LLVM adds SGPR spills to the scratch size.
5937 * Find out if we really need the scratch buffer.
5938 */
5939 for (i = 0; i < binary->reloc_count; i++) {
5940 const struct radeon_shader_reloc *reloc = &binary->relocs[i];
5941
5942 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name) ||
5943 !strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
5944 really_needs_scratch = true;
5945 break;
5946 }
5947 }
5948
5949 /* XXX: We may be able to emit some of these values directly rather than
5950 * extracting fields to be emitted later.
5951 */
5952
5953 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
5954 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
5955 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
5956 switch (reg) {
5957 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
5958 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
5959 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
5960 case R_00B848_COMPUTE_PGM_RSRC1:
5961 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
5962 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
5963 conf->float_mode = G_00B028_FLOAT_MODE(value);
5964 conf->rsrc1 = value;
5965 break;
5966 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
5967 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
5968 break;
5969 case R_00B84C_COMPUTE_PGM_RSRC2:
5970 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
5971 conf->rsrc2 = value;
5972 break;
5973 case R_0286CC_SPI_PS_INPUT_ENA:
5974 conf->spi_ps_input_ena = value;
5975 break;
5976 case R_0286D0_SPI_PS_INPUT_ADDR:
5977 conf->spi_ps_input_addr = value;
5978 break;
5979 case R_0286E8_SPI_TMPRING_SIZE:
5980 case R_00B860_COMPUTE_TMPRING_SIZE:
5981 /* WAVESIZE is in units of 256 dwords. */
5982 if (really_needs_scratch)
5983 conf->scratch_bytes_per_wave =
5984 G_00B860_WAVESIZE(value) * 256 * 4;
5985 break;
5986 case 0x4: /* SPILLED_SGPRS */
5987 conf->spilled_sgprs = value;
5988 break;
5989 case 0x8: /* SPILLED_VGPRS */
5990 conf->spilled_vgprs = value;
5991 break;
5992 default:
5993 {
5994 static bool printed;
5995
5996 if (!printed) {
5997 fprintf(stderr, "Warning: LLVM emitted unknown "
5998 "config register: 0x%x\n", reg);
5999 printed = true;
6000 }
6001 }
6002 break;
6003 }
6004 }
6005
6006 if (!conf->spi_ps_input_addr)
6007 conf->spi_ps_input_addr = conf->spi_ps_input_ena;
6008 }
6009
6010 void si_shader_apply_scratch_relocs(struct si_context *sctx,
6011 struct si_shader *shader,
6012 struct si_shader_config *config,
6013 uint64_t scratch_va)
6014 {
6015 unsigned i;
6016 uint32_t scratch_rsrc_dword0 = scratch_va;
6017 uint32_t scratch_rsrc_dword1 =
6018 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
6019
6020 /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
6021 * correctly.
6022 */
6023 if (HAVE_LLVM >= 0x0309)
6024 scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
6025 else
6026 scratch_rsrc_dword1 |=
6027 S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
6028
6029 for (i = 0 ; i < shader->binary.reloc_count; i++) {
6030 const struct radeon_shader_reloc *reloc =
6031 &shader->binary.relocs[i];
6032 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
6033 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
6034 &scratch_rsrc_dword0, 4);
6035 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
6036 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
6037 &scratch_rsrc_dword1, 4);
6038 }
6039 }
6040 }
6041
6042 static unsigned si_get_shader_binary_size(struct si_shader *shader)
6043 {
6044 unsigned size = shader->binary.code_size;
6045
6046 if (shader->prolog)
6047 size += shader->prolog->binary.code_size;
6048 if (shader->epilog)
6049 size += shader->epilog->binary.code_size;
6050 return size;
6051 }
6052
6053 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
6054 {
6055 const struct radeon_shader_binary *prolog =
6056 shader->prolog ? &shader->prolog->binary : NULL;
6057 const struct radeon_shader_binary *epilog =
6058 shader->epilog ? &shader->epilog->binary : NULL;
6059 const struct radeon_shader_binary *mainb = &shader->binary;
6060 unsigned bo_size = si_get_shader_binary_size(shader) +
6061 (!epilog ? mainb->rodata_size : 0);
6062 unsigned char *ptr;
6063
6064 assert(!prolog || !prolog->rodata_size);
6065 assert((!prolog && !epilog) || !mainb->rodata_size);
6066 assert(!epilog || !epilog->rodata_size);
6067
6068 r600_resource_reference(&shader->bo, NULL);
6069 shader->bo = si_resource_create_custom(&sscreen->b.b,
6070 PIPE_USAGE_IMMUTABLE,
6071 bo_size);
6072 if (!shader->bo)
6073 return -ENOMEM;
6074
6075 /* Upload. */
6076 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
6077 PIPE_TRANSFER_READ_WRITE);
6078
6079 if (prolog) {
6080 util_memcpy_cpu_to_le32(ptr, prolog->code, prolog->code_size);
6081 ptr += prolog->code_size;
6082 }
6083
6084 util_memcpy_cpu_to_le32(ptr, mainb->code, mainb->code_size);
6085 ptr += mainb->code_size;
6086
6087 if (epilog)
6088 util_memcpy_cpu_to_le32(ptr, epilog->code, epilog->code_size);
6089 else if (mainb->rodata_size > 0)
6090 util_memcpy_cpu_to_le32(ptr, mainb->rodata, mainb->rodata_size);
6091
6092 sscreen->b.ws->buffer_unmap(shader->bo->buf);
6093 return 0;
6094 }
6095
6096 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
6097 struct pipe_debug_callback *debug,
6098 const char *name, FILE *file)
6099 {
6100 char *line, *p;
6101 unsigned i, count;
6102
6103 if (binary->disasm_string) {
6104 fprintf(file, "Shader %s disassembly:\n", name);
6105 fprintf(file, "%s", binary->disasm_string);
6106
6107 if (debug && debug->debug_message) {
6108 /* Very long debug messages are cut off, so send the
6109 * disassembly one line at a time. This causes more
6110 * overhead, but on the plus side it simplifies
6111 * parsing of resulting logs.
6112 */
6113 pipe_debug_message(debug, SHADER_INFO,
6114 "Shader Disassembly Begin");
6115
6116 line = binary->disasm_string;
6117 while (*line) {
6118 p = util_strchrnul(line, '\n');
6119 count = p - line;
6120
6121 if (count) {
6122 pipe_debug_message(debug, SHADER_INFO,
6123 "%.*s", count, line);
6124 }
6125
6126 if (!*p)
6127 break;
6128 line = p + 1;
6129 }
6130
6131 pipe_debug_message(debug, SHADER_INFO,
6132 "Shader Disassembly End");
6133 }
6134 } else {
6135 fprintf(file, "Shader %s binary:\n", name);
6136 for (i = 0; i < binary->code_size; i += 4) {
6137 fprintf(file, "@0x%x: %02x%02x%02x%02x\n", i,
6138 binary->code[i + 3], binary->code[i + 2],
6139 binary->code[i + 1], binary->code[i]);
6140 }
6141 }
6142 }
6143
6144 static void si_shader_dump_stats(struct si_screen *sscreen,
6145 struct si_shader_config *conf,
6146 unsigned num_inputs,
6147 unsigned code_size,
6148 struct pipe_debug_callback *debug,
6149 unsigned processor,
6150 FILE *file)
6151 {
6152 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
6153 unsigned lds_per_wave = 0;
6154 unsigned max_simd_waves = 10;
6155
6156 /* Compute LDS usage for PS. */
6157 if (processor == PIPE_SHADER_FRAGMENT) {
6158 /* The minimum usage per wave is (num_inputs * 48). The maximum
6159 * usage is (num_inputs * 48 * 16).
6160 * We can get anything in between and it varies between waves.
6161 *
6162 * The 48 bytes per input for a single primitive is equal to
6163 * 4 bytes/component * 4 components/input * 3 points.
6164 *
6165 * Other stages don't know the size at compile time or don't
6166 * allocate LDS per wave, but instead they do it per thread group.
6167 */
6168 lds_per_wave = conf->lds_size * lds_increment +
6169 align(num_inputs * 48, lds_increment);
6170 }
6171
6172 /* Compute the per-SIMD wave counts. */
6173 if (conf->num_sgprs) {
6174 if (sscreen->b.chip_class >= VI)
6175 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
6176 else
6177 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
6178 }
6179
6180 if (conf->num_vgprs)
6181 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
6182
6183 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
6184 * that PS can use.
6185 */
6186 if (lds_per_wave)
6187 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
6188
6189 if (file != stderr ||
6190 r600_can_dump_shader(&sscreen->b, processor)) {
6191 if (processor == PIPE_SHADER_FRAGMENT) {
6192 fprintf(file, "*** SHADER CONFIG ***\n"
6193 "SPI_PS_INPUT_ADDR = 0x%04x\n"
6194 "SPI_PS_INPUT_ENA = 0x%04x\n",
6195 conf->spi_ps_input_addr, conf->spi_ps_input_ena);
6196 }
6197
6198 fprintf(file, "*** SHADER STATS ***\n"
6199 "SGPRS: %d\n"
6200 "VGPRS: %d\n"
6201 "Spilled SGPRs: %d\n"
6202 "Spilled VGPRs: %d\n"
6203 "Code Size: %d bytes\n"
6204 "LDS: %d blocks\n"
6205 "Scratch: %d bytes per wave\n"
6206 "Max Waves: %d\n"
6207 "********************\n\n\n",
6208 conf->num_sgprs, conf->num_vgprs,
6209 conf->spilled_sgprs, conf->spilled_vgprs, code_size,
6210 conf->lds_size, conf->scratch_bytes_per_wave,
6211 max_simd_waves);
6212 }
6213
6214 pipe_debug_message(debug, SHADER_INFO,
6215 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
6216 "LDS: %d Scratch: %d Max Waves: %d Spilled SGPRs: %d "
6217 "Spilled VGPRs: %d",
6218 conf->num_sgprs, conf->num_vgprs, code_size,
6219 conf->lds_size, conf->scratch_bytes_per_wave,
6220 max_simd_waves, conf->spilled_sgprs,
6221 conf->spilled_vgprs);
6222 }
6223
6224 static const char *si_get_shader_name(struct si_shader *shader,
6225 unsigned processor)
6226 {
6227 switch (processor) {
6228 case PIPE_SHADER_VERTEX:
6229 if (shader->key.vs.as_es)
6230 return "Vertex Shader as ES";
6231 else if (shader->key.vs.as_ls)
6232 return "Vertex Shader as LS";
6233 else
6234 return "Vertex Shader as VS";
6235 case PIPE_SHADER_TESS_CTRL:
6236 return "Tessellation Control Shader";
6237 case PIPE_SHADER_TESS_EVAL:
6238 if (shader->key.tes.as_es)
6239 return "Tessellation Evaluation Shader as ES";
6240 else
6241 return "Tessellation Evaluation Shader as VS";
6242 case PIPE_SHADER_GEOMETRY:
6243 if (shader->gs_copy_shader == NULL)
6244 return "GS Copy Shader as VS";
6245 else
6246 return "Geometry Shader";
6247 case PIPE_SHADER_FRAGMENT:
6248 return "Pixel Shader";
6249 case PIPE_SHADER_COMPUTE:
6250 return "Compute Shader";
6251 default:
6252 return "Unknown Shader";
6253 }
6254 }
6255
6256 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
6257 struct pipe_debug_callback *debug, unsigned processor,
6258 FILE *file)
6259 {
6260 if (file != stderr ||
6261 r600_can_dump_shader(&sscreen->b, processor))
6262 si_dump_shader_key(processor, &shader->key, file);
6263
6264 if (file != stderr && shader->binary.llvm_ir_string) {
6265 fprintf(file, "\n%s - main shader part - LLVM IR:\n\n",
6266 si_get_shader_name(shader, processor));
6267 fprintf(file, "%s\n", shader->binary.llvm_ir_string);
6268 }
6269
6270 if (file != stderr ||
6271 (r600_can_dump_shader(&sscreen->b, processor) &&
6272 !(sscreen->b.debug_flags & DBG_NO_ASM))) {
6273 fprintf(file, "\n%s:\n", si_get_shader_name(shader, processor));
6274
6275 if (shader->prolog)
6276 si_shader_dump_disassembly(&shader->prolog->binary,
6277 debug, "prolog", file);
6278
6279 si_shader_dump_disassembly(&shader->binary, debug, "main", file);
6280
6281 if (shader->epilog)
6282 si_shader_dump_disassembly(&shader->epilog->binary,
6283 debug, "epilog", file);
6284 fprintf(file, "\n");
6285 }
6286
6287 si_shader_dump_stats(sscreen, &shader->config,
6288 shader->selector ? shader->selector->info.num_inputs : 0,
6289 si_get_shader_binary_size(shader), debug, processor,
6290 file);
6291 }
6292
6293 int si_compile_llvm(struct si_screen *sscreen,
6294 struct radeon_shader_binary *binary,
6295 struct si_shader_config *conf,
6296 LLVMTargetMachineRef tm,
6297 LLVMModuleRef mod,
6298 struct pipe_debug_callback *debug,
6299 unsigned processor,
6300 const char *name)
6301 {
6302 int r = 0;
6303 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
6304
6305 if (r600_can_dump_shader(&sscreen->b, processor)) {
6306 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
6307
6308 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR))) {
6309 fprintf(stderr, "%s LLVM IR:\n\n", name);
6310 LLVMDumpModule(mod);
6311 fprintf(stderr, "\n");
6312 }
6313 }
6314
6315 if (sscreen->record_llvm_ir) {
6316 char *ir = LLVMPrintModuleToString(mod);
6317 binary->llvm_ir_string = strdup(ir);
6318 LLVMDisposeMessage(ir);
6319 }
6320
6321 if (!si_replace_shader(count, binary)) {
6322 r = radeon_llvm_compile(mod, binary, tm, debug);
6323 if (r)
6324 return r;
6325 }
6326
6327 si_shader_binary_read_config(binary, conf, 0);
6328
6329 /* Enable 64-bit and 16-bit denormals, because there is no performance
6330 * cost.
6331 *
6332 * If denormals are enabled, all floating-point output modifiers are
6333 * ignored.
6334 *
6335 * Don't enable denormals for 32-bit floats, because:
6336 * - Floating-point output modifiers would be ignored by the hw.
6337 * - Some opcodes don't support denormals, such as v_mad_f32. We would
6338 * have to stop using those.
6339 * - SI & CI would be very slow.
6340 */
6341 conf->float_mode |= V_00B028_FP_64_DENORMS;
6342
6343 FREE(binary->config);
6344 FREE(binary->global_symbol_offsets);
6345 binary->config = NULL;
6346 binary->global_symbol_offsets = NULL;
6347
6348 /* Some shaders can't have rodata because their binaries can be
6349 * concatenated.
6350 */
6351 if (binary->rodata_size &&
6352 (processor == PIPE_SHADER_VERTEX ||
6353 processor == PIPE_SHADER_TESS_CTRL ||
6354 processor == PIPE_SHADER_TESS_EVAL ||
6355 processor == PIPE_SHADER_FRAGMENT)) {
6356 fprintf(stderr, "radeonsi: The shader can't have rodata.");
6357 return -EINVAL;
6358 }
6359
6360 return r;
6361 }
6362
6363 static void si_llvm_build_ret(struct si_shader_context *ctx, LLVMValueRef ret)
6364 {
6365 if (LLVMGetTypeKind(LLVMTypeOf(ret)) == LLVMVoidTypeKind)
6366 LLVMBuildRetVoid(ctx->radeon_bld.gallivm.builder);
6367 else
6368 LLVMBuildRet(ctx->radeon_bld.gallivm.builder, ret);
6369 }
6370
6371 /* Generate code for the hardware VS shader stage to go with a geometry shader */
6372 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
6373 struct si_shader_context *ctx,
6374 struct si_shader *gs,
6375 struct pipe_debug_callback *debug)
6376 {
6377 struct gallivm_state *gallivm = &ctx->radeon_bld.gallivm;
6378 struct lp_build_tgsi_context *bld_base = &ctx->radeon_bld.soa.bld_base;
6379 struct lp_build_context *uint = &bld_base->uint_bld;
6380 struct si_shader_output_values *outputs;
6381 struct tgsi_shader_info *gsinfo = &gs->selector->info;
6382 LLVMValueRef args[9];
6383 int i, r;
6384
6385 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
6386
6387 si_init_shader_ctx(ctx, sscreen, ctx->shader, ctx->tm);
6388 ctx->type = PIPE_SHADER_VERTEX;
6389 ctx->is_gs_copy_shader = true;
6390
6391 create_meta_data(ctx);
6392 create_function(ctx);
6393 preload_ring_buffers(ctx);
6394
6395 args[0] = ctx->gsvs_ring[0];
6396 args[1] = lp_build_mul_imm(uint,
6397 LLVMGetParam(ctx->radeon_bld.main_fn,
6398 ctx->param_vertex_id),
6399 4);
6400 args[3] = uint->zero;
6401 args[4] = uint->one; /* OFFEN */
6402 args[5] = uint->zero; /* IDXEN */
6403 args[6] = uint->one; /* GLC */
6404 args[7] = uint->one; /* SLC */
6405 args[8] = uint->zero; /* TFE */
6406
6407 /* Fetch vertex data from GSVS ring */
6408 for (i = 0; i < gsinfo->num_outputs; ++i) {
6409 unsigned chan;
6410
6411 outputs[i].name = gsinfo->output_semantic_name[i];
6412 outputs[i].sid = gsinfo->output_semantic_index[i];
6413
6414 for (chan = 0; chan < 4; chan++) {
6415 args[2] = lp_build_const_int32(gallivm,
6416 (i * 4 + chan) *
6417 gs->selector->gs_max_out_vertices * 16 * 4);
6418
6419 outputs[i].values[chan] =
6420 LLVMBuildBitCast(gallivm->builder,
6421 lp_build_intrinsic(gallivm->builder,
6422 "llvm.SI.buffer.load.dword.i32.i32",
6423 ctx->i32, args, 9,
6424 LLVMReadOnlyAttribute),
6425 ctx->f32, "");
6426 }
6427 }
6428
6429 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
6430
6431 LLVMBuildRetVoid(gallivm->builder);
6432
6433 /* Dump LLVM IR before any optimization passes */
6434 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6435 r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6436 LLVMDumpModule(bld_base->base.gallivm->module);
6437
6438 radeon_llvm_finalize_module(
6439 &ctx->radeon_bld,
6440 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_GEOMETRY));
6441
6442 r = si_compile_llvm(sscreen, &ctx->shader->binary,
6443 &ctx->shader->config, ctx->tm,
6444 bld_base->base.gallivm->module,
6445 debug, PIPE_SHADER_GEOMETRY,
6446 "GS Copy Shader");
6447 if (!r) {
6448 if (r600_can_dump_shader(&sscreen->b, PIPE_SHADER_GEOMETRY))
6449 fprintf(stderr, "GS Copy Shader:\n");
6450 si_shader_dump(sscreen, ctx->shader, debug,
6451 PIPE_SHADER_GEOMETRY, stderr);
6452 r = si_shader_binary_upload(sscreen, ctx->shader);
6453 }
6454
6455 radeon_llvm_dispose(&ctx->radeon_bld);
6456
6457 FREE(outputs);
6458 return r;
6459 }
6460
6461 static void si_dump_shader_key(unsigned shader, union si_shader_key *key,
6462 FILE *f)
6463 {
6464 int i;
6465
6466 fprintf(f, "SHADER KEY\n");
6467
6468 switch (shader) {
6469 case PIPE_SHADER_VERTEX:
6470 fprintf(f, " instance_divisors = {");
6471 for (i = 0; i < ARRAY_SIZE(key->vs.prolog.instance_divisors); i++)
6472 fprintf(f, !i ? "%u" : ", %u",
6473 key->vs.prolog.instance_divisors[i]);
6474 fprintf(f, "}\n");
6475 fprintf(f, " as_es = %u\n", key->vs.as_es);
6476 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
6477 fprintf(f, " export_prim_id = %u\n", key->vs.epilog.export_prim_id);
6478 break;
6479
6480 case PIPE_SHADER_TESS_CTRL:
6481 fprintf(f, " prim_mode = %u\n", key->tcs.epilog.prim_mode);
6482 break;
6483
6484 case PIPE_SHADER_TESS_EVAL:
6485 fprintf(f, " as_es = %u\n", key->tes.as_es);
6486 fprintf(f, " export_prim_id = %u\n", key->tes.epilog.export_prim_id);
6487 break;
6488
6489 case PIPE_SHADER_GEOMETRY:
6490 case PIPE_SHADER_COMPUTE:
6491 break;
6492
6493 case PIPE_SHADER_FRAGMENT:
6494 fprintf(f, " prolog.color_two_side = %u\n", key->ps.prolog.color_two_side);
6495 fprintf(f, " prolog.flatshade_colors = %u\n", key->ps.prolog.flatshade_colors);
6496 fprintf(f, " prolog.poly_stipple = %u\n", key->ps.prolog.poly_stipple);
6497 fprintf(f, " prolog.force_persp_sample_interp = %u\n", key->ps.prolog.force_persp_sample_interp);
6498 fprintf(f, " prolog.force_linear_sample_interp = %u\n", key->ps.prolog.force_linear_sample_interp);
6499 fprintf(f, " prolog.force_persp_center_interp = %u\n", key->ps.prolog.force_persp_center_interp);
6500 fprintf(f, " prolog.force_linear_center_interp = %u\n", key->ps.prolog.force_linear_center_interp);
6501 fprintf(f, " prolog.bc_optimize_for_persp = %u\n", key->ps.prolog.bc_optimize_for_persp);
6502 fprintf(f, " prolog.bc_optimize_for_linear = %u\n", key->ps.prolog.bc_optimize_for_linear);
6503 fprintf(f, " epilog.spi_shader_col_format = 0x%x\n", key->ps.epilog.spi_shader_col_format);
6504 fprintf(f, " epilog.color_is_int8 = 0x%X\n", key->ps.epilog.color_is_int8);
6505 fprintf(f, " epilog.last_cbuf = %u\n", key->ps.epilog.last_cbuf);
6506 fprintf(f, " epilog.alpha_func = %u\n", key->ps.epilog.alpha_func);
6507 fprintf(f, " epilog.alpha_to_one = %u\n", key->ps.epilog.alpha_to_one);
6508 fprintf(f, " epilog.poly_line_smoothing = %u\n", key->ps.epilog.poly_line_smoothing);
6509 fprintf(f, " epilog.clamp_color = %u\n", key->ps.epilog.clamp_color);
6510 break;
6511
6512 default:
6513 assert(0);
6514 }
6515 }
6516
6517 static void si_init_shader_ctx(struct si_shader_context *ctx,
6518 struct si_screen *sscreen,
6519 struct si_shader *shader,
6520 LLVMTargetMachineRef tm)
6521 {
6522 struct lp_build_tgsi_context *bld_base;
6523 struct lp_build_tgsi_action tmpl = {};
6524
6525 memset(ctx, 0, sizeof(*ctx));
6526 radeon_llvm_context_init(
6527 &ctx->radeon_bld, "amdgcn--",
6528 (shader && shader->selector) ? &shader->selector->info : NULL,
6529 (shader && shader->selector) ? shader->selector->tokens : NULL);
6530 ctx->tm = tm;
6531 ctx->screen = sscreen;
6532 if (shader && shader->selector)
6533 ctx->type = shader->selector->info.processor;
6534 else
6535 ctx->type = -1;
6536 ctx->shader = shader;
6537
6538 ctx->voidt = LLVMVoidTypeInContext(ctx->radeon_bld.gallivm.context);
6539 ctx->i1 = LLVMInt1TypeInContext(ctx->radeon_bld.gallivm.context);
6540 ctx->i8 = LLVMInt8TypeInContext(ctx->radeon_bld.gallivm.context);
6541 ctx->i32 = LLVMInt32TypeInContext(ctx->radeon_bld.gallivm.context);
6542 ctx->i64 = LLVMInt64TypeInContext(ctx->radeon_bld.gallivm.context);
6543 ctx->i128 = LLVMIntTypeInContext(ctx->radeon_bld.gallivm.context, 128);
6544 ctx->f32 = LLVMFloatTypeInContext(ctx->radeon_bld.gallivm.context);
6545 ctx->v16i8 = LLVMVectorType(ctx->i8, 16);
6546 ctx->v2i32 = LLVMVectorType(ctx->i32, 2);
6547 ctx->v4i32 = LLVMVectorType(ctx->i32, 4);
6548 ctx->v4f32 = LLVMVectorType(ctx->f32, 4);
6549 ctx->v8i32 = LLVMVectorType(ctx->i32, 8);
6550
6551 bld_base = &ctx->radeon_bld.soa.bld_base;
6552 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
6553
6554 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
6555 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
6556 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
6557
6558 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
6559 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
6560 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
6561 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
6562 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
6563 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
6564 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
6565 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
6566 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
6567 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
6568 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
6569 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
6570 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
6571 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
6572
6573 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
6574 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
6575 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
6576 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
6577 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
6578 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
6579
6580 tmpl.fetch_args = atomic_fetch_args;
6581 tmpl.emit = atomic_emit;
6582 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
6583 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
6584 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
6585 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
6586 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
6587 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
6588 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
6589 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
6590 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
6591 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
6592 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
6593 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
6594 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
6595 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
6596 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
6597 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
6598 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
6599 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
6600 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
6601 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
6602
6603 bld_base->op_actions[TGSI_OPCODE_MEMBAR].emit = membar_emit;
6604
6605 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
6606 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
6607 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
6608 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
6609
6610 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
6611 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
6612 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
6613
6614 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
6615 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
6616 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
6617 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
6618 }
6619
6620 int si_compile_tgsi_shader(struct si_screen *sscreen,
6621 LLVMTargetMachineRef tm,
6622 struct si_shader *shader,
6623 bool is_monolithic,
6624 struct pipe_debug_callback *debug)
6625 {
6626 struct si_shader_selector *sel = shader->selector;
6627 struct si_shader_context ctx;
6628 struct lp_build_tgsi_context *bld_base;
6629 LLVMModuleRef mod;
6630 int r = 0;
6631
6632 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
6633 * conversion fails. */
6634 if (r600_can_dump_shader(&sscreen->b, sel->info.processor) &&
6635 !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
6636 tgsi_dump(sel->tokens, 0);
6637 si_dump_streamout(&sel->so);
6638 }
6639
6640 si_init_shader_ctx(&ctx, sscreen, shader, tm);
6641 ctx.is_monolithic = is_monolithic;
6642
6643 shader->info.uses_instanceid = sel->info.uses_instanceid;
6644
6645 bld_base = &ctx.radeon_bld.soa.bld_base;
6646 ctx.radeon_bld.load_system_value = declare_system_value;
6647
6648 switch (ctx.type) {
6649 case PIPE_SHADER_VERTEX:
6650 ctx.radeon_bld.load_input = declare_input_vs;
6651 if (shader->key.vs.as_ls)
6652 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
6653 else if (shader->key.vs.as_es)
6654 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6655 else
6656 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6657 break;
6658 case PIPE_SHADER_TESS_CTRL:
6659 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
6660 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
6661 bld_base->emit_store = store_output_tcs;
6662 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
6663 break;
6664 case PIPE_SHADER_TESS_EVAL:
6665 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
6666 if (shader->key.tes.as_es)
6667 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
6668 else
6669 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
6670 break;
6671 case PIPE_SHADER_GEOMETRY:
6672 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
6673 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
6674 break;
6675 case PIPE_SHADER_FRAGMENT:
6676 ctx.radeon_bld.load_input = declare_input_fs;
6677 if (is_monolithic)
6678 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
6679 else
6680 bld_base->emit_epilogue = si_llvm_return_fs_outputs;
6681 break;
6682 case PIPE_SHADER_COMPUTE:
6683 ctx.radeon_bld.declare_memory_region = declare_compute_memory;
6684 break;
6685 default:
6686 assert(!"Unsupported shader type");
6687 return -1;
6688 }
6689
6690 create_meta_data(&ctx);
6691 create_function(&ctx);
6692 preload_ring_buffers(&ctx);
6693
6694 if (ctx.is_monolithic && sel->type == PIPE_SHADER_FRAGMENT &&
6695 shader->key.ps.prolog.poly_stipple) {
6696 LLVMValueRef list = LLVMGetParam(ctx.radeon_bld.main_fn,
6697 SI_PARAM_RW_BUFFERS);
6698 si_llvm_emit_polygon_stipple(&ctx, list,
6699 SI_PARAM_POS_FIXED_PT);
6700 }
6701
6702 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6703 int i;
6704 for (i = 0; i < 4; i++) {
6705 ctx.gs_next_vertex[i] =
6706 lp_build_alloca(bld_base->base.gallivm,
6707 ctx.i32, "");
6708 }
6709 }
6710
6711 if (!lp_build_tgsi_llvm(bld_base, sel->tokens)) {
6712 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
6713 goto out;
6714 }
6715
6716 si_llvm_build_ret(&ctx, ctx.return_value);
6717 mod = bld_base->base.gallivm->module;
6718
6719 /* Dump LLVM IR before any optimization passes */
6720 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
6721 r600_can_dump_shader(&sscreen->b, ctx.type))
6722 LLVMDumpModule(mod);
6723
6724 radeon_llvm_finalize_module(
6725 &ctx.radeon_bld,
6726 r600_extra_shader_checks(&sscreen->b, ctx.type));
6727
6728 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
6729 mod, debug, ctx.type, "TGSI shader");
6730 if (r) {
6731 fprintf(stderr, "LLVM failed to compile shader\n");
6732 goto out;
6733 }
6734
6735 radeon_llvm_dispose(&ctx.radeon_bld);
6736
6737 /* Validate SGPR and VGPR usage for compute to detect compiler bugs.
6738 * LLVM 3.9svn has this bug.
6739 */
6740 if (sel->type == PIPE_SHADER_COMPUTE) {
6741 unsigned *props = sel->info.properties;
6742 unsigned wave_size = 64;
6743 unsigned max_vgprs = 256;
6744 unsigned max_sgprs = sscreen->b.chip_class >= VI ? 800 : 512;
6745 unsigned max_sgprs_per_wave = 128;
6746 unsigned max_block_threads;
6747
6748 if (props[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH])
6749 max_block_threads = props[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] *
6750 props[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] *
6751 props[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH];
6752 else
6753 max_block_threads = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
6754
6755 unsigned min_waves_per_cu = DIV_ROUND_UP(max_block_threads, wave_size);
6756 unsigned min_waves_per_simd = DIV_ROUND_UP(min_waves_per_cu, 4);
6757
6758 max_vgprs = max_vgprs / min_waves_per_simd;
6759 max_sgprs = MIN2(max_sgprs / min_waves_per_simd, max_sgprs_per_wave);
6760
6761 if (shader->config.num_sgprs > max_sgprs ||
6762 shader->config.num_vgprs > max_vgprs) {
6763 fprintf(stderr, "LLVM failed to compile a shader correctly: "
6764 "SGPR:VGPR usage is %u:%u, but the hw limit is %u:%u\n",
6765 shader->config.num_sgprs, shader->config.num_vgprs,
6766 max_sgprs, max_vgprs);
6767
6768 /* Just terminate the process, because dependent
6769 * shaders can hang due to bad input data, but use
6770 * the env var to allow shader-db to work.
6771 */
6772 if (!debug_get_bool_option("SI_PASS_BAD_SHADERS", false))
6773 abort();
6774 }
6775 }
6776
6777 /* Add the scratch offset to input SGPRs. */
6778 if (shader->config.scratch_bytes_per_wave)
6779 shader->info.num_input_sgprs += 1; /* scratch byte offset */
6780
6781 /* Calculate the number of fragment input VGPRs. */
6782 if (ctx.type == PIPE_SHADER_FRAGMENT) {
6783 shader->info.num_input_vgprs = 0;
6784 shader->info.face_vgpr_index = -1;
6785
6786 if (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6787 shader->info.num_input_vgprs += 2;
6788 if (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr))
6789 shader->info.num_input_vgprs += 2;
6790 if (G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_addr))
6791 shader->info.num_input_vgprs += 2;
6792 if (G_0286CC_PERSP_PULL_MODEL_ENA(shader->config.spi_ps_input_addr))
6793 shader->info.num_input_vgprs += 3;
6794 if (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_addr))
6795 shader->info.num_input_vgprs += 2;
6796 if (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr))
6797 shader->info.num_input_vgprs += 2;
6798 if (G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_addr))
6799 shader->info.num_input_vgprs += 2;
6800 if (G_0286CC_LINE_STIPPLE_TEX_ENA(shader->config.spi_ps_input_addr))
6801 shader->info.num_input_vgprs += 1;
6802 if (G_0286CC_POS_X_FLOAT_ENA(shader->config.spi_ps_input_addr))
6803 shader->info.num_input_vgprs += 1;
6804 if (G_0286CC_POS_Y_FLOAT_ENA(shader->config.spi_ps_input_addr))
6805 shader->info.num_input_vgprs += 1;
6806 if (G_0286CC_POS_Z_FLOAT_ENA(shader->config.spi_ps_input_addr))
6807 shader->info.num_input_vgprs += 1;
6808 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_addr))
6809 shader->info.num_input_vgprs += 1;
6810 if (G_0286CC_FRONT_FACE_ENA(shader->config.spi_ps_input_addr)) {
6811 shader->info.face_vgpr_index = shader->info.num_input_vgprs;
6812 shader->info.num_input_vgprs += 1;
6813 }
6814 if (G_0286CC_ANCILLARY_ENA(shader->config.spi_ps_input_addr))
6815 shader->info.num_input_vgprs += 1;
6816 if (G_0286CC_SAMPLE_COVERAGE_ENA(shader->config.spi_ps_input_addr))
6817 shader->info.num_input_vgprs += 1;
6818 if (G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr))
6819 shader->info.num_input_vgprs += 1;
6820 }
6821
6822 if (ctx.type == PIPE_SHADER_GEOMETRY) {
6823 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
6824 shader->gs_copy_shader->selector = shader->selector;
6825 ctx.shader = shader->gs_copy_shader;
6826 if ((r = si_generate_gs_copy_shader(sscreen, &ctx,
6827 shader, debug))) {
6828 free(shader->gs_copy_shader);
6829 shader->gs_copy_shader = NULL;
6830 goto out;
6831 }
6832 }
6833
6834 out:
6835 return r;
6836 }
6837
6838 /**
6839 * Create, compile and return a shader part (prolog or epilog).
6840 *
6841 * \param sscreen screen
6842 * \param list list of shader parts of the same category
6843 * \param key shader part key
6844 * \param tm LLVM target machine
6845 * \param debug debug callback
6846 * \param compile the callback responsible for compilation
6847 * \return non-NULL on success
6848 */
6849 static struct si_shader_part *
6850 si_get_shader_part(struct si_screen *sscreen,
6851 struct si_shader_part **list,
6852 union si_shader_part_key *key,
6853 LLVMTargetMachineRef tm,
6854 struct pipe_debug_callback *debug,
6855 bool (*compile)(struct si_screen *,
6856 LLVMTargetMachineRef,
6857 struct pipe_debug_callback *,
6858 struct si_shader_part *))
6859 {
6860 struct si_shader_part *result;
6861
6862 pipe_mutex_lock(sscreen->shader_parts_mutex);
6863
6864 /* Find existing. */
6865 for (result = *list; result; result = result->next) {
6866 if (memcmp(&result->key, key, sizeof(*key)) == 0) {
6867 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6868 return result;
6869 }
6870 }
6871
6872 /* Compile a new one. */
6873 result = CALLOC_STRUCT(si_shader_part);
6874 result->key = *key;
6875 if (!compile(sscreen, tm, debug, result)) {
6876 FREE(result);
6877 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6878 return NULL;
6879 }
6880
6881 result->next = *list;
6882 *list = result;
6883 pipe_mutex_unlock(sscreen->shader_parts_mutex);
6884 return result;
6885 }
6886
6887 /**
6888 * Create a vertex shader prolog.
6889 *
6890 * The inputs are the same as VS (a lot of SGPRs and 4 VGPR system values).
6891 * All inputs are returned unmodified. The vertex load indices are
6892 * stored after them, which will used by the API VS for fetching inputs.
6893 *
6894 * For example, the expected outputs for instance_divisors[] = {0, 1, 2} are:
6895 * input_v0,
6896 * input_v1,
6897 * input_v2,
6898 * input_v3,
6899 * (VertexID + BaseVertex),
6900 * (InstanceID + StartInstance),
6901 * (InstanceID / 2 + StartInstance)
6902 */
6903 static bool si_compile_vs_prolog(struct si_screen *sscreen,
6904 LLVMTargetMachineRef tm,
6905 struct pipe_debug_callback *debug,
6906 struct si_shader_part *out)
6907 {
6908 union si_shader_part_key *key = &out->key;
6909 struct si_shader shader = {};
6910 struct si_shader_context ctx;
6911 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
6912 LLVMTypeRef *params, *returns;
6913 LLVMValueRef ret, func;
6914 int last_sgpr, num_params, num_returns, i;
6915 bool status = true;
6916
6917 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
6918 ctx.type = PIPE_SHADER_VERTEX;
6919 ctx.param_vertex_id = key->vs_prolog.num_input_sgprs;
6920 ctx.param_instance_id = key->vs_prolog.num_input_sgprs + 3;
6921
6922 /* 4 preloaded VGPRs + vertex load indices as prolog outputs */
6923 params = alloca((key->vs_prolog.num_input_sgprs + 4) *
6924 sizeof(LLVMTypeRef));
6925 returns = alloca((key->vs_prolog.num_input_sgprs + 4 +
6926 key->vs_prolog.last_input + 1) *
6927 sizeof(LLVMTypeRef));
6928 num_params = 0;
6929 num_returns = 0;
6930
6931 /* Declare input and output SGPRs. */
6932 num_params = 0;
6933 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6934 params[num_params++] = ctx.i32;
6935 returns[num_returns++] = ctx.i32;
6936 }
6937 last_sgpr = num_params - 1;
6938
6939 /* 4 preloaded VGPRs (outputs must be floats) */
6940 for (i = 0; i < 4; i++) {
6941 params[num_params++] = ctx.i32;
6942 returns[num_returns++] = ctx.f32;
6943 }
6944
6945 /* Vertex load indices. */
6946 for (i = 0; i <= key->vs_prolog.last_input; i++)
6947 returns[num_returns++] = ctx.f32;
6948
6949 /* Create the function. */
6950 si_create_function(&ctx, returns, num_returns, params,
6951 num_params, last_sgpr);
6952 func = ctx.radeon_bld.main_fn;
6953
6954 /* Copy inputs to outputs. This should be no-op, as the registers match,
6955 * but it will prevent the compiler from overwriting them unintentionally.
6956 */
6957 ret = ctx.return_value;
6958 for (i = 0; i < key->vs_prolog.num_input_sgprs; i++) {
6959 LLVMValueRef p = LLVMGetParam(func, i);
6960 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6961 }
6962 for (i = num_params - 4; i < num_params; i++) {
6963 LLVMValueRef p = LLVMGetParam(func, i);
6964 p = LLVMBuildBitCast(gallivm->builder, p, ctx.f32, "");
6965 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
6966 }
6967
6968 /* Compute vertex load indices from instance divisors. */
6969 for (i = 0; i <= key->vs_prolog.last_input; i++) {
6970 unsigned divisor = key->vs_prolog.states.instance_divisors[i];
6971 LLVMValueRef index;
6972
6973 if (divisor) {
6974 /* InstanceID / Divisor + StartInstance */
6975 index = get_instance_index_for_fetch(&ctx.radeon_bld,
6976 SI_SGPR_START_INSTANCE,
6977 divisor);
6978 } else {
6979 /* VertexID + BaseVertex */
6980 index = LLVMBuildAdd(gallivm->builder,
6981 LLVMGetParam(func, ctx.param_vertex_id),
6982 LLVMGetParam(func, SI_SGPR_BASE_VERTEX), "");
6983 }
6984
6985 index = LLVMBuildBitCast(gallivm->builder, index, ctx.f32, "");
6986 ret = LLVMBuildInsertValue(gallivm->builder, ret, index,
6987 num_params++, "");
6988 }
6989
6990 /* Compile. */
6991 si_llvm_build_ret(&ctx, ret);
6992 radeon_llvm_finalize_module(
6993 &ctx.radeon_bld,
6994 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_VERTEX));
6995
6996 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
6997 gallivm->module, debug, ctx.type,
6998 "Vertex Shader Prolog"))
6999 status = false;
7000
7001 radeon_llvm_dispose(&ctx.radeon_bld);
7002 return status;
7003 }
7004
7005 /**
7006 * Compile the vertex shader epilog. This is also used by the tessellation
7007 * evaluation shader compiled as VS.
7008 *
7009 * The input is PrimitiveID.
7010 *
7011 * If PrimitiveID is required by the pixel shader, export it.
7012 * Otherwise, do nothing.
7013 */
7014 static bool si_compile_vs_epilog(struct si_screen *sscreen,
7015 LLVMTargetMachineRef tm,
7016 struct pipe_debug_callback *debug,
7017 struct si_shader_part *out)
7018 {
7019 union si_shader_part_key *key = &out->key;
7020 struct si_shader_context ctx;
7021 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7022 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7023 LLVMTypeRef params[5];
7024 int num_params, i;
7025 bool status = true;
7026
7027 si_init_shader_ctx(&ctx, sscreen, NULL, tm);
7028 ctx.type = PIPE_SHADER_VERTEX;
7029
7030 /* Declare input VGPRs. */
7031 num_params = key->vs_epilog.states.export_prim_id ?
7032 (VS_EPILOG_PRIMID_LOC + 1) : 0;
7033 assert(num_params <= ARRAY_SIZE(params));
7034
7035 for (i = 0; i < num_params; i++)
7036 params[i] = ctx.f32;
7037
7038 /* Create the function. */
7039 si_create_function(&ctx, NULL, 0, params, num_params, -1);
7040
7041 /* Emit exports. */
7042 if (key->vs_epilog.states.export_prim_id) {
7043 struct lp_build_context *base = &bld_base->base;
7044 struct lp_build_context *uint = &bld_base->uint_bld;
7045 LLVMValueRef args[9];
7046
7047 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
7048 args[1] = uint->zero; /* whether the EXEC mask is valid */
7049 args[2] = uint->zero; /* DONE bit */
7050 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_PARAM +
7051 key->vs_epilog.prim_id_param_offset);
7052 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
7053 args[5] = LLVMGetParam(ctx.radeon_bld.main_fn,
7054 VS_EPILOG_PRIMID_LOC); /* X */
7055 args[6] = uint->undef; /* Y */
7056 args[7] = uint->undef; /* Z */
7057 args[8] = uint->undef; /* W */
7058
7059 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
7060 LLVMVoidTypeInContext(base->gallivm->context),
7061 args, 9, 0);
7062 }
7063
7064 /* Compile. */
7065 LLVMBuildRetVoid(gallivm->builder);
7066 radeon_llvm_finalize_module(
7067 &ctx.radeon_bld,
7068 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_VERTEX));
7069
7070 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7071 gallivm->module, debug, ctx.type,
7072 "Vertex Shader Epilog"))
7073 status = false;
7074
7075 radeon_llvm_dispose(&ctx.radeon_bld);
7076 return status;
7077 }
7078
7079 /**
7080 * Create & compile a vertex shader epilog. This a helper used by VS and TES.
7081 */
7082 static bool si_get_vs_epilog(struct si_screen *sscreen,
7083 LLVMTargetMachineRef tm,
7084 struct si_shader *shader,
7085 struct pipe_debug_callback *debug,
7086 struct si_vs_epilog_bits *states)
7087 {
7088 union si_shader_part_key epilog_key;
7089
7090 memset(&epilog_key, 0, sizeof(epilog_key));
7091 epilog_key.vs_epilog.states = *states;
7092
7093 /* Set up the PrimitiveID output. */
7094 if (shader->key.vs.epilog.export_prim_id) {
7095 unsigned index = shader->selector->info.num_outputs;
7096 unsigned offset = shader->info.nr_param_exports++;
7097
7098 epilog_key.vs_epilog.prim_id_param_offset = offset;
7099 assert(index < ARRAY_SIZE(shader->info.vs_output_param_offset));
7100 shader->info.vs_output_param_offset[index] = offset;
7101 }
7102
7103 shader->epilog = si_get_shader_part(sscreen, &sscreen->vs_epilogs,
7104 &epilog_key, tm, debug,
7105 si_compile_vs_epilog);
7106 return shader->epilog != NULL;
7107 }
7108
7109 /**
7110 * Select and compile (or reuse) vertex shader parts (prolog & epilog).
7111 */
7112 static bool si_shader_select_vs_parts(struct si_screen *sscreen,
7113 LLVMTargetMachineRef tm,
7114 struct si_shader *shader,
7115 struct pipe_debug_callback *debug)
7116 {
7117 struct tgsi_shader_info *info = &shader->selector->info;
7118 union si_shader_part_key prolog_key;
7119 unsigned i;
7120
7121 /* Get the prolog. */
7122 memset(&prolog_key, 0, sizeof(prolog_key));
7123 prolog_key.vs_prolog.states = shader->key.vs.prolog;
7124 prolog_key.vs_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7125 prolog_key.vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
7126
7127 /* The prolog is a no-op if there are no inputs. */
7128 if (info->num_inputs) {
7129 shader->prolog =
7130 si_get_shader_part(sscreen, &sscreen->vs_prologs,
7131 &prolog_key, tm, debug,
7132 si_compile_vs_prolog);
7133 if (!shader->prolog)
7134 return false;
7135 }
7136
7137 /* Get the epilog. */
7138 if (!shader->key.vs.as_es && !shader->key.vs.as_ls &&
7139 !si_get_vs_epilog(sscreen, tm, shader, debug,
7140 &shader->key.vs.epilog))
7141 return false;
7142
7143 /* Set the instanceID flag. */
7144 for (i = 0; i < info->num_inputs; i++)
7145 if (prolog_key.vs_prolog.states.instance_divisors[i])
7146 shader->info.uses_instanceid = true;
7147
7148 return true;
7149 }
7150
7151 /**
7152 * Select and compile (or reuse) TES parts (epilog).
7153 */
7154 static bool si_shader_select_tes_parts(struct si_screen *sscreen,
7155 LLVMTargetMachineRef tm,
7156 struct si_shader *shader,
7157 struct pipe_debug_callback *debug)
7158 {
7159 if (shader->key.tes.as_es)
7160 return true;
7161
7162 /* TES compiled as VS. */
7163 return si_get_vs_epilog(sscreen, tm, shader, debug,
7164 &shader->key.tes.epilog);
7165 }
7166
7167 /**
7168 * Compile the TCS epilog. This writes tesselation factors to memory based on
7169 * the output primitive type of the tesselator (determined by TES).
7170 */
7171 static bool si_compile_tcs_epilog(struct si_screen *sscreen,
7172 LLVMTargetMachineRef tm,
7173 struct pipe_debug_callback *debug,
7174 struct si_shader_part *out)
7175 {
7176 union si_shader_part_key *key = &out->key;
7177 struct si_shader shader = {};
7178 struct si_shader_context ctx;
7179 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7180 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7181 LLVMTypeRef params[16];
7182 LLVMValueRef func;
7183 int last_sgpr, num_params;
7184 bool status = true;
7185
7186 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7187 ctx.type = PIPE_SHADER_TESS_CTRL;
7188 shader.key.tcs.epilog = key->tcs_epilog.states;
7189
7190 /* Declare inputs. Only RW_BUFFERS and TESS_FACTOR_OFFSET are used. */
7191 params[SI_PARAM_RW_BUFFERS] = const_array(ctx.v16i8, SI_NUM_RW_BUFFERS);
7192 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
7193 params[SI_PARAM_SAMPLERS] = ctx.i64;
7194 params[SI_PARAM_IMAGES] = ctx.i64;
7195 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
7196 params[SI_PARAM_TCS_OFFCHIP_LAYOUT] = ctx.i32;
7197 params[SI_PARAM_TCS_OUT_OFFSETS] = ctx.i32;
7198 params[SI_PARAM_TCS_OUT_LAYOUT] = ctx.i32;
7199 params[SI_PARAM_TCS_IN_LAYOUT] = ctx.i32;
7200 params[ctx.param_oc_lds = SI_PARAM_TCS_OC_LDS] = ctx.i32;
7201 params[SI_PARAM_TESS_FACTOR_OFFSET] = ctx.i32;
7202 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
7203 num_params = last_sgpr + 1;
7204
7205 params[num_params++] = ctx.i32; /* patch index within the wave (REL_PATCH_ID) */
7206 params[num_params++] = ctx.i32; /* invocation ID within the patch */
7207 params[num_params++] = ctx.i32; /* LDS offset where tess factors should be loaded from */
7208
7209 /* Create the function. */
7210 si_create_function(&ctx, NULL, 0, params, num_params, last_sgpr);
7211 declare_tess_lds(&ctx);
7212 func = ctx.radeon_bld.main_fn;
7213
7214 si_write_tess_factors(bld_base,
7215 LLVMGetParam(func, last_sgpr + 1),
7216 LLVMGetParam(func, last_sgpr + 2),
7217 LLVMGetParam(func, last_sgpr + 3));
7218
7219 /* Compile. */
7220 LLVMBuildRetVoid(gallivm->builder);
7221 radeon_llvm_finalize_module(
7222 &ctx.radeon_bld,
7223 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_TESS_CTRL));
7224
7225 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7226 gallivm->module, debug, ctx.type,
7227 "Tessellation Control Shader Epilog"))
7228 status = false;
7229
7230 radeon_llvm_dispose(&ctx.radeon_bld);
7231 return status;
7232 }
7233
7234 /**
7235 * Select and compile (or reuse) TCS parts (epilog).
7236 */
7237 static bool si_shader_select_tcs_parts(struct si_screen *sscreen,
7238 LLVMTargetMachineRef tm,
7239 struct si_shader *shader,
7240 struct pipe_debug_callback *debug)
7241 {
7242 union si_shader_part_key epilog_key;
7243
7244 /* Get the epilog. */
7245 memset(&epilog_key, 0, sizeof(epilog_key));
7246 epilog_key.tcs_epilog.states = shader->key.tcs.epilog;
7247
7248 shader->epilog = si_get_shader_part(sscreen, &sscreen->tcs_epilogs,
7249 &epilog_key, tm, debug,
7250 si_compile_tcs_epilog);
7251 return shader->epilog != NULL;
7252 }
7253
7254 /**
7255 * Compile the pixel shader prolog. This handles:
7256 * - two-side color selection and interpolation
7257 * - overriding interpolation parameters for the API PS
7258 * - polygon stippling
7259 *
7260 * All preloaded SGPRs and VGPRs are passed through unmodified unless they are
7261 * overriden by other states. (e.g. per-sample interpolation)
7262 * Interpolated colors are stored after the preloaded VGPRs.
7263 */
7264 static bool si_compile_ps_prolog(struct si_screen *sscreen,
7265 LLVMTargetMachineRef tm,
7266 struct pipe_debug_callback *debug,
7267 struct si_shader_part *out)
7268 {
7269 union si_shader_part_key *key = &out->key;
7270 struct si_shader shader = {};
7271 struct si_shader_context ctx;
7272 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7273 LLVMTypeRef *params;
7274 LLVMValueRef ret, func;
7275 int last_sgpr, num_params, num_returns, i, num_color_channels;
7276 bool status = true;
7277
7278 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7279 ctx.type = PIPE_SHADER_FRAGMENT;
7280 shader.key.ps.prolog = key->ps_prolog.states;
7281
7282 /* Number of inputs + 8 color elements. */
7283 params = alloca((key->ps_prolog.num_input_sgprs +
7284 key->ps_prolog.num_input_vgprs + 8) *
7285 sizeof(LLVMTypeRef));
7286
7287 /* Declare inputs. */
7288 num_params = 0;
7289 for (i = 0; i < key->ps_prolog.num_input_sgprs; i++)
7290 params[num_params++] = ctx.i32;
7291 last_sgpr = num_params - 1;
7292
7293 for (i = 0; i < key->ps_prolog.num_input_vgprs; i++)
7294 params[num_params++] = ctx.f32;
7295
7296 /* Declare outputs (same as inputs + add colors if needed) */
7297 num_returns = num_params;
7298 num_color_channels = util_bitcount(key->ps_prolog.colors_read);
7299 for (i = 0; i < num_color_channels; i++)
7300 params[num_returns++] = ctx.f32;
7301
7302 /* Create the function. */
7303 si_create_function(&ctx, params, num_returns, params,
7304 num_params, last_sgpr);
7305 func = ctx.radeon_bld.main_fn;
7306
7307 /* Copy inputs to outputs. This should be no-op, as the registers match,
7308 * but it will prevent the compiler from overwriting them unintentionally.
7309 */
7310 ret = ctx.return_value;
7311 for (i = 0; i < num_params; i++) {
7312 LLVMValueRef p = LLVMGetParam(func, i);
7313 ret = LLVMBuildInsertValue(gallivm->builder, ret, p, i, "");
7314 }
7315
7316 /* Polygon stippling. */
7317 if (key->ps_prolog.states.poly_stipple) {
7318 /* POS_FIXED_PT is always last. */
7319 unsigned pos = key->ps_prolog.num_input_sgprs +
7320 key->ps_prolog.num_input_vgprs - 1;
7321 LLVMValueRef ptr[2], list;
7322
7323 /* Get the pointer to rw buffers. */
7324 ptr[0] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS);
7325 ptr[1] = LLVMGetParam(func, SI_SGPR_RW_BUFFERS_HI);
7326 list = lp_build_gather_values(gallivm, ptr, 2);
7327 list = LLVMBuildBitCast(gallivm->builder, list, ctx.i64, "");
7328 list = LLVMBuildIntToPtr(gallivm->builder, list,
7329 const_array(ctx.v16i8, SI_NUM_RW_BUFFERS), "");
7330
7331 si_llvm_emit_polygon_stipple(&ctx, list, pos);
7332 }
7333
7334 if (key->ps_prolog.states.bc_optimize_for_persp ||
7335 key->ps_prolog.states.bc_optimize_for_linear) {
7336 unsigned i, base = key->ps_prolog.num_input_sgprs;
7337 LLVMValueRef center[2], centroid[2], tmp, bc_optimize;
7338
7339 /* The shader should do: if (PRIM_MASK[31]) CENTROID = CENTER;
7340 * The hw doesn't compute CENTROID if the whole wave only
7341 * contains fully-covered quads.
7342 *
7343 * PRIM_MASK is after user SGPRs.
7344 */
7345 bc_optimize = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7346 bc_optimize = LLVMBuildLShr(gallivm->builder, bc_optimize,
7347 LLVMConstInt(ctx.i32, 31, 0), "");
7348 bc_optimize = LLVMBuildTrunc(gallivm->builder, bc_optimize,
7349 ctx.i1, "");
7350
7351 if (key->ps_prolog.states.bc_optimize_for_persp) {
7352 /* Read PERSP_CENTER. */
7353 for (i = 0; i < 2; i++)
7354 center[i] = LLVMGetParam(func, base + 2 + i);
7355 /* Read PERSP_CENTROID. */
7356 for (i = 0; i < 2; i++)
7357 centroid[i] = LLVMGetParam(func, base + 4 + i);
7358 /* Select PERSP_CENTROID. */
7359 for (i = 0; i < 2; i++) {
7360 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7361 center[i], centroid[i], "");
7362 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7363 tmp, base + 4 + i, "");
7364 }
7365 }
7366 if (key->ps_prolog.states.bc_optimize_for_linear) {
7367 /* Read LINEAR_CENTER. */
7368 for (i = 0; i < 2; i++)
7369 center[i] = LLVMGetParam(func, base + 8 + i);
7370 /* Read LINEAR_CENTROID. */
7371 for (i = 0; i < 2; i++)
7372 centroid[i] = LLVMGetParam(func, base + 10 + i);
7373 /* Select LINEAR_CENTROID. */
7374 for (i = 0; i < 2; i++) {
7375 tmp = LLVMBuildSelect(gallivm->builder, bc_optimize,
7376 center[i], centroid[i], "");
7377 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7378 tmp, base + 10 + i, "");
7379 }
7380 }
7381 }
7382
7383 /* Force per-sample interpolation. */
7384 if (key->ps_prolog.states.force_persp_sample_interp) {
7385 unsigned i, base = key->ps_prolog.num_input_sgprs;
7386 LLVMValueRef persp_sample[2];
7387
7388 /* Read PERSP_SAMPLE. */
7389 for (i = 0; i < 2; i++)
7390 persp_sample[i] = LLVMGetParam(func, base + i);
7391 /* Overwrite PERSP_CENTER. */
7392 for (i = 0; i < 2; i++)
7393 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7394 persp_sample[i], base + 2 + i, "");
7395 /* Overwrite PERSP_CENTROID. */
7396 for (i = 0; i < 2; i++)
7397 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7398 persp_sample[i], base + 4 + i, "");
7399 }
7400 if (key->ps_prolog.states.force_linear_sample_interp) {
7401 unsigned i, base = key->ps_prolog.num_input_sgprs;
7402 LLVMValueRef linear_sample[2];
7403
7404 /* Read LINEAR_SAMPLE. */
7405 for (i = 0; i < 2; i++)
7406 linear_sample[i] = LLVMGetParam(func, base + 6 + i);
7407 /* Overwrite LINEAR_CENTER. */
7408 for (i = 0; i < 2; i++)
7409 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7410 linear_sample[i], base + 8 + i, "");
7411 /* Overwrite LINEAR_CENTROID. */
7412 for (i = 0; i < 2; i++)
7413 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7414 linear_sample[i], base + 10 + i, "");
7415 }
7416
7417 /* Force center interpolation. */
7418 if (key->ps_prolog.states.force_persp_center_interp) {
7419 unsigned i, base = key->ps_prolog.num_input_sgprs;
7420 LLVMValueRef persp_center[2];
7421
7422 /* Read PERSP_CENTER. */
7423 for (i = 0; i < 2; i++)
7424 persp_center[i] = LLVMGetParam(func, base + 2 + i);
7425 /* Overwrite PERSP_SAMPLE. */
7426 for (i = 0; i < 2; i++)
7427 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7428 persp_center[i], base + i, "");
7429 /* Overwrite PERSP_CENTROID. */
7430 for (i = 0; i < 2; i++)
7431 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7432 persp_center[i], base + 4 + i, "");
7433 }
7434 if (key->ps_prolog.states.force_linear_center_interp) {
7435 unsigned i, base = key->ps_prolog.num_input_sgprs;
7436 LLVMValueRef linear_center[2];
7437
7438 /* Read LINEAR_CENTER. */
7439 for (i = 0; i < 2; i++)
7440 linear_center[i] = LLVMGetParam(func, base + 8 + i);
7441 /* Overwrite LINEAR_SAMPLE. */
7442 for (i = 0; i < 2; i++)
7443 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7444 linear_center[i], base + 6 + i, "");
7445 /* Overwrite LINEAR_CENTROID. */
7446 for (i = 0; i < 2; i++)
7447 ret = LLVMBuildInsertValue(gallivm->builder, ret,
7448 linear_center[i], base + 10 + i, "");
7449 }
7450
7451 /* Interpolate colors. */
7452 for (i = 0; i < 2; i++) {
7453 unsigned writemask = (key->ps_prolog.colors_read >> (i * 4)) & 0xf;
7454 unsigned face_vgpr = key->ps_prolog.num_input_sgprs +
7455 key->ps_prolog.face_vgpr_index;
7456 LLVMValueRef interp[2], color[4];
7457 LLVMValueRef interp_ij = NULL, prim_mask = NULL, face = NULL;
7458
7459 if (!writemask)
7460 continue;
7461
7462 /* If the interpolation qualifier is not CONSTANT (-1). */
7463 if (key->ps_prolog.color_interp_vgpr_index[i] != -1) {
7464 unsigned interp_vgpr = key->ps_prolog.num_input_sgprs +
7465 key->ps_prolog.color_interp_vgpr_index[i];
7466
7467 /* Get the (i,j) updated by bc_optimize handling. */
7468 interp[0] = LLVMBuildExtractValue(gallivm->builder, ret,
7469 interp_vgpr, "");
7470 interp[1] = LLVMBuildExtractValue(gallivm->builder, ret,
7471 interp_vgpr + 1, "");
7472 interp_ij = lp_build_gather_values(gallivm, interp, 2);
7473 interp_ij = LLVMBuildBitCast(gallivm->builder, interp_ij,
7474 ctx.v2i32, "");
7475 }
7476
7477 /* Use the absolute location of the input. */
7478 prim_mask = LLVMGetParam(func, SI_PS_NUM_USER_SGPR);
7479
7480 if (key->ps_prolog.states.color_two_side) {
7481 face = LLVMGetParam(func, face_vgpr);
7482 face = LLVMBuildBitCast(gallivm->builder, face, ctx.i32, "");
7483 }
7484
7485 interp_fs_input(&ctx,
7486 key->ps_prolog.color_attr_index[i],
7487 TGSI_SEMANTIC_COLOR, i,
7488 key->ps_prolog.num_interp_inputs,
7489 key->ps_prolog.colors_read, interp_ij,
7490 prim_mask, face, color);
7491
7492 while (writemask) {
7493 unsigned chan = u_bit_scan(&writemask);
7494 ret = LLVMBuildInsertValue(gallivm->builder, ret, color[chan],
7495 num_params++, "");
7496 }
7497 }
7498
7499 /* Tell LLVM to insert WQM instruction sequence when needed. */
7500 if (key->ps_prolog.wqm) {
7501 LLVMAddTargetDependentFunctionAttr(func,
7502 "amdgpu-ps-wqm-outputs", "");
7503 }
7504
7505 /* Compile. */
7506 si_llvm_build_ret(&ctx, ret);
7507 radeon_llvm_finalize_module(
7508 &ctx.radeon_bld,
7509 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
7510
7511 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7512 gallivm->module, debug, ctx.type,
7513 "Fragment Shader Prolog"))
7514 status = false;
7515
7516 radeon_llvm_dispose(&ctx.radeon_bld);
7517 return status;
7518 }
7519
7520 /**
7521 * Compile the pixel shader epilog. This handles everything that must be
7522 * emulated for pixel shader exports. (alpha-test, format conversions, etc)
7523 */
7524 static bool si_compile_ps_epilog(struct si_screen *sscreen,
7525 LLVMTargetMachineRef tm,
7526 struct pipe_debug_callback *debug,
7527 struct si_shader_part *out)
7528 {
7529 union si_shader_part_key *key = &out->key;
7530 struct si_shader shader = {};
7531 struct si_shader_context ctx;
7532 struct gallivm_state *gallivm = &ctx.radeon_bld.gallivm;
7533 struct lp_build_tgsi_context *bld_base = &ctx.radeon_bld.soa.bld_base;
7534 LLVMTypeRef params[16+8*4+3];
7535 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
7536 int last_sgpr, num_params, i;
7537 bool status = true;
7538 struct si_ps_exports exp = {};
7539
7540 si_init_shader_ctx(&ctx, sscreen, &shader, tm);
7541 ctx.type = PIPE_SHADER_FRAGMENT;
7542 shader.key.ps.epilog = key->ps_epilog.states;
7543
7544 /* Declare input SGPRs. */
7545 params[SI_PARAM_RW_BUFFERS] = ctx.i64;
7546 params[SI_PARAM_CONST_BUFFERS] = ctx.i64;
7547 params[SI_PARAM_SAMPLERS] = ctx.i64;
7548 params[SI_PARAM_IMAGES] = ctx.i64;
7549 params[SI_PARAM_SHADER_BUFFERS] = ctx.i64;
7550 params[SI_PARAM_ALPHA_REF] = ctx.f32;
7551 last_sgpr = SI_PARAM_ALPHA_REF;
7552
7553 /* Declare input VGPRs. */
7554 num_params = (last_sgpr + 1) +
7555 util_bitcount(key->ps_epilog.colors_written) * 4 +
7556 key->ps_epilog.writes_z +
7557 key->ps_epilog.writes_stencil +
7558 key->ps_epilog.writes_samplemask;
7559
7560 num_params = MAX2(num_params,
7561 last_sgpr + 1 + PS_EPILOG_SAMPLEMASK_MIN_LOC + 1);
7562
7563 assert(num_params <= ARRAY_SIZE(params));
7564
7565 for (i = last_sgpr + 1; i < num_params; i++)
7566 params[i] = ctx.f32;
7567
7568 /* Create the function. */
7569 si_create_function(&ctx, NULL, 0, params, num_params, last_sgpr);
7570 /* Disable elimination of unused inputs. */
7571 radeon_llvm_add_attribute(ctx.radeon_bld.main_fn,
7572 "InitialPSInputAddr", 0xffffff);
7573
7574 /* Process colors. */
7575 unsigned vgpr = last_sgpr + 1;
7576 unsigned colors_written = key->ps_epilog.colors_written;
7577 int last_color_export = -1;
7578
7579 /* Find the last color export. */
7580 if (!key->ps_epilog.writes_z &&
7581 !key->ps_epilog.writes_stencil &&
7582 !key->ps_epilog.writes_samplemask) {
7583 unsigned spi_format = key->ps_epilog.states.spi_shader_col_format;
7584
7585 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
7586 if (colors_written == 0x1 && key->ps_epilog.states.last_cbuf > 0) {
7587 /* Just set this if any of the colorbuffers are enabled. */
7588 if (spi_format &
7589 ((1llu << (4 * (key->ps_epilog.states.last_cbuf + 1))) - 1))
7590 last_color_export = 0;
7591 } else {
7592 for (i = 0; i < 8; i++)
7593 if (colors_written & (1 << i) &&
7594 (spi_format >> (i * 4)) & 0xf)
7595 last_color_export = i;
7596 }
7597 }
7598
7599 while (colors_written) {
7600 LLVMValueRef color[4];
7601 int mrt = u_bit_scan(&colors_written);
7602
7603 for (i = 0; i < 4; i++)
7604 color[i] = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7605
7606 si_export_mrt_color(bld_base, color, mrt,
7607 num_params - 1,
7608 mrt == last_color_export, &exp);
7609 }
7610
7611 /* Process depth, stencil, samplemask. */
7612 if (key->ps_epilog.writes_z)
7613 depth = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7614 if (key->ps_epilog.writes_stencil)
7615 stencil = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7616 if (key->ps_epilog.writes_samplemask)
7617 samplemask = LLVMGetParam(ctx.radeon_bld.main_fn, vgpr++);
7618
7619 if (depth || stencil || samplemask)
7620 si_export_mrt_z(bld_base, depth, stencil, samplemask, &exp);
7621 else if (last_color_export == -1)
7622 si_export_null(bld_base);
7623
7624 if (exp.num)
7625 si_emit_ps_exports(&ctx, &exp);
7626
7627 /* Compile. */
7628 LLVMBuildRetVoid(gallivm->builder);
7629 radeon_llvm_finalize_module(
7630 &ctx.radeon_bld,
7631 r600_extra_shader_checks(&sscreen->b, PIPE_SHADER_FRAGMENT));
7632
7633 if (si_compile_llvm(sscreen, &out->binary, &out->config, tm,
7634 gallivm->module, debug, ctx.type,
7635 "Fragment Shader Epilog"))
7636 status = false;
7637
7638 radeon_llvm_dispose(&ctx.radeon_bld);
7639 return status;
7640 }
7641
7642 /**
7643 * Select and compile (or reuse) pixel shader parts (prolog & epilog).
7644 */
7645 static bool si_shader_select_ps_parts(struct si_screen *sscreen,
7646 LLVMTargetMachineRef tm,
7647 struct si_shader *shader,
7648 struct pipe_debug_callback *debug)
7649 {
7650 struct tgsi_shader_info *info = &shader->selector->info;
7651 union si_shader_part_key prolog_key;
7652 union si_shader_part_key epilog_key;
7653 unsigned i;
7654
7655 /* Get the prolog. */
7656 memset(&prolog_key, 0, sizeof(prolog_key));
7657 prolog_key.ps_prolog.states = shader->key.ps.prolog;
7658 prolog_key.ps_prolog.colors_read = info->colors_read;
7659 prolog_key.ps_prolog.num_input_sgprs = shader->info.num_input_sgprs;
7660 prolog_key.ps_prolog.num_input_vgprs = shader->info.num_input_vgprs;
7661 prolog_key.ps_prolog.wqm = info->uses_derivatives &&
7662 (prolog_key.ps_prolog.colors_read ||
7663 prolog_key.ps_prolog.states.force_persp_sample_interp ||
7664 prolog_key.ps_prolog.states.force_linear_sample_interp ||
7665 prolog_key.ps_prolog.states.force_persp_center_interp ||
7666 prolog_key.ps_prolog.states.force_linear_center_interp ||
7667 prolog_key.ps_prolog.states.bc_optimize_for_persp ||
7668 prolog_key.ps_prolog.states.bc_optimize_for_linear);
7669
7670 if (info->colors_read) {
7671 unsigned *color = shader->selector->color_attr_index;
7672
7673 if (shader->key.ps.prolog.color_two_side) {
7674 /* BCOLORs are stored after the last input. */
7675 prolog_key.ps_prolog.num_interp_inputs = info->num_inputs;
7676 prolog_key.ps_prolog.face_vgpr_index = shader->info.face_vgpr_index;
7677 shader->config.spi_ps_input_ena |= S_0286CC_FRONT_FACE_ENA(1);
7678 }
7679
7680 for (i = 0; i < 2; i++) {
7681 unsigned interp = info->input_interpolate[color[i]];
7682 unsigned location = info->input_interpolate_loc[color[i]];
7683
7684 if (!(info->colors_read & (0xf << i*4)))
7685 continue;
7686
7687 prolog_key.ps_prolog.color_attr_index[i] = color[i];
7688
7689 if (shader->key.ps.prolog.flatshade_colors &&
7690 interp == TGSI_INTERPOLATE_COLOR)
7691 interp = TGSI_INTERPOLATE_CONSTANT;
7692
7693 switch (interp) {
7694 case TGSI_INTERPOLATE_CONSTANT:
7695 prolog_key.ps_prolog.color_interp_vgpr_index[i] = -1;
7696 break;
7697 case TGSI_INTERPOLATE_PERSPECTIVE:
7698 case TGSI_INTERPOLATE_COLOR:
7699 /* Force the interpolation location for colors here. */
7700 if (shader->key.ps.prolog.force_persp_sample_interp)
7701 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7702 if (shader->key.ps.prolog.force_persp_center_interp)
7703 location = TGSI_INTERPOLATE_LOC_CENTER;
7704
7705 switch (location) {
7706 case TGSI_INTERPOLATE_LOC_SAMPLE:
7707 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 0;
7708 shader->config.spi_ps_input_ena |=
7709 S_0286CC_PERSP_SAMPLE_ENA(1);
7710 break;
7711 case TGSI_INTERPOLATE_LOC_CENTER:
7712 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 2;
7713 shader->config.spi_ps_input_ena |=
7714 S_0286CC_PERSP_CENTER_ENA(1);
7715 break;
7716 case TGSI_INTERPOLATE_LOC_CENTROID:
7717 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 4;
7718 shader->config.spi_ps_input_ena |=
7719 S_0286CC_PERSP_CENTROID_ENA(1);
7720 break;
7721 default:
7722 assert(0);
7723 }
7724 break;
7725 case TGSI_INTERPOLATE_LINEAR:
7726 /* Force the interpolation location for colors here. */
7727 if (shader->key.ps.prolog.force_linear_sample_interp)
7728 location = TGSI_INTERPOLATE_LOC_SAMPLE;
7729 if (shader->key.ps.prolog.force_linear_center_interp)
7730 location = TGSI_INTERPOLATE_LOC_CENTER;
7731
7732 switch (location) {
7733 case TGSI_INTERPOLATE_LOC_SAMPLE:
7734 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 6;
7735 shader->config.spi_ps_input_ena |=
7736 S_0286CC_LINEAR_SAMPLE_ENA(1);
7737 break;
7738 case TGSI_INTERPOLATE_LOC_CENTER:
7739 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 8;
7740 shader->config.spi_ps_input_ena |=
7741 S_0286CC_LINEAR_CENTER_ENA(1);
7742 break;
7743 case TGSI_INTERPOLATE_LOC_CENTROID:
7744 prolog_key.ps_prolog.color_interp_vgpr_index[i] = 10;
7745 shader->config.spi_ps_input_ena |=
7746 S_0286CC_LINEAR_CENTROID_ENA(1);
7747 break;
7748 default:
7749 assert(0);
7750 }
7751 break;
7752 default:
7753 assert(0);
7754 }
7755 }
7756 }
7757
7758 /* The prolog is a no-op if these aren't set. */
7759 if (prolog_key.ps_prolog.colors_read ||
7760 prolog_key.ps_prolog.states.force_persp_sample_interp ||
7761 prolog_key.ps_prolog.states.force_linear_sample_interp ||
7762 prolog_key.ps_prolog.states.force_persp_center_interp ||
7763 prolog_key.ps_prolog.states.force_linear_center_interp ||
7764 prolog_key.ps_prolog.states.bc_optimize_for_persp ||
7765 prolog_key.ps_prolog.states.bc_optimize_for_linear ||
7766 prolog_key.ps_prolog.states.poly_stipple) {
7767 shader->prolog =
7768 si_get_shader_part(sscreen, &sscreen->ps_prologs,
7769 &prolog_key, tm, debug,
7770 si_compile_ps_prolog);
7771 if (!shader->prolog)
7772 return false;
7773 }
7774
7775 /* Get the epilog. */
7776 memset(&epilog_key, 0, sizeof(epilog_key));
7777 epilog_key.ps_epilog.colors_written = info->colors_written;
7778 epilog_key.ps_epilog.writes_z = info->writes_z;
7779 epilog_key.ps_epilog.writes_stencil = info->writes_stencil;
7780 epilog_key.ps_epilog.writes_samplemask = info->writes_samplemask;
7781 epilog_key.ps_epilog.states = shader->key.ps.epilog;
7782
7783 shader->epilog =
7784 si_get_shader_part(sscreen, &sscreen->ps_epilogs,
7785 &epilog_key, tm, debug,
7786 si_compile_ps_epilog);
7787 if (!shader->epilog)
7788 return false;
7789
7790 /* Enable POS_FIXED_PT if polygon stippling is enabled. */
7791 if (shader->key.ps.prolog.poly_stipple) {
7792 shader->config.spi_ps_input_ena |= S_0286CC_POS_FIXED_PT_ENA(1);
7793 assert(G_0286CC_POS_FIXED_PT_ENA(shader->config.spi_ps_input_addr));
7794 }
7795
7796 /* Set up the enable bits for per-sample shading if needed. */
7797 if (shader->key.ps.prolog.force_persp_sample_interp &&
7798 (G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7799 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7800 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTER_ENA;
7801 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7802 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_SAMPLE_ENA(1);
7803 }
7804 if (shader->key.ps.prolog.force_linear_sample_interp &&
7805 (G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_ena) ||
7806 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7807 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTER_ENA;
7808 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7809 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_SAMPLE_ENA(1);
7810 }
7811 if (shader->key.ps.prolog.force_persp_center_interp &&
7812 (G_0286CC_PERSP_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7813 G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7814 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_SAMPLE_ENA;
7815 shader->config.spi_ps_input_ena &= C_0286CC_PERSP_CENTROID_ENA;
7816 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7817 }
7818 if (shader->key.ps.prolog.force_linear_center_interp &&
7819 (G_0286CC_LINEAR_SAMPLE_ENA(shader->config.spi_ps_input_ena) ||
7820 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena))) {
7821 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_SAMPLE_ENA;
7822 shader->config.spi_ps_input_ena &= C_0286CC_LINEAR_CENTROID_ENA;
7823 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7824 }
7825
7826 /* POW_W_FLOAT requires that one of the perspective weights is enabled. */
7827 if (G_0286CC_POS_W_FLOAT_ENA(shader->config.spi_ps_input_ena) &&
7828 !(shader->config.spi_ps_input_ena & 0xf)) {
7829 shader->config.spi_ps_input_ena |= S_0286CC_PERSP_CENTER_ENA(1);
7830 assert(G_0286CC_PERSP_CENTER_ENA(shader->config.spi_ps_input_addr));
7831 }
7832
7833 /* At least one pair of interpolation weights must be enabled. */
7834 if (!(shader->config.spi_ps_input_ena & 0x7f)) {
7835 shader->config.spi_ps_input_ena |= S_0286CC_LINEAR_CENTER_ENA(1);
7836 assert(G_0286CC_LINEAR_CENTER_ENA(shader->config.spi_ps_input_addr));
7837 }
7838
7839 /* The sample mask input is always enabled, because the API shader always
7840 * passes it through to the epilog. Disable it here if it's unused.
7841 */
7842 if (!shader->key.ps.epilog.poly_line_smoothing &&
7843 !shader->selector->info.reads_samplemask)
7844 shader->config.spi_ps_input_ena &= C_0286CC_SAMPLE_COVERAGE_ENA;
7845
7846 return true;
7847 }
7848
7849 static void si_fix_num_sgprs(struct si_shader *shader)
7850 {
7851 unsigned min_sgprs = shader->info.num_input_sgprs + 2; /* VCC */
7852
7853 shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
7854 }
7855
7856 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
7857 struct si_shader *shader,
7858 struct pipe_debug_callback *debug)
7859 {
7860 struct si_shader_selector *sel = shader->selector;
7861 struct si_shader *mainp = sel->main_shader_part;
7862 int r;
7863
7864 /* LS, ES, VS are compiled on demand if the main part hasn't been
7865 * compiled for that stage.
7866 */
7867 if (!mainp ||
7868 (sel->type == PIPE_SHADER_VERTEX &&
7869 (shader->key.vs.as_es != mainp->key.vs.as_es ||
7870 shader->key.vs.as_ls != mainp->key.vs.as_ls)) ||
7871 (sel->type == PIPE_SHADER_TESS_EVAL &&
7872 shader->key.tes.as_es != mainp->key.tes.as_es) ||
7873 (sel->type == PIPE_SHADER_TESS_CTRL &&
7874 shader->key.tcs.epilog.inputs_to_copy) ||
7875 sel->type == PIPE_SHADER_COMPUTE) {
7876 /* Monolithic shader (compiled as a whole, has many variants,
7877 * may take a long time to compile).
7878 */
7879 r = si_compile_tgsi_shader(sscreen, tm, shader, true, debug);
7880 if (r)
7881 return r;
7882 } else {
7883 /* The shader consists of 2-3 parts:
7884 *
7885 * - the middle part is the user shader, it has 1 variant only
7886 * and it was compiled during the creation of the shader
7887 * selector
7888 * - the prolog part is inserted at the beginning
7889 * - the epilog part is inserted at the end
7890 *
7891 * The prolog and epilog have many (but simple) variants.
7892 */
7893
7894 /* Copy the compiled TGSI shader data over. */
7895 shader->is_binary_shared = true;
7896 shader->binary = mainp->binary;
7897 shader->config = mainp->config;
7898 shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
7899 shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
7900 shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
7901 memcpy(shader->info.vs_output_param_offset,
7902 mainp->info.vs_output_param_offset,
7903 sizeof(mainp->info.vs_output_param_offset));
7904 shader->info.uses_instanceid = mainp->info.uses_instanceid;
7905 shader->info.nr_pos_exports = mainp->info.nr_pos_exports;
7906 shader->info.nr_param_exports = mainp->info.nr_param_exports;
7907
7908 /* Select prologs and/or epilogs. */
7909 switch (sel->type) {
7910 case PIPE_SHADER_VERTEX:
7911 if (!si_shader_select_vs_parts(sscreen, tm, shader, debug))
7912 return -1;
7913 break;
7914 case PIPE_SHADER_TESS_CTRL:
7915 if (!si_shader_select_tcs_parts(sscreen, tm, shader, debug))
7916 return -1;
7917 break;
7918 case PIPE_SHADER_TESS_EVAL:
7919 if (!si_shader_select_tes_parts(sscreen, tm, shader, debug))
7920 return -1;
7921 break;
7922 case PIPE_SHADER_FRAGMENT:
7923 if (!si_shader_select_ps_parts(sscreen, tm, shader, debug))
7924 return -1;
7925
7926 /* Make sure we have at least as many VGPRs as there
7927 * are allocated inputs.
7928 */
7929 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7930 shader->info.num_input_vgprs);
7931 break;
7932 }
7933
7934 /* Update SGPR and VGPR counts. */
7935 if (shader->prolog) {
7936 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7937 shader->prolog->config.num_sgprs);
7938 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7939 shader->prolog->config.num_vgprs);
7940 }
7941 if (shader->epilog) {
7942 shader->config.num_sgprs = MAX2(shader->config.num_sgprs,
7943 shader->epilog->config.num_sgprs);
7944 shader->config.num_vgprs = MAX2(shader->config.num_vgprs,
7945 shader->epilog->config.num_vgprs);
7946 }
7947 }
7948
7949 si_fix_num_sgprs(shader);
7950 si_shader_dump(sscreen, shader, debug, sel->info.processor,
7951 stderr);
7952
7953 /* Upload. */
7954 r = si_shader_binary_upload(sscreen, shader);
7955 if (r) {
7956 fprintf(stderr, "LLVM failed to upload shader\n");
7957 return r;
7958 }
7959
7960 return 0;
7961 }
7962
7963 void si_shader_destroy(struct si_shader *shader)
7964 {
7965 if (shader->gs_copy_shader) {
7966 si_shader_destroy(shader->gs_copy_shader);
7967 FREE(shader->gs_copy_shader);
7968 }
7969
7970 if (shader->scratch_bo)
7971 r600_resource_reference(&shader->scratch_bo, NULL);
7972
7973 r600_resource_reference(&shader->bo, NULL);
7974
7975 if (!shader->is_binary_shared)
7976 radeon_shader_binary_clean(&shader->binary);
7977
7978 free(shader->shader_log);
7979 }