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radeonsi: move BCOLOR PS input locations after all other inputs
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_dump.h"
45
46 #include "si_pipe.h"
47 #include "si_shader.h"
48 #include "sid.h"
49
50 #include <errno.h>
51
52 static const char *scratch_rsrc_dword0_symbol =
53 "SCRATCH_RSRC_DWORD0";
54
55 static const char *scratch_rsrc_dword1_symbol =
56 "SCRATCH_RSRC_DWORD1";
57
58 struct si_shader_output_values
59 {
60 LLVMValueRef values[4];
61 unsigned name;
62 unsigned sid;
63 };
64
65 struct si_shader_context
66 {
67 struct radeon_llvm_context radeon_bld;
68 struct si_shader *shader;
69 struct si_screen *screen;
70 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
71 bool is_gs_copy_shader;
72 int param_streamout_config;
73 int param_streamout_write_index;
74 int param_streamout_offset[4];
75 int param_vertex_id;
76 int param_rel_auto_id;
77 int param_vs_prim_id;
78 int param_instance_id;
79 int param_tes_u;
80 int param_tes_v;
81 int param_tes_rel_patch_id;
82 int param_tes_patch_id;
83 int param_es2gs_offset;
84 LLVMTargetMachineRef tm;
85 LLVMValueRef const_md;
86 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
87 LLVMValueRef lds;
88 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
89 LLVMValueRef sampler_views[SI_NUM_SAMPLER_VIEWS];
90 LLVMValueRef sampler_states[SI_NUM_SAMPLER_STATES];
91 LLVMValueRef so_buffers[4];
92 LLVMValueRef esgs_ring;
93 LLVMValueRef gsvs_ring[4];
94 LLVMValueRef gs_next_vertex[4];
95 };
96
97 static struct si_shader_context * si_shader_context(
98 struct lp_build_tgsi_context * bld_base)
99 {
100 return (struct si_shader_context *)bld_base;
101 }
102
103
104 #define PERSPECTIVE_BASE 0
105 #define LINEAR_BASE 9
106
107 #define SAMPLE_OFFSET 0
108 #define CENTER_OFFSET 2
109 #define CENTROID_OFSET 4
110
111 #define USE_SGPR_MAX_SUFFIX_LEN 5
112 #define CONST_ADDR_SPACE 2
113 #define LOCAL_ADDR_SPACE 3
114 #define USER_SGPR_ADDR_SPACE 8
115
116
117 #define SENDMSG_GS 2
118 #define SENDMSG_GS_DONE 3
119
120 #define SENDMSG_GS_OP_NOP (0 << 4)
121 #define SENDMSG_GS_OP_CUT (1 << 4)
122 #define SENDMSG_GS_OP_EMIT (2 << 4)
123 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
124
125 /**
126 * Returns a unique index for a semantic name and index. The index must be
127 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
128 * calculated.
129 */
130 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
131 {
132 switch (semantic_name) {
133 case TGSI_SEMANTIC_POSITION:
134 return 0;
135 case TGSI_SEMANTIC_PSIZE:
136 return 1;
137 case TGSI_SEMANTIC_CLIPDIST:
138 assert(index <= 1);
139 return 2 + index;
140 case TGSI_SEMANTIC_GENERIC:
141 if (index <= 63-4)
142 return 4 + index;
143 else
144 /* same explanation as in the default statement,
145 * the only user hitting this is st/nine.
146 */
147 return 0;
148
149 /* patch indices are completely separate and thus start from 0 */
150 case TGSI_SEMANTIC_TESSOUTER:
151 return 0;
152 case TGSI_SEMANTIC_TESSINNER:
153 return 1;
154 case TGSI_SEMANTIC_PATCH:
155 return 2 + index;
156
157 default:
158 /* Don't fail here. The result of this function is only used
159 * for LS, TCS, TES, and GS, where legacy GL semantics can't
160 * occur, but this function is called for all vertex shaders
161 * before it's known whether LS will be compiled or not.
162 */
163 return 0;
164 }
165 }
166
167 /**
168 * Get the value of a shader input parameter and extract a bitfield.
169 */
170 static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx,
171 unsigned param, unsigned rshift,
172 unsigned bitwidth)
173 {
174 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
175 LLVMValueRef value = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
176 param);
177
178 if (rshift)
179 value = LLVMBuildLShr(gallivm->builder, value,
180 lp_build_const_int32(gallivm, rshift), "");
181
182 if (rshift + bitwidth < 32) {
183 unsigned mask = (1 << bitwidth) - 1;
184 value = LLVMBuildAnd(gallivm->builder, value,
185 lp_build_const_int32(gallivm, mask), "");
186 }
187
188 return value;
189 }
190
191 static LLVMValueRef get_rel_patch_id(struct si_shader_context *si_shader_ctx)
192 {
193 switch (si_shader_ctx->type) {
194 case TGSI_PROCESSOR_TESS_CTRL:
195 return unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 0, 8);
196
197 case TGSI_PROCESSOR_TESS_EVAL:
198 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
199 si_shader_ctx->param_tes_rel_patch_id);
200
201 default:
202 assert(0);
203 return NULL;
204 }
205 }
206
207 /* Tessellation shaders pass outputs to the next shader using LDS.
208 *
209 * LS outputs = TCS inputs
210 * TCS outputs = TES inputs
211 *
212 * The LDS layout is:
213 * - TCS inputs for patch 0
214 * - TCS inputs for patch 1
215 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
216 * - ...
217 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
218 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
219 * - TCS outputs for patch 1
220 * - Per-patch TCS outputs for patch 1
221 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
222 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
223 * - ...
224 *
225 * All three shaders VS(LS), TCS, TES share the same LDS space.
226 */
227
228 static LLVMValueRef
229 get_tcs_in_patch_stride(struct si_shader_context *si_shader_ctx)
230 {
231 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX)
232 return unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
233 else if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
234 return unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
235 else {
236 assert(0);
237 return NULL;
238 }
239 }
240
241 static LLVMValueRef
242 get_tcs_out_patch_stride(struct si_shader_context *si_shader_ctx)
243 {
244 return unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
245 }
246
247 static LLVMValueRef
248 get_tcs_out_patch0_offset(struct si_shader_context *si_shader_ctx)
249 {
250 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
251 unpack_param(si_shader_ctx,
252 SI_PARAM_TCS_OUT_OFFSETS,
253 0, 16),
254 4);
255 }
256
257 static LLVMValueRef
258 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *si_shader_ctx)
259 {
260 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
261 unpack_param(si_shader_ctx,
262 SI_PARAM_TCS_OUT_OFFSETS,
263 16, 16),
264 4);
265 }
266
267 static LLVMValueRef
268 get_tcs_in_current_patch_offset(struct si_shader_context *si_shader_ctx)
269 {
270 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
271 LLVMValueRef patch_stride = get_tcs_in_patch_stride(si_shader_ctx);
272 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
273
274 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
275 }
276
277 static LLVMValueRef
278 get_tcs_out_current_patch_offset(struct si_shader_context *si_shader_ctx)
279 {
280 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
281 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(si_shader_ctx);
282 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
283 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
284
285 return LLVMBuildAdd(gallivm->builder, patch0_offset,
286 LLVMBuildMul(gallivm->builder, patch_stride,
287 rel_patch_id, ""),
288 "");
289 }
290
291 static LLVMValueRef
292 get_tcs_out_current_patch_data_offset(struct si_shader_context *si_shader_ctx)
293 {
294 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
295 LLVMValueRef patch0_patch_data_offset =
296 get_tcs_out_patch0_patch_data_offset(si_shader_ctx);
297 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
298 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
299
300 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
301 LLVMBuildMul(gallivm->builder, patch_stride,
302 rel_patch_id, ""),
303 "");
304 }
305
306 static void build_indexed_store(struct si_shader_context *si_shader_ctx,
307 LLVMValueRef base_ptr, LLVMValueRef index,
308 LLVMValueRef value)
309 {
310 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
311 struct gallivm_state *gallivm = bld_base->base.gallivm;
312 LLVMValueRef indices[2], pointer;
313
314 indices[0] = bld_base->uint_bld.zero;
315 indices[1] = index;
316
317 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
318 LLVMBuildStore(gallivm->builder, value, pointer);
319 }
320
321 /**
322 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
323 * It's equivalent to doing a load from &base_ptr[index].
324 *
325 * \param base_ptr Where the array starts.
326 * \param index The element index into the array.
327 */
328 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
329 LLVMValueRef base_ptr, LLVMValueRef index)
330 {
331 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
332 struct gallivm_state *gallivm = bld_base->base.gallivm;
333 LLVMValueRef indices[2], pointer;
334
335 indices[0] = bld_base->uint_bld.zero;
336 indices[1] = index;
337
338 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
339 return LLVMBuildLoad(gallivm->builder, pointer, "");
340 }
341
342 /**
343 * Do a load from &base_ptr[index], but also add a flag that it's loading
344 * a constant.
345 */
346 static LLVMValueRef build_indexed_load_const(
347 struct si_shader_context * si_shader_ctx,
348 LLVMValueRef base_ptr, LLVMValueRef index)
349 {
350 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
351 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
352 return result;
353 }
354
355 static LLVMValueRef get_instance_index_for_fetch(
356 struct radeon_llvm_context * radeon_bld,
357 unsigned divisor)
358 {
359 struct si_shader_context *si_shader_ctx =
360 si_shader_context(&radeon_bld->soa.bld_base);
361 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
362
363 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
364 si_shader_ctx->param_instance_id);
365
366 /* The division must be done before START_INSTANCE is added. */
367 if (divisor > 1)
368 result = LLVMBuildUDiv(gallivm->builder, result,
369 lp_build_const_int32(gallivm, divisor), "");
370
371 return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
372 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
373 }
374
375 static void declare_input_vs(
376 struct radeon_llvm_context *radeon_bld,
377 unsigned input_index,
378 const struct tgsi_full_declaration *decl)
379 {
380 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
381 struct gallivm_state *gallivm = base->gallivm;
382 struct si_shader_context *si_shader_ctx =
383 si_shader_context(&radeon_bld->soa.bld_base);
384 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
385
386 unsigned chan;
387
388 LLVMValueRef t_list_ptr;
389 LLVMValueRef t_offset;
390 LLVMValueRef t_list;
391 LLVMValueRef attribute_offset;
392 LLVMValueRef buffer_index;
393 LLVMValueRef args[3];
394 LLVMTypeRef vec4_type;
395 LLVMValueRef input;
396
397 /* Load the T list */
398 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
399
400 t_offset = lp_build_const_int32(gallivm, input_index);
401
402 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
403
404 /* Build the attribute offset */
405 attribute_offset = lp_build_const_int32(gallivm, 0);
406
407 if (divisor) {
408 /* Build index from instance ID, start instance and divisor */
409 si_shader_ctx->shader->uses_instanceid = true;
410 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
411 } else {
412 /* Load the buffer index for vertices. */
413 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
414 si_shader_ctx->param_vertex_id);
415 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
416 SI_PARAM_BASE_VERTEX);
417 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
418 }
419
420 vec4_type = LLVMVectorType(base->elem_type, 4);
421 args[0] = t_list;
422 args[1] = attribute_offset;
423 args[2] = buffer_index;
424 input = lp_build_intrinsic(gallivm->builder,
425 "llvm.SI.vs.load.input", vec4_type, args, 3,
426 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
427
428 /* Break up the vec4 into individual components */
429 for (chan = 0; chan < 4; chan++) {
430 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
431 /* XXX: Use a helper function for this. There is one in
432 * tgsi_llvm.c. */
433 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
434 LLVMBuildExtractElement(gallivm->builder,
435 input, llvm_chan, "");
436 }
437 }
438
439 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
440 unsigned swizzle)
441 {
442 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
443
444 if (swizzle > 0)
445 return bld_base->uint_bld.zero;
446
447 switch (si_shader_ctx->type) {
448 case TGSI_PROCESSOR_VERTEX:
449 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
450 si_shader_ctx->param_vs_prim_id);
451 case TGSI_PROCESSOR_TESS_CTRL:
452 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
453 SI_PARAM_PATCH_ID);
454 case TGSI_PROCESSOR_TESS_EVAL:
455 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
456 si_shader_ctx->param_tes_patch_id);
457 case TGSI_PROCESSOR_GEOMETRY:
458 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
459 SI_PARAM_PRIMITIVE_ID);
460 default:
461 assert(0);
462 return bld_base->uint_bld.zero;
463 }
464 }
465
466 /**
467 * Return the value of tgsi_ind_register for indexing.
468 * This is the indirect index with the constant offset added to it.
469 */
470 static LLVMValueRef get_indirect_index(struct si_shader_context *si_shader_ctx,
471 const struct tgsi_ind_register *ind,
472 int rel_index)
473 {
474 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
475 LLVMValueRef result;
476
477 result = si_shader_ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
478 result = LLVMBuildLoad(gallivm->builder, result, "");
479 result = LLVMBuildAdd(gallivm->builder, result,
480 lp_build_const_int32(gallivm, rel_index), "");
481 return result;
482 }
483
484 /**
485 * Calculate a dword address given an input or output register and a stride.
486 */
487 static LLVMValueRef get_dw_address(struct si_shader_context *si_shader_ctx,
488 const struct tgsi_full_dst_register *dst,
489 const struct tgsi_full_src_register *src,
490 LLVMValueRef vertex_dw_stride,
491 LLVMValueRef base_addr)
492 {
493 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
494 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
495 ubyte *name, *index, *array_first;
496 int first, param;
497 struct tgsi_full_dst_register reg;
498
499 /* Set the register description. The address computation is the same
500 * for sources and destinations. */
501 if (src) {
502 reg.Register.File = src->Register.File;
503 reg.Register.Index = src->Register.Index;
504 reg.Register.Indirect = src->Register.Indirect;
505 reg.Register.Dimension = src->Register.Dimension;
506 reg.Indirect = src->Indirect;
507 reg.Dimension = src->Dimension;
508 reg.DimIndirect = src->DimIndirect;
509 } else
510 reg = *dst;
511
512 /* If the register is 2-dimensional (e.g. an array of vertices
513 * in a primitive), calculate the base address of the vertex. */
514 if (reg.Register.Dimension) {
515 LLVMValueRef index;
516
517 if (reg.Dimension.Indirect)
518 index = get_indirect_index(si_shader_ctx, &reg.DimIndirect,
519 reg.Dimension.Index);
520 else
521 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
522
523 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
524 LLVMBuildMul(gallivm->builder, index,
525 vertex_dw_stride, ""), "");
526 }
527
528 /* Get information about the register. */
529 if (reg.Register.File == TGSI_FILE_INPUT) {
530 name = info->input_semantic_name;
531 index = info->input_semantic_index;
532 array_first = info->input_array_first;
533 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
534 name = info->output_semantic_name;
535 index = info->output_semantic_index;
536 array_first = info->output_array_first;
537 } else {
538 assert(0);
539 return NULL;
540 }
541
542 if (reg.Register.Indirect) {
543 /* Add the relative address of the element. */
544 LLVMValueRef ind_index;
545
546 if (reg.Indirect.ArrayID)
547 first = array_first[reg.Indirect.ArrayID];
548 else
549 first = reg.Register.Index;
550
551 ind_index = get_indirect_index(si_shader_ctx, &reg.Indirect,
552 reg.Register.Index - first);
553
554 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
555 LLVMBuildMul(gallivm->builder, ind_index,
556 lp_build_const_int32(gallivm, 4), ""), "");
557
558 param = si_shader_io_get_unique_index(name[first], index[first]);
559 } else {
560 param = si_shader_io_get_unique_index(name[reg.Register.Index],
561 index[reg.Register.Index]);
562 }
563
564 /* Add the base address of the element. */
565 return LLVMBuildAdd(gallivm->builder, base_addr,
566 lp_build_const_int32(gallivm, param * 4), "");
567 }
568
569 /**
570 * Load from LDS.
571 *
572 * \param type output value type
573 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
574 * \param dw_addr address in dwords
575 */
576 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
577 enum tgsi_opcode_type type, unsigned swizzle,
578 LLVMValueRef dw_addr)
579 {
580 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
581 struct gallivm_state *gallivm = bld_base->base.gallivm;
582 LLVMValueRef value;
583
584 if (swizzle == ~0) {
585 LLVMValueRef values[TGSI_NUM_CHANNELS];
586
587 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
588 values[chan] = lds_load(bld_base, type, chan, dw_addr);
589
590 return lp_build_gather_values(bld_base->base.gallivm, values,
591 TGSI_NUM_CHANNELS);
592 }
593
594 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
595 lp_build_const_int32(gallivm, swizzle));
596
597 value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
598 if (type == TGSI_TYPE_DOUBLE) {
599 LLVMValueRef value2;
600 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
601 lp_build_const_int32(gallivm, swizzle + 1));
602 value2 = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
603 return radeon_llvm_emit_fetch_double(bld_base, value, value2);
604 }
605
606 return LLVMBuildBitCast(gallivm->builder, value,
607 tgsi2llvmtype(bld_base, type), "");
608 }
609
610 /**
611 * Store to LDS.
612 *
613 * \param swizzle offset (typically 0..3)
614 * \param dw_addr address in dwords
615 * \param value value to store
616 */
617 static void lds_store(struct lp_build_tgsi_context * bld_base,
618 unsigned swizzle, LLVMValueRef dw_addr,
619 LLVMValueRef value)
620 {
621 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
622 struct gallivm_state *gallivm = bld_base->base.gallivm;
623
624 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
625 lp_build_const_int32(gallivm, swizzle));
626
627 value = LLVMBuildBitCast(gallivm->builder, value,
628 LLVMInt32TypeInContext(gallivm->context), "");
629 build_indexed_store(si_shader_ctx, si_shader_ctx->lds,
630 dw_addr, value);
631 }
632
633 static LLVMValueRef fetch_input_tcs(
634 struct lp_build_tgsi_context *bld_base,
635 const struct tgsi_full_src_register *reg,
636 enum tgsi_opcode_type type, unsigned swizzle)
637 {
638 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
639 LLVMValueRef dw_addr, stride;
640
641 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
642 dw_addr = get_tcs_in_current_patch_offset(si_shader_ctx);
643 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
644
645 return lds_load(bld_base, type, swizzle, dw_addr);
646 }
647
648 static LLVMValueRef fetch_output_tcs(
649 struct lp_build_tgsi_context *bld_base,
650 const struct tgsi_full_src_register *reg,
651 enum tgsi_opcode_type type, unsigned swizzle)
652 {
653 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
654 LLVMValueRef dw_addr, stride;
655
656 if (reg->Register.Dimension) {
657 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
658 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
659 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
660 } else {
661 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
662 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
663 }
664
665 return lds_load(bld_base, type, swizzle, dw_addr);
666 }
667
668 static LLVMValueRef fetch_input_tes(
669 struct lp_build_tgsi_context *bld_base,
670 const struct tgsi_full_src_register *reg,
671 enum tgsi_opcode_type type, unsigned swizzle)
672 {
673 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
674 LLVMValueRef dw_addr, stride;
675
676 if (reg->Register.Dimension) {
677 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
678 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
679 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
680 } else {
681 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
682 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
683 }
684
685 return lds_load(bld_base, type, swizzle, dw_addr);
686 }
687
688 static void store_output_tcs(struct lp_build_tgsi_context * bld_base,
689 const struct tgsi_full_instruction * inst,
690 const struct tgsi_opcode_info * info,
691 LLVMValueRef dst[4])
692 {
693 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
694 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
695 unsigned chan_index;
696 LLVMValueRef dw_addr, stride;
697
698 /* Only handle per-patch and per-vertex outputs here.
699 * Vectors will be lowered to scalars and this function will be called again.
700 */
701 if (reg->Register.File != TGSI_FILE_OUTPUT ||
702 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
703 radeon_llvm_emit_store(bld_base, inst, info, dst);
704 return;
705 }
706
707 if (reg->Register.Dimension) {
708 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
709 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
710 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, stride, dw_addr);
711 } else {
712 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
713 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, NULL, dw_addr);
714 }
715
716 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
717 LLVMValueRef value = dst[chan_index];
718
719 if (inst->Instruction.Saturate)
720 value = radeon_llvm_saturate(bld_base, value);
721
722 lds_store(bld_base, chan_index, dw_addr, value);
723 }
724 }
725
726 static LLVMValueRef fetch_input_gs(
727 struct lp_build_tgsi_context *bld_base,
728 const struct tgsi_full_src_register *reg,
729 enum tgsi_opcode_type type,
730 unsigned swizzle)
731 {
732 struct lp_build_context *base = &bld_base->base;
733 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
734 struct si_shader *shader = si_shader_ctx->shader;
735 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
736 struct gallivm_state *gallivm = base->gallivm;
737 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
738 LLVMValueRef vtx_offset;
739 LLVMValueRef args[9];
740 unsigned vtx_offset_param;
741 struct tgsi_shader_info *info = &shader->selector->info;
742 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
743 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
744 unsigned param;
745 LLVMValueRef value;
746
747 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
748 return get_primitive_id(bld_base, swizzle);
749
750 if (!reg->Register.Dimension)
751 return NULL;
752
753 if (swizzle == ~0) {
754 LLVMValueRef values[TGSI_NUM_CHANNELS];
755 unsigned chan;
756 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
757 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
758 }
759 return lp_build_gather_values(bld_base->base.gallivm, values,
760 TGSI_NUM_CHANNELS);
761 }
762
763 /* Get the vertex offset parameter */
764 vtx_offset_param = reg->Dimension.Index;
765 if (vtx_offset_param < 2) {
766 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
767 } else {
768 assert(vtx_offset_param < 6);
769 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
770 }
771 vtx_offset = lp_build_mul_imm(uint,
772 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
773 vtx_offset_param),
774 4);
775
776 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
777 args[0] = si_shader_ctx->esgs_ring;
778 args[1] = vtx_offset;
779 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
780 args[3] = uint->zero;
781 args[4] = uint->one; /* OFFEN */
782 args[5] = uint->zero; /* IDXEN */
783 args[6] = uint->one; /* GLC */
784 args[7] = uint->zero; /* SLC */
785 args[8] = uint->zero; /* TFE */
786
787 value = lp_build_intrinsic(gallivm->builder,
788 "llvm.SI.buffer.load.dword.i32.i32",
789 i32, args, 9,
790 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
791 if (type == TGSI_TYPE_DOUBLE) {
792 LLVMValueRef value2;
793 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
794 value2 = lp_build_intrinsic(gallivm->builder,
795 "llvm.SI.buffer.load.dword.i32.i32",
796 i32, args, 9,
797 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
798 return radeon_llvm_emit_fetch_double(bld_base,
799 value, value2);
800 }
801 return LLVMBuildBitCast(gallivm->builder,
802 value,
803 tgsi2llvmtype(bld_base, type), "");
804 }
805
806 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
807 {
808 switch (interpolate) {
809 case TGSI_INTERPOLATE_CONSTANT:
810 return 0;
811
812 case TGSI_INTERPOLATE_LINEAR:
813 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
814 return SI_PARAM_LINEAR_SAMPLE;
815 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
816 return SI_PARAM_LINEAR_CENTROID;
817 else
818 return SI_PARAM_LINEAR_CENTER;
819 break;
820 case TGSI_INTERPOLATE_COLOR:
821 case TGSI_INTERPOLATE_PERSPECTIVE:
822 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
823 return SI_PARAM_PERSP_SAMPLE;
824 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
825 return SI_PARAM_PERSP_CENTROID;
826 else
827 return SI_PARAM_PERSP_CENTER;
828 break;
829 default:
830 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
831 return -1;
832 }
833 }
834
835 /* This shouldn't be used by explicit INTERP opcodes. */
836 static LLVMValueRef get_interp_param(struct si_shader_context *si_shader_ctx,
837 unsigned param)
838 {
839 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
840 unsigned sample_param = 0;
841 LLVMValueRef default_ij, sample_ij, force_sample;
842
843 default_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, param);
844
845 /* If the shader doesn't use center/centroid, just return the parameter.
846 *
847 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
848 * switch between center/centroid and sample without shader changes.
849 */
850 switch (param) {
851 case SI_PARAM_PERSP_CENTROID:
852 case SI_PARAM_PERSP_CENTER:
853 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_persp)
854 return default_ij;
855
856 sample_param = SI_PARAM_PERSP_SAMPLE;
857 break;
858
859 case SI_PARAM_LINEAR_CENTROID:
860 case SI_PARAM_LINEAR_CENTER:
861 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_linear)
862 return default_ij;
863
864 sample_param = SI_PARAM_LINEAR_SAMPLE;
865 break;
866
867 default:
868 return default_ij;
869 }
870
871 /* Otherwise, we have to select (i,j) based on a user data SGPR. */
872 sample_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, sample_param);
873
874 /* TODO: this can be done more efficiently by switching between
875 * 2 prologs.
876 */
877 force_sample = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
878 SI_PARAM_PS_STATE_BITS);
879 force_sample = LLVMBuildTrunc(gallivm->builder, force_sample,
880 LLVMInt1TypeInContext(gallivm->context), "");
881 return LLVMBuildSelect(gallivm->builder, force_sample,
882 sample_ij, default_ij, "");
883 }
884
885 static void declare_input_fs(
886 struct radeon_llvm_context *radeon_bld,
887 unsigned input_index,
888 const struct tgsi_full_declaration *decl)
889 {
890 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
891 struct si_shader_context *si_shader_ctx =
892 si_shader_context(&radeon_bld->soa.bld_base);
893 struct si_shader *shader = si_shader_ctx->shader;
894 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
895 struct gallivm_state *gallivm = base->gallivm;
896 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
897 LLVMValueRef main_fn = radeon_bld->main_fn;
898
899 LLVMValueRef interp_param = NULL;
900 int interp_param_idx;
901 const char * intr_name;
902
903 /* This value is:
904 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
905 * quad begins a new primitive. Bit 0 always needs
906 * to be unset)
907 * [32:16] ParamOffset
908 *
909 */
910 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
911 LLVMValueRef attr_number;
912
913 unsigned chan;
914
915 attr_number = lp_build_const_int32(gallivm, input_index);
916
917 shader->ps_input_interpolate[input_index] = decl->Interp.Interpolate;
918 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
919 decl->Interp.Location);
920 if (interp_param_idx == -1)
921 return;
922 else if (interp_param_idx)
923 interp_param = get_interp_param(si_shader_ctx, interp_param_idx);
924
925 /* fs.constant returns the param from the middle vertex, so it's not
926 * really useful for flat shading. It's meant to be used for custom
927 * interpolation (but the intrinsic can't fetch from the other two
928 * vertices).
929 *
930 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
931 * to do the right thing. The only reason we use fs.constant is that
932 * fs.interp cannot be used on integers, because they can be equal
933 * to NaN.
934 */
935 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
936
937 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
938 si_shader_ctx->shader->key.ps.color_two_side) {
939 struct tgsi_shader_info *info = &shader->selector->info;
940 LLVMValueRef args[4];
941 LLVMValueRef face, is_face_positive;
942 LLVMValueRef back_attr_number;
943
944 /* If BCOLOR0 is used, BCOLOR1 is at offset "num_inputs + 1",
945 * otherwise it's at offset "num_inputs".
946 */
947 unsigned back_attr_offset = shader->selector->info.num_inputs;
948 if (decl->Semantic.Index == 1 && info->colors_read & 0xf)
949 back_attr_offset += 1;
950
951 back_attr_number = lp_build_const_int32(gallivm, back_attr_offset);
952
953 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
954
955 is_face_positive = LLVMBuildICmp(gallivm->builder, LLVMIntNE,
956 face, uint->zero, "");
957
958 args[2] = params;
959 args[3] = interp_param;
960 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
961 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
962 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
963 LLVMValueRef front, back;
964
965 args[0] = llvm_chan;
966 args[1] = attr_number;
967 front = lp_build_intrinsic(gallivm->builder, intr_name,
968 input_type, args, args[3] ? 4 : 3,
969 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
970
971 args[1] = back_attr_number;
972 back = lp_build_intrinsic(gallivm->builder, intr_name,
973 input_type, args, args[3] ? 4 : 3,
974 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
975
976 radeon_bld->inputs[soa_index] =
977 LLVMBuildSelect(gallivm->builder,
978 is_face_positive,
979 front,
980 back,
981 "");
982 }
983 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
984 LLVMValueRef args[4];
985
986 args[0] = uint->zero;
987 args[1] = attr_number;
988 args[2] = params;
989 args[3] = interp_param;
990 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
991 lp_build_intrinsic(gallivm->builder, intr_name,
992 input_type, args, args[3] ? 4 : 3,
993 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
994 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
995 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
996 lp_build_const_float(gallivm, 0.0f);
997 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
998 lp_build_const_float(gallivm, 1.0f);
999 } else {
1000 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1001 LLVMValueRef args[4];
1002 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1003 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
1004 args[0] = llvm_chan;
1005 args[1] = attr_number;
1006 args[2] = params;
1007 args[3] = interp_param;
1008 radeon_bld->inputs[soa_index] =
1009 lp_build_intrinsic(gallivm->builder, intr_name,
1010 input_type, args, args[3] ? 4 : 3,
1011 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1012 }
1013 }
1014 }
1015
1016 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1017 {
1018 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1019 SI_PARAM_ANCILLARY, 8, 4);
1020 }
1021
1022 /**
1023 * Load a dword from a constant buffer.
1024 */
1025 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1026 LLVMValueRef offset, LLVMTypeRef return_type)
1027 {
1028 LLVMValueRef args[2] = {resource, offset};
1029
1030 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1031 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1032 }
1033
1034 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1035 {
1036 struct si_shader_context *si_shader_ctx =
1037 si_shader_context(&radeon_bld->soa.bld_base);
1038 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1039 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1040 LLVMBuilderRef builder = gallivm->builder;
1041 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1042 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1043 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
1044
1045 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1046 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1047 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1048
1049 LLVMValueRef pos[4] = {
1050 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
1051 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
1052 lp_build_const_float(gallivm, 0),
1053 lp_build_const_float(gallivm, 0)
1054 };
1055
1056 return lp_build_gather_values(gallivm, pos, 4);
1057 }
1058
1059 static void declare_system_value(
1060 struct radeon_llvm_context * radeon_bld,
1061 unsigned index,
1062 const struct tgsi_full_declaration *decl)
1063 {
1064 struct si_shader_context *si_shader_ctx =
1065 si_shader_context(&radeon_bld->soa.bld_base);
1066 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1067 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1068 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1069 LLVMValueRef value = 0;
1070
1071 switch (decl->Semantic.Name) {
1072 case TGSI_SEMANTIC_INSTANCEID:
1073 value = LLVMGetParam(radeon_bld->main_fn,
1074 si_shader_ctx->param_instance_id);
1075 break;
1076
1077 case TGSI_SEMANTIC_VERTEXID:
1078 value = LLVMBuildAdd(gallivm->builder,
1079 LLVMGetParam(radeon_bld->main_fn,
1080 si_shader_ctx->param_vertex_id),
1081 LLVMGetParam(radeon_bld->main_fn,
1082 SI_PARAM_BASE_VERTEX), "");
1083 break;
1084
1085 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1086 value = LLVMGetParam(radeon_bld->main_fn,
1087 si_shader_ctx->param_vertex_id);
1088 break;
1089
1090 case TGSI_SEMANTIC_BASEVERTEX:
1091 value = LLVMGetParam(radeon_bld->main_fn,
1092 SI_PARAM_BASE_VERTEX);
1093 break;
1094
1095 case TGSI_SEMANTIC_INVOCATIONID:
1096 if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1097 value = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1098 else if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY)
1099 value = LLVMGetParam(radeon_bld->main_fn,
1100 SI_PARAM_GS_INSTANCE_ID);
1101 else
1102 assert(!"INVOCATIONID not implemented");
1103 break;
1104
1105 case TGSI_SEMANTIC_POSITION:
1106 {
1107 LLVMValueRef pos[4] = {
1108 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1109 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1110 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Z_FLOAT),
1111 lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base, TGSI_OPCODE_RCP,
1112 LLVMGetParam(radeon_bld->main_fn,
1113 SI_PARAM_POS_W_FLOAT)),
1114 };
1115 value = lp_build_gather_values(gallivm, pos, 4);
1116 break;
1117 }
1118
1119 case TGSI_SEMANTIC_FACE:
1120 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_FRONT_FACE);
1121 break;
1122
1123 case TGSI_SEMANTIC_SAMPLEID:
1124 value = get_sample_id(radeon_bld);
1125 break;
1126
1127 case TGSI_SEMANTIC_SAMPLEPOS: {
1128 LLVMValueRef pos[4] = {
1129 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_X_FLOAT),
1130 LLVMGetParam(radeon_bld->main_fn, SI_PARAM_POS_Y_FLOAT),
1131 lp_build_const_float(gallivm, 0),
1132 lp_build_const_float(gallivm, 0)
1133 };
1134 pos[0] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1135 TGSI_OPCODE_FRC, pos[0]);
1136 pos[1] = lp_build_emit_llvm_unary(&radeon_bld->soa.bld_base,
1137 TGSI_OPCODE_FRC, pos[1]);
1138 value = lp_build_gather_values(gallivm, pos, 4);
1139 break;
1140 }
1141
1142 case TGSI_SEMANTIC_SAMPLEMASK:
1143 /* Smoothing isn't MSAA in GL, but it's MSAA in hardware.
1144 * Therefore, force gl_SampleMaskIn to 1 for GL. */
1145 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
1146 value = uint_bld->one;
1147 else
1148 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1149 break;
1150
1151 case TGSI_SEMANTIC_TESSCOORD:
1152 {
1153 LLVMValueRef coord[4] = {
1154 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_u),
1155 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_v),
1156 bld->zero,
1157 bld->zero
1158 };
1159
1160 /* For triangles, the vector should be (u, v, 1-u-v). */
1161 if (si_shader_ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1162 PIPE_PRIM_TRIANGLES)
1163 coord[2] = lp_build_sub(bld, bld->one,
1164 lp_build_add(bld, coord[0], coord[1]));
1165
1166 value = lp_build_gather_values(gallivm, coord, 4);
1167 break;
1168 }
1169
1170 case TGSI_SEMANTIC_VERTICESIN:
1171 value = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1172 break;
1173
1174 case TGSI_SEMANTIC_TESSINNER:
1175 case TGSI_SEMANTIC_TESSOUTER:
1176 {
1177 LLVMValueRef dw_addr;
1178 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1179
1180 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1181 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1182 lp_build_const_int32(gallivm, param * 4), "");
1183
1184 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1185 ~0, dw_addr);
1186 break;
1187 }
1188
1189 case TGSI_SEMANTIC_PRIMID:
1190 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1191 break;
1192
1193 default:
1194 assert(!"unknown system value");
1195 return;
1196 }
1197
1198 radeon_bld->system_values[index] = value;
1199 }
1200
1201 static LLVMValueRef fetch_constant(
1202 struct lp_build_tgsi_context * bld_base,
1203 const struct tgsi_full_src_register *reg,
1204 enum tgsi_opcode_type type,
1205 unsigned swizzle)
1206 {
1207 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1208 struct lp_build_context * base = &bld_base->base;
1209 const struct tgsi_ind_register *ireg = &reg->Indirect;
1210 unsigned buf, idx;
1211
1212 LLVMValueRef addr, bufp;
1213 LLVMValueRef result;
1214
1215 if (swizzle == LP_CHAN_ALL) {
1216 unsigned chan;
1217 LLVMValueRef values[4];
1218 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1219 values[chan] = fetch_constant(bld_base, reg, type, chan);
1220
1221 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1222 }
1223
1224 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1225 idx = reg->Register.Index * 4 + swizzle;
1226
1227 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1228 if (type != TGSI_TYPE_DOUBLE)
1229 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
1230 else {
1231 return radeon_llvm_emit_fetch_double(bld_base,
1232 si_shader_ctx->constants[buf][idx],
1233 si_shader_ctx->constants[buf][idx + 1]);
1234 }
1235 }
1236
1237 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1238 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1239 LLVMValueRef index;
1240 index = get_indirect_index(si_shader_ctx, &reg->DimIndirect,
1241 reg->Dimension.Index);
1242 bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
1243 } else
1244 bufp = si_shader_ctx->const_buffers[buf];
1245
1246 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1247 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1248 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1249 addr = lp_build_add(&bld_base->uint_bld, addr,
1250 lp_build_const_int32(base->gallivm, idx * 4));
1251
1252 result = buffer_load_const(base->gallivm->builder, bufp,
1253 addr, bld_base->base.elem_type);
1254
1255 if (type != TGSI_TYPE_DOUBLE)
1256 result = bitcast(bld_base, type, result);
1257 else {
1258 LLVMValueRef addr2, result2;
1259 addr2 = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1260 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1261 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1262 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1263 lp_build_const_int32(base->gallivm, idx * 4));
1264
1265 result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_buffers[buf],
1266 addr2, bld_base->base.elem_type);
1267
1268 result = radeon_llvm_emit_fetch_double(bld_base,
1269 result, result2);
1270 }
1271 return result;
1272 }
1273
1274 /* Upper 16 bits must be zero. */
1275 static LLVMValueRef si_llvm_pack_two_int16(struct gallivm_state *gallivm,
1276 LLVMValueRef val[2])
1277 {
1278 return LLVMBuildOr(gallivm->builder, val[0],
1279 LLVMBuildShl(gallivm->builder, val[1],
1280 lp_build_const_int32(gallivm, 16),
1281 ""), "");
1282 }
1283
1284 /* Upper 16 bits are ignored and will be dropped. */
1285 static LLVMValueRef si_llvm_pack_two_int32_as_int16(struct gallivm_state *gallivm,
1286 LLVMValueRef val[2])
1287 {
1288 LLVMValueRef v[2] = {
1289 LLVMBuildAnd(gallivm->builder, val[0],
1290 lp_build_const_int32(gallivm, 0xffff), ""),
1291 val[1],
1292 };
1293 return si_llvm_pack_two_int16(gallivm, v);
1294 }
1295
1296 /* Initialize arguments for the shader export intrinsic */
1297 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1298 LLVMValueRef *values,
1299 unsigned target,
1300 LLVMValueRef *args)
1301 {
1302 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1303 struct lp_build_context *uint =
1304 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1305 struct lp_build_context *base = &bld_base->base;
1306 struct gallivm_state *gallivm = base->gallivm;
1307 LLVMBuilderRef builder = base->gallivm->builder;
1308 LLVMValueRef val[4];
1309 unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
1310 unsigned chan;
1311 bool is_int8;
1312
1313 /* Default is 0xf. Adjusted below depending on the format. */
1314 args[0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1315
1316 /* Specify whether the EXEC mask represents the valid mask */
1317 args[1] = uint->zero;
1318
1319 /* Specify whether this is the last export */
1320 args[2] = uint->zero;
1321
1322 /* Specify the target we are exporting */
1323 args[3] = lp_build_const_int32(base->gallivm, target);
1324
1325 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1326 const union si_shader_key *key = &si_shader_ctx->shader->key;
1327 unsigned col_formats = key->ps.spi_shader_col_format;
1328 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1329
1330 assert(cbuf >= 0 && cbuf < 8);
1331 spi_shader_col_format = (col_formats >> (cbuf * 4)) & 0xf;
1332 is_int8 = (key->ps.color_is_int8 >> cbuf) & 0x1;
1333 }
1334
1335 args[4] = uint->zero; /* COMPR flag */
1336 args[5] = base->undef;
1337 args[6] = base->undef;
1338 args[7] = base->undef;
1339 args[8] = base->undef;
1340
1341 switch (spi_shader_col_format) {
1342 case V_028714_SPI_SHADER_ZERO:
1343 args[0] = uint->zero; /* writemask */
1344 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
1345 break;
1346
1347 case V_028714_SPI_SHADER_32_R:
1348 args[0] = uint->one; /* writemask */
1349 args[5] = values[0];
1350 break;
1351
1352 case V_028714_SPI_SHADER_32_GR:
1353 args[0] = lp_build_const_int32(base->gallivm, 0x3); /* writemask */
1354 args[5] = values[0];
1355 args[6] = values[1];
1356 break;
1357
1358 case V_028714_SPI_SHADER_32_AR:
1359 args[0] = lp_build_const_int32(base->gallivm, 0x9); /* writemask */
1360 args[5] = values[0];
1361 args[8] = values[3];
1362 break;
1363
1364 case V_028714_SPI_SHADER_FP16_ABGR:
1365 args[4] = uint->one; /* COMPR flag */
1366
1367 for (chan = 0; chan < 2; chan++) {
1368 LLVMValueRef pack_args[2] = {
1369 values[2 * chan],
1370 values[2 * chan + 1]
1371 };
1372 LLVMValueRef packed;
1373
1374 packed = lp_build_intrinsic(base->gallivm->builder,
1375 "llvm.SI.packf16",
1376 uint->elem_type, pack_args, 2,
1377 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1378 args[chan + 5] =
1379 LLVMBuildBitCast(base->gallivm->builder,
1380 packed, base->elem_type, "");
1381 }
1382 break;
1383
1384 case V_028714_SPI_SHADER_UNORM16_ABGR:
1385 for (chan = 0; chan < 4; chan++) {
1386 val[chan] = radeon_llvm_saturate(bld_base, values[chan]);
1387 val[chan] = LLVMBuildFMul(builder, val[chan],
1388 lp_build_const_float(gallivm, 65535), "");
1389 val[chan] = LLVMBuildFAdd(builder, val[chan],
1390 lp_build_const_float(gallivm, 0.5), "");
1391 val[chan] = LLVMBuildFPToUI(builder, val[chan],
1392 uint->elem_type, "");
1393 }
1394
1395 args[4] = uint->one; /* COMPR flag */
1396 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1397 si_llvm_pack_two_int16(gallivm, val));
1398 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1399 si_llvm_pack_two_int16(gallivm, val+2));
1400 break;
1401
1402 case V_028714_SPI_SHADER_SNORM16_ABGR:
1403 for (chan = 0; chan < 4; chan++) {
1404 /* Clamp between [-1, 1]. */
1405 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MIN,
1406 values[chan],
1407 lp_build_const_float(gallivm, 1));
1408 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_MAX,
1409 val[chan],
1410 lp_build_const_float(gallivm, -1));
1411 /* Convert to a signed integer in [-32767, 32767]. */
1412 val[chan] = LLVMBuildFMul(builder, val[chan],
1413 lp_build_const_float(gallivm, 32767), "");
1414 /* If positive, add 0.5, else add -0.5. */
1415 val[chan] = LLVMBuildFAdd(builder, val[chan],
1416 LLVMBuildSelect(builder,
1417 LLVMBuildFCmp(builder, LLVMRealOGE,
1418 val[chan], base->zero, ""),
1419 lp_build_const_float(gallivm, 0.5),
1420 lp_build_const_float(gallivm, -0.5), ""), "");
1421 val[chan] = LLVMBuildFPToSI(builder, val[chan], uint->elem_type, "");
1422 }
1423
1424 args[4] = uint->one; /* COMPR flag */
1425 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1426 si_llvm_pack_two_int32_as_int16(gallivm, val));
1427 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1428 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1429 break;
1430
1431 case V_028714_SPI_SHADER_UINT16_ABGR: {
1432 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1433 255 : 65535);
1434 /* Clamp. */
1435 for (chan = 0; chan < 4; chan++) {
1436 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1437 val[chan] = lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_UMIN,
1438 val[chan], max);
1439 }
1440
1441 args[4] = uint->one; /* COMPR flag */
1442 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1443 si_llvm_pack_two_int16(gallivm, val));
1444 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1445 si_llvm_pack_two_int16(gallivm, val+2));
1446 break;
1447 }
1448
1449 case V_028714_SPI_SHADER_SINT16_ABGR: {
1450 LLVMValueRef max = lp_build_const_int32(gallivm, is_int8 ?
1451 127 : 32767);
1452 LLVMValueRef min = lp_build_const_int32(gallivm, is_int8 ?
1453 -128 : -32768);
1454 /* Clamp. */
1455 for (chan = 0; chan < 4; chan++) {
1456 val[chan] = bitcast(bld_base, TGSI_TYPE_UNSIGNED, values[chan]);
1457 val[chan] = lp_build_emit_llvm_binary(bld_base,
1458 TGSI_OPCODE_IMIN,
1459 val[chan], max);
1460 val[chan] = lp_build_emit_llvm_binary(bld_base,
1461 TGSI_OPCODE_IMAX,
1462 val[chan], min);
1463 }
1464
1465 args[4] = uint->one; /* COMPR flag */
1466 args[5] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1467 si_llvm_pack_two_int32_as_int16(gallivm, val));
1468 args[6] = bitcast(bld_base, TGSI_TYPE_FLOAT,
1469 si_llvm_pack_two_int32_as_int16(gallivm, val+2));
1470 break;
1471 }
1472
1473 case V_028714_SPI_SHADER_32_ABGR:
1474 memcpy(&args[5], values, sizeof(values[0]) * 4);
1475 break;
1476 }
1477 }
1478
1479 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1480 LLVMValueRef alpha)
1481 {
1482 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1483 struct gallivm_state *gallivm = bld_base->base.gallivm;
1484
1485 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
1486 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1487 SI_PARAM_ALPHA_REF);
1488
1489 LLVMValueRef alpha_pass =
1490 lp_build_cmp(&bld_base->base,
1491 si_shader_ctx->shader->key.ps.alpha_func,
1492 alpha, alpha_ref);
1493 LLVMValueRef arg =
1494 lp_build_select(&bld_base->base,
1495 alpha_pass,
1496 lp_build_const_float(gallivm, 1.0f),
1497 lp_build_const_float(gallivm, -1.0f));
1498
1499 lp_build_intrinsic(gallivm->builder,
1500 "llvm.AMDGPU.kill",
1501 LLVMVoidTypeInContext(gallivm->context),
1502 &arg, 1, 0);
1503 } else {
1504 lp_build_intrinsic(gallivm->builder,
1505 "llvm.AMDGPU.kilp",
1506 LLVMVoidTypeInContext(gallivm->context),
1507 NULL, 0, 0);
1508 }
1509 }
1510
1511 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1512 LLVMValueRef alpha)
1513 {
1514 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1515 struct gallivm_state *gallivm = bld_base->base.gallivm;
1516 LLVMValueRef coverage;
1517
1518 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1519 coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1520 SI_PARAM_SAMPLE_COVERAGE);
1521 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1522
1523 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1524 bld_base->int_bld.elem_type,
1525 &coverage, 1, LLVMReadNoneAttribute);
1526
1527 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1528 bld_base->base.elem_type, "");
1529
1530 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1531 lp_build_const_float(gallivm,
1532 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1533
1534 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1535 }
1536
1537 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
1538 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1539 {
1540 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1541 struct lp_build_context *base = &bld_base->base;
1542 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1543 unsigned reg_index;
1544 unsigned chan;
1545 unsigned const_chan;
1546 LLVMValueRef base_elt;
1547 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1548 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1549 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
1550
1551 for (reg_index = 0; reg_index < 2; reg_index ++) {
1552 LLVMValueRef *args = pos[2 + reg_index];
1553
1554 args[5] =
1555 args[6] =
1556 args[7] =
1557 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1558
1559 /* Compute dot products of position and user clip plane vectors */
1560 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1561 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1562 args[1] = lp_build_const_int32(base->gallivm,
1563 ((reg_index * 4 + chan) * 4 +
1564 const_chan) * 4);
1565 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1566 args[1], base->elem_type);
1567 args[5 + chan] =
1568 lp_build_add(base, args[5 + chan],
1569 lp_build_mul(base, base_elt,
1570 out_elts[const_chan]));
1571 }
1572 }
1573
1574 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1575 args[1] = uint->zero;
1576 args[2] = uint->zero;
1577 args[3] = lp_build_const_int32(base->gallivm,
1578 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1579 args[4] = uint->zero;
1580 }
1581 }
1582
1583 static void si_dump_streamout(struct pipe_stream_output_info *so)
1584 {
1585 unsigned i;
1586
1587 if (so->num_outputs)
1588 fprintf(stderr, "STREAMOUT\n");
1589
1590 for (i = 0; i < so->num_outputs; i++) {
1591 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1592 so->output[i].start_component;
1593 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1594 i, so->output[i].output_buffer,
1595 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1596 so->output[i].register_index,
1597 mask & 1 ? "x" : "",
1598 mask & 2 ? "y" : "",
1599 mask & 4 ? "z" : "",
1600 mask & 8 ? "w" : "");
1601 }
1602 }
1603
1604 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1605 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1606 * or v4i32 (num_channels=3,4). */
1607 static void build_tbuffer_store(struct si_shader_context *shader,
1608 LLVMValueRef rsrc,
1609 LLVMValueRef vdata,
1610 unsigned num_channels,
1611 LLVMValueRef vaddr,
1612 LLVMValueRef soffset,
1613 unsigned inst_offset,
1614 unsigned dfmt,
1615 unsigned nfmt,
1616 unsigned offen,
1617 unsigned idxen,
1618 unsigned glc,
1619 unsigned slc,
1620 unsigned tfe)
1621 {
1622 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1623 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1624 LLVMValueRef args[] = {
1625 rsrc,
1626 vdata,
1627 LLVMConstInt(i32, num_channels, 0),
1628 vaddr,
1629 soffset,
1630 LLVMConstInt(i32, inst_offset, 0),
1631 LLVMConstInt(i32, dfmt, 0),
1632 LLVMConstInt(i32, nfmt, 0),
1633 LLVMConstInt(i32, offen, 0),
1634 LLVMConstInt(i32, idxen, 0),
1635 LLVMConstInt(i32, glc, 0),
1636 LLVMConstInt(i32, slc, 0),
1637 LLVMConstInt(i32, tfe, 0)
1638 };
1639
1640 /* The instruction offset field has 12 bits */
1641 assert(offen || inst_offset < (1 << 12));
1642
1643 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1644 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1645 const char *types[] = {"i32", "v2i32", "v4i32"};
1646 char name[256];
1647 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1648
1649 lp_build_intrinsic(gallivm->builder, name,
1650 LLVMVoidTypeInContext(gallivm->context),
1651 args, Elements(args), 0);
1652 }
1653
1654 static void build_tbuffer_store_dwords(struct si_shader_context *shader,
1655 LLVMValueRef rsrc,
1656 LLVMValueRef vdata,
1657 unsigned num_channels,
1658 LLVMValueRef vaddr,
1659 LLVMValueRef soffset,
1660 unsigned inst_offset)
1661 {
1662 static unsigned dfmt[] = {
1663 V_008F0C_BUF_DATA_FORMAT_32,
1664 V_008F0C_BUF_DATA_FORMAT_32_32,
1665 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1666 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1667 };
1668 assert(num_channels >= 1 && num_channels <= 4);
1669
1670 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
1671 inst_offset, dfmt[num_channels-1],
1672 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1673 }
1674
1675 /* On SI, the vertex shader is responsible for writing streamout data
1676 * to buffers. */
1677 static void si_llvm_emit_streamout(struct si_shader_context *shader,
1678 struct si_shader_output_values *outputs,
1679 unsigned noutput)
1680 {
1681 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1682 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1683 LLVMBuilderRef builder = gallivm->builder;
1684 int i, j;
1685 struct lp_build_if_state if_ctx;
1686
1687 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1688
1689 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1690 LLVMValueRef so_vtx_count =
1691 unpack_param(shader, shader->param_streamout_config, 16, 7);
1692
1693 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", i32,
1694 NULL, 0, LLVMReadNoneAttribute);
1695
1696 /* can_emit = tid < so_vtx_count; */
1697 LLVMValueRef can_emit =
1698 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1699
1700 LLVMValueRef stream_id =
1701 unpack_param(shader, shader->param_streamout_config, 24, 2);
1702
1703 /* Emit the streamout code conditionally. This actually avoids
1704 * out-of-bounds buffer access. The hw tells us via the SGPR
1705 * (so_vtx_count) which threads are allowed to emit streamout data. */
1706 lp_build_if(&if_ctx, gallivm, can_emit);
1707 {
1708 /* The buffer offset is computed as follows:
1709 * ByteOffset = streamout_offset[buffer_id]*4 +
1710 * (streamout_write_index + thread_id)*stride[buffer_id] +
1711 * attrib_offset
1712 */
1713
1714 LLVMValueRef so_write_index =
1715 LLVMGetParam(shader->radeon_bld.main_fn,
1716 shader->param_streamout_write_index);
1717
1718 /* Compute (streamout_write_index + thread_id). */
1719 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1720
1721 /* Compute the write offset for each enabled buffer. */
1722 LLVMValueRef so_write_offset[4] = {};
1723 for (i = 0; i < 4; i++) {
1724 if (!so->stride[i])
1725 continue;
1726
1727 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1728 shader->param_streamout_offset[i]);
1729 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1730
1731 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1732 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1733 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1734 }
1735
1736 /* Write streamout data. */
1737 for (i = 0; i < so->num_outputs; i++) {
1738 unsigned buf_idx = so->output[i].output_buffer;
1739 unsigned reg = so->output[i].register_index;
1740 unsigned start = so->output[i].start_component;
1741 unsigned num_comps = so->output[i].num_components;
1742 unsigned stream = so->output[i].stream;
1743 LLVMValueRef out[4];
1744 struct lp_build_if_state if_ctx_stream;
1745
1746 assert(num_comps && num_comps <= 4);
1747 if (!num_comps || num_comps > 4)
1748 continue;
1749
1750 if (reg >= noutput)
1751 continue;
1752
1753 /* Load the output as int. */
1754 for (j = 0; j < num_comps; j++) {
1755 out[j] = LLVMBuildBitCast(builder,
1756 outputs[reg].values[start+j],
1757 i32, "");
1758 }
1759
1760 /* Pack the output. */
1761 LLVMValueRef vdata = NULL;
1762
1763 switch (num_comps) {
1764 case 1: /* as i32 */
1765 vdata = out[0];
1766 break;
1767 case 2: /* as v2i32 */
1768 case 3: /* as v4i32 (aligned to 4) */
1769 case 4: /* as v4i32 */
1770 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1771 for (j = 0; j < num_comps; j++) {
1772 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1773 LLVMConstInt(i32, j, 0), "");
1774 }
1775 break;
1776 }
1777
1778 LLVMValueRef can_emit_stream =
1779 LLVMBuildICmp(builder, LLVMIntEQ,
1780 stream_id,
1781 lp_build_const_int32(gallivm, stream), "");
1782
1783 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1784 build_tbuffer_store_dwords(shader, shader->so_buffers[buf_idx],
1785 vdata, num_comps,
1786 so_write_offset[buf_idx],
1787 LLVMConstInt(i32, 0, 0),
1788 so->output[i].dst_offset*4);
1789 lp_build_endif(&if_ctx_stream);
1790 }
1791 }
1792 lp_build_endif(&if_ctx);
1793 }
1794
1795
1796 /* Generate export instructions for hardware VS shader stage */
1797 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1798 struct si_shader_output_values *outputs,
1799 unsigned noutput)
1800 {
1801 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1802 struct si_shader * shader = si_shader_ctx->shader;
1803 struct lp_build_context * base = &bld_base->base;
1804 struct lp_build_context * uint =
1805 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1806 LLVMValueRef args[9];
1807 LLVMValueRef pos_args[4][9] = { { 0 } };
1808 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1809 unsigned semantic_name, semantic_index;
1810 unsigned target;
1811 unsigned param_count = 0;
1812 unsigned pos_idx;
1813 int i;
1814
1815 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1816 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1817 }
1818
1819 for (i = 0; i < noutput; i++) {
1820 semantic_name = outputs[i].name;
1821 semantic_index = outputs[i].sid;
1822
1823 handle_semantic:
1824 /* Select the correct target */
1825 switch(semantic_name) {
1826 case TGSI_SEMANTIC_PSIZE:
1827 psize_value = outputs[i].values[0];
1828 continue;
1829 case TGSI_SEMANTIC_EDGEFLAG:
1830 edgeflag_value = outputs[i].values[0];
1831 continue;
1832 case TGSI_SEMANTIC_LAYER:
1833 layer_value = outputs[i].values[0];
1834 semantic_name = TGSI_SEMANTIC_GENERIC;
1835 goto handle_semantic;
1836 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1837 viewport_index_value = outputs[i].values[0];
1838 semantic_name = TGSI_SEMANTIC_GENERIC;
1839 goto handle_semantic;
1840 case TGSI_SEMANTIC_POSITION:
1841 target = V_008DFC_SQ_EXP_POS;
1842 break;
1843 case TGSI_SEMANTIC_COLOR:
1844 case TGSI_SEMANTIC_BCOLOR:
1845 target = V_008DFC_SQ_EXP_PARAM + param_count;
1846 shader->vs_output_param_offset[i] = param_count;
1847 param_count++;
1848 break;
1849 case TGSI_SEMANTIC_CLIPDIST:
1850 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1851 break;
1852 case TGSI_SEMANTIC_CLIPVERTEX:
1853 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1854 continue;
1855 case TGSI_SEMANTIC_PRIMID:
1856 case TGSI_SEMANTIC_FOG:
1857 case TGSI_SEMANTIC_TEXCOORD:
1858 case TGSI_SEMANTIC_GENERIC:
1859 target = V_008DFC_SQ_EXP_PARAM + param_count;
1860 shader->vs_output_param_offset[i] = param_count;
1861 param_count++;
1862 break;
1863 default:
1864 target = 0;
1865 fprintf(stderr,
1866 "Warning: SI unhandled vs output type:%d\n",
1867 semantic_name);
1868 }
1869
1870 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1871
1872 if (target >= V_008DFC_SQ_EXP_POS &&
1873 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1874 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1875 args, sizeof(args));
1876 } else {
1877 lp_build_intrinsic(base->gallivm->builder,
1878 "llvm.SI.export",
1879 LLVMVoidTypeInContext(base->gallivm->context),
1880 args, 9, 0);
1881 }
1882
1883 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1884 semantic_name = TGSI_SEMANTIC_GENERIC;
1885 goto handle_semantic;
1886 }
1887 }
1888
1889 shader->nr_param_exports = param_count;
1890
1891 /* We need to add the position output manually if it's missing. */
1892 if (!pos_args[0][0]) {
1893 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1894 pos_args[0][1] = uint->zero; /* EXEC mask */
1895 pos_args[0][2] = uint->zero; /* last export? */
1896 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1897 pos_args[0][4] = uint->zero; /* COMPR flag */
1898 pos_args[0][5] = base->zero; /* X */
1899 pos_args[0][6] = base->zero; /* Y */
1900 pos_args[0][7] = base->zero; /* Z */
1901 pos_args[0][8] = base->one; /* W */
1902 }
1903
1904 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1905 if (shader->selector->info.writes_psize ||
1906 shader->selector->info.writes_edgeflag ||
1907 shader->selector->info.writes_viewport_index ||
1908 shader->selector->info.writes_layer) {
1909 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1910 shader->selector->info.writes_psize |
1911 (shader->selector->info.writes_edgeflag << 1) |
1912 (shader->selector->info.writes_layer << 2) |
1913 (shader->selector->info.writes_viewport_index << 3));
1914 pos_args[1][1] = uint->zero; /* EXEC mask */
1915 pos_args[1][2] = uint->zero; /* last export? */
1916 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1917 pos_args[1][4] = uint->zero; /* COMPR flag */
1918 pos_args[1][5] = base->zero; /* X */
1919 pos_args[1][6] = base->zero; /* Y */
1920 pos_args[1][7] = base->zero; /* Z */
1921 pos_args[1][8] = base->zero; /* W */
1922
1923 if (shader->selector->info.writes_psize)
1924 pos_args[1][5] = psize_value;
1925
1926 if (shader->selector->info.writes_edgeflag) {
1927 /* The output is a float, but the hw expects an integer
1928 * with the first bit containing the edge flag. */
1929 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1930 edgeflag_value,
1931 bld_base->uint_bld.elem_type, "");
1932 edgeflag_value = lp_build_min(&bld_base->int_bld,
1933 edgeflag_value,
1934 bld_base->int_bld.one);
1935
1936 /* The LLVM intrinsic expects a float. */
1937 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1938 edgeflag_value,
1939 base->elem_type, "");
1940 }
1941
1942 if (shader->selector->info.writes_layer)
1943 pos_args[1][7] = layer_value;
1944
1945 if (shader->selector->info.writes_viewport_index)
1946 pos_args[1][8] = viewport_index_value;
1947 }
1948
1949 for (i = 0; i < 4; i++)
1950 if (pos_args[i][0])
1951 shader->nr_pos_exports++;
1952
1953 pos_idx = 0;
1954 for (i = 0; i < 4; i++) {
1955 if (!pos_args[i][0])
1956 continue;
1957
1958 /* Specify the target we are exporting */
1959 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1960
1961 if (pos_idx == shader->nr_pos_exports)
1962 /* Specify that this is the last export */
1963 pos_args[i][2] = uint->one;
1964
1965 lp_build_intrinsic(base->gallivm->builder,
1966 "llvm.SI.export",
1967 LLVMVoidTypeInContext(base->gallivm->context),
1968 pos_args[i], 9, 0);
1969 }
1970 }
1971
1972 /* This only writes the tessellation factor levels. */
1973 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
1974 {
1975 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1976 struct gallivm_state *gallivm = bld_base->base.gallivm;
1977 struct si_shader *shader = si_shader_ctx->shader;
1978 unsigned tess_inner_index, tess_outer_index;
1979 LLVMValueRef lds_base, lds_inner, lds_outer;
1980 LLVMValueRef tf_base, rel_patch_id, byteoffset, buffer, rw_buffers;
1981 LLVMValueRef out[6], vec0, vec1, invocation_id;
1982 unsigned stride, outer_comps, inner_comps, i;
1983 struct lp_build_if_state if_ctx;
1984
1985 invocation_id = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1986
1987 /* Do this only for invocation 0, because the tess levels are per-patch,
1988 * not per-vertex.
1989 *
1990 * This can't jump, because invocation 0 executes this. It should
1991 * at least mask out the loads and stores for other invocations.
1992 */
1993 lp_build_if(&if_ctx, gallivm,
1994 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
1995 invocation_id, bld_base->uint_bld.zero, ""));
1996
1997 /* Determine the layout of one tess factor element in the buffer. */
1998 switch (shader->key.tcs.prim_mode) {
1999 case PIPE_PRIM_LINES:
2000 stride = 2; /* 2 dwords, 1 vec2 store */
2001 outer_comps = 2;
2002 inner_comps = 0;
2003 break;
2004 case PIPE_PRIM_TRIANGLES:
2005 stride = 4; /* 4 dwords, 1 vec4 store */
2006 outer_comps = 3;
2007 inner_comps = 1;
2008 break;
2009 case PIPE_PRIM_QUADS:
2010 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
2011 outer_comps = 4;
2012 inner_comps = 2;
2013 break;
2014 default:
2015 assert(0);
2016 return;
2017 }
2018
2019 /* Load tess_inner and tess_outer from LDS.
2020 * Any invocation can write them, so we can't get them from a temporary.
2021 */
2022 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
2023 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
2024
2025 lds_base = get_tcs_out_current_patch_data_offset(si_shader_ctx);
2026 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
2027 lp_build_const_int32(gallivm,
2028 tess_inner_index * 4), "");
2029 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
2030 lp_build_const_int32(gallivm,
2031 tess_outer_index * 4), "");
2032
2033 for (i = 0; i < outer_comps; i++)
2034 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
2035 for (i = 0; i < inner_comps; i++)
2036 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
2037
2038 /* Convert the outputs to vectors for stores. */
2039 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
2040 vec1 = NULL;
2041
2042 if (stride > 4)
2043 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
2044
2045 /* Get the buffer. */
2046 rw_buffers = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2047 SI_PARAM_RW_BUFFERS);
2048 buffer = build_indexed_load_const(si_shader_ctx, rw_buffers,
2049 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
2050
2051 /* Get the offset. */
2052 tf_base = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2053 SI_PARAM_TESS_FACTOR_OFFSET);
2054 rel_patch_id = get_rel_patch_id(si_shader_ctx);
2055 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
2056 lp_build_const_int32(gallivm, 4 * stride), "");
2057
2058 /* Store the outputs. */
2059 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec0,
2060 MIN2(stride, 4), byteoffset, tf_base, 0);
2061 if (vec1)
2062 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec1,
2063 stride - 4, byteoffset, tf_base, 16);
2064 lp_build_endif(&if_ctx);
2065 }
2066
2067 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context * bld_base)
2068 {
2069 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2070 struct si_shader *shader = si_shader_ctx->shader;
2071 struct tgsi_shader_info *info = &shader->selector->info;
2072 struct gallivm_state *gallivm = bld_base->base.gallivm;
2073 unsigned i, chan;
2074 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2075 si_shader_ctx->param_rel_auto_id);
2076 LLVMValueRef vertex_dw_stride =
2077 unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
2078 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
2079 vertex_dw_stride, "");
2080
2081 /* Write outputs to LDS. The next shader (TCS aka HS) will read
2082 * its inputs from it. */
2083 for (i = 0; i < info->num_outputs; i++) {
2084 LLVMValueRef *out_ptr = si_shader_ctx->radeon_bld.soa.outputs[i];
2085 unsigned name = info->output_semantic_name[i];
2086 unsigned index = info->output_semantic_index[i];
2087 int param = si_shader_io_get_unique_index(name, index);
2088 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
2089 lp_build_const_int32(gallivm, param * 4), "");
2090
2091 for (chan = 0; chan < 4; chan++) {
2092 lds_store(bld_base, chan, dw_addr,
2093 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
2094 }
2095 }
2096 }
2097
2098 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
2099 {
2100 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2101 struct gallivm_state *gallivm = bld_base->base.gallivm;
2102 struct si_shader *es = si_shader_ctx->shader;
2103 struct tgsi_shader_info *info = &es->selector->info;
2104 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2105 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2106 si_shader_ctx->param_es2gs_offset);
2107 unsigned chan;
2108 int i;
2109
2110 for (i = 0; i < info->num_outputs; i++) {
2111 LLVMValueRef *out_ptr =
2112 si_shader_ctx->radeon_bld.soa.outputs[i];
2113 int param_index;
2114
2115 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
2116 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
2117 continue;
2118
2119 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
2120 info->output_semantic_index[i]);
2121
2122 for (chan = 0; chan < 4; chan++) {
2123 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
2124 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
2125
2126 build_tbuffer_store(si_shader_ctx,
2127 si_shader_ctx->esgs_ring,
2128 out_val, 1,
2129 LLVMGetUndef(i32), soffset,
2130 (4 * param_index + chan) * 4,
2131 V_008F0C_BUF_DATA_FORMAT_32,
2132 V_008F0C_BUF_NUM_FORMAT_UINT,
2133 0, 0, 1, 1, 0);
2134 }
2135 }
2136 }
2137
2138 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
2139 {
2140 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2141 struct gallivm_state *gallivm = bld_base->base.gallivm;
2142 LLVMValueRef args[2];
2143
2144 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2145 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2146 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2147 LLVMVoidTypeInContext(gallivm->context), args, 2,
2148 LLVMNoUnwindAttribute);
2149 }
2150
2151 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
2152 {
2153 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2154 struct gallivm_state *gallivm = bld_base->base.gallivm;
2155 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
2156 struct si_shader_output_values *outputs = NULL;
2157 int i,j;
2158
2159 assert(!si_shader_ctx->is_gs_copy_shader);
2160
2161 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2162
2163 /* Vertex color clamping.
2164 *
2165 * This uses a state constant loaded in a user data SGPR and
2166 * an IF statement is added that clamps all colors if the constant
2167 * is true.
2168 */
2169 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX) {
2170 struct lp_build_if_state if_ctx;
2171 LLVMValueRef cond = NULL;
2172 LLVMValueRef addr, val;
2173
2174 for (i = 0; i < info->num_outputs; i++) {
2175 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2176 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2177 continue;
2178
2179 /* We've found a color. */
2180 if (!cond) {
2181 /* The state is in the first bit of the user SGPR. */
2182 cond = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2183 SI_PARAM_VS_STATE_BITS);
2184 cond = LLVMBuildTrunc(gallivm->builder, cond,
2185 LLVMInt1TypeInContext(gallivm->context), "");
2186 lp_build_if(&if_ctx, gallivm, cond);
2187 }
2188
2189 for (j = 0; j < 4; j++) {
2190 addr = si_shader_ctx->radeon_bld.soa.outputs[i][j];
2191 val = LLVMBuildLoad(gallivm->builder, addr, "");
2192 val = radeon_llvm_saturate(bld_base, val);
2193 LLVMBuildStore(gallivm->builder, val, addr);
2194 }
2195 }
2196
2197 if (cond)
2198 lp_build_endif(&if_ctx);
2199 }
2200
2201 for (i = 0; i < info->num_outputs; i++) {
2202 outputs[i].name = info->output_semantic_name[i];
2203 outputs[i].sid = info->output_semantic_index[i];
2204
2205 for (j = 0; j < 4; j++)
2206 outputs[i].values[j] =
2207 LLVMBuildLoad(gallivm->builder,
2208 si_shader_ctx->radeon_bld.soa.outputs[i][j],
2209 "");
2210 }
2211
2212 /* Export PrimitiveID when PS needs it. */
2213 if (si_vs_exports_prim_id(si_shader_ctx->shader)) {
2214 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2215 outputs[i].sid = 0;
2216 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2217 get_primitive_id(bld_base, 0));
2218 outputs[i].values[1] = bld_base->base.undef;
2219 outputs[i].values[2] = bld_base->base.undef;
2220 outputs[i].values[3] = bld_base->base.undef;
2221 i++;
2222 }
2223
2224 si_llvm_export_vs(bld_base, outputs, i);
2225 FREE(outputs);
2226 }
2227
2228 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2229 LLVMValueRef depth, LLVMValueRef stencil,
2230 LLVMValueRef samplemask)
2231 {
2232 struct si_screen *sscreen = si_shader_context(bld_base)->screen;
2233 struct lp_build_context *base = &bld_base->base;
2234 struct lp_build_context *uint = &bld_base->uint_bld;
2235 LLVMValueRef args[9];
2236 unsigned mask = 0;
2237
2238 assert(depth || stencil || samplemask);
2239
2240 args[1] = uint->one; /* whether the EXEC mask is valid */
2241 args[2] = uint->one; /* DONE bit */
2242
2243 /* Specify the target we are exporting */
2244 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2245
2246 args[4] = uint->zero; /* COMP flag */
2247 args[5] = base->undef; /* R, depth */
2248 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2249 args[7] = base->undef; /* B, sample mask */
2250 args[8] = base->undef; /* A, alpha to mask */
2251
2252 if (depth) {
2253 args[5] = depth;
2254 mask |= 0x1;
2255 }
2256
2257 if (stencil) {
2258 args[6] = stencil;
2259 mask |= 0x2;
2260 }
2261
2262 if (samplemask) {
2263 args[7] = samplemask;
2264 mask |= 0x4;
2265 }
2266
2267 /* SI (except OLAND) has a bug that it only looks
2268 * at the X writemask component. */
2269 if (sscreen->b.chip_class == SI &&
2270 sscreen->b.family != CHIP_OLAND)
2271 mask |= 0x1;
2272
2273 /* Specify which components to enable */
2274 args[0] = lp_build_const_int32(base->gallivm, mask);
2275
2276 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2277 LLVMVoidTypeInContext(base->gallivm->context),
2278 args, 9, 0);
2279 }
2280
2281 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2282 LLVMValueRef *color, unsigned index,
2283 bool is_last)
2284 {
2285 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2286 struct lp_build_context *base = &bld_base->base;
2287 LLVMValueRef args[9];
2288 int i;
2289
2290 /* Clamp color */
2291 if (si_shader_ctx->shader->key.ps.clamp_color)
2292 for (i = 0; i < 4; i++)
2293 color[i] = radeon_llvm_saturate(bld_base, color[i]);
2294
2295 /* Alpha to one */
2296 if (si_shader_ctx->shader->key.ps.alpha_to_one)
2297 color[3] = base->one;
2298
2299 /* Alpha test */
2300 if (index == 0 &&
2301 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
2302 si_alpha_test(bld_base, color[3]);
2303
2304 /* Line & polygon smoothing */
2305 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
2306 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3]);
2307
2308 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2309 if (index == 0 &&
2310 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
2311 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
2312 si_llvm_init_export_args(bld_base, color,
2313 V_008DFC_SQ_EXP_MRT + c, args);
2314 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2315 LLVMVoidTypeInContext(base->gallivm->context),
2316 args, 9, 0);
2317 }
2318 }
2319
2320 /* Export */
2321 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2322 args);
2323 if (is_last) {
2324 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2325 args[2] = bld_base->uint_bld.one; /* DONE bit */
2326 }
2327 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2328 LLVMVoidTypeInContext(base->gallivm->context),
2329 args, 9, 0);
2330 }
2331
2332 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2333 {
2334 struct lp_build_context *base = &bld_base->base;
2335 struct lp_build_context *uint = &bld_base->uint_bld;
2336 LLVMValueRef args[9];
2337
2338 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
2339 args[1] = uint->one; /* whether the EXEC mask is valid */
2340 args[2] = uint->one; /* DONE bit */
2341 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2342 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
2343 args[5] = uint->undef; /* R */
2344 args[6] = uint->undef; /* G */
2345 args[7] = uint->undef; /* B */
2346 args[8] = uint->undef; /* A */
2347
2348 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2349 LLVMVoidTypeInContext(base->gallivm->context),
2350 args, 9, 0);
2351 }
2352
2353 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
2354 {
2355 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
2356 struct si_shader * shader = si_shader_ctx->shader;
2357 struct lp_build_context * base = &bld_base->base;
2358 struct tgsi_shader_info *info = &shader->selector->info;
2359 LLVMBuilderRef builder = base->gallivm->builder;
2360 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2361 int last_color_export = -1;
2362 int i;
2363
2364 /* If there are no outputs, add a dummy export. */
2365 if (!info->num_outputs) {
2366 si_export_null(bld_base);
2367 return;
2368 }
2369
2370 /* Determine the last export. If MRTZ is present, it's always last.
2371 * Otherwise, find the last color export.
2372 */
2373 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask)
2374 for (i = 0; i < info->num_outputs; i++)
2375 if (info->output_semantic_name[i] == TGSI_SEMANTIC_COLOR)
2376 last_color_export = i;
2377
2378 for (i = 0; i < info->num_outputs; i++) {
2379 unsigned semantic_name = info->output_semantic_name[i];
2380 unsigned semantic_index = info->output_semantic_index[i];
2381 unsigned j;
2382 LLVMValueRef color[4] = {};
2383
2384 /* Select the correct target */
2385 switch (semantic_name) {
2386 case TGSI_SEMANTIC_POSITION:
2387 depth = LLVMBuildLoad(builder,
2388 si_shader_ctx->radeon_bld.soa.outputs[i][2], "");
2389 break;
2390 case TGSI_SEMANTIC_STENCIL:
2391 stencil = LLVMBuildLoad(builder,
2392 si_shader_ctx->radeon_bld.soa.outputs[i][1], "");
2393 break;
2394 case TGSI_SEMANTIC_SAMPLEMASK:
2395 samplemask = LLVMBuildLoad(builder,
2396 si_shader_ctx->radeon_bld.soa.outputs[i][0], "");
2397 break;
2398 case TGSI_SEMANTIC_COLOR:
2399 for (j = 0; j < 4; j++)
2400 color[j] = LLVMBuildLoad(builder,
2401 si_shader_ctx->radeon_bld.soa.outputs[i][j], "");
2402
2403 si_export_mrt_color(bld_base, color, semantic_index,
2404 last_color_export == i);
2405 break;
2406 default:
2407 fprintf(stderr,
2408 "Warning: SI unhandled fs output type:%d\n",
2409 semantic_name);
2410 }
2411 }
2412
2413 if (depth || stencil || samplemask)
2414 si_export_mrt_z(bld_base, depth, stencil, samplemask);
2415 }
2416
2417 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2418 struct lp_build_tgsi_context * bld_base,
2419 struct lp_build_emit_data * emit_data);
2420
2421 static bool tgsi_is_array_sampler(unsigned target)
2422 {
2423 return target == TGSI_TEXTURE_1D_ARRAY ||
2424 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2425 target == TGSI_TEXTURE_2D_ARRAY ||
2426 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2427 target == TGSI_TEXTURE_CUBE_ARRAY ||
2428 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2429 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2430 }
2431
2432 static void set_tex_fetch_args(struct gallivm_state *gallivm,
2433 struct lp_build_emit_data *emit_data,
2434 unsigned opcode, unsigned target,
2435 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
2436 LLVMValueRef *param, unsigned count,
2437 unsigned dmask)
2438 {
2439 unsigned num_args;
2440 unsigned is_rect = target == TGSI_TEXTURE_RECT;
2441 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2442
2443 /* Pad to power of two vector */
2444 while (count < util_next_power_of_two(count))
2445 param[count++] = LLVMGetUndef(i32);
2446
2447 /* Texture coordinates. */
2448 if (count > 1)
2449 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
2450 else
2451 emit_data->args[0] = param[0];
2452
2453 /* Resource. */
2454 emit_data->args[1] = res_ptr;
2455 num_args = 2;
2456
2457 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
2458 emit_data->dst_type = LLVMVectorType(i32, 4);
2459 else {
2460 emit_data->dst_type = LLVMVectorType(
2461 LLVMFloatTypeInContext(gallivm->context), 4);
2462
2463 emit_data->args[num_args++] = samp_ptr;
2464 }
2465
2466 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
2467 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
2468 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
2469 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
2470 tgsi_is_array_sampler(target)); /* da */
2471 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
2472 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
2473 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
2474 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
2475
2476 emit_data->arg_count = num_args;
2477 }
2478
2479 static const struct lp_build_tgsi_action tex_action;
2480
2481 static void tex_fetch_ptrs(
2482 struct lp_build_tgsi_context * bld_base,
2483 struct lp_build_emit_data * emit_data,
2484 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
2485 {
2486 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2487 struct gallivm_state *gallivm = bld_base->base.gallivm;
2488 const struct tgsi_full_instruction * inst = emit_data->inst;
2489 unsigned target = inst->Texture.Texture;
2490 unsigned sampler_src;
2491 unsigned sampler_index;
2492
2493 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
2494 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
2495
2496 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
2497 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
2498 LLVMValueRef ind_index;
2499
2500 ind_index = get_indirect_index(si_shader_ctx, &reg->Indirect, reg->Register.Index);
2501
2502 *res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
2503 *res_ptr = build_indexed_load_const(si_shader_ctx, *res_ptr, ind_index);
2504
2505 *samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
2506 *samp_ptr = build_indexed_load_const(si_shader_ctx, *samp_ptr, ind_index);
2507
2508 if (target == TGSI_TEXTURE_2D_MSAA ||
2509 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2510 ind_index = LLVMBuildAdd(gallivm->builder, ind_index,
2511 lp_build_const_int32(gallivm,
2512 SI_FMASK_TEX_OFFSET), "");
2513 *fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
2514 *fmask_ptr = build_indexed_load_const(si_shader_ctx, *fmask_ptr, ind_index);
2515 }
2516 } else {
2517 *res_ptr = si_shader_ctx->sampler_views[sampler_index];
2518 *samp_ptr = si_shader_ctx->sampler_states[sampler_index];
2519 *fmask_ptr = si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + sampler_index];
2520 }
2521 }
2522
2523 static void tex_fetch_args(
2524 struct lp_build_tgsi_context * bld_base,
2525 struct lp_build_emit_data * emit_data)
2526 {
2527 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2528 struct gallivm_state *gallivm = bld_base->base.gallivm;
2529 LLVMBuilderRef builder = gallivm->builder;
2530 const struct tgsi_full_instruction * inst = emit_data->inst;
2531 unsigned opcode = inst->Instruction.Opcode;
2532 unsigned target = inst->Texture.Texture;
2533 LLVMValueRef coords[5], derivs[6];
2534 LLVMValueRef address[16];
2535 int ref_pos;
2536 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
2537 unsigned count = 0;
2538 unsigned chan;
2539 unsigned num_deriv_channels = 0;
2540 bool has_offset = inst->Texture.NumOffsets > 0;
2541 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2542 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2543 unsigned dmask = 0xf;
2544
2545 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2546
2547 if (opcode == TGSI_OPCODE_TXQ) {
2548 if (target == TGSI_TEXTURE_BUFFER) {
2549 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2550
2551 /* Read the size from the buffer descriptor directly. */
2552 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2553 LLVMValueRef size = LLVMBuildExtractElement(builder, res,
2554 lp_build_const_int32(gallivm, 6), "");
2555
2556 if (si_shader_ctx->screen->b.chip_class >= VI) {
2557 /* On VI, the descriptor contains the size in bytes,
2558 * but TXQ must return the size in elements.
2559 * The stride is always non-zero for resources using TXQ.
2560 */
2561 LLVMValueRef stride =
2562 LLVMBuildExtractElement(builder, res,
2563 lp_build_const_int32(gallivm, 5), "");
2564 stride = LLVMBuildLShr(builder, stride,
2565 lp_build_const_int32(gallivm, 16), "");
2566 stride = LLVMBuildAnd(builder, stride,
2567 lp_build_const_int32(gallivm, 0x3FFF), "");
2568
2569 size = LLVMBuildUDiv(builder, size, stride, "");
2570 }
2571
2572 emit_data->args[0] = size;
2573 return;
2574 }
2575
2576 /* Textures - set the mip level. */
2577 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2578
2579 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2580 NULL, address, count, 0xf);
2581 return;
2582 }
2583
2584 if (target == TGSI_TEXTURE_BUFFER) {
2585 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
2586 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
2587 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
2588 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
2589
2590 /* Bitcast and truncate v8i32 to v16i8. */
2591 LLVMValueRef res = res_ptr;
2592 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
2593 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
2594 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
2595
2596 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
2597 emit_data->args[0] = res;
2598 emit_data->args[1] = bld_base->uint_bld.zero;
2599 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_X);
2600 emit_data->arg_count = 3;
2601 return;
2602 }
2603
2604 /* Fetch and project texture coordinates */
2605 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
2606 for (chan = 0; chan < 3; chan++ ) {
2607 coords[chan] = lp_build_emit_fetch(bld_base,
2608 emit_data->inst, 0,
2609 chan);
2610 if (opcode == TGSI_OPCODE_TXP)
2611 coords[chan] = lp_build_emit_llvm_binary(bld_base,
2612 TGSI_OPCODE_DIV,
2613 coords[chan],
2614 coords[3]);
2615 }
2616
2617 if (opcode == TGSI_OPCODE_TXP)
2618 coords[3] = bld_base->base.one;
2619
2620 /* Pack offsets. */
2621 if (has_offset && opcode != TGSI_OPCODE_TXF) {
2622 /* The offsets are six-bit signed integers packed like this:
2623 * X=[5:0], Y=[13:8], and Z=[21:16].
2624 */
2625 LLVMValueRef offset[3], pack;
2626
2627 assert(inst->Texture.NumOffsets == 1);
2628
2629 for (chan = 0; chan < 3; chan++) {
2630 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
2631 emit_data->inst, 0, chan);
2632 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
2633 lp_build_const_int32(gallivm, 0x3f), "");
2634 if (chan)
2635 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
2636 lp_build_const_int32(gallivm, chan*8), "");
2637 }
2638
2639 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
2640 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
2641 address[count++] = pack;
2642 }
2643
2644 /* Pack LOD bias value */
2645 if (opcode == TGSI_OPCODE_TXB)
2646 address[count++] = coords[3];
2647 if (opcode == TGSI_OPCODE_TXB2)
2648 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2649
2650 /* Pack depth comparison value */
2651 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
2652 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2653 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2654 } else {
2655 assert(ref_pos >= 0);
2656 address[count++] = coords[ref_pos];
2657 }
2658 }
2659
2660 /* Pack user derivatives */
2661 if (opcode == TGSI_OPCODE_TXD) {
2662 int param, num_src_deriv_channels;
2663
2664 switch (target) {
2665 case TGSI_TEXTURE_3D:
2666 num_src_deriv_channels = 3;
2667 num_deriv_channels = 3;
2668 break;
2669 case TGSI_TEXTURE_2D:
2670 case TGSI_TEXTURE_SHADOW2D:
2671 case TGSI_TEXTURE_RECT:
2672 case TGSI_TEXTURE_SHADOWRECT:
2673 case TGSI_TEXTURE_2D_ARRAY:
2674 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2675 num_src_deriv_channels = 2;
2676 num_deriv_channels = 2;
2677 break;
2678 case TGSI_TEXTURE_CUBE:
2679 case TGSI_TEXTURE_SHADOWCUBE:
2680 case TGSI_TEXTURE_CUBE_ARRAY:
2681 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
2682 /* Cube derivatives will be converted to 2D. */
2683 num_src_deriv_channels = 3;
2684 num_deriv_channels = 2;
2685 break;
2686 case TGSI_TEXTURE_1D:
2687 case TGSI_TEXTURE_SHADOW1D:
2688 case TGSI_TEXTURE_1D_ARRAY:
2689 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2690 num_src_deriv_channels = 1;
2691 num_deriv_channels = 1;
2692 break;
2693 default:
2694 unreachable("invalid target");
2695 }
2696
2697 for (param = 0; param < 2; param++)
2698 for (chan = 0; chan < num_src_deriv_channels; chan++)
2699 derivs[param * num_src_deriv_channels + chan] =
2700 lp_build_emit_fetch(bld_base, inst, param+1, chan);
2701 }
2702
2703 if (target == TGSI_TEXTURE_CUBE ||
2704 target == TGSI_TEXTURE_CUBE_ARRAY ||
2705 target == TGSI_TEXTURE_SHADOWCUBE ||
2706 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2707 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
2708
2709 if (opcode == TGSI_OPCODE_TXD)
2710 for (int i = 0; i < num_deriv_channels * 2; i++)
2711 address[count++] = derivs[i];
2712
2713 /* Pack texture coordinates */
2714 address[count++] = coords[0];
2715 if (num_coords > 1)
2716 address[count++] = coords[1];
2717 if (num_coords > 2)
2718 address[count++] = coords[2];
2719
2720 /* Pack LOD or sample index */
2721 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
2722 address[count++] = coords[3];
2723 else if (opcode == TGSI_OPCODE_TXL2)
2724 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
2725
2726 if (count > 16) {
2727 assert(!"Cannot handle more than 16 texture address parameters");
2728 count = 16;
2729 }
2730
2731 for (chan = 0; chan < count; chan++ ) {
2732 address[chan] = LLVMBuildBitCast(gallivm->builder,
2733 address[chan], i32, "");
2734 }
2735
2736 /* Adjust the sample index according to FMASK.
2737 *
2738 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2739 * which is the identity mapping. Each nibble says which physical sample
2740 * should be fetched to get that sample.
2741 *
2742 * For example, 0x11111100 means there are only 2 samples stored and
2743 * the second sample covers 3/4 of the pixel. When reading samples 0
2744 * and 1, return physical sample 0 (determined by the first two 0s
2745 * in FMASK), otherwise return physical sample 1.
2746 *
2747 * The sample index should be adjusted as follows:
2748 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2749 */
2750 if (target == TGSI_TEXTURE_2D_MSAA ||
2751 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2752 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2753 struct lp_build_emit_data txf_emit_data = *emit_data;
2754 LLVMValueRef txf_address[4];
2755 unsigned txf_count = count;
2756 struct tgsi_full_instruction inst = {};
2757
2758 memcpy(txf_address, address, sizeof(txf_address));
2759
2760 if (target == TGSI_TEXTURE_2D_MSAA) {
2761 txf_address[2] = bld_base->uint_bld.zero;
2762 }
2763 txf_address[3] = bld_base->uint_bld.zero;
2764
2765 /* Read FMASK using TXF. */
2766 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
2767 inst.Texture.Texture = target;
2768 txf_emit_data.inst = &inst;
2769 txf_emit_data.chan = 0;
2770 set_tex_fetch_args(gallivm, &txf_emit_data, TGSI_OPCODE_TXF,
2771 target, fmask_ptr, NULL,
2772 txf_address, txf_count, 0xf);
2773 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
2774
2775 /* Initialize some constants. */
2776 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
2777 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
2778
2779 /* Apply the formula. */
2780 LLVMValueRef fmask =
2781 LLVMBuildExtractElement(gallivm->builder,
2782 txf_emit_data.output[0],
2783 uint_bld->zero, "");
2784
2785 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
2786
2787 LLVMValueRef sample_index4 =
2788 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
2789
2790 LLVMValueRef shifted_fmask =
2791 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
2792
2793 LLVMValueRef final_sample =
2794 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
2795
2796 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2797 * resource descriptor is 0 (invalid),
2798 */
2799 LLVMValueRef fmask_desc =
2800 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
2801 LLVMVectorType(uint_bld->elem_type, 8), "");
2802
2803 LLVMValueRef fmask_word1 =
2804 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
2805 uint_bld->one, "");
2806
2807 LLVMValueRef word1_is_nonzero =
2808 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
2809 fmask_word1, uint_bld->zero, "");
2810
2811 /* Replace the MSAA sample index. */
2812 address[sample_chan] =
2813 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
2814 final_sample, address[sample_chan], "");
2815 }
2816
2817 if (opcode == TGSI_OPCODE_TXF) {
2818 /* add tex offsets */
2819 if (inst->Texture.NumOffsets) {
2820 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2821 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
2822 const struct tgsi_texture_offset * off = inst->TexOffsets;
2823
2824 assert(inst->Texture.NumOffsets == 1);
2825
2826 switch (target) {
2827 case TGSI_TEXTURE_3D:
2828 address[2] = lp_build_add(uint_bld, address[2],
2829 bld->immediates[off->Index][off->SwizzleZ]);
2830 /* fall through */
2831 case TGSI_TEXTURE_2D:
2832 case TGSI_TEXTURE_SHADOW2D:
2833 case TGSI_TEXTURE_RECT:
2834 case TGSI_TEXTURE_SHADOWRECT:
2835 case TGSI_TEXTURE_2D_ARRAY:
2836 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2837 address[1] =
2838 lp_build_add(uint_bld, address[1],
2839 bld->immediates[off->Index][off->SwizzleY]);
2840 /* fall through */
2841 case TGSI_TEXTURE_1D:
2842 case TGSI_TEXTURE_SHADOW1D:
2843 case TGSI_TEXTURE_1D_ARRAY:
2844 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2845 address[0] =
2846 lp_build_add(uint_bld, address[0],
2847 bld->immediates[off->Index][off->SwizzleX]);
2848 break;
2849 /* texture offsets do not apply to other texture targets */
2850 }
2851 }
2852 }
2853
2854 if (opcode == TGSI_OPCODE_TG4) {
2855 unsigned gather_comp = 0;
2856
2857 /* DMASK was repurposed for GATHER4. 4 components are always
2858 * returned and DMASK works like a swizzle - it selects
2859 * the component to fetch. The only valid DMASK values are
2860 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2861 * (red,red,red,red) etc.) The ISA document doesn't mention
2862 * this.
2863 */
2864
2865 /* Get the component index from src1.x for Gather4. */
2866 if (!tgsi_is_shadow_target(target)) {
2867 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
2868 LLVMValueRef comp_imm;
2869 struct tgsi_src_register src1 = inst->Src[1].Register;
2870
2871 assert(src1.File == TGSI_FILE_IMMEDIATE);
2872
2873 comp_imm = imms[src1.Index][src1.SwizzleX];
2874 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
2875 gather_comp = CLAMP(gather_comp, 0, 3);
2876 }
2877
2878 dmask = 1 << gather_comp;
2879 }
2880
2881 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2882 samp_ptr, address, count, dmask);
2883 }
2884
2885 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2886 struct lp_build_tgsi_context * bld_base,
2887 struct lp_build_emit_data * emit_data)
2888 {
2889 struct lp_build_context * base = &bld_base->base;
2890 unsigned opcode = emit_data->inst->Instruction.Opcode;
2891 unsigned target = emit_data->inst->Texture.Texture;
2892 char intr_name[127];
2893 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
2894 bool is_shadow = tgsi_is_shadow_target(target);
2895 char type[64];
2896 const char *name = "llvm.SI.image.sample";
2897 const char *infix = "";
2898
2899 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
2900 /* Just return the buffer size. */
2901 emit_data->output[emit_data->chan] = emit_data->args[0];
2902 return;
2903 }
2904
2905 if (target == TGSI_TEXTURE_BUFFER) {
2906 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2907 base->gallivm->builder,
2908 "llvm.SI.vs.load.input", emit_data->dst_type,
2909 emit_data->args, emit_data->arg_count,
2910 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2911 return;
2912 }
2913
2914 switch (opcode) {
2915 case TGSI_OPCODE_TXF:
2916 name = target == TGSI_TEXTURE_2D_MSAA ||
2917 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
2918 "llvm.SI.image.load" :
2919 "llvm.SI.image.load.mip";
2920 is_shadow = false;
2921 has_offset = false;
2922 break;
2923 case TGSI_OPCODE_TXQ:
2924 name = "llvm.SI.getresinfo";
2925 is_shadow = false;
2926 has_offset = false;
2927 break;
2928 case TGSI_OPCODE_LODQ:
2929 name = "llvm.SI.getlod";
2930 is_shadow = false;
2931 has_offset = false;
2932 break;
2933 case TGSI_OPCODE_TEX:
2934 case TGSI_OPCODE_TEX2:
2935 case TGSI_OPCODE_TXP:
2936 break;
2937 case TGSI_OPCODE_TXB:
2938 case TGSI_OPCODE_TXB2:
2939 infix = ".b";
2940 break;
2941 case TGSI_OPCODE_TXL:
2942 case TGSI_OPCODE_TXL2:
2943 infix = ".l";
2944 break;
2945 case TGSI_OPCODE_TXD:
2946 infix = ".d";
2947 break;
2948 case TGSI_OPCODE_TG4:
2949 name = "llvm.SI.gather4";
2950 break;
2951 default:
2952 assert(0);
2953 return;
2954 }
2955
2956 if (LLVMGetTypeKind(LLVMTypeOf(emit_data->args[0])) == LLVMVectorTypeKind)
2957 sprintf(type, ".v%ui32",
2958 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2959 else
2960 strcpy(type, ".i32");
2961
2962 /* Add the type and suffixes .c, .o if needed. */
2963 sprintf(intr_name, "%s%s%s%s%s",
2964 name, is_shadow ? ".c" : "", infix,
2965 has_offset ? ".o" : "", type);
2966
2967 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2968 base->gallivm->builder, intr_name, emit_data->dst_type,
2969 emit_data->args, emit_data->arg_count,
2970 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2971
2972 /* Divide the number of layers by 6 to get the number of cubes. */
2973 if (opcode == TGSI_OPCODE_TXQ &&
2974 (target == TGSI_TEXTURE_CUBE_ARRAY ||
2975 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
2976 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2977 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2978 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2979
2980 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2981 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2982 z = LLVMBuildSDiv(builder, z, six, "");
2983
2984 emit_data->output[emit_data->chan] =
2985 LLVMBuildInsertElement(builder, v4, z, two, "");
2986 }
2987 }
2988
2989 static void si_llvm_emit_txqs(
2990 const struct lp_build_tgsi_action * action,
2991 struct lp_build_tgsi_context * bld_base,
2992 struct lp_build_emit_data * emit_data)
2993 {
2994 struct gallivm_state *gallivm = bld_base->base.gallivm;
2995 LLVMBuilderRef builder = gallivm->builder;
2996 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2997 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2998 LLVMValueRef res, samples;
2999 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
3000
3001 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
3002
3003
3004 /* Read the samples from the descriptor directly. */
3005 res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
3006 samples = LLVMBuildExtractElement(
3007 builder, res,
3008 lp_build_const_int32(gallivm, 3), "");
3009 samples = LLVMBuildLShr(builder, samples,
3010 lp_build_const_int32(gallivm, 16), "");
3011 samples = LLVMBuildAnd(builder, samples,
3012 lp_build_const_int32(gallivm, 0xf), "");
3013 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
3014 samples, "");
3015
3016 emit_data->output[emit_data->chan] = samples;
3017 }
3018
3019 /*
3020 * SI implements derivatives using the local data store (LDS)
3021 * All writes to the LDS happen in all executing threads at
3022 * the same time. TID is the Thread ID for the current
3023 * thread and is a value between 0 and 63, representing
3024 * the thread's position in the wavefront.
3025 *
3026 * For the pixel shader threads are grouped into quads of four pixels.
3027 * The TIDs of the pixels of a quad are:
3028 *
3029 * +------+------+
3030 * |4n + 0|4n + 1|
3031 * +------+------+
3032 * |4n + 2|4n + 3|
3033 * +------+------+
3034 *
3035 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
3036 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
3037 * the current pixel's column, and masking with 0xfffffffe yields the TID
3038 * of the left pixel of the current pixel's row.
3039 *
3040 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
3041 * adding 2 yields the TID of the pixel below the top pixel.
3042 */
3043 /* masks for thread ID. */
3044 #define TID_MASK_TOP_LEFT 0xfffffffc
3045 #define TID_MASK_TOP 0xfffffffd
3046 #define TID_MASK_LEFT 0xfffffffe
3047
3048 static void si_llvm_emit_ddxy(
3049 const struct lp_build_tgsi_action * action,
3050 struct lp_build_tgsi_context * bld_base,
3051 struct lp_build_emit_data * emit_data)
3052 {
3053 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3054 struct gallivm_state *gallivm = bld_base->base.gallivm;
3055 struct lp_build_context * base = &bld_base->base;
3056 const struct tgsi_full_instruction *inst = emit_data->inst;
3057 unsigned opcode = inst->Instruction.Opcode;
3058 LLVMValueRef indices[2];
3059 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
3060 LLVMValueRef tl, trbl, result[4];
3061 LLVMTypeRef i32;
3062 unsigned swizzle[4];
3063 unsigned c;
3064 int idx;
3065 unsigned mask;
3066
3067 i32 = LLVMInt32TypeInContext(gallivm->context);
3068
3069 indices[0] = bld_base->uint_bld.zero;
3070 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
3071 NULL, 0, LLVMReadNoneAttribute);
3072 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3073 indices, 2, "");
3074
3075 if (opcode == TGSI_OPCODE_DDX_FINE)
3076 mask = TID_MASK_LEFT;
3077 else if (opcode == TGSI_OPCODE_DDY_FINE)
3078 mask = TID_MASK_TOP;
3079 else
3080 mask = TID_MASK_TOP_LEFT;
3081
3082 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
3083 lp_build_const_int32(gallivm, mask), "");
3084 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3085 indices, 2, "");
3086
3087 /* for DDX we want to next X pixel, DDY next Y pixel. */
3088 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
3089 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
3090 lp_build_const_int32(gallivm, idx), "");
3091 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3092 indices, 2, "");
3093
3094 for (c = 0; c < 4; ++c) {
3095 unsigned i;
3096
3097 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
3098 for (i = 0; i < c; ++i) {
3099 if (swizzle[i] == swizzle[c]) {
3100 result[c] = result[i];
3101 break;
3102 }
3103 }
3104 if (i != c)
3105 continue;
3106
3107 LLVMBuildStore(gallivm->builder,
3108 LLVMBuildBitCast(gallivm->builder,
3109 lp_build_emit_fetch(bld_base, inst, 0, c),
3110 i32, ""),
3111 store_ptr);
3112
3113 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
3114 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3115
3116 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
3117 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
3118
3119 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
3120 }
3121
3122 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
3123 }
3124
3125 /*
3126 * this takes an I,J coordinate pair,
3127 * and works out the X and Y derivatives.
3128 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
3129 */
3130 static LLVMValueRef si_llvm_emit_ddxy_interp(
3131 struct lp_build_tgsi_context *bld_base,
3132 LLVMValueRef interp_ij)
3133 {
3134 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3135 struct gallivm_state *gallivm = bld_base->base.gallivm;
3136 struct lp_build_context *base = &bld_base->base;
3137 LLVMValueRef indices[2];
3138 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
3139 LLVMValueRef tl, tr, bl, result[4];
3140 LLVMTypeRef i32;
3141 unsigned c;
3142
3143 i32 = LLVMInt32TypeInContext(gallivm->context);
3144
3145 indices[0] = bld_base->uint_bld.zero;
3146 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
3147 NULL, 0, LLVMReadNoneAttribute);
3148 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3149 indices, 2, "");
3150
3151 temp = LLVMBuildAnd(gallivm->builder, indices[1],
3152 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
3153
3154 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
3155 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
3156
3157 indices[1] = temp;
3158 load_ptr_x = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3159 indices, 2, "");
3160
3161 indices[1] = temp2;
3162 load_ptr_y = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3163 indices, 2, "");
3164
3165 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
3166 lp_build_const_int32(gallivm, 1), "");
3167 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3168 indices, 2, "");
3169
3170 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
3171 lp_build_const_int32(gallivm, 2), "");
3172 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3173 indices, 2, "");
3174
3175 for (c = 0; c < 2; ++c) {
3176 LLVMValueRef store_val;
3177 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
3178
3179 store_val = LLVMBuildExtractElement(gallivm->builder,
3180 interp_ij, c_ll, "");
3181 LLVMBuildStore(gallivm->builder,
3182 store_val,
3183 store_ptr);
3184
3185 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
3186 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3187
3188 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
3189 tr = LLVMBuildBitCast(gallivm->builder, tr, base->elem_type, "");
3190
3191 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
3192
3193 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
3194 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3195
3196 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
3197 bl = LLVMBuildBitCast(gallivm->builder, bl, base->elem_type, "");
3198
3199 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
3200 }
3201
3202 return lp_build_gather_values(gallivm, result, 4);
3203 }
3204
3205 static void interp_fetch_args(
3206 struct lp_build_tgsi_context *bld_base,
3207 struct lp_build_emit_data *emit_data)
3208 {
3209 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3210 struct gallivm_state *gallivm = bld_base->base.gallivm;
3211 const struct tgsi_full_instruction *inst = emit_data->inst;
3212
3213 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3214 /* offset is in second src, first two channels */
3215 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3216 emit_data->inst, 1,
3217 TGSI_CHAN_X);
3218 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3219 emit_data->inst, 1,
3220 TGSI_CHAN_Y);
3221 emit_data->arg_count = 2;
3222 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3223 LLVMValueRef sample_position;
3224 LLVMValueRef sample_id;
3225 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
3226
3227 /* fetch sample ID, then fetch its sample position,
3228 * and place into first two channels.
3229 */
3230 sample_id = lp_build_emit_fetch(bld_base,
3231 emit_data->inst, 1, TGSI_CHAN_X);
3232 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3233 LLVMInt32TypeInContext(gallivm->context),
3234 "");
3235 sample_position = load_sample_position(&si_shader_ctx->radeon_bld, sample_id);
3236
3237 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3238 sample_position,
3239 lp_build_const_int32(gallivm, 0), "");
3240
3241 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3242 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3243 sample_position,
3244 lp_build_const_int32(gallivm, 1), "");
3245 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3246 emit_data->arg_count = 2;
3247 }
3248 }
3249
3250 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3251 struct lp_build_tgsi_context *bld_base,
3252 struct lp_build_emit_data *emit_data)
3253 {
3254 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3255 struct si_shader *shader = si_shader_ctx->shader;
3256 struct gallivm_state *gallivm = bld_base->base.gallivm;
3257 LLVMValueRef interp_param;
3258 const struct tgsi_full_instruction *inst = emit_data->inst;
3259 const char *intr_name;
3260 int input_index;
3261 int chan;
3262 int i;
3263 LLVMValueRef attr_number;
3264 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
3265 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
3266 int interp_param_idx;
3267 unsigned location;
3268
3269 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
3270 input_index = inst->Src[0].Register.Index;
3271
3272 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3273 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3274 location = TGSI_INTERPOLATE_LOC_CENTER;
3275 else
3276 location = TGSI_INTERPOLATE_LOC_CENTROID;
3277
3278 interp_param_idx = lookup_interp_param_index(shader->ps_input_interpolate[input_index],
3279 location);
3280 if (interp_param_idx == -1)
3281 return;
3282 else if (interp_param_idx)
3283 interp_param = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, interp_param_idx);
3284 else
3285 interp_param = NULL;
3286
3287 attr_number = lp_build_const_int32(gallivm, input_index);
3288
3289 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3290 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3291 LLVMValueRef ij_out[2];
3292 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3293
3294 /*
3295 * take the I then J parameters, and the DDX/Y for it, and
3296 * calculate the IJ inputs for the interpolator.
3297 * temp1 = ddx * offset/sample.x + I;
3298 * interp_param.I = ddy * offset/sample.y + temp1;
3299 * temp1 = ddx * offset/sample.x + J;
3300 * interp_param.J = ddy * offset/sample.y + temp1;
3301 */
3302 for (i = 0; i < 2; i++) {
3303 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
3304 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
3305 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3306 ddxy_out, ix_ll, "");
3307 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3308 ddxy_out, iy_ll, "");
3309 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3310 interp_param, ix_ll, "");
3311 LLVMValueRef temp1, temp2;
3312
3313 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3314 LLVMFloatTypeInContext(gallivm->context), "");
3315
3316 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3317
3318 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3319
3320 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3321
3322 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3323
3324 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
3325 temp2,
3326 LLVMIntTypeInContext(gallivm->context, 32), "");
3327 }
3328 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
3329 }
3330
3331 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3332 for (chan = 0; chan < 2; chan++) {
3333 LLVMValueRef args[4];
3334 LLVMValueRef llvm_chan;
3335 unsigned schan;
3336
3337 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3338 llvm_chan = lp_build_const_int32(gallivm, schan);
3339
3340 args[0] = llvm_chan;
3341 args[1] = attr_number;
3342 args[2] = params;
3343 args[3] = interp_param;
3344
3345 emit_data->output[chan] =
3346 lp_build_intrinsic(gallivm->builder, intr_name,
3347 input_type, args, args[3] ? 4 : 3,
3348 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3349 }
3350 }
3351
3352 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3353 struct lp_build_emit_data *emit_data)
3354 {
3355 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3356 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3357 unsigned stream;
3358
3359 assert(src0.File == TGSI_FILE_IMMEDIATE);
3360
3361 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
3362 return stream;
3363 }
3364
3365 /* Emit one vertex from the geometry shader */
3366 static void si_llvm_emit_vertex(
3367 const struct lp_build_tgsi_action *action,
3368 struct lp_build_tgsi_context *bld_base,
3369 struct lp_build_emit_data *emit_data)
3370 {
3371 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3372 struct lp_build_context *uint = &bld_base->uint_bld;
3373 struct si_shader *shader = si_shader_ctx->shader;
3374 struct tgsi_shader_info *info = &shader->selector->info;
3375 struct gallivm_state *gallivm = bld_base->base.gallivm;
3376 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
3377 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3378 SI_PARAM_GS2VS_OFFSET);
3379 LLVMValueRef gs_next_vertex;
3380 LLVMValueRef can_emit, kill;
3381 LLVMValueRef args[2];
3382 unsigned chan;
3383 int i;
3384 unsigned stream;
3385
3386 stream = si_llvm_get_stream(bld_base, emit_data);
3387
3388 /* Write vertex attribute values to GSVS ring */
3389 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3390 si_shader_ctx->gs_next_vertex[stream],
3391 "");
3392
3393 /* If this thread has already emitted the declared maximum number of
3394 * vertices, kill it: excessive vertex emissions are not supposed to
3395 * have any effect, and GS threads have no externally observable
3396 * effects other than emitting vertices.
3397 */
3398 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
3399 lp_build_const_int32(gallivm,
3400 shader->selector->gs_max_out_vertices), "");
3401 kill = lp_build_select(&bld_base->base, can_emit,
3402 lp_build_const_float(gallivm, 1.0f),
3403 lp_build_const_float(gallivm, -1.0f));
3404
3405 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
3406 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
3407
3408 for (i = 0; i < info->num_outputs; i++) {
3409 LLVMValueRef *out_ptr =
3410 si_shader_ctx->radeon_bld.soa.outputs[i];
3411
3412 for (chan = 0; chan < 4; chan++) {
3413 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3414 LLVMValueRef voffset =
3415 lp_build_const_int32(gallivm, (i * 4 + chan) *
3416 shader->selector->gs_max_out_vertices);
3417
3418 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3419 voffset = lp_build_mul_imm(uint, voffset, 4);
3420
3421 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
3422
3423 build_tbuffer_store(si_shader_ctx,
3424 si_shader_ctx->gsvs_ring[stream],
3425 out_val, 1,
3426 voffset, soffset, 0,
3427 V_008F0C_BUF_DATA_FORMAT_32,
3428 V_008F0C_BUF_NUM_FORMAT_UINT,
3429 1, 0, 1, 1, 0);
3430 }
3431 }
3432 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
3433 lp_build_const_int32(gallivm, 1));
3434
3435 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex[stream]);
3436
3437 /* Signal vertex emission */
3438 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
3439 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3440 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3441 LLVMVoidTypeInContext(gallivm->context), args, 2,
3442 LLVMNoUnwindAttribute);
3443 }
3444
3445 /* Cut one primitive from the geometry shader */
3446 static void si_llvm_emit_primitive(
3447 const struct lp_build_tgsi_action *action,
3448 struct lp_build_tgsi_context *bld_base,
3449 struct lp_build_emit_data *emit_data)
3450 {
3451 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3452 struct gallivm_state *gallivm = bld_base->base.gallivm;
3453 LLVMValueRef args[2];
3454 unsigned stream;
3455
3456 /* Signal primitive cut */
3457 stream = si_llvm_get_stream(bld_base, emit_data);
3458 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
3459 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3460 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3461 LLVMVoidTypeInContext(gallivm->context), args, 2,
3462 LLVMNoUnwindAttribute);
3463 }
3464
3465 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
3466 struct lp_build_tgsi_context *bld_base,
3467 struct lp_build_emit_data *emit_data)
3468 {
3469 struct gallivm_state *gallivm = bld_base->base.gallivm;
3470
3471 lp_build_intrinsic(gallivm->builder,
3472 HAVE_LLVM >= 0x0309 ? "llvm.amdgcn.s.barrier"
3473 : "llvm.AMDGPU.barrier.local",
3474 LLVMVoidTypeInContext(gallivm->context), NULL, 0,
3475 LLVMNoUnwindAttribute);
3476 }
3477
3478 static const struct lp_build_tgsi_action tex_action = {
3479 .fetch_args = tex_fetch_args,
3480 .emit = build_tex_intrinsic,
3481 };
3482
3483 static const struct lp_build_tgsi_action interp_action = {
3484 .fetch_args = interp_fetch_args,
3485 .emit = build_interp_intrinsic,
3486 };
3487
3488 static void create_meta_data(struct si_shader_context *si_shader_ctx)
3489 {
3490 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3491 LLVMValueRef args[3];
3492
3493 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
3494 args[1] = 0;
3495 args[2] = lp_build_const_int32(gallivm, 1);
3496
3497 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
3498 }
3499
3500 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3501 {
3502 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3503 CONST_ADDR_SPACE);
3504 }
3505
3506 static void declare_streamout_params(struct si_shader_context *si_shader_ctx,
3507 struct pipe_stream_output_info *so,
3508 LLVMTypeRef *params, LLVMTypeRef i32,
3509 unsigned *num_params)
3510 {
3511 int i;
3512
3513 /* Streamout SGPRs. */
3514 if (so->num_outputs) {
3515 params[si_shader_ctx->param_streamout_config = (*num_params)++] = i32;
3516 params[si_shader_ctx->param_streamout_write_index = (*num_params)++] = i32;
3517 }
3518 /* A streamout buffer offset is loaded if the stride is non-zero. */
3519 for (i = 0; i < 4; i++) {
3520 if (!so->stride[i])
3521 continue;
3522
3523 params[si_shader_ctx->param_streamout_offset[i] = (*num_params)++] = i32;
3524 }
3525 }
3526
3527 static void create_function(struct si_shader_context *si_shader_ctx)
3528 {
3529 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3530 struct gallivm_state *gallivm = bld_base->base.gallivm;
3531 struct si_shader *shader = si_shader_ctx->shader;
3532 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
3533 unsigned i, last_array_pointer, last_sgpr, num_params;
3534
3535 i8 = LLVMInt8TypeInContext(gallivm->context);
3536 i32 = LLVMInt32TypeInContext(gallivm->context);
3537 f32 = LLVMFloatTypeInContext(gallivm->context);
3538 v2i32 = LLVMVectorType(i32, 2);
3539 v3i32 = LLVMVectorType(i32, 3);
3540 v4i32 = LLVMVectorType(i32, 4);
3541 v8i32 = LLVMVectorType(i32, 8);
3542 v16i8 = LLVMVectorType(i8, 16);
3543
3544 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
3545 params[SI_PARAM_CONST_BUFFERS] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
3546 params[SI_PARAM_SAMPLER_STATES] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
3547 params[SI_PARAM_SAMPLER_VIEWS] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
3548 last_array_pointer = SI_PARAM_SAMPLER_VIEWS;
3549
3550 switch (si_shader_ctx->type) {
3551 case TGSI_PROCESSOR_VERTEX:
3552 params[SI_PARAM_VERTEX_BUFFERS] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
3553 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
3554 params[SI_PARAM_BASE_VERTEX] = i32;
3555 params[SI_PARAM_START_INSTANCE] = i32;
3556 num_params = SI_PARAM_START_INSTANCE+1;
3557
3558 if (shader->key.vs.as_es) {
3559 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3560 } else if (shader->key.vs.as_ls) {
3561 params[SI_PARAM_LS_OUT_LAYOUT] = i32;
3562 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
3563 } else {
3564 if (si_shader_ctx->is_gs_copy_shader) {
3565 last_array_pointer = SI_PARAM_CONST_BUFFERS;
3566 num_params = SI_PARAM_CONST_BUFFERS+1;
3567 } else {
3568 params[SI_PARAM_VS_STATE_BITS] = i32;
3569 num_params = SI_PARAM_VS_STATE_BITS+1;
3570 }
3571
3572 /* The locations of the other parameters are assigned dynamically. */
3573 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3574 params, i32, &num_params);
3575 }
3576
3577 last_sgpr = num_params-1;
3578
3579 /* VGPRs */
3580 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
3581 params[si_shader_ctx->param_rel_auto_id = num_params++] = i32;
3582 params[si_shader_ctx->param_vs_prim_id = num_params++] = i32;
3583 params[si_shader_ctx->param_instance_id = num_params++] = i32;
3584 break;
3585
3586 case TGSI_PROCESSOR_TESS_CTRL:
3587 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3588 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3589 params[SI_PARAM_TCS_IN_LAYOUT] = i32;
3590 params[SI_PARAM_TESS_FACTOR_OFFSET] = i32;
3591 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
3592
3593 /* VGPRs */
3594 params[SI_PARAM_PATCH_ID] = i32;
3595 params[SI_PARAM_REL_IDS] = i32;
3596 num_params = SI_PARAM_REL_IDS+1;
3597 break;
3598
3599 case TGSI_PROCESSOR_TESS_EVAL:
3600 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3601 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3602 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
3603
3604 if (shader->key.tes.as_es) {
3605 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3606 } else {
3607 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3608 params, i32, &num_params);
3609 }
3610 last_sgpr = num_params - 1;
3611
3612 /* VGPRs */
3613 params[si_shader_ctx->param_tes_u = num_params++] = f32;
3614 params[si_shader_ctx->param_tes_v = num_params++] = f32;
3615 params[si_shader_ctx->param_tes_rel_patch_id = num_params++] = i32;
3616 params[si_shader_ctx->param_tes_patch_id = num_params++] = i32;
3617 break;
3618
3619 case TGSI_PROCESSOR_GEOMETRY:
3620 params[SI_PARAM_GS2VS_OFFSET] = i32;
3621 params[SI_PARAM_GS_WAVE_ID] = i32;
3622 last_sgpr = SI_PARAM_GS_WAVE_ID;
3623
3624 /* VGPRs */
3625 params[SI_PARAM_VTX0_OFFSET] = i32;
3626 params[SI_PARAM_VTX1_OFFSET] = i32;
3627 params[SI_PARAM_PRIMITIVE_ID] = i32;
3628 params[SI_PARAM_VTX2_OFFSET] = i32;
3629 params[SI_PARAM_VTX3_OFFSET] = i32;
3630 params[SI_PARAM_VTX4_OFFSET] = i32;
3631 params[SI_PARAM_VTX5_OFFSET] = i32;
3632 params[SI_PARAM_GS_INSTANCE_ID] = i32;
3633 num_params = SI_PARAM_GS_INSTANCE_ID+1;
3634 break;
3635
3636 case TGSI_PROCESSOR_FRAGMENT:
3637 params[SI_PARAM_ALPHA_REF] = f32;
3638 params[SI_PARAM_PS_STATE_BITS] = i32;
3639 params[SI_PARAM_PRIM_MASK] = i32;
3640 last_sgpr = SI_PARAM_PRIM_MASK;
3641 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
3642 params[SI_PARAM_PERSP_CENTER] = v2i32;
3643 params[SI_PARAM_PERSP_CENTROID] = v2i32;
3644 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
3645 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
3646 params[SI_PARAM_LINEAR_CENTER] = v2i32;
3647 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
3648 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
3649 params[SI_PARAM_POS_X_FLOAT] = f32;
3650 params[SI_PARAM_POS_Y_FLOAT] = f32;
3651 params[SI_PARAM_POS_Z_FLOAT] = f32;
3652 params[SI_PARAM_POS_W_FLOAT] = f32;
3653 params[SI_PARAM_FRONT_FACE] = i32;
3654 params[SI_PARAM_ANCILLARY] = i32;
3655 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
3656 params[SI_PARAM_POS_FIXED_PT] = f32;
3657 num_params = SI_PARAM_POS_FIXED_PT+1;
3658 break;
3659
3660 default:
3661 assert(0 && "unimplemented shader");
3662 return;
3663 }
3664
3665 assert(num_params <= Elements(params));
3666 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
3667 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
3668
3669 if (shader->dx10_clamp_mode)
3670 LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
3671 "enable-no-nans-fp-math", "true");
3672
3673 for (i = 0; i <= last_sgpr; ++i) {
3674 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
3675
3676 /* We tell llvm that array inputs are passed by value to allow Sinking pass
3677 * to move load. Inputs are constant so this is fine. */
3678 if (i <= last_array_pointer)
3679 LLVMAddAttribute(P, LLVMByValAttribute);
3680 else
3681 LLVMAddAttribute(P, LLVMInRegAttribute);
3682 }
3683
3684 if (bld_base->info &&
3685 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
3686 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
3687 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
3688 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
3689 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
3690 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
3691 si_shader_ctx->lds =
3692 LLVMAddGlobalInAddressSpace(gallivm->module,
3693 LLVMArrayType(i32, 64),
3694 "ddxy_lds",
3695 LOCAL_ADDR_SPACE);
3696
3697 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
3698 si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
3699 si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
3700 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
3701 unsigned vertex_data_dw_size = 32*32*4;
3702 unsigned patch_data_dw_size = 32*4;
3703 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
3704 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
3705 unsigned lds_dwords = patch_dw_size;
3706
3707 /* The actual size is computed outside of the shader to reduce
3708 * the number of shader variants. */
3709 si_shader_ctx->lds =
3710 LLVMAddGlobalInAddressSpace(gallivm->module,
3711 LLVMArrayType(i32, lds_dwords),
3712 "tess_lds",
3713 LOCAL_ADDR_SPACE);
3714 }
3715 }
3716
3717 static void preload_constants(struct si_shader_context *si_shader_ctx)
3718 {
3719 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3720 struct gallivm_state * gallivm = bld_base->base.gallivm;
3721 const struct tgsi_shader_info * info = bld_base->info;
3722 unsigned buf;
3723 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
3724
3725 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
3726 unsigned i, num_const = info->const_file_max[buf] + 1;
3727
3728 if (num_const == 0)
3729 continue;
3730
3731 /* Allocate space for the constant values */
3732 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
3733
3734 /* Load the resource descriptor */
3735 si_shader_ctx->const_buffers[buf] =
3736 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
3737
3738 /* Load the constants, we rely on the code sinking to do the rest */
3739 for (i = 0; i < num_const * 4; ++i) {
3740 si_shader_ctx->constants[buf][i] =
3741 buffer_load_const(gallivm->builder,
3742 si_shader_ctx->const_buffers[buf],
3743 lp_build_const_int32(gallivm, i * 4),
3744 bld_base->base.elem_type);
3745 }
3746 }
3747 }
3748
3749 static void preload_samplers(struct si_shader_context *si_shader_ctx)
3750 {
3751 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3752 struct gallivm_state * gallivm = bld_base->base.gallivm;
3753 const struct tgsi_shader_info * info = bld_base->info;
3754
3755 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
3756
3757 LLVMValueRef res_ptr, samp_ptr;
3758 LLVMValueRef offset;
3759
3760 if (num_samplers == 0)
3761 return;
3762
3763 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
3764 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
3765
3766 /* Load the resources and samplers, we rely on the code sinking to do the rest */
3767 for (i = 0; i < num_samplers; ++i) {
3768 /* Resource */
3769 offset = lp_build_const_int32(gallivm, i);
3770 si_shader_ctx->sampler_views[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3771
3772 /* Sampler */
3773 offset = lp_build_const_int32(gallivm, i);
3774 si_shader_ctx->sampler_states[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
3775
3776 /* FMASK resource */
3777 if (info->is_msaa_sampler[i]) {
3778 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
3779 si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + i] =
3780 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3781 }
3782 }
3783 }
3784
3785 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
3786 {
3787 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3788 struct gallivm_state * gallivm = bld_base->base.gallivm;
3789 unsigned i;
3790
3791 /* Streamout can only be used if the shader is compiled as VS. */
3792 if (!si_shader_ctx->shader->selector->so.num_outputs ||
3793 (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3794 (si_shader_ctx->shader->key.vs.as_es ||
3795 si_shader_ctx->shader->key.vs.as_ls)) ||
3796 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3797 si_shader_ctx->shader->key.tes.as_es))
3798 return;
3799
3800 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3801 SI_PARAM_RW_BUFFERS);
3802
3803 /* Load the resources, we rely on the code sinking to do the rest */
3804 for (i = 0; i < 4; ++i) {
3805 if (si_shader_ctx->shader->selector->so.stride[i]) {
3806 LLVMValueRef offset = lp_build_const_int32(gallivm,
3807 SI_SO_BUF_OFFSET + i);
3808
3809 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3810 }
3811 }
3812 }
3813
3814 /**
3815 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
3816 * for later use.
3817 */
3818 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
3819 {
3820 struct gallivm_state *gallivm =
3821 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3822
3823 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3824 SI_PARAM_RW_BUFFERS);
3825
3826 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3827 si_shader_ctx->shader->key.vs.as_es) ||
3828 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3829 si_shader_ctx->shader->key.tes.as_es) ||
3830 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3831 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
3832
3833 si_shader_ctx->esgs_ring =
3834 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3835 }
3836
3837 if (si_shader_ctx->is_gs_copy_shader) {
3838 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
3839
3840 si_shader_ctx->gsvs_ring[0] =
3841 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3842 }
3843 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3844 int i;
3845 for (i = 0; i < 4; i++) {
3846 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
3847
3848 si_shader_ctx->gsvs_ring[i] =
3849 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3850 }
3851 }
3852 }
3853
3854 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
3855 struct si_shader_config *conf,
3856 unsigned symbol_offset)
3857 {
3858 unsigned i;
3859 const unsigned char *config =
3860 radeon_shader_binary_config_start(binary, symbol_offset);
3861
3862 /* XXX: We may be able to emit some of these values directly rather than
3863 * extracting fields to be emitted later.
3864 */
3865
3866 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
3867 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
3868 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
3869 switch (reg) {
3870 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
3871 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
3872 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
3873 case R_00B848_COMPUTE_PGM_RSRC1:
3874 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
3875 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
3876 conf->float_mode = G_00B028_FLOAT_MODE(value);
3877 conf->rsrc1 = value;
3878 break;
3879 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
3880 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
3881 break;
3882 case R_00B84C_COMPUTE_PGM_RSRC2:
3883 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
3884 conf->rsrc2 = value;
3885 break;
3886 case R_0286CC_SPI_PS_INPUT_ENA:
3887 conf->spi_ps_input_ena = value;
3888 break;
3889 case R_0286D0_SPI_PS_INPUT_ADDR:
3890 /* Not used yet, but will be in the future */
3891 break;
3892 case R_0286E8_SPI_TMPRING_SIZE:
3893 case R_00B860_COMPUTE_TMPRING_SIZE:
3894 /* WAVESIZE is in units of 256 dwords. */
3895 conf->scratch_bytes_per_wave =
3896 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
3897 break;
3898 default:
3899 {
3900 static bool printed;
3901
3902 if (!printed) {
3903 fprintf(stderr, "Warning: LLVM emitted unknown "
3904 "config register: 0x%x\n", reg);
3905 printed = true;
3906 }
3907 }
3908 break;
3909 }
3910 }
3911 }
3912
3913 void si_shader_apply_scratch_relocs(struct si_context *sctx,
3914 struct si_shader *shader,
3915 uint64_t scratch_va)
3916 {
3917 unsigned i;
3918 uint32_t scratch_rsrc_dword0 = scratch_va;
3919 uint32_t scratch_rsrc_dword1 =
3920 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
3921 | S_008F04_STRIDE(shader->config.scratch_bytes_per_wave / 64);
3922
3923 for (i = 0 ; i < shader->binary.reloc_count; i++) {
3924 const struct radeon_shader_reloc *reloc =
3925 &shader->binary.relocs[i];
3926 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
3927 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3928 &scratch_rsrc_dword0, 4);
3929 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
3930 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3931 &scratch_rsrc_dword1, 4);
3932 }
3933 }
3934 }
3935
3936 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
3937 {
3938 const struct radeon_shader_binary *binary = &shader->binary;
3939 unsigned code_size = binary->code_size + binary->rodata_size;
3940 unsigned char *ptr;
3941
3942 r600_resource_reference(&shader->bo, NULL);
3943 shader->bo = si_resource_create_custom(&sscreen->b.b,
3944 PIPE_USAGE_IMMUTABLE,
3945 code_size);
3946 if (!shader->bo)
3947 return -ENOMEM;
3948
3949 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
3950 PIPE_TRANSFER_READ_WRITE);
3951 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
3952 if (binary->rodata_size > 0) {
3953 ptr += binary->code_size;
3954 util_memcpy_cpu_to_le32(ptr, binary->rodata,
3955 binary->rodata_size);
3956 }
3957
3958 sscreen->b.ws->buffer_unmap(shader->bo->buf);
3959 return 0;
3960 }
3961
3962 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
3963 struct pipe_debug_callback *debug)
3964 {
3965 char *line, *p;
3966 unsigned i, count;
3967
3968 if (binary->disasm_string) {
3969 fprintf(stderr, "\nShader Disassembly:\n\n");
3970 fprintf(stderr, "%s\n", binary->disasm_string);
3971
3972 if (debug && debug->debug_message) {
3973 /* Very long debug messages are cut off, so send the
3974 * disassembly one line at a time. This causes more
3975 * overhead, but on the plus side it simplifies
3976 * parsing of resulting logs.
3977 */
3978 pipe_debug_message(debug, SHADER_INFO,
3979 "Shader Disassembly Begin");
3980
3981 line = binary->disasm_string;
3982 while (*line) {
3983 p = strchrnul(line, '\n');
3984 count = p - line;
3985
3986 if (count) {
3987 pipe_debug_message(debug, SHADER_INFO,
3988 "%.*s", count, line);
3989 }
3990
3991 if (!*p)
3992 break;
3993 line = p + 1;
3994 }
3995
3996 pipe_debug_message(debug, SHADER_INFO,
3997 "Shader Disassembly End");
3998 }
3999 } else {
4000 fprintf(stderr, "SI CODE:\n");
4001 for (i = 0; i < binary->code_size; i += 4) {
4002 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i,
4003 binary->code[i + 3], binary->code[i + 2],
4004 binary->code[i + 1], binary->code[i]);
4005 }
4006 }
4007 }
4008
4009 static void si_shader_dump_stats(struct si_screen *sscreen,
4010 struct si_shader_config *conf,
4011 unsigned num_inputs,
4012 unsigned code_size,
4013 struct pipe_debug_callback *debug,
4014 unsigned processor)
4015 {
4016 unsigned lds_increment = sscreen->b.chip_class >= CIK ? 512 : 256;
4017 unsigned lds_per_wave = 0;
4018 unsigned max_simd_waves = 10;
4019
4020 /* Compute LDS usage for PS. */
4021 if (processor == TGSI_PROCESSOR_FRAGMENT) {
4022 /* The minimum usage per wave is (num_inputs * 36). The maximum
4023 * usage is (num_inputs * 36 * 16).
4024 * We can get anything in between and it varies between waves.
4025 *
4026 * Other stages don't know the size at compile time or don't
4027 * allocate LDS per wave, but instead they do it per thread group.
4028 */
4029 lds_per_wave = conf->lds_size * lds_increment +
4030 align(num_inputs * 36, lds_increment);
4031 }
4032
4033 /* Compute the per-SIMD wave counts. */
4034 if (conf->num_sgprs) {
4035 if (sscreen->b.chip_class >= VI)
4036 max_simd_waves = MIN2(max_simd_waves, 800 / conf->num_sgprs);
4037 else
4038 max_simd_waves = MIN2(max_simd_waves, 512 / conf->num_sgprs);
4039 }
4040
4041 if (conf->num_vgprs)
4042 max_simd_waves = MIN2(max_simd_waves, 256 / conf->num_vgprs);
4043
4044 /* LDS is 64KB per CU (4 SIMDs), divided into 16KB blocks per SIMD
4045 * that PS can use.
4046 */
4047 if (lds_per_wave)
4048 max_simd_waves = MIN2(max_simd_waves, 16384 / lds_per_wave);
4049
4050 if (r600_can_dump_shader(&sscreen->b, processor)) {
4051 fprintf(stderr, "*** SHADER STATS ***\n"
4052 "SGPRS: %d\n"
4053 "VGPRS: %d\n"
4054 "Code Size: %d bytes\n"
4055 "LDS: %d blocks\n"
4056 "Scratch: %d bytes per wave\n"
4057 "Max Waves: %d\n"
4058 "********************\n",
4059 conf->num_sgprs, conf->num_vgprs, code_size,
4060 conf->lds_size, conf->scratch_bytes_per_wave,
4061 max_simd_waves);
4062 }
4063
4064 pipe_debug_message(debug, SHADER_INFO,
4065 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d "
4066 "LDS: %d Scratch: %d Max Waves: %d",
4067 conf->num_sgprs, conf->num_vgprs, code_size,
4068 conf->lds_size, conf->scratch_bytes_per_wave,
4069 max_simd_waves);
4070 }
4071
4072 void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
4073 struct pipe_debug_callback *debug, unsigned processor)
4074 {
4075 if (r600_can_dump_shader(&sscreen->b, processor))
4076 if (!(sscreen->b.debug_flags & DBG_NO_ASM))
4077 si_shader_dump_disassembly(&shader->binary, debug);
4078
4079 si_shader_dump_stats(sscreen, &shader->config,
4080 shader->selector ? shader->selector->info.num_inputs : 0,
4081 shader->binary.code_size, debug, processor);
4082 }
4083
4084 int si_compile_llvm(struct si_screen *sscreen,
4085 struct radeon_shader_binary *binary,
4086 struct si_shader_config *conf,
4087 LLVMTargetMachineRef tm,
4088 LLVMModuleRef mod,
4089 struct pipe_debug_callback *debug,
4090 unsigned processor)
4091 {
4092 int r = 0;
4093 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
4094
4095 if (r600_can_dump_shader(&sscreen->b, processor)) {
4096 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
4097
4098 if (!(sscreen->b.debug_flags & (DBG_NO_IR | DBG_PREOPT_IR)))
4099 LLVMDumpModule(mod);
4100 }
4101
4102 if (!si_replace_shader(count, binary)) {
4103 r = radeon_llvm_compile(mod, binary,
4104 r600_get_llvm_processor_name(sscreen->b.family), tm,
4105 debug);
4106 if (r)
4107 return r;
4108 }
4109
4110 si_shader_binary_read_config(binary, conf, 0);
4111
4112 FREE(binary->config);
4113 FREE(binary->global_symbol_offsets);
4114 binary->config = NULL;
4115 binary->global_symbol_offsets = NULL;
4116 return r;
4117 }
4118
4119 /* Generate code for the hardware VS shader stage to go with a geometry shader */
4120 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
4121 struct si_shader_context *si_shader_ctx,
4122 struct si_shader *gs, bool dump,
4123 struct pipe_debug_callback *debug)
4124 {
4125 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
4126 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
4127 struct lp_build_context *base = &bld_base->base;
4128 struct lp_build_context *uint = &bld_base->uint_bld;
4129 struct si_shader_output_values *outputs;
4130 struct tgsi_shader_info *gsinfo = &gs->selector->info;
4131 LLVMValueRef args[9];
4132 int i, r;
4133
4134 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
4135
4136 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
4137 si_shader_ctx->is_gs_copy_shader = true;
4138
4139 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
4140
4141 create_meta_data(si_shader_ctx);
4142 create_function(si_shader_ctx);
4143 preload_streamout_buffers(si_shader_ctx);
4144 preload_ring_buffers(si_shader_ctx);
4145
4146 args[0] = si_shader_ctx->gsvs_ring[0];
4147 args[1] = lp_build_mul_imm(uint,
4148 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
4149 si_shader_ctx->param_vertex_id),
4150 4);
4151 args[3] = uint->zero;
4152 args[4] = uint->one; /* OFFEN */
4153 args[5] = uint->zero; /* IDXEN */
4154 args[6] = uint->one; /* GLC */
4155 args[7] = uint->one; /* SLC */
4156 args[8] = uint->zero; /* TFE */
4157
4158 /* Fetch vertex data from GSVS ring */
4159 for (i = 0; i < gsinfo->num_outputs; ++i) {
4160 unsigned chan;
4161
4162 outputs[i].name = gsinfo->output_semantic_name[i];
4163 outputs[i].sid = gsinfo->output_semantic_index[i];
4164
4165 for (chan = 0; chan < 4; chan++) {
4166 args[2] = lp_build_const_int32(gallivm,
4167 (i * 4 + chan) *
4168 gs->selector->gs_max_out_vertices * 16 * 4);
4169
4170 outputs[i].values[chan] =
4171 LLVMBuildBitCast(gallivm->builder,
4172 lp_build_intrinsic(gallivm->builder,
4173 "llvm.SI.buffer.load.dword.i32.i32",
4174 LLVMInt32TypeInContext(gallivm->context),
4175 args, 9,
4176 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
4177 base->elem_type, "");
4178 }
4179 }
4180
4181 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
4182
4183 LLVMBuildRetVoid(bld_base->base.gallivm->builder);
4184
4185 /* Dump LLVM IR before any optimization passes */
4186 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
4187 r600_can_dump_shader(&sscreen->b, TGSI_PROCESSOR_GEOMETRY))
4188 LLVMDumpModule(bld_base->base.gallivm->module);
4189
4190 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
4191
4192 if (dump)
4193 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
4194
4195 r = si_compile_llvm(sscreen, &si_shader_ctx->shader->binary,
4196 &si_shader_ctx->shader->config, si_shader_ctx->tm,
4197 bld_base->base.gallivm->module,
4198 debug, TGSI_PROCESSOR_GEOMETRY);
4199 if (!r) {
4200 si_shader_dump(sscreen, si_shader_ctx->shader, debug,
4201 TGSI_PROCESSOR_GEOMETRY);
4202 r = si_shader_binary_upload(sscreen, si_shader_ctx->shader);
4203 }
4204
4205 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
4206
4207 FREE(outputs);
4208 return r;
4209 }
4210
4211 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
4212 {
4213 int i;
4214
4215 fprintf(f, "SHADER KEY\n");
4216
4217 switch (shader) {
4218 case PIPE_SHADER_VERTEX:
4219 fprintf(f, " instance_divisors = {");
4220 for (i = 0; i < Elements(key->vs.instance_divisors); i++)
4221 fprintf(f, !i ? "%u" : ", %u",
4222 key->vs.instance_divisors[i]);
4223 fprintf(f, "}\n");
4224 fprintf(f, " as_es = %u\n", key->vs.as_es);
4225 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
4226 fprintf(f, " export_prim_id = %u\n", key->vs.export_prim_id);
4227 break;
4228
4229 case PIPE_SHADER_TESS_CTRL:
4230 fprintf(f, " prim_mode = %u\n", key->tcs.prim_mode);
4231 break;
4232
4233 case PIPE_SHADER_TESS_EVAL:
4234 fprintf(f, " as_es = %u\n", key->tes.as_es);
4235 fprintf(f, " export_prim_id = %u\n", key->tes.export_prim_id);
4236 break;
4237
4238 case PIPE_SHADER_GEOMETRY:
4239 break;
4240
4241 case PIPE_SHADER_FRAGMENT:
4242 fprintf(f, " spi_shader_col_format = 0x%x\n", key->ps.spi_shader_col_format);
4243 fprintf(f, " last_cbuf = %u\n", key->ps.last_cbuf);
4244 fprintf(f, " color_two_side = %u\n", key->ps.color_two_side);
4245 fprintf(f, " alpha_func = %u\n", key->ps.alpha_func);
4246 fprintf(f, " alpha_to_one = %u\n", key->ps.alpha_to_one);
4247 fprintf(f, " poly_stipple = %u\n", key->ps.poly_stipple);
4248 fprintf(f, " clamp_color = %u\n", key->ps.clamp_color);
4249 break;
4250
4251 default:
4252 assert(0);
4253 }
4254 }
4255
4256 static void si_init_shader_ctx(struct si_shader_context *ctx,
4257 struct si_screen *sscreen,
4258 struct si_shader *shader,
4259 LLVMTargetMachineRef tm,
4260 struct tgsi_shader_info *info)
4261 {
4262 struct lp_build_tgsi_context *bld_base;
4263
4264 memset(ctx, 0, sizeof(*ctx));
4265 radeon_llvm_context_init(&ctx->radeon_bld);
4266 ctx->tm = tm;
4267 ctx->screen = sscreen;
4268 if (shader && shader->selector)
4269 ctx->type = shader->selector->info.processor;
4270 else
4271 ctx->type = -1;
4272 ctx->shader = shader;
4273
4274 bld_base = &ctx->radeon_bld.soa.bld_base;
4275 bld_base->info = info;
4276 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
4277
4278 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
4279 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
4280 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
4281
4282 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
4283 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
4284 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
4285 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
4286 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
4287 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
4288 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
4289 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
4290 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
4291 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
4292 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
4293 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
4294 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
4295
4296 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
4297 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
4298 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
4299 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
4300
4301 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
4302 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
4303 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
4304
4305 if (HAVE_LLVM >= 0x0306) {
4306 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
4307 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
4308 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
4309 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
4310 }
4311 }
4312
4313 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
4314 struct si_shader *shader,
4315 struct pipe_debug_callback *debug)
4316 {
4317 struct si_shader_selector *sel = shader->selector;
4318 struct tgsi_token *tokens = sel->tokens;
4319 struct si_shader_context si_shader_ctx;
4320 struct lp_build_tgsi_context * bld_base;
4321 struct tgsi_shader_info stipple_shader_info;
4322 LLVMModuleRef mod;
4323 int r = 0;
4324 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
4325 shader->key.ps.poly_stipple;
4326 bool dump = r600_can_dump_shader(&sscreen->b, sel->info.processor);
4327
4328 if (poly_stipple) {
4329 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
4330 SI_POLY_STIPPLE_SAMPLER,
4331 TGSI_FILE_SYSTEM_VALUE);
4332 tgsi_scan_shader(tokens, &stipple_shader_info);
4333 }
4334
4335 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
4336 * conversion fails. */
4337 if (dump && !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
4338 si_dump_shader_key(sel->type, &shader->key, stderr);
4339 tgsi_dump(tokens, 0);
4340 si_dump_streamout(&sel->so);
4341 }
4342
4343 si_init_shader_ctx(&si_shader_ctx, sscreen, shader, tm,
4344 poly_stipple ? &stipple_shader_info : &sel->info);
4345
4346 if (sel->type != PIPE_SHADER_COMPUTE)
4347 shader->dx10_clamp_mode = true;
4348
4349 shader->uses_instanceid = sel->info.uses_instanceid;
4350
4351 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
4352 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
4353
4354 switch (si_shader_ctx.type) {
4355 case TGSI_PROCESSOR_VERTEX:
4356 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
4357 if (shader->key.vs.as_ls)
4358 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
4359 else if (shader->key.vs.as_es)
4360 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4361 else
4362 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4363 break;
4364 case TGSI_PROCESSOR_TESS_CTRL:
4365 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
4366 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
4367 bld_base->emit_store = store_output_tcs;
4368 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
4369 break;
4370 case TGSI_PROCESSOR_TESS_EVAL:
4371 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
4372 if (shader->key.tes.as_es)
4373 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4374 else
4375 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4376 break;
4377 case TGSI_PROCESSOR_GEOMETRY:
4378 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
4379 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
4380 break;
4381 case TGSI_PROCESSOR_FRAGMENT:
4382 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
4383 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
4384 break;
4385 default:
4386 assert(!"Unsupported shader type");
4387 return -1;
4388 }
4389
4390 create_meta_data(&si_shader_ctx);
4391 create_function(&si_shader_ctx);
4392 preload_constants(&si_shader_ctx);
4393 preload_samplers(&si_shader_ctx);
4394 preload_streamout_buffers(&si_shader_ctx);
4395 preload_ring_buffers(&si_shader_ctx);
4396
4397 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4398 int i;
4399 for (i = 0; i < 4; i++) {
4400 si_shader_ctx.gs_next_vertex[i] =
4401 lp_build_alloca(bld_base->base.gallivm,
4402 bld_base->uint_bld.elem_type, "");
4403 }
4404 }
4405
4406 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
4407 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
4408 goto out;
4409 }
4410
4411 LLVMBuildRetVoid(bld_base->base.gallivm->builder);
4412 mod = bld_base->base.gallivm->module;
4413
4414 /* Dump LLVM IR before any optimization passes */
4415 if (sscreen->b.debug_flags & DBG_PREOPT_IR &&
4416 r600_can_dump_shader(&sscreen->b, si_shader_ctx.type))
4417 LLVMDumpModule(mod);
4418
4419 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
4420
4421 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
4422 mod, debug, si_shader_ctx.type);
4423 if (r) {
4424 fprintf(stderr, "LLVM failed to compile shader\n");
4425 goto out;
4426 }
4427
4428 si_shader_dump(sscreen, shader, debug, si_shader_ctx.type);
4429
4430 r = si_shader_binary_upload(sscreen, shader);
4431 if (r) {
4432 fprintf(stderr, "LLVM failed to upload shader\n");
4433 goto out;
4434 }
4435
4436 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
4437
4438 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4439 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
4440 shader->gs_copy_shader->selector = shader->selector;
4441 si_shader_ctx.shader = shader->gs_copy_shader;
4442 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
4443 shader, dump, debug))) {
4444 free(shader->gs_copy_shader);
4445 shader->gs_copy_shader = NULL;
4446 goto out;
4447 }
4448 }
4449
4450 out:
4451 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
4452 FREE(si_shader_ctx.constants[i]);
4453 if (poly_stipple)
4454 tgsi_free_tokens(tokens);
4455 return r;
4456 }
4457
4458 void si_shader_destroy(struct si_shader *shader)
4459 {
4460 if (shader->gs_copy_shader) {
4461 si_shader_destroy(shader->gs_copy_shader);
4462 FREE(shader->gs_copy_shader);
4463 }
4464
4465 if (shader->scratch_bo)
4466 r600_resource_reference(&shader->scratch_bo, NULL);
4467
4468 r600_resource_reference(&shader->bo, NULL);
4469
4470 radeon_shader_binary_clean(&shader->binary);
4471 }