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radeonsi: separate shader dumping code to si_shader_dump and *_dump_stats
[mesa.git] / src / gallium / drivers / radeonsi / si_shader.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Tom Stellard <thomas.stellard@amd.com>
25 * Michel Dänzer <michel.daenzer@amd.com>
26 * Christian König <christian.koenig@amd.com>
27 */
28
29 #include "gallivm/lp_bld_const.h"
30 #include "gallivm/lp_bld_gather.h"
31 #include "gallivm/lp_bld_intr.h"
32 #include "gallivm/lp_bld_logic.h"
33 #include "gallivm/lp_bld_arit.h"
34 #include "gallivm/lp_bld_bitarit.h"
35 #include "gallivm/lp_bld_flow.h"
36 #include "radeon/r600_cs.h"
37 #include "radeon/radeon_llvm.h"
38 #include "radeon/radeon_elf_util.h"
39 #include "radeon/radeon_llvm_emit.h"
40 #include "util/u_memory.h"
41 #include "util/u_pstipple.h"
42 #include "tgsi/tgsi_parse.h"
43 #include "tgsi/tgsi_util.h"
44 #include "tgsi/tgsi_dump.h"
45
46 #include "si_pipe.h"
47 #include "si_shader.h"
48 #include "sid.h"
49
50 #include <errno.h>
51
52 static const char *scratch_rsrc_dword0_symbol =
53 "SCRATCH_RSRC_DWORD0";
54
55 static const char *scratch_rsrc_dword1_symbol =
56 "SCRATCH_RSRC_DWORD1";
57
58 struct si_shader_output_values
59 {
60 LLVMValueRef values[4];
61 unsigned name;
62 unsigned sid;
63 };
64
65 struct si_shader_context
66 {
67 struct radeon_llvm_context radeon_bld;
68 struct si_shader *shader;
69 struct si_screen *screen;
70 unsigned type; /* TGSI_PROCESSOR_* specifies the type of shader. */
71 int param_streamout_config;
72 int param_streamout_write_index;
73 int param_streamout_offset[4];
74 int param_vertex_id;
75 int param_rel_auto_id;
76 int param_vs_prim_id;
77 int param_instance_id;
78 int param_tes_u;
79 int param_tes_v;
80 int param_tes_rel_patch_id;
81 int param_tes_patch_id;
82 int param_es2gs_offset;
83 LLVMTargetMachineRef tm;
84 LLVMValueRef const_md;
85 LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
86 LLVMValueRef lds;
87 LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
88 LLVMValueRef sampler_views[SI_NUM_SAMPLER_VIEWS];
89 LLVMValueRef sampler_states[SI_NUM_SAMPLER_STATES];
90 LLVMValueRef so_buffers[4];
91 LLVMValueRef esgs_ring;
92 LLVMValueRef gsvs_ring[4];
93 LLVMValueRef gs_next_vertex[4];
94 };
95
96 static struct si_shader_context * si_shader_context(
97 struct lp_build_tgsi_context * bld_base)
98 {
99 return (struct si_shader_context *)bld_base;
100 }
101
102
103 #define PERSPECTIVE_BASE 0
104 #define LINEAR_BASE 9
105
106 #define SAMPLE_OFFSET 0
107 #define CENTER_OFFSET 2
108 #define CENTROID_OFSET 4
109
110 #define USE_SGPR_MAX_SUFFIX_LEN 5
111 #define CONST_ADDR_SPACE 2
112 #define LOCAL_ADDR_SPACE 3
113 #define USER_SGPR_ADDR_SPACE 8
114
115
116 #define SENDMSG_GS 2
117 #define SENDMSG_GS_DONE 3
118
119 #define SENDMSG_GS_OP_NOP (0 << 4)
120 #define SENDMSG_GS_OP_CUT (1 << 4)
121 #define SENDMSG_GS_OP_EMIT (2 << 4)
122 #define SENDMSG_GS_OP_EMIT_CUT (3 << 4)
123
124 /**
125 * Returns a unique index for a semantic name and index. The index must be
126 * less than 64, so that a 64-bit bitmask of used inputs or outputs can be
127 * calculated.
128 */
129 unsigned si_shader_io_get_unique_index(unsigned semantic_name, unsigned index)
130 {
131 switch (semantic_name) {
132 case TGSI_SEMANTIC_POSITION:
133 return 0;
134 case TGSI_SEMANTIC_PSIZE:
135 return 1;
136 case TGSI_SEMANTIC_CLIPDIST:
137 assert(index <= 1);
138 return 2 + index;
139 case TGSI_SEMANTIC_GENERIC:
140 if (index <= 63-4)
141 return 4 + index;
142 else
143 /* same explanation as in the default statement,
144 * the only user hitting this is st/nine.
145 */
146 return 0;
147
148 /* patch indices are completely separate and thus start from 0 */
149 case TGSI_SEMANTIC_TESSOUTER:
150 return 0;
151 case TGSI_SEMANTIC_TESSINNER:
152 return 1;
153 case TGSI_SEMANTIC_PATCH:
154 return 2 + index;
155
156 default:
157 /* Don't fail here. The result of this function is only used
158 * for LS, TCS, TES, and GS, where legacy GL semantics can't
159 * occur, but this function is called for all vertex shaders
160 * before it's known whether LS will be compiled or not.
161 */
162 return 0;
163 }
164 }
165
166 /**
167 * Get the value of a shader input parameter and extract a bitfield.
168 */
169 static LLVMValueRef unpack_param(struct si_shader_context *si_shader_ctx,
170 unsigned param, unsigned rshift,
171 unsigned bitwidth)
172 {
173 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
174 LLVMValueRef value = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
175 param);
176
177 if (rshift)
178 value = LLVMBuildLShr(gallivm->builder, value,
179 lp_build_const_int32(gallivm, rshift), "");
180
181 if (rshift + bitwidth < 32) {
182 unsigned mask = (1 << bitwidth) - 1;
183 value = LLVMBuildAnd(gallivm->builder, value,
184 lp_build_const_int32(gallivm, mask), "");
185 }
186
187 return value;
188 }
189
190 static LLVMValueRef get_rel_patch_id(struct si_shader_context *si_shader_ctx)
191 {
192 switch (si_shader_ctx->type) {
193 case TGSI_PROCESSOR_TESS_CTRL:
194 return unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 0, 8);
195
196 case TGSI_PROCESSOR_TESS_EVAL:
197 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
198 si_shader_ctx->param_tes_rel_patch_id);
199
200 default:
201 assert(0);
202 return NULL;
203 }
204 }
205
206 /* Tessellation shaders pass outputs to the next shader using LDS.
207 *
208 * LS outputs = TCS inputs
209 * TCS outputs = TES inputs
210 *
211 * The LDS layout is:
212 * - TCS inputs for patch 0
213 * - TCS inputs for patch 1
214 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
215 * - ...
216 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
217 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
218 * - TCS outputs for patch 1
219 * - Per-patch TCS outputs for patch 1
220 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
221 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
222 * - ...
223 *
224 * All three shaders VS(LS), TCS, TES share the same LDS space.
225 */
226
227 static LLVMValueRef
228 get_tcs_in_patch_stride(struct si_shader_context *si_shader_ctx)
229 {
230 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX)
231 return unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 0, 13);
232 else if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
233 return unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 0, 13);
234 else {
235 assert(0);
236 return NULL;
237 }
238 }
239
240 static LLVMValueRef
241 get_tcs_out_patch_stride(struct si_shader_context *si_shader_ctx)
242 {
243 return unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 0, 13);
244 }
245
246 static LLVMValueRef
247 get_tcs_out_patch0_offset(struct si_shader_context *si_shader_ctx)
248 {
249 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
250 unpack_param(si_shader_ctx,
251 SI_PARAM_TCS_OUT_OFFSETS,
252 0, 16),
253 4);
254 }
255
256 static LLVMValueRef
257 get_tcs_out_patch0_patch_data_offset(struct si_shader_context *si_shader_ctx)
258 {
259 return lp_build_mul_imm(&si_shader_ctx->radeon_bld.soa.bld_base.uint_bld,
260 unpack_param(si_shader_ctx,
261 SI_PARAM_TCS_OUT_OFFSETS,
262 16, 16),
263 4);
264 }
265
266 static LLVMValueRef
267 get_tcs_in_current_patch_offset(struct si_shader_context *si_shader_ctx)
268 {
269 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
270 LLVMValueRef patch_stride = get_tcs_in_patch_stride(si_shader_ctx);
271 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
272
273 return LLVMBuildMul(gallivm->builder, patch_stride, rel_patch_id, "");
274 }
275
276 static LLVMValueRef
277 get_tcs_out_current_patch_offset(struct si_shader_context *si_shader_ctx)
278 {
279 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
280 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(si_shader_ctx);
281 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
282 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
283
284 return LLVMBuildAdd(gallivm->builder, patch0_offset,
285 LLVMBuildMul(gallivm->builder, patch_stride,
286 rel_patch_id, ""),
287 "");
288 }
289
290 static LLVMValueRef
291 get_tcs_out_current_patch_data_offset(struct si_shader_context *si_shader_ctx)
292 {
293 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
294 LLVMValueRef patch0_patch_data_offset =
295 get_tcs_out_patch0_patch_data_offset(si_shader_ctx);
296 LLVMValueRef patch_stride = get_tcs_out_patch_stride(si_shader_ctx);
297 LLVMValueRef rel_patch_id = get_rel_patch_id(si_shader_ctx);
298
299 return LLVMBuildAdd(gallivm->builder, patch0_patch_data_offset,
300 LLVMBuildMul(gallivm->builder, patch_stride,
301 rel_patch_id, ""),
302 "");
303 }
304
305 static void build_indexed_store(struct si_shader_context *si_shader_ctx,
306 LLVMValueRef base_ptr, LLVMValueRef index,
307 LLVMValueRef value)
308 {
309 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
310 struct gallivm_state *gallivm = bld_base->base.gallivm;
311 LLVMValueRef indices[2], pointer;
312
313 indices[0] = bld_base->uint_bld.zero;
314 indices[1] = index;
315
316 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
317 LLVMBuildStore(gallivm->builder, value, pointer);
318 }
319
320 /**
321 * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
322 * It's equivalent to doing a load from &base_ptr[index].
323 *
324 * \param base_ptr Where the array starts.
325 * \param index The element index into the array.
326 */
327 static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
328 LLVMValueRef base_ptr, LLVMValueRef index)
329 {
330 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
331 struct gallivm_state *gallivm = bld_base->base.gallivm;
332 LLVMValueRef indices[2], pointer;
333
334 indices[0] = bld_base->uint_bld.zero;
335 indices[1] = index;
336
337 pointer = LLVMBuildGEP(gallivm->builder, base_ptr, indices, 2, "");
338 return LLVMBuildLoad(gallivm->builder, pointer, "");
339 }
340
341 /**
342 * Do a load from &base_ptr[index], but also add a flag that it's loading
343 * a constant.
344 */
345 static LLVMValueRef build_indexed_load_const(
346 struct si_shader_context * si_shader_ctx,
347 LLVMValueRef base_ptr, LLVMValueRef index)
348 {
349 LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr, index);
350 LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
351 return result;
352 }
353
354 static LLVMValueRef get_instance_index_for_fetch(
355 struct radeon_llvm_context * radeon_bld,
356 unsigned divisor)
357 {
358 struct si_shader_context *si_shader_ctx =
359 si_shader_context(&radeon_bld->soa.bld_base);
360 struct gallivm_state * gallivm = radeon_bld->soa.bld_base.base.gallivm;
361
362 LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn,
363 si_shader_ctx->param_instance_id);
364
365 /* The division must be done before START_INSTANCE is added. */
366 if (divisor > 1)
367 result = LLVMBuildUDiv(gallivm->builder, result,
368 lp_build_const_int32(gallivm, divisor), "");
369
370 return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam(
371 radeon_bld->main_fn, SI_PARAM_START_INSTANCE), "");
372 }
373
374 static void declare_input_vs(
375 struct radeon_llvm_context *radeon_bld,
376 unsigned input_index,
377 const struct tgsi_full_declaration *decl)
378 {
379 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
380 struct gallivm_state *gallivm = base->gallivm;
381 struct si_shader_context *si_shader_ctx =
382 si_shader_context(&radeon_bld->soa.bld_base);
383 unsigned divisor = si_shader_ctx->shader->key.vs.instance_divisors[input_index];
384
385 unsigned chan;
386
387 LLVMValueRef t_list_ptr;
388 LLVMValueRef t_offset;
389 LLVMValueRef t_list;
390 LLVMValueRef attribute_offset;
391 LLVMValueRef buffer_index;
392 LLVMValueRef args[3];
393 LLVMTypeRef vec4_type;
394 LLVMValueRef input;
395
396 /* Load the T list */
397 t_list_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_VERTEX_BUFFERS);
398
399 t_offset = lp_build_const_int32(gallivm, input_index);
400
401 t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
402
403 /* Build the attribute offset */
404 attribute_offset = lp_build_const_int32(gallivm, 0);
405
406 if (divisor) {
407 /* Build index from instance ID, start instance and divisor */
408 si_shader_ctx->shader->uses_instanceid = true;
409 buffer_index = get_instance_index_for_fetch(&si_shader_ctx->radeon_bld, divisor);
410 } else {
411 /* Load the buffer index for vertices. */
412 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
413 si_shader_ctx->param_vertex_id);
414 LLVMValueRef base_vertex = LLVMGetParam(radeon_bld->main_fn,
415 SI_PARAM_BASE_VERTEX);
416 buffer_index = LLVMBuildAdd(gallivm->builder, base_vertex, vertex_id, "");
417 }
418
419 vec4_type = LLVMVectorType(base->elem_type, 4);
420 args[0] = t_list;
421 args[1] = attribute_offset;
422 args[2] = buffer_index;
423 input = lp_build_intrinsic(gallivm->builder,
424 "llvm.SI.vs.load.input", vec4_type, args, 3,
425 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
426
427 /* Break up the vec4 into individual components */
428 for (chan = 0; chan < 4; chan++) {
429 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
430 /* XXX: Use a helper function for this. There is one in
431 * tgsi_llvm.c. */
432 si_shader_ctx->radeon_bld.inputs[radeon_llvm_reg_index_soa(input_index, chan)] =
433 LLVMBuildExtractElement(gallivm->builder,
434 input, llvm_chan, "");
435 }
436 }
437
438 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
439 unsigned swizzle)
440 {
441 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
442
443 if (swizzle > 0)
444 return bld_base->uint_bld.zero;
445
446 switch (si_shader_ctx->type) {
447 case TGSI_PROCESSOR_VERTEX:
448 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
449 si_shader_ctx->param_vs_prim_id);
450 case TGSI_PROCESSOR_TESS_CTRL:
451 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
452 SI_PARAM_PATCH_ID);
453 case TGSI_PROCESSOR_TESS_EVAL:
454 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
455 si_shader_ctx->param_tes_patch_id);
456 case TGSI_PROCESSOR_GEOMETRY:
457 return LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
458 SI_PARAM_PRIMITIVE_ID);
459 default:
460 assert(0);
461 return bld_base->uint_bld.zero;
462 }
463 }
464
465 /**
466 * Return the value of tgsi_ind_register for indexing.
467 * This is the indirect index with the constant offset added to it.
468 */
469 static LLVMValueRef get_indirect_index(struct si_shader_context *si_shader_ctx,
470 const struct tgsi_ind_register *ind,
471 int rel_index)
472 {
473 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
474 LLVMValueRef result;
475
476 result = si_shader_ctx->radeon_bld.soa.addr[ind->Index][ind->Swizzle];
477 result = LLVMBuildLoad(gallivm->builder, result, "");
478 result = LLVMBuildAdd(gallivm->builder, result,
479 lp_build_const_int32(gallivm, rel_index), "");
480 return result;
481 }
482
483 /**
484 * Calculate a dword address given an input or output register and a stride.
485 */
486 static LLVMValueRef get_dw_address(struct si_shader_context *si_shader_ctx,
487 const struct tgsi_full_dst_register *dst,
488 const struct tgsi_full_src_register *src,
489 LLVMValueRef vertex_dw_stride,
490 LLVMValueRef base_addr)
491 {
492 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
493 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
494 ubyte *name, *index, *array_first;
495 int first, param;
496 struct tgsi_full_dst_register reg;
497
498 /* Set the register description. The address computation is the same
499 * for sources and destinations. */
500 if (src) {
501 reg.Register.File = src->Register.File;
502 reg.Register.Index = src->Register.Index;
503 reg.Register.Indirect = src->Register.Indirect;
504 reg.Register.Dimension = src->Register.Dimension;
505 reg.Indirect = src->Indirect;
506 reg.Dimension = src->Dimension;
507 reg.DimIndirect = src->DimIndirect;
508 } else
509 reg = *dst;
510
511 /* If the register is 2-dimensional (e.g. an array of vertices
512 * in a primitive), calculate the base address of the vertex. */
513 if (reg.Register.Dimension) {
514 LLVMValueRef index;
515
516 if (reg.Dimension.Indirect)
517 index = get_indirect_index(si_shader_ctx, &reg.DimIndirect,
518 reg.Dimension.Index);
519 else
520 index = lp_build_const_int32(gallivm, reg.Dimension.Index);
521
522 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
523 LLVMBuildMul(gallivm->builder, index,
524 vertex_dw_stride, ""), "");
525 }
526
527 /* Get information about the register. */
528 if (reg.Register.File == TGSI_FILE_INPUT) {
529 name = info->input_semantic_name;
530 index = info->input_semantic_index;
531 array_first = info->input_array_first;
532 } else if (reg.Register.File == TGSI_FILE_OUTPUT) {
533 name = info->output_semantic_name;
534 index = info->output_semantic_index;
535 array_first = info->output_array_first;
536 } else {
537 assert(0);
538 return NULL;
539 }
540
541 if (reg.Register.Indirect) {
542 /* Add the relative address of the element. */
543 LLVMValueRef ind_index;
544
545 if (reg.Indirect.ArrayID)
546 first = array_first[reg.Indirect.ArrayID];
547 else
548 first = reg.Register.Index;
549
550 ind_index = get_indirect_index(si_shader_ctx, &reg.Indirect,
551 reg.Register.Index - first);
552
553 base_addr = LLVMBuildAdd(gallivm->builder, base_addr,
554 LLVMBuildMul(gallivm->builder, ind_index,
555 lp_build_const_int32(gallivm, 4), ""), "");
556
557 param = si_shader_io_get_unique_index(name[first], index[first]);
558 } else {
559 param = si_shader_io_get_unique_index(name[reg.Register.Index],
560 index[reg.Register.Index]);
561 }
562
563 /* Add the base address of the element. */
564 return LLVMBuildAdd(gallivm->builder, base_addr,
565 lp_build_const_int32(gallivm, param * 4), "");
566 }
567
568 /**
569 * Load from LDS.
570 *
571 * \param type output value type
572 * \param swizzle offset (typically 0..3); it can be ~0, which loads a vec4
573 * \param dw_addr address in dwords
574 */
575 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
576 enum tgsi_opcode_type type, unsigned swizzle,
577 LLVMValueRef dw_addr)
578 {
579 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
580 struct gallivm_state *gallivm = bld_base->base.gallivm;
581 LLVMValueRef value;
582
583 if (swizzle == ~0) {
584 LLVMValueRef values[TGSI_NUM_CHANNELS];
585
586 for (unsigned chan = 0; chan < TGSI_NUM_CHANNELS; chan++)
587 values[chan] = lds_load(bld_base, type, chan, dw_addr);
588
589 return lp_build_gather_values(bld_base->base.gallivm, values,
590 TGSI_NUM_CHANNELS);
591 }
592
593 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
594 lp_build_const_int32(gallivm, swizzle));
595
596 value = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
597 if (type == TGSI_TYPE_DOUBLE) {
598 LLVMValueRef value2;
599 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
600 lp_build_const_int32(gallivm, swizzle + 1));
601 value2 = build_indexed_load(si_shader_ctx, si_shader_ctx->lds, dw_addr);
602 return radeon_llvm_emit_fetch_double(bld_base, value, value2);
603 }
604
605 return LLVMBuildBitCast(gallivm->builder, value,
606 tgsi2llvmtype(bld_base, type), "");
607 }
608
609 /**
610 * Store to LDS.
611 *
612 * \param swizzle offset (typically 0..3)
613 * \param dw_addr address in dwords
614 * \param value value to store
615 */
616 static void lds_store(struct lp_build_tgsi_context * bld_base,
617 unsigned swizzle, LLVMValueRef dw_addr,
618 LLVMValueRef value)
619 {
620 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
621 struct gallivm_state *gallivm = bld_base->base.gallivm;
622
623 dw_addr = lp_build_add(&bld_base->uint_bld, dw_addr,
624 lp_build_const_int32(gallivm, swizzle));
625
626 value = LLVMBuildBitCast(gallivm->builder, value,
627 LLVMInt32TypeInContext(gallivm->context), "");
628 build_indexed_store(si_shader_ctx, si_shader_ctx->lds,
629 dw_addr, value);
630 }
631
632 static LLVMValueRef fetch_input_tcs(
633 struct lp_build_tgsi_context *bld_base,
634 const struct tgsi_full_src_register *reg,
635 enum tgsi_opcode_type type, unsigned swizzle)
636 {
637 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
638 LLVMValueRef dw_addr, stride;
639
640 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_IN_LAYOUT, 13, 8);
641 dw_addr = get_tcs_in_current_patch_offset(si_shader_ctx);
642 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
643
644 return lds_load(bld_base, type, swizzle, dw_addr);
645 }
646
647 static LLVMValueRef fetch_output_tcs(
648 struct lp_build_tgsi_context *bld_base,
649 const struct tgsi_full_src_register *reg,
650 enum tgsi_opcode_type type, unsigned swizzle)
651 {
652 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
653 LLVMValueRef dw_addr, stride;
654
655 if (reg->Register.Dimension) {
656 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
657 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
658 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
659 } else {
660 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
661 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
662 }
663
664 return lds_load(bld_base, type, swizzle, dw_addr);
665 }
666
667 static LLVMValueRef fetch_input_tes(
668 struct lp_build_tgsi_context *bld_base,
669 const struct tgsi_full_src_register *reg,
670 enum tgsi_opcode_type type, unsigned swizzle)
671 {
672 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
673 LLVMValueRef dw_addr, stride;
674
675 if (reg->Register.Dimension) {
676 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
677 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
678 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, stride, dw_addr);
679 } else {
680 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
681 dw_addr = get_dw_address(si_shader_ctx, NULL, reg, NULL, dw_addr);
682 }
683
684 return lds_load(bld_base, type, swizzle, dw_addr);
685 }
686
687 static void store_output_tcs(struct lp_build_tgsi_context * bld_base,
688 const struct tgsi_full_instruction * inst,
689 const struct tgsi_opcode_info * info,
690 LLVMValueRef dst[4])
691 {
692 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
693 const struct tgsi_full_dst_register *reg = &inst->Dst[0];
694 unsigned chan_index;
695 LLVMValueRef dw_addr, stride;
696
697 /* Only handle per-patch and per-vertex outputs here.
698 * Vectors will be lowered to scalars and this function will be called again.
699 */
700 if (reg->Register.File != TGSI_FILE_OUTPUT ||
701 (dst[0] && LLVMGetTypeKind(LLVMTypeOf(dst[0])) == LLVMVectorTypeKind)) {
702 radeon_llvm_emit_store(bld_base, inst, info, dst);
703 return;
704 }
705
706 if (reg->Register.Dimension) {
707 stride = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 13, 8);
708 dw_addr = get_tcs_out_current_patch_offset(si_shader_ctx);
709 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, stride, dw_addr);
710 } else {
711 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
712 dw_addr = get_dw_address(si_shader_ctx, reg, NULL, NULL, dw_addr);
713 }
714
715 TGSI_FOR_EACH_DST0_ENABLED_CHANNEL(inst, chan_index) {
716 LLVMValueRef value = dst[chan_index];
717
718 if (inst->Instruction.Saturate)
719 value = radeon_llvm_saturate(bld_base, value);
720
721 lds_store(bld_base, chan_index, dw_addr, value);
722 }
723 }
724
725 static LLVMValueRef fetch_input_gs(
726 struct lp_build_tgsi_context *bld_base,
727 const struct tgsi_full_src_register *reg,
728 enum tgsi_opcode_type type,
729 unsigned swizzle)
730 {
731 struct lp_build_context *base = &bld_base->base;
732 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
733 struct si_shader *shader = si_shader_ctx->shader;
734 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
735 struct gallivm_state *gallivm = base->gallivm;
736 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
737 LLVMValueRef vtx_offset;
738 LLVMValueRef args[9];
739 unsigned vtx_offset_param;
740 struct tgsi_shader_info *info = &shader->selector->info;
741 unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
742 unsigned semantic_index = info->input_semantic_index[reg->Register.Index];
743 unsigned param;
744 LLVMValueRef value;
745
746 if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
747 return get_primitive_id(bld_base, swizzle);
748
749 if (!reg->Register.Dimension)
750 return NULL;
751
752 if (swizzle == ~0) {
753 LLVMValueRef values[TGSI_NUM_CHANNELS];
754 unsigned chan;
755 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
756 values[chan] = fetch_input_gs(bld_base, reg, type, chan);
757 }
758 return lp_build_gather_values(bld_base->base.gallivm, values,
759 TGSI_NUM_CHANNELS);
760 }
761
762 /* Get the vertex offset parameter */
763 vtx_offset_param = reg->Dimension.Index;
764 if (vtx_offset_param < 2) {
765 vtx_offset_param += SI_PARAM_VTX0_OFFSET;
766 } else {
767 assert(vtx_offset_param < 6);
768 vtx_offset_param += SI_PARAM_VTX2_OFFSET - 2;
769 }
770 vtx_offset = lp_build_mul_imm(uint,
771 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
772 vtx_offset_param),
773 4);
774
775 param = si_shader_io_get_unique_index(semantic_name, semantic_index);
776 args[0] = si_shader_ctx->esgs_ring;
777 args[1] = vtx_offset;
778 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle) * 256);
779 args[3] = uint->zero;
780 args[4] = uint->one; /* OFFEN */
781 args[5] = uint->zero; /* IDXEN */
782 args[6] = uint->one; /* GLC */
783 args[7] = uint->zero; /* SLC */
784 args[8] = uint->zero; /* TFE */
785
786 value = lp_build_intrinsic(gallivm->builder,
787 "llvm.SI.buffer.load.dword.i32.i32",
788 i32, args, 9,
789 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
790 if (type == TGSI_TYPE_DOUBLE) {
791 LLVMValueRef value2;
792 args[2] = lp_build_const_int32(gallivm, (param * 4 + swizzle + 1) * 256);
793 value2 = lp_build_intrinsic(gallivm->builder,
794 "llvm.SI.buffer.load.dword.i32.i32",
795 i32, args, 9,
796 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute);
797 return radeon_llvm_emit_fetch_double(bld_base,
798 value, value2);
799 }
800 return LLVMBuildBitCast(gallivm->builder,
801 value,
802 tgsi2llvmtype(bld_base, type), "");
803 }
804
805 static int lookup_interp_param_index(unsigned interpolate, unsigned location)
806 {
807 switch (interpolate) {
808 case TGSI_INTERPOLATE_CONSTANT:
809 return 0;
810
811 case TGSI_INTERPOLATE_LINEAR:
812 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
813 return SI_PARAM_LINEAR_SAMPLE;
814 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
815 return SI_PARAM_LINEAR_CENTROID;
816 else
817 return SI_PARAM_LINEAR_CENTER;
818 break;
819 case TGSI_INTERPOLATE_COLOR:
820 case TGSI_INTERPOLATE_PERSPECTIVE:
821 if (location == TGSI_INTERPOLATE_LOC_SAMPLE)
822 return SI_PARAM_PERSP_SAMPLE;
823 else if (location == TGSI_INTERPOLATE_LOC_CENTROID)
824 return SI_PARAM_PERSP_CENTROID;
825 else
826 return SI_PARAM_PERSP_CENTER;
827 break;
828 default:
829 fprintf(stderr, "Warning: Unhandled interpolation mode.\n");
830 return -1;
831 }
832 }
833
834 /* This shouldn't be used by explicit INTERP opcodes. */
835 static LLVMValueRef get_interp_param(struct si_shader_context *si_shader_ctx,
836 unsigned param)
837 {
838 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
839 unsigned sample_param = 0;
840 LLVMValueRef default_ij, sample_ij, force_sample;
841
842 default_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, param);
843
844 /* If the shader doesn't use center/centroid, just return the parameter.
845 *
846 * If the shader only uses one set of (i,j), "si_emit_spi_ps_input" can
847 * switch between center/centroid and sample without shader changes.
848 */
849 switch (param) {
850 case SI_PARAM_PERSP_CENTROID:
851 case SI_PARAM_PERSP_CENTER:
852 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_persp)
853 return default_ij;
854
855 sample_param = SI_PARAM_PERSP_SAMPLE;
856 break;
857
858 case SI_PARAM_LINEAR_CENTROID:
859 case SI_PARAM_LINEAR_CENTER:
860 if (!si_shader_ctx->shader->selector->forces_persample_interp_for_linear)
861 return default_ij;
862
863 sample_param = SI_PARAM_LINEAR_SAMPLE;
864 break;
865
866 default:
867 return default_ij;
868 }
869
870 /* Otherwise, we have to select (i,j) based on a user data SGPR. */
871 sample_ij = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, sample_param);
872
873 /* TODO: this can be done more efficiently by switching between
874 * 2 prologs.
875 */
876 force_sample = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
877 SI_PARAM_PS_STATE_BITS);
878 force_sample = LLVMBuildTrunc(gallivm->builder, force_sample,
879 LLVMInt1TypeInContext(gallivm->context), "");
880 return LLVMBuildSelect(gallivm->builder, force_sample,
881 sample_ij, default_ij, "");
882 }
883
884 static void declare_input_fs(
885 struct radeon_llvm_context *radeon_bld,
886 unsigned input_index,
887 const struct tgsi_full_declaration *decl)
888 {
889 struct lp_build_context *base = &radeon_bld->soa.bld_base.base;
890 struct si_shader_context *si_shader_ctx =
891 si_shader_context(&radeon_bld->soa.bld_base);
892 struct si_shader *shader = si_shader_ctx->shader;
893 struct lp_build_context *uint = &radeon_bld->soa.bld_base.uint_bld;
894 struct gallivm_state *gallivm = base->gallivm;
895 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
896 LLVMValueRef main_fn = radeon_bld->main_fn;
897
898 LLVMValueRef interp_param = NULL;
899 int interp_param_idx;
900 const char * intr_name;
901
902 /* This value is:
903 * [15:0] NewPrimMask (Bit mask for each quad. It is set it the
904 * quad begins a new primitive. Bit 0 always needs
905 * to be unset)
906 * [32:16] ParamOffset
907 *
908 */
909 LLVMValueRef params = LLVMGetParam(main_fn, SI_PARAM_PRIM_MASK);
910 LLVMValueRef attr_number;
911
912 unsigned chan;
913
914 if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
915 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
916 unsigned soa_index =
917 radeon_llvm_reg_index_soa(input_index, chan);
918 radeon_bld->inputs[soa_index] =
919 LLVMGetParam(main_fn, SI_PARAM_POS_X_FLOAT + chan);
920
921 if (chan == 3)
922 /* RCP for fragcoord.w */
923 radeon_bld->inputs[soa_index] =
924 LLVMBuildFDiv(gallivm->builder,
925 lp_build_const_float(gallivm, 1.0f),
926 radeon_bld->inputs[soa_index],
927 "");
928 }
929 return;
930 }
931
932 if (decl->Semantic.Name == TGSI_SEMANTIC_FACE) {
933 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
934 LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
935 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
936 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
937 lp_build_const_float(gallivm, 0.0f);
938 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
939 lp_build_const_float(gallivm, 1.0f);
940
941 return;
942 }
943
944 shader->ps_input_param_offset[input_index] = shader->nparam++;
945 attr_number = lp_build_const_int32(gallivm,
946 shader->ps_input_param_offset[input_index]);
947
948 shader->ps_input_interpolate[input_index] = decl->Interp.Interpolate;
949 interp_param_idx = lookup_interp_param_index(decl->Interp.Interpolate,
950 decl->Interp.Location);
951 if (interp_param_idx == -1)
952 return;
953 else if (interp_param_idx)
954 interp_param = get_interp_param(si_shader_ctx, interp_param_idx);
955
956 /* fs.constant returns the param from the middle vertex, so it's not
957 * really useful for flat shading. It's meant to be used for custom
958 * interpolation (but the intrinsic can't fetch from the other two
959 * vertices).
960 *
961 * Luckily, it doesn't matter, because we rely on the FLAT_SHADE state
962 * to do the right thing. The only reason we use fs.constant is that
963 * fs.interp cannot be used on integers, because they can be equal
964 * to NaN.
965 */
966 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
967
968 if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR &&
969 si_shader_ctx->shader->key.ps.color_two_side) {
970 LLVMValueRef args[4];
971 LLVMValueRef face, is_face_positive;
972 LLVMValueRef back_attr_number =
973 lp_build_const_int32(gallivm,
974 shader->ps_input_param_offset[input_index] + 1);
975
976 face = LLVMGetParam(main_fn, SI_PARAM_FRONT_FACE);
977
978 is_face_positive = LLVMBuildFCmp(gallivm->builder,
979 LLVMRealOGT, face,
980 lp_build_const_float(gallivm, 0.0f),
981 "");
982
983 args[2] = params;
984 args[3] = interp_param;
985 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
986 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
987 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
988 LLVMValueRef front, back;
989
990 args[0] = llvm_chan;
991 args[1] = attr_number;
992 front = lp_build_intrinsic(gallivm->builder, intr_name,
993 input_type, args, args[3] ? 4 : 3,
994 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
995
996 args[1] = back_attr_number;
997 back = lp_build_intrinsic(gallivm->builder, intr_name,
998 input_type, args, args[3] ? 4 : 3,
999 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1000
1001 radeon_bld->inputs[soa_index] =
1002 LLVMBuildSelect(gallivm->builder,
1003 is_face_positive,
1004 front,
1005 back,
1006 "");
1007 }
1008
1009 shader->nparam++;
1010 } else if (decl->Semantic.Name == TGSI_SEMANTIC_FOG) {
1011 LLVMValueRef args[4];
1012
1013 args[0] = uint->zero;
1014 args[1] = attr_number;
1015 args[2] = params;
1016 args[3] = interp_param;
1017 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 0)] =
1018 lp_build_intrinsic(gallivm->builder, intr_name,
1019 input_type, args, args[3] ? 4 : 3,
1020 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1021 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 1)] =
1022 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 2)] =
1023 lp_build_const_float(gallivm, 0.0f);
1024 radeon_bld->inputs[radeon_llvm_reg_index_soa(input_index, 3)] =
1025 lp_build_const_float(gallivm, 1.0f);
1026 } else {
1027 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1028 LLVMValueRef args[4];
1029 LLVMValueRef llvm_chan = lp_build_const_int32(gallivm, chan);
1030 unsigned soa_index = radeon_llvm_reg_index_soa(input_index, chan);
1031 args[0] = llvm_chan;
1032 args[1] = attr_number;
1033 args[2] = params;
1034 args[3] = interp_param;
1035 radeon_bld->inputs[soa_index] =
1036 lp_build_intrinsic(gallivm->builder, intr_name,
1037 input_type, args, args[3] ? 4 : 3,
1038 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1039 }
1040 }
1041 }
1042
1043 static LLVMValueRef get_sample_id(struct radeon_llvm_context *radeon_bld)
1044 {
1045 return unpack_param(si_shader_context(&radeon_bld->soa.bld_base),
1046 SI_PARAM_ANCILLARY, 8, 4);
1047 }
1048
1049 /**
1050 * Load a dword from a constant buffer.
1051 */
1052 static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef resource,
1053 LLVMValueRef offset, LLVMTypeRef return_type)
1054 {
1055 LLVMValueRef args[2] = {resource, offset};
1056
1057 return lp_build_intrinsic(builder, "llvm.SI.load.const", return_type, args, 2,
1058 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1059 }
1060
1061 static LLVMValueRef load_sample_position(struct radeon_llvm_context *radeon_bld, LLVMValueRef sample_id)
1062 {
1063 struct si_shader_context *si_shader_ctx =
1064 si_shader_context(&radeon_bld->soa.bld_base);
1065 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1066 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1067 LLVMBuilderRef builder = gallivm->builder;
1068 LLVMValueRef desc = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1069 LLVMValueRef buf_index = lp_build_const_int32(gallivm, SI_DRIVER_STATE_CONST_BUF);
1070 LLVMValueRef resource = build_indexed_load_const(si_shader_ctx, desc, buf_index);
1071
1072 /* offset = sample_id * 8 (8 = 2 floats containing samplepos.xy) */
1073 LLVMValueRef offset0 = lp_build_mul_imm(uint_bld, sample_id, 8);
1074 LLVMValueRef offset1 = LLVMBuildAdd(builder, offset0, lp_build_const_int32(gallivm, 4), "");
1075
1076 LLVMValueRef pos[4] = {
1077 buffer_load_const(builder, resource, offset0, radeon_bld->soa.bld_base.base.elem_type),
1078 buffer_load_const(builder, resource, offset1, radeon_bld->soa.bld_base.base.elem_type),
1079 lp_build_const_float(gallivm, 0),
1080 lp_build_const_float(gallivm, 0)
1081 };
1082
1083 return lp_build_gather_values(gallivm, pos, 4);
1084 }
1085
1086 static void declare_system_value(
1087 struct radeon_llvm_context * radeon_bld,
1088 unsigned index,
1089 const struct tgsi_full_declaration *decl)
1090 {
1091 struct si_shader_context *si_shader_ctx =
1092 si_shader_context(&radeon_bld->soa.bld_base);
1093 struct lp_build_context *bld = &radeon_bld->soa.bld_base.base;
1094 struct lp_build_context *uint_bld = &radeon_bld->soa.bld_base.uint_bld;
1095 struct gallivm_state *gallivm = &radeon_bld->gallivm;
1096 LLVMValueRef value = 0;
1097
1098 switch (decl->Semantic.Name) {
1099 case TGSI_SEMANTIC_INSTANCEID:
1100 value = LLVMGetParam(radeon_bld->main_fn,
1101 si_shader_ctx->param_instance_id);
1102 break;
1103
1104 case TGSI_SEMANTIC_VERTEXID:
1105 value = LLVMBuildAdd(gallivm->builder,
1106 LLVMGetParam(radeon_bld->main_fn,
1107 si_shader_ctx->param_vertex_id),
1108 LLVMGetParam(radeon_bld->main_fn,
1109 SI_PARAM_BASE_VERTEX), "");
1110 break;
1111
1112 case TGSI_SEMANTIC_VERTEXID_NOBASE:
1113 value = LLVMGetParam(radeon_bld->main_fn,
1114 si_shader_ctx->param_vertex_id);
1115 break;
1116
1117 case TGSI_SEMANTIC_BASEVERTEX:
1118 value = LLVMGetParam(radeon_bld->main_fn,
1119 SI_PARAM_BASE_VERTEX);
1120 break;
1121
1122 case TGSI_SEMANTIC_INVOCATIONID:
1123 if (si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL)
1124 value = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1125 else if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY)
1126 value = LLVMGetParam(radeon_bld->main_fn,
1127 SI_PARAM_GS_INSTANCE_ID);
1128 else
1129 assert(!"INVOCATIONID not implemented");
1130 break;
1131
1132 case TGSI_SEMANTIC_SAMPLEID:
1133 value = get_sample_id(radeon_bld);
1134 break;
1135
1136 case TGSI_SEMANTIC_SAMPLEPOS:
1137 value = load_sample_position(radeon_bld, get_sample_id(radeon_bld));
1138 break;
1139
1140 case TGSI_SEMANTIC_SAMPLEMASK:
1141 /* Smoothing isn't MSAA in GL, but it's MSAA in hardware.
1142 * Therefore, force gl_SampleMaskIn to 1 for GL. */
1143 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
1144 value = uint_bld->one;
1145 else
1146 value = LLVMGetParam(radeon_bld->main_fn, SI_PARAM_SAMPLE_COVERAGE);
1147 break;
1148
1149 case TGSI_SEMANTIC_TESSCOORD:
1150 {
1151 LLVMValueRef coord[4] = {
1152 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_u),
1153 LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_tes_v),
1154 bld->zero,
1155 bld->zero
1156 };
1157
1158 /* For triangles, the vector should be (u, v, 1-u-v). */
1159 if (si_shader_ctx->shader->selector->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] ==
1160 PIPE_PRIM_TRIANGLES)
1161 coord[2] = lp_build_sub(bld, bld->one,
1162 lp_build_add(bld, coord[0], coord[1]));
1163
1164 value = lp_build_gather_values(gallivm, coord, 4);
1165 break;
1166 }
1167
1168 case TGSI_SEMANTIC_VERTICESIN:
1169 value = unpack_param(si_shader_ctx, SI_PARAM_TCS_OUT_LAYOUT, 26, 6);
1170 break;
1171
1172 case TGSI_SEMANTIC_TESSINNER:
1173 case TGSI_SEMANTIC_TESSOUTER:
1174 {
1175 LLVMValueRef dw_addr;
1176 int param = si_shader_io_get_unique_index(decl->Semantic.Name, 0);
1177
1178 dw_addr = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1179 dw_addr = LLVMBuildAdd(gallivm->builder, dw_addr,
1180 lp_build_const_int32(gallivm, param * 4), "");
1181
1182 value = lds_load(&radeon_bld->soa.bld_base, TGSI_TYPE_FLOAT,
1183 ~0, dw_addr);
1184 break;
1185 }
1186
1187 case TGSI_SEMANTIC_PRIMID:
1188 value = get_primitive_id(&radeon_bld->soa.bld_base, 0);
1189 break;
1190
1191 default:
1192 assert(!"unknown system value");
1193 return;
1194 }
1195
1196 radeon_bld->system_values[index] = value;
1197 }
1198
1199 static LLVMValueRef fetch_constant(
1200 struct lp_build_tgsi_context * bld_base,
1201 const struct tgsi_full_src_register *reg,
1202 enum tgsi_opcode_type type,
1203 unsigned swizzle)
1204 {
1205 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1206 struct lp_build_context * base = &bld_base->base;
1207 const struct tgsi_ind_register *ireg = &reg->Indirect;
1208 unsigned buf, idx;
1209
1210 LLVMValueRef addr, bufp;
1211 LLVMValueRef result;
1212
1213 if (swizzle == LP_CHAN_ALL) {
1214 unsigned chan;
1215 LLVMValueRef values[4];
1216 for (chan = 0; chan < TGSI_NUM_CHANNELS; ++chan)
1217 values[chan] = fetch_constant(bld_base, reg, type, chan);
1218
1219 return lp_build_gather_values(bld_base->base.gallivm, values, 4);
1220 }
1221
1222 buf = reg->Register.Dimension ? reg->Dimension.Index : 0;
1223 idx = reg->Register.Index * 4 + swizzle;
1224
1225 if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
1226 if (type != TGSI_TYPE_DOUBLE)
1227 return bitcast(bld_base, type, si_shader_ctx->constants[buf][idx]);
1228 else {
1229 return radeon_llvm_emit_fetch_double(bld_base,
1230 si_shader_ctx->constants[buf][idx],
1231 si_shader_ctx->constants[buf][idx + 1]);
1232 }
1233 }
1234
1235 if (reg->Register.Dimension && reg->Dimension.Indirect) {
1236 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1237 LLVMValueRef index;
1238 index = get_indirect_index(si_shader_ctx, &reg->DimIndirect,
1239 reg->Dimension.Index);
1240 bufp = build_indexed_load_const(si_shader_ctx, ptr, index);
1241 } else
1242 bufp = si_shader_ctx->const_buffers[buf];
1243
1244 addr = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle];
1245 addr = LLVMBuildLoad(base->gallivm->builder, addr, "load addr reg");
1246 addr = lp_build_mul_imm(&bld_base->uint_bld, addr, 16);
1247 addr = lp_build_add(&bld_base->uint_bld, addr,
1248 lp_build_const_int32(base->gallivm, idx * 4));
1249
1250 result = buffer_load_const(base->gallivm->builder, bufp,
1251 addr, bld_base->base.elem_type);
1252
1253 if (type != TGSI_TYPE_DOUBLE)
1254 result = bitcast(bld_base, type, result);
1255 else {
1256 LLVMValueRef addr2, result2;
1257 addr2 = si_shader_ctx->radeon_bld.soa.addr[ireg->Index][ireg->Swizzle + 1];
1258 addr2 = LLVMBuildLoad(base->gallivm->builder, addr2, "load addr reg2");
1259 addr2 = lp_build_mul_imm(&bld_base->uint_bld, addr2, 16);
1260 addr2 = lp_build_add(&bld_base->uint_bld, addr2,
1261 lp_build_const_int32(base->gallivm, idx * 4));
1262
1263 result2 = buffer_load_const(base->gallivm->builder, si_shader_ctx->const_buffers[buf],
1264 addr2, bld_base->base.elem_type);
1265
1266 result = radeon_llvm_emit_fetch_double(bld_base,
1267 result, result2);
1268 }
1269 return result;
1270 }
1271
1272 /* Initialize arguments for the shader export intrinsic */
1273 static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
1274 LLVMValueRef *values,
1275 unsigned target,
1276 LLVMValueRef *args)
1277 {
1278 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1279 struct lp_build_context *uint =
1280 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1281 struct lp_build_context *base = &bld_base->base;
1282 unsigned compressed = 0;
1283 unsigned chan;
1284
1285 /* XXX: This controls which components of the output
1286 * registers actually get exported. (e.g bit 0 means export
1287 * X component, bit 1 means export Y component, etc.) I'm
1288 * hard coding this to 0xf for now. In the future, we might
1289 * want to do something else.
1290 */
1291 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1292
1293 /* Specify whether the EXEC mask represents the valid mask */
1294 args[1] = uint->zero;
1295
1296 /* Specify whether this is the last export */
1297 args[2] = uint->zero;
1298
1299 /* Specify the target we are exporting */
1300 args[3] = lp_build_const_int32(base->gallivm, target);
1301
1302 if (si_shader_ctx->type == TGSI_PROCESSOR_FRAGMENT) {
1303 int cbuf = target - V_008DFC_SQ_EXP_MRT;
1304
1305 if (cbuf >= 0 && cbuf < 8)
1306 compressed = (si_shader_ctx->shader->key.ps.export_16bpc >> cbuf) & 0x1;
1307 }
1308
1309 /* Set COMPR flag */
1310 args[4] = compressed ? uint->one : uint->zero;
1311
1312 if (compressed) {
1313 /* Pixel shader needs to pack output values before export */
1314 for (chan = 0; chan < 2; chan++) {
1315 LLVMValueRef pack_args[2] = {
1316 values[2 * chan],
1317 values[2 * chan + 1]
1318 };
1319 LLVMValueRef packed;
1320
1321 packed = lp_build_intrinsic(base->gallivm->builder,
1322 "llvm.SI.packf16",
1323 LLVMInt32TypeInContext(base->gallivm->context),
1324 pack_args, 2,
1325 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
1326 args[chan + 5] =
1327 LLVMBuildBitCast(base->gallivm->builder,
1328 packed,
1329 LLVMFloatTypeInContext(base->gallivm->context),
1330 "");
1331 args[chan + 7] = base->undef;
1332 }
1333 } else
1334 memcpy(&args[5], values, sizeof(values[0]) * 4);
1335 }
1336
1337 static void si_alpha_test(struct lp_build_tgsi_context *bld_base,
1338 LLVMValueRef alpha)
1339 {
1340 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1341 struct gallivm_state *gallivm = bld_base->base.gallivm;
1342
1343 if (si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_NEVER) {
1344 LLVMValueRef alpha_ref = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1345 SI_PARAM_ALPHA_REF);
1346
1347 LLVMValueRef alpha_pass =
1348 lp_build_cmp(&bld_base->base,
1349 si_shader_ctx->shader->key.ps.alpha_func,
1350 alpha, alpha_ref);
1351 LLVMValueRef arg =
1352 lp_build_select(&bld_base->base,
1353 alpha_pass,
1354 lp_build_const_float(gallivm, 1.0f),
1355 lp_build_const_float(gallivm, -1.0f));
1356
1357 lp_build_intrinsic(gallivm->builder,
1358 "llvm.AMDGPU.kill",
1359 LLVMVoidTypeInContext(gallivm->context),
1360 &arg, 1, 0);
1361 } else {
1362 lp_build_intrinsic(gallivm->builder,
1363 "llvm.AMDGPU.kilp",
1364 LLVMVoidTypeInContext(gallivm->context),
1365 NULL, 0, 0);
1366 }
1367 }
1368
1369 static LLVMValueRef si_scale_alpha_by_sample_mask(struct lp_build_tgsi_context *bld_base,
1370 LLVMValueRef alpha)
1371 {
1372 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1373 struct gallivm_state *gallivm = bld_base->base.gallivm;
1374 LLVMValueRef coverage;
1375
1376 /* alpha = alpha * popcount(coverage) / SI_NUM_SMOOTH_AA_SAMPLES */
1377 coverage = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1378 SI_PARAM_SAMPLE_COVERAGE);
1379 coverage = bitcast(bld_base, TGSI_TYPE_SIGNED, coverage);
1380
1381 coverage = lp_build_intrinsic(gallivm->builder, "llvm.ctpop.i32",
1382 bld_base->int_bld.elem_type,
1383 &coverage, 1, LLVMReadNoneAttribute);
1384
1385 coverage = LLVMBuildUIToFP(gallivm->builder, coverage,
1386 bld_base->base.elem_type, "");
1387
1388 coverage = LLVMBuildFMul(gallivm->builder, coverage,
1389 lp_build_const_float(gallivm,
1390 1.0 / SI_NUM_SMOOTH_AA_SAMPLES), "");
1391
1392 return LLVMBuildFMul(gallivm->builder, alpha, coverage, "");
1393 }
1394
1395 static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context * bld_base,
1396 LLVMValueRef (*pos)[9], LLVMValueRef *out_elts)
1397 {
1398 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1399 struct lp_build_context *base = &bld_base->base;
1400 struct lp_build_context *uint = &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1401 unsigned reg_index;
1402 unsigned chan;
1403 unsigned const_chan;
1404 LLVMValueRef base_elt;
1405 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
1406 LLVMValueRef constbuf_index = lp_build_const_int32(base->gallivm, SI_DRIVER_STATE_CONST_BUF);
1407 LLVMValueRef const_resource = build_indexed_load_const(si_shader_ctx, ptr, constbuf_index);
1408
1409 for (reg_index = 0; reg_index < 2; reg_index ++) {
1410 LLVMValueRef *args = pos[2 + reg_index];
1411
1412 args[5] =
1413 args[6] =
1414 args[7] =
1415 args[8] = lp_build_const_float(base->gallivm, 0.0f);
1416
1417 /* Compute dot products of position and user clip plane vectors */
1418 for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
1419 for (const_chan = 0; const_chan < TGSI_NUM_CHANNELS; const_chan++) {
1420 args[1] = lp_build_const_int32(base->gallivm,
1421 ((reg_index * 4 + chan) * 4 +
1422 const_chan) * 4);
1423 base_elt = buffer_load_const(base->gallivm->builder, const_resource,
1424 args[1], base->elem_type);
1425 args[5 + chan] =
1426 lp_build_add(base, args[5 + chan],
1427 lp_build_mul(base, base_elt,
1428 out_elts[const_chan]));
1429 }
1430 }
1431
1432 args[0] = lp_build_const_int32(base->gallivm, 0xf);
1433 args[1] = uint->zero;
1434 args[2] = uint->zero;
1435 args[3] = lp_build_const_int32(base->gallivm,
1436 V_008DFC_SQ_EXP_POS + 2 + reg_index);
1437 args[4] = uint->zero;
1438 }
1439 }
1440
1441 static void si_dump_streamout(struct pipe_stream_output_info *so)
1442 {
1443 unsigned i;
1444
1445 if (so->num_outputs)
1446 fprintf(stderr, "STREAMOUT\n");
1447
1448 for (i = 0; i < so->num_outputs; i++) {
1449 unsigned mask = ((1 << so->output[i].num_components) - 1) <<
1450 so->output[i].start_component;
1451 fprintf(stderr, " %i: BUF%i[%i..%i] <- OUT[%i].%s%s%s%s\n",
1452 i, so->output[i].output_buffer,
1453 so->output[i].dst_offset, so->output[i].dst_offset + so->output[i].num_components - 1,
1454 so->output[i].register_index,
1455 mask & 1 ? "x" : "",
1456 mask & 2 ? "y" : "",
1457 mask & 4 ? "z" : "",
1458 mask & 8 ? "w" : "");
1459 }
1460 }
1461
1462 /* TBUFFER_STORE_FORMAT_{X,XY,XYZ,XYZW} <- the suffix is selected by num_channels=1..4.
1463 * The type of vdata must be one of i32 (num_channels=1), v2i32 (num_channels=2),
1464 * or v4i32 (num_channels=3,4). */
1465 static void build_tbuffer_store(struct si_shader_context *shader,
1466 LLVMValueRef rsrc,
1467 LLVMValueRef vdata,
1468 unsigned num_channels,
1469 LLVMValueRef vaddr,
1470 LLVMValueRef soffset,
1471 unsigned inst_offset,
1472 unsigned dfmt,
1473 unsigned nfmt,
1474 unsigned offen,
1475 unsigned idxen,
1476 unsigned glc,
1477 unsigned slc,
1478 unsigned tfe)
1479 {
1480 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1481 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1482 LLVMValueRef args[] = {
1483 rsrc,
1484 vdata,
1485 LLVMConstInt(i32, num_channels, 0),
1486 vaddr,
1487 soffset,
1488 LLVMConstInt(i32, inst_offset, 0),
1489 LLVMConstInt(i32, dfmt, 0),
1490 LLVMConstInt(i32, nfmt, 0),
1491 LLVMConstInt(i32, offen, 0),
1492 LLVMConstInt(i32, idxen, 0),
1493 LLVMConstInt(i32, glc, 0),
1494 LLVMConstInt(i32, slc, 0),
1495 LLVMConstInt(i32, tfe, 0)
1496 };
1497
1498 /* The instruction offset field has 12 bits */
1499 assert(offen || inst_offset < (1 << 12));
1500
1501 /* The intrinsic is overloaded, we need to add a type suffix for overloading to work. */
1502 unsigned func = CLAMP(num_channels, 1, 3) - 1;
1503 const char *types[] = {"i32", "v2i32", "v4i32"};
1504 char name[256];
1505 snprintf(name, sizeof(name), "llvm.SI.tbuffer.store.%s", types[func]);
1506
1507 lp_build_intrinsic(gallivm->builder, name,
1508 LLVMVoidTypeInContext(gallivm->context),
1509 args, Elements(args), 0);
1510 }
1511
1512 static void build_tbuffer_store_dwords(struct si_shader_context *shader,
1513 LLVMValueRef rsrc,
1514 LLVMValueRef vdata,
1515 unsigned num_channels,
1516 LLVMValueRef vaddr,
1517 LLVMValueRef soffset,
1518 unsigned inst_offset)
1519 {
1520 static unsigned dfmt[] = {
1521 V_008F0C_BUF_DATA_FORMAT_32,
1522 V_008F0C_BUF_DATA_FORMAT_32_32,
1523 V_008F0C_BUF_DATA_FORMAT_32_32_32,
1524 V_008F0C_BUF_DATA_FORMAT_32_32_32_32
1525 };
1526 assert(num_channels >= 1 && num_channels <= 4);
1527
1528 build_tbuffer_store(shader, rsrc, vdata, num_channels, vaddr, soffset,
1529 inst_offset, dfmt[num_channels-1],
1530 V_008F0C_BUF_NUM_FORMAT_UINT, 1, 0, 1, 1, 0);
1531 }
1532
1533 /* On SI, the vertex shader is responsible for writing streamout data
1534 * to buffers. */
1535 static void si_llvm_emit_streamout(struct si_shader_context *shader,
1536 struct si_shader_output_values *outputs,
1537 unsigned noutput)
1538 {
1539 struct pipe_stream_output_info *so = &shader->shader->selector->so;
1540 struct gallivm_state *gallivm = &shader->radeon_bld.gallivm;
1541 LLVMBuilderRef builder = gallivm->builder;
1542 int i, j;
1543 struct lp_build_if_state if_ctx;
1544
1545 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1546
1547 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1548 LLVMValueRef so_vtx_count =
1549 unpack_param(shader, shader->param_streamout_config, 16, 7);
1550
1551 LLVMValueRef tid = lp_build_intrinsic(builder, "llvm.SI.tid", i32,
1552 NULL, 0, LLVMReadNoneAttribute);
1553
1554 /* can_emit = tid < so_vtx_count; */
1555 LLVMValueRef can_emit =
1556 LLVMBuildICmp(builder, LLVMIntULT, tid, so_vtx_count, "");
1557
1558 LLVMValueRef stream_id =
1559 unpack_param(shader, shader->param_streamout_config, 24, 2);
1560
1561 /* Emit the streamout code conditionally. This actually avoids
1562 * out-of-bounds buffer access. The hw tells us via the SGPR
1563 * (so_vtx_count) which threads are allowed to emit streamout data. */
1564 lp_build_if(&if_ctx, gallivm, can_emit);
1565 {
1566 /* The buffer offset is computed as follows:
1567 * ByteOffset = streamout_offset[buffer_id]*4 +
1568 * (streamout_write_index + thread_id)*stride[buffer_id] +
1569 * attrib_offset
1570 */
1571
1572 LLVMValueRef so_write_index =
1573 LLVMGetParam(shader->radeon_bld.main_fn,
1574 shader->param_streamout_write_index);
1575
1576 /* Compute (streamout_write_index + thread_id). */
1577 so_write_index = LLVMBuildAdd(builder, so_write_index, tid, "");
1578
1579 /* Compute the write offset for each enabled buffer. */
1580 LLVMValueRef so_write_offset[4] = {};
1581 for (i = 0; i < 4; i++) {
1582 if (!so->stride[i])
1583 continue;
1584
1585 LLVMValueRef so_offset = LLVMGetParam(shader->radeon_bld.main_fn,
1586 shader->param_streamout_offset[i]);
1587 so_offset = LLVMBuildMul(builder, so_offset, LLVMConstInt(i32, 4, 0), "");
1588
1589 so_write_offset[i] = LLVMBuildMul(builder, so_write_index,
1590 LLVMConstInt(i32, so->stride[i]*4, 0), "");
1591 so_write_offset[i] = LLVMBuildAdd(builder, so_write_offset[i], so_offset, "");
1592 }
1593
1594 /* Write streamout data. */
1595 for (i = 0; i < so->num_outputs; i++) {
1596 unsigned buf_idx = so->output[i].output_buffer;
1597 unsigned reg = so->output[i].register_index;
1598 unsigned start = so->output[i].start_component;
1599 unsigned num_comps = so->output[i].num_components;
1600 unsigned stream = so->output[i].stream;
1601 LLVMValueRef out[4];
1602 struct lp_build_if_state if_ctx_stream;
1603
1604 assert(num_comps && num_comps <= 4);
1605 if (!num_comps || num_comps > 4)
1606 continue;
1607
1608 if (reg >= noutput)
1609 continue;
1610
1611 /* Load the output as int. */
1612 for (j = 0; j < num_comps; j++) {
1613 out[j] = LLVMBuildBitCast(builder,
1614 outputs[reg].values[start+j],
1615 i32, "");
1616 }
1617
1618 /* Pack the output. */
1619 LLVMValueRef vdata = NULL;
1620
1621 switch (num_comps) {
1622 case 1: /* as i32 */
1623 vdata = out[0];
1624 break;
1625 case 2: /* as v2i32 */
1626 case 3: /* as v4i32 (aligned to 4) */
1627 case 4: /* as v4i32 */
1628 vdata = LLVMGetUndef(LLVMVectorType(i32, util_next_power_of_two(num_comps)));
1629 for (j = 0; j < num_comps; j++) {
1630 vdata = LLVMBuildInsertElement(builder, vdata, out[j],
1631 LLVMConstInt(i32, j, 0), "");
1632 }
1633 break;
1634 }
1635
1636 LLVMValueRef can_emit_stream =
1637 LLVMBuildICmp(builder, LLVMIntEQ,
1638 stream_id,
1639 lp_build_const_int32(gallivm, stream), "");
1640
1641 lp_build_if(&if_ctx_stream, gallivm, can_emit_stream);
1642 build_tbuffer_store_dwords(shader, shader->so_buffers[buf_idx],
1643 vdata, num_comps,
1644 so_write_offset[buf_idx],
1645 LLVMConstInt(i32, 0, 0),
1646 so->output[i].dst_offset*4);
1647 lp_build_endif(&if_ctx_stream);
1648 }
1649 }
1650 lp_build_endif(&if_ctx);
1651 }
1652
1653
1654 /* Generate export instructions for hardware VS shader stage */
1655 static void si_llvm_export_vs(struct lp_build_tgsi_context *bld_base,
1656 struct si_shader_output_values *outputs,
1657 unsigned noutput)
1658 {
1659 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
1660 struct si_shader * shader = si_shader_ctx->shader;
1661 struct lp_build_context * base = &bld_base->base;
1662 struct lp_build_context * uint =
1663 &si_shader_ctx->radeon_bld.soa.bld_base.uint_bld;
1664 LLVMValueRef args[9];
1665 LLVMValueRef pos_args[4][9] = { { 0 } };
1666 LLVMValueRef psize_value = NULL, edgeflag_value = NULL, layer_value = NULL, viewport_index_value = NULL;
1667 unsigned semantic_name, semantic_index;
1668 unsigned target;
1669 unsigned param_count = 0;
1670 unsigned pos_idx;
1671 int i;
1672
1673 if (outputs && si_shader_ctx->shader->selector->so.num_outputs) {
1674 si_llvm_emit_streamout(si_shader_ctx, outputs, noutput);
1675 }
1676
1677 for (i = 0; i < noutput; i++) {
1678 semantic_name = outputs[i].name;
1679 semantic_index = outputs[i].sid;
1680
1681 handle_semantic:
1682 /* Select the correct target */
1683 switch(semantic_name) {
1684 case TGSI_SEMANTIC_PSIZE:
1685 psize_value = outputs[i].values[0];
1686 continue;
1687 case TGSI_SEMANTIC_EDGEFLAG:
1688 edgeflag_value = outputs[i].values[0];
1689 continue;
1690 case TGSI_SEMANTIC_LAYER:
1691 layer_value = outputs[i].values[0];
1692 semantic_name = TGSI_SEMANTIC_GENERIC;
1693 goto handle_semantic;
1694 case TGSI_SEMANTIC_VIEWPORT_INDEX:
1695 viewport_index_value = outputs[i].values[0];
1696 semantic_name = TGSI_SEMANTIC_GENERIC;
1697 goto handle_semantic;
1698 case TGSI_SEMANTIC_POSITION:
1699 target = V_008DFC_SQ_EXP_POS;
1700 break;
1701 case TGSI_SEMANTIC_COLOR:
1702 case TGSI_SEMANTIC_BCOLOR:
1703 target = V_008DFC_SQ_EXP_PARAM + param_count;
1704 shader->vs_output_param_offset[i] = param_count;
1705 param_count++;
1706 break;
1707 case TGSI_SEMANTIC_CLIPDIST:
1708 target = V_008DFC_SQ_EXP_POS + 2 + semantic_index;
1709 break;
1710 case TGSI_SEMANTIC_CLIPVERTEX:
1711 si_llvm_emit_clipvertex(bld_base, pos_args, outputs[i].values);
1712 continue;
1713 case TGSI_SEMANTIC_PRIMID:
1714 case TGSI_SEMANTIC_FOG:
1715 case TGSI_SEMANTIC_TEXCOORD:
1716 case TGSI_SEMANTIC_GENERIC:
1717 target = V_008DFC_SQ_EXP_PARAM + param_count;
1718 shader->vs_output_param_offset[i] = param_count;
1719 param_count++;
1720 break;
1721 default:
1722 target = 0;
1723 fprintf(stderr,
1724 "Warning: SI unhandled vs output type:%d\n",
1725 semantic_name);
1726 }
1727
1728 si_llvm_init_export_args(bld_base, outputs[i].values, target, args);
1729
1730 if (target >= V_008DFC_SQ_EXP_POS &&
1731 target <= (V_008DFC_SQ_EXP_POS + 3)) {
1732 memcpy(pos_args[target - V_008DFC_SQ_EXP_POS],
1733 args, sizeof(args));
1734 } else {
1735 lp_build_intrinsic(base->gallivm->builder,
1736 "llvm.SI.export",
1737 LLVMVoidTypeInContext(base->gallivm->context),
1738 args, 9, 0);
1739 }
1740
1741 if (semantic_name == TGSI_SEMANTIC_CLIPDIST) {
1742 semantic_name = TGSI_SEMANTIC_GENERIC;
1743 goto handle_semantic;
1744 }
1745 }
1746
1747 shader->nr_param_exports = param_count;
1748
1749 /* We need to add the position output manually if it's missing. */
1750 if (!pos_args[0][0]) {
1751 pos_args[0][0] = lp_build_const_int32(base->gallivm, 0xf); /* writemask */
1752 pos_args[0][1] = uint->zero; /* EXEC mask */
1753 pos_args[0][2] = uint->zero; /* last export? */
1754 pos_args[0][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS);
1755 pos_args[0][4] = uint->zero; /* COMPR flag */
1756 pos_args[0][5] = base->zero; /* X */
1757 pos_args[0][6] = base->zero; /* Y */
1758 pos_args[0][7] = base->zero; /* Z */
1759 pos_args[0][8] = base->one; /* W */
1760 }
1761
1762 /* Write the misc vector (point size, edgeflag, layer, viewport). */
1763 if (shader->selector->info.writes_psize ||
1764 shader->selector->info.writes_edgeflag ||
1765 shader->selector->info.writes_viewport_index ||
1766 shader->selector->info.writes_layer) {
1767 pos_args[1][0] = lp_build_const_int32(base->gallivm, /* writemask */
1768 shader->selector->info.writes_psize |
1769 (shader->selector->info.writes_edgeflag << 1) |
1770 (shader->selector->info.writes_layer << 2) |
1771 (shader->selector->info.writes_viewport_index << 3));
1772 pos_args[1][1] = uint->zero; /* EXEC mask */
1773 pos_args[1][2] = uint->zero; /* last export? */
1774 pos_args[1][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + 1);
1775 pos_args[1][4] = uint->zero; /* COMPR flag */
1776 pos_args[1][5] = base->zero; /* X */
1777 pos_args[1][6] = base->zero; /* Y */
1778 pos_args[1][7] = base->zero; /* Z */
1779 pos_args[1][8] = base->zero; /* W */
1780
1781 if (shader->selector->info.writes_psize)
1782 pos_args[1][5] = psize_value;
1783
1784 if (shader->selector->info.writes_edgeflag) {
1785 /* The output is a float, but the hw expects an integer
1786 * with the first bit containing the edge flag. */
1787 edgeflag_value = LLVMBuildFPToUI(base->gallivm->builder,
1788 edgeflag_value,
1789 bld_base->uint_bld.elem_type, "");
1790 edgeflag_value = lp_build_min(&bld_base->int_bld,
1791 edgeflag_value,
1792 bld_base->int_bld.one);
1793
1794 /* The LLVM intrinsic expects a float. */
1795 pos_args[1][6] = LLVMBuildBitCast(base->gallivm->builder,
1796 edgeflag_value,
1797 base->elem_type, "");
1798 }
1799
1800 if (shader->selector->info.writes_layer)
1801 pos_args[1][7] = layer_value;
1802
1803 if (shader->selector->info.writes_viewport_index)
1804 pos_args[1][8] = viewport_index_value;
1805 }
1806
1807 for (i = 0; i < 4; i++)
1808 if (pos_args[i][0])
1809 shader->nr_pos_exports++;
1810
1811 pos_idx = 0;
1812 for (i = 0; i < 4; i++) {
1813 if (!pos_args[i][0])
1814 continue;
1815
1816 /* Specify the target we are exporting */
1817 pos_args[i][3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_POS + pos_idx++);
1818
1819 if (pos_idx == shader->nr_pos_exports)
1820 /* Specify that this is the last export */
1821 pos_args[i][2] = uint->one;
1822
1823 lp_build_intrinsic(base->gallivm->builder,
1824 "llvm.SI.export",
1825 LLVMVoidTypeInContext(base->gallivm->context),
1826 pos_args[i], 9, 0);
1827 }
1828 }
1829
1830 /* This only writes the tessellation factor levels. */
1831 static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
1832 {
1833 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1834 struct gallivm_state *gallivm = bld_base->base.gallivm;
1835 struct si_shader *shader = si_shader_ctx->shader;
1836 unsigned tess_inner_index, tess_outer_index;
1837 LLVMValueRef lds_base, lds_inner, lds_outer;
1838 LLVMValueRef tf_base, rel_patch_id, byteoffset, buffer, rw_buffers;
1839 LLVMValueRef out[6], vec0, vec1, invocation_id;
1840 unsigned stride, outer_comps, inner_comps, i;
1841 struct lp_build_if_state if_ctx;
1842
1843 invocation_id = unpack_param(si_shader_ctx, SI_PARAM_REL_IDS, 8, 5);
1844
1845 /* Do this only for invocation 0, because the tess levels are per-patch,
1846 * not per-vertex.
1847 *
1848 * This can't jump, because invocation 0 executes this. It should
1849 * at least mask out the loads and stores for other invocations.
1850 */
1851 lp_build_if(&if_ctx, gallivm,
1852 LLVMBuildICmp(gallivm->builder, LLVMIntEQ,
1853 invocation_id, bld_base->uint_bld.zero, ""));
1854
1855 /* Determine the layout of one tess factor element in the buffer. */
1856 switch (shader->key.tcs.prim_mode) {
1857 case PIPE_PRIM_LINES:
1858 stride = 2; /* 2 dwords, 1 vec2 store */
1859 outer_comps = 2;
1860 inner_comps = 0;
1861 break;
1862 case PIPE_PRIM_TRIANGLES:
1863 stride = 4; /* 4 dwords, 1 vec4 store */
1864 outer_comps = 3;
1865 inner_comps = 1;
1866 break;
1867 case PIPE_PRIM_QUADS:
1868 stride = 6; /* 6 dwords, 2 stores (vec4 + vec2) */
1869 outer_comps = 4;
1870 inner_comps = 2;
1871 break;
1872 default:
1873 assert(0);
1874 return;
1875 }
1876
1877 /* Load tess_inner and tess_outer from LDS.
1878 * Any invocation can write them, so we can't get them from a temporary.
1879 */
1880 tess_inner_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSINNER, 0);
1881 tess_outer_index = si_shader_io_get_unique_index(TGSI_SEMANTIC_TESSOUTER, 0);
1882
1883 lds_base = get_tcs_out_current_patch_data_offset(si_shader_ctx);
1884 lds_inner = LLVMBuildAdd(gallivm->builder, lds_base,
1885 lp_build_const_int32(gallivm,
1886 tess_inner_index * 4), "");
1887 lds_outer = LLVMBuildAdd(gallivm->builder, lds_base,
1888 lp_build_const_int32(gallivm,
1889 tess_outer_index * 4), "");
1890
1891 for (i = 0; i < outer_comps; i++)
1892 out[i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_outer);
1893 for (i = 0; i < inner_comps; i++)
1894 out[outer_comps+i] = lds_load(bld_base, TGSI_TYPE_SIGNED, i, lds_inner);
1895
1896 /* Convert the outputs to vectors for stores. */
1897 vec0 = lp_build_gather_values(gallivm, out, MIN2(stride, 4));
1898 vec1 = NULL;
1899
1900 if (stride > 4)
1901 vec1 = lp_build_gather_values(gallivm, out+4, stride - 4);
1902
1903 /* Get the buffer. */
1904 rw_buffers = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1905 SI_PARAM_RW_BUFFERS);
1906 buffer = build_indexed_load_const(si_shader_ctx, rw_buffers,
1907 lp_build_const_int32(gallivm, SI_RING_TESS_FACTOR));
1908
1909 /* Get the offset. */
1910 tf_base = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1911 SI_PARAM_TESS_FACTOR_OFFSET);
1912 rel_patch_id = get_rel_patch_id(si_shader_ctx);
1913 byteoffset = LLVMBuildMul(gallivm->builder, rel_patch_id,
1914 lp_build_const_int32(gallivm, 4 * stride), "");
1915
1916 /* Store the outputs. */
1917 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec0,
1918 MIN2(stride, 4), byteoffset, tf_base, 0);
1919 if (vec1)
1920 build_tbuffer_store_dwords(si_shader_ctx, buffer, vec1,
1921 stride - 4, byteoffset, tf_base, 16);
1922 lp_build_endif(&if_ctx);
1923 }
1924
1925 static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context * bld_base)
1926 {
1927 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1928 struct si_shader *shader = si_shader_ctx->shader;
1929 struct tgsi_shader_info *info = &shader->selector->info;
1930 struct gallivm_state *gallivm = bld_base->base.gallivm;
1931 unsigned i, chan;
1932 LLVMValueRef vertex_id = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1933 si_shader_ctx->param_rel_auto_id);
1934 LLVMValueRef vertex_dw_stride =
1935 unpack_param(si_shader_ctx, SI_PARAM_LS_OUT_LAYOUT, 13, 8);
1936 LLVMValueRef base_dw_addr = LLVMBuildMul(gallivm->builder, vertex_id,
1937 vertex_dw_stride, "");
1938
1939 /* Write outputs to LDS. The next shader (TCS aka HS) will read
1940 * its inputs from it. */
1941 for (i = 0; i < info->num_outputs; i++) {
1942 LLVMValueRef *out_ptr = si_shader_ctx->radeon_bld.soa.outputs[i];
1943 unsigned name = info->output_semantic_name[i];
1944 unsigned index = info->output_semantic_index[i];
1945 int param = si_shader_io_get_unique_index(name, index);
1946 LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr,
1947 lp_build_const_int32(gallivm, param * 4), "");
1948
1949 for (chan = 0; chan < 4; chan++) {
1950 lds_store(bld_base, chan, dw_addr,
1951 LLVMBuildLoad(gallivm->builder, out_ptr[chan], ""));
1952 }
1953 }
1954 }
1955
1956 static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context * bld_base)
1957 {
1958 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1959 struct gallivm_state *gallivm = bld_base->base.gallivm;
1960 struct si_shader *es = si_shader_ctx->shader;
1961 struct tgsi_shader_info *info = &es->selector->info;
1962 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
1963 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
1964 si_shader_ctx->param_es2gs_offset);
1965 unsigned chan;
1966 int i;
1967
1968 for (i = 0; i < info->num_outputs; i++) {
1969 LLVMValueRef *out_ptr =
1970 si_shader_ctx->radeon_bld.soa.outputs[i];
1971 int param_index;
1972
1973 if (info->output_semantic_name[i] == TGSI_SEMANTIC_VIEWPORT_INDEX ||
1974 info->output_semantic_name[i] == TGSI_SEMANTIC_LAYER)
1975 continue;
1976
1977 param_index = si_shader_io_get_unique_index(info->output_semantic_name[i],
1978 info->output_semantic_index[i]);
1979
1980 for (chan = 0; chan < 4; chan++) {
1981 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
1982 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
1983
1984 build_tbuffer_store(si_shader_ctx,
1985 si_shader_ctx->esgs_ring,
1986 out_val, 1,
1987 LLVMGetUndef(i32), soffset,
1988 (4 * param_index + chan) * 4,
1989 V_008F0C_BUF_DATA_FORMAT_32,
1990 V_008F0C_BUF_NUM_FORMAT_UINT,
1991 0, 0, 1, 1, 0);
1992 }
1993 }
1994 }
1995
1996 static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
1997 {
1998 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
1999 struct gallivm_state *gallivm = bld_base->base.gallivm;
2000 LLVMValueRef args[2];
2001
2002 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_NOP | SENDMSG_GS_DONE);
2003 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
2004 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
2005 LLVMVoidTypeInContext(gallivm->context), args, 2,
2006 LLVMNoUnwindAttribute);
2007 }
2008
2009 static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context * bld_base)
2010 {
2011 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2012 struct gallivm_state *gallivm = bld_base->base.gallivm;
2013 struct tgsi_shader_info *info = &si_shader_ctx->shader->selector->info;
2014 struct si_shader_output_values *outputs = NULL;
2015 int i,j;
2016
2017 outputs = MALLOC((info->num_outputs + 1) * sizeof(outputs[0]));
2018
2019 /* Vertex color clamping.
2020 *
2021 * This uses a state constant loaded in a user data SGPR and
2022 * an IF statement is added that clamps all colors if the constant
2023 * is true.
2024 */
2025 if (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
2026 !si_shader_ctx->shader->is_gs_copy_shader) {
2027 struct lp_build_if_state if_ctx;
2028 LLVMValueRef cond = NULL;
2029 LLVMValueRef addr, val;
2030
2031 for (i = 0; i < info->num_outputs; i++) {
2032 if (info->output_semantic_name[i] != TGSI_SEMANTIC_COLOR &&
2033 info->output_semantic_name[i] != TGSI_SEMANTIC_BCOLOR)
2034 continue;
2035
2036 /* We've found a color. */
2037 if (!cond) {
2038 /* The state is in the first bit of the user SGPR. */
2039 cond = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
2040 SI_PARAM_VS_STATE_BITS);
2041 cond = LLVMBuildTrunc(gallivm->builder, cond,
2042 LLVMInt1TypeInContext(gallivm->context), "");
2043 lp_build_if(&if_ctx, gallivm, cond);
2044 }
2045
2046 for (j = 0; j < 4; j++) {
2047 addr = si_shader_ctx->radeon_bld.soa.outputs[i][j];
2048 val = LLVMBuildLoad(gallivm->builder, addr, "");
2049 val = radeon_llvm_saturate(bld_base, val);
2050 LLVMBuildStore(gallivm->builder, val, addr);
2051 }
2052 }
2053
2054 if (cond)
2055 lp_build_endif(&if_ctx);
2056 }
2057
2058 for (i = 0; i < info->num_outputs; i++) {
2059 outputs[i].name = info->output_semantic_name[i];
2060 outputs[i].sid = info->output_semantic_index[i];
2061
2062 for (j = 0; j < 4; j++)
2063 outputs[i].values[j] =
2064 LLVMBuildLoad(gallivm->builder,
2065 si_shader_ctx->radeon_bld.soa.outputs[i][j],
2066 "");
2067 }
2068
2069 /* Export PrimitiveID when PS needs it. */
2070 if (si_vs_exports_prim_id(si_shader_ctx->shader)) {
2071 outputs[i].name = TGSI_SEMANTIC_PRIMID;
2072 outputs[i].sid = 0;
2073 outputs[i].values[0] = bitcast(bld_base, TGSI_TYPE_FLOAT,
2074 get_primitive_id(bld_base, 0));
2075 outputs[i].values[1] = bld_base->base.undef;
2076 outputs[i].values[2] = bld_base->base.undef;
2077 outputs[i].values[3] = bld_base->base.undef;
2078 i++;
2079 }
2080
2081 si_llvm_export_vs(bld_base, outputs, i);
2082 FREE(outputs);
2083 }
2084
2085 static void si_export_mrt_z(struct lp_build_tgsi_context *bld_base,
2086 LLVMValueRef depth, LLVMValueRef stencil,
2087 LLVMValueRef samplemask)
2088 {
2089 struct si_screen *sscreen = si_shader_context(bld_base)->screen;
2090 struct lp_build_context *base = &bld_base->base;
2091 struct lp_build_context *uint = &bld_base->uint_bld;
2092 LLVMValueRef args[9];
2093 unsigned mask = 0;
2094
2095 assert(depth || stencil || samplemask);
2096
2097 args[1] = uint->one; /* whether the EXEC mask is valid */
2098 args[2] = uint->one; /* DONE bit */
2099
2100 /* Specify the target we are exporting */
2101 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_MRTZ);
2102
2103 args[4] = uint->zero; /* COMP flag */
2104 args[5] = base->undef; /* R, depth */
2105 args[6] = base->undef; /* G, stencil test value[0:7], stencil op value[8:15] */
2106 args[7] = base->undef; /* B, sample mask */
2107 args[8] = base->undef; /* A, alpha to mask */
2108
2109 if (depth) {
2110 args[5] = depth;
2111 mask |= 0x1;
2112 }
2113
2114 if (stencil) {
2115 args[6] = stencil;
2116 mask |= 0x2;
2117 }
2118
2119 if (samplemask) {
2120 args[7] = samplemask;
2121 mask |= 0x4;
2122 }
2123
2124 /* SI (except OLAND) has a bug that it only looks
2125 * at the X writemask component. */
2126 if (sscreen->b.chip_class == SI &&
2127 sscreen->b.family != CHIP_OLAND)
2128 mask |= 0x1;
2129
2130 /* Specify which components to enable */
2131 args[0] = lp_build_const_int32(base->gallivm, mask);
2132
2133 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2134 LLVMVoidTypeInContext(base->gallivm->context),
2135 args, 9, 0);
2136 }
2137
2138 static void si_export_mrt_color(struct lp_build_tgsi_context *bld_base,
2139 LLVMValueRef *color, unsigned index,
2140 bool is_last)
2141 {
2142 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2143 struct lp_build_context *base = &bld_base->base;
2144 LLVMValueRef args[9];
2145 int i;
2146
2147 /* Clamp color */
2148 if (si_shader_ctx->shader->key.ps.clamp_color)
2149 for (i = 0; i < 4; i++)
2150 color[i] = radeon_llvm_saturate(bld_base, color[i]);
2151
2152 /* Alpha to one */
2153 if (si_shader_ctx->shader->key.ps.alpha_to_one)
2154 color[3] = base->one;
2155
2156 /* Alpha test */
2157 if (index == 0 &&
2158 si_shader_ctx->shader->key.ps.alpha_func != PIPE_FUNC_ALWAYS)
2159 si_alpha_test(bld_base, color[3]);
2160
2161 /* Line & polygon smoothing */
2162 if (si_shader_ctx->shader->key.ps.poly_line_smoothing)
2163 color[3] = si_scale_alpha_by_sample_mask(bld_base, color[3]);
2164
2165 /* If last_cbuf > 0, FS_COLOR0_WRITES_ALL_CBUFS is true. */
2166 if (index == 0 &&
2167 si_shader_ctx->shader->key.ps.last_cbuf > 0) {
2168 for (int c = 1; c <= si_shader_ctx->shader->key.ps.last_cbuf; c++) {
2169 si_llvm_init_export_args(bld_base, color,
2170 V_008DFC_SQ_EXP_MRT + c, args);
2171 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2172 LLVMVoidTypeInContext(base->gallivm->context),
2173 args, 9, 0);
2174 }
2175 }
2176
2177 /* Export */
2178 si_llvm_init_export_args(bld_base, color, V_008DFC_SQ_EXP_MRT + index,
2179 args);
2180 if (is_last) {
2181 args[1] = bld_base->uint_bld.one; /* whether the EXEC mask is valid */
2182 args[2] = bld_base->uint_bld.one; /* DONE bit */
2183 }
2184 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2185 LLVMVoidTypeInContext(base->gallivm->context),
2186 args, 9, 0);
2187 }
2188
2189 static void si_export_null(struct lp_build_tgsi_context *bld_base)
2190 {
2191 struct lp_build_context *base = &bld_base->base;
2192 struct lp_build_context *uint = &bld_base->uint_bld;
2193 LLVMValueRef args[9];
2194
2195 args[0] = lp_build_const_int32(base->gallivm, 0x0); /* enabled channels */
2196 args[1] = uint->one; /* whether the EXEC mask is valid */
2197 args[2] = uint->one; /* DONE bit */
2198 args[3] = lp_build_const_int32(base->gallivm, V_008DFC_SQ_EXP_NULL);
2199 args[4] = uint->zero; /* COMPR flag (0 = 32-bit export) */
2200 args[5] = uint->undef; /* R */
2201 args[6] = uint->undef; /* G */
2202 args[7] = uint->undef; /* B */
2203 args[8] = uint->undef; /* A */
2204
2205 lp_build_intrinsic(base->gallivm->builder, "llvm.SI.export",
2206 LLVMVoidTypeInContext(base->gallivm->context),
2207 args, 9, 0);
2208 }
2209
2210 static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
2211 {
2212 struct si_shader_context * si_shader_ctx = si_shader_context(bld_base);
2213 struct si_shader * shader = si_shader_ctx->shader;
2214 struct lp_build_context * base = &bld_base->base;
2215 struct tgsi_shader_info *info = &shader->selector->info;
2216 LLVMBuilderRef builder = base->gallivm->builder;
2217 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
2218 int last_color_export = -1;
2219 int i;
2220
2221 /* If there are no outputs, add a dummy export. */
2222 if (!info->num_outputs) {
2223 si_export_null(bld_base);
2224 return;
2225 }
2226
2227 /* Determine the last export. If MRTZ is present, it's always last.
2228 * Otherwise, find the last color export.
2229 */
2230 if (!info->writes_z && !info->writes_stencil && !info->writes_samplemask)
2231 for (i = 0; i < info->num_outputs; i++)
2232 if (info->output_semantic_name[i] == TGSI_SEMANTIC_COLOR)
2233 last_color_export = i;
2234
2235 for (i = 0; i < info->num_outputs; i++) {
2236 unsigned semantic_name = info->output_semantic_name[i];
2237 unsigned semantic_index = info->output_semantic_index[i];
2238 unsigned j;
2239 LLVMValueRef color[4] = {};
2240
2241 /* Select the correct target */
2242 switch (semantic_name) {
2243 case TGSI_SEMANTIC_POSITION:
2244 depth = LLVMBuildLoad(builder,
2245 si_shader_ctx->radeon_bld.soa.outputs[i][2], "");
2246 break;
2247 case TGSI_SEMANTIC_STENCIL:
2248 stencil = LLVMBuildLoad(builder,
2249 si_shader_ctx->radeon_bld.soa.outputs[i][1], "");
2250 break;
2251 case TGSI_SEMANTIC_SAMPLEMASK:
2252 samplemask = LLVMBuildLoad(builder,
2253 si_shader_ctx->radeon_bld.soa.outputs[i][0], "");
2254 break;
2255 case TGSI_SEMANTIC_COLOR:
2256 for (j = 0; j < 4; j++)
2257 color[j] = LLVMBuildLoad(builder,
2258 si_shader_ctx->radeon_bld.soa.outputs[i][j], "");
2259
2260 si_export_mrt_color(bld_base, color, semantic_index,
2261 last_color_export == i);
2262 break;
2263 default:
2264 fprintf(stderr,
2265 "Warning: SI unhandled fs output type:%d\n",
2266 semantic_name);
2267 }
2268 }
2269
2270 if (depth || stencil || samplemask)
2271 si_export_mrt_z(bld_base, depth, stencil, samplemask);
2272 }
2273
2274 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2275 struct lp_build_tgsi_context * bld_base,
2276 struct lp_build_emit_data * emit_data);
2277
2278 static bool tgsi_is_array_sampler(unsigned target)
2279 {
2280 return target == TGSI_TEXTURE_1D_ARRAY ||
2281 target == TGSI_TEXTURE_SHADOW1D_ARRAY ||
2282 target == TGSI_TEXTURE_2D_ARRAY ||
2283 target == TGSI_TEXTURE_SHADOW2D_ARRAY ||
2284 target == TGSI_TEXTURE_CUBE_ARRAY ||
2285 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY ||
2286 target == TGSI_TEXTURE_2D_ARRAY_MSAA;
2287 }
2288
2289 static void set_tex_fetch_args(struct gallivm_state *gallivm,
2290 struct lp_build_emit_data *emit_data,
2291 unsigned opcode, unsigned target,
2292 LLVMValueRef res_ptr, LLVMValueRef samp_ptr,
2293 LLVMValueRef *param, unsigned count,
2294 unsigned dmask)
2295 {
2296 unsigned num_args;
2297 unsigned is_rect = target == TGSI_TEXTURE_RECT;
2298 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2299
2300 /* Pad to power of two vector */
2301 while (count < util_next_power_of_two(count))
2302 param[count++] = LLVMGetUndef(i32);
2303
2304 /* Texture coordinates. */
2305 if (count > 1)
2306 emit_data->args[0] = lp_build_gather_values(gallivm, param, count);
2307 else
2308 emit_data->args[0] = param[0];
2309
2310 /* Resource. */
2311 emit_data->args[1] = res_ptr;
2312 num_args = 2;
2313
2314 if (opcode == TGSI_OPCODE_TXF || opcode == TGSI_OPCODE_TXQ)
2315 emit_data->dst_type = LLVMVectorType(i32, 4);
2316 else {
2317 emit_data->dst_type = LLVMVectorType(
2318 LLVMFloatTypeInContext(gallivm->context), 4);
2319
2320 emit_data->args[num_args++] = samp_ptr;
2321 }
2322
2323 emit_data->args[num_args++] = lp_build_const_int32(gallivm, dmask);
2324 emit_data->args[num_args++] = lp_build_const_int32(gallivm, is_rect); /* unorm */
2325 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* r128 */
2326 emit_data->args[num_args++] = lp_build_const_int32(gallivm,
2327 tgsi_is_array_sampler(target)); /* da */
2328 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* glc */
2329 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* slc */
2330 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* tfe */
2331 emit_data->args[num_args++] = lp_build_const_int32(gallivm, 0); /* lwe */
2332
2333 emit_data->arg_count = num_args;
2334 }
2335
2336 static const struct lp_build_tgsi_action tex_action;
2337
2338 static void tex_fetch_ptrs(
2339 struct lp_build_tgsi_context * bld_base,
2340 struct lp_build_emit_data * emit_data,
2341 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
2342 {
2343 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2344 struct gallivm_state *gallivm = bld_base->base.gallivm;
2345 const struct tgsi_full_instruction * inst = emit_data->inst;
2346 unsigned target = inst->Texture.Texture;
2347 unsigned sampler_src;
2348 unsigned sampler_index;
2349
2350 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
2351 sampler_index = emit_data->inst->Src[sampler_src].Register.Index;
2352
2353 if (emit_data->inst->Src[sampler_src].Register.Indirect) {
2354 const struct tgsi_full_src_register *reg = &emit_data->inst->Src[sampler_src];
2355 LLVMValueRef ind_index;
2356
2357 ind_index = get_indirect_index(si_shader_ctx, &reg->Indirect, reg->Register.Index);
2358
2359 *res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
2360 *res_ptr = build_indexed_load_const(si_shader_ctx, *res_ptr, ind_index);
2361
2362 *samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
2363 *samp_ptr = build_indexed_load_const(si_shader_ctx, *samp_ptr, ind_index);
2364
2365 if (target == TGSI_TEXTURE_2D_MSAA ||
2366 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2367 ind_index = LLVMBuildAdd(gallivm->builder, ind_index,
2368 lp_build_const_int32(gallivm,
2369 SI_FMASK_TEX_OFFSET), "");
2370 *fmask_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
2371 *fmask_ptr = build_indexed_load_const(si_shader_ctx, *fmask_ptr, ind_index);
2372 }
2373 } else {
2374 *res_ptr = si_shader_ctx->sampler_views[sampler_index];
2375 *samp_ptr = si_shader_ctx->sampler_states[sampler_index];
2376 *fmask_ptr = si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + sampler_index];
2377 }
2378 }
2379
2380 static void tex_fetch_args(
2381 struct lp_build_tgsi_context * bld_base,
2382 struct lp_build_emit_data * emit_data)
2383 {
2384 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2385 struct gallivm_state *gallivm = bld_base->base.gallivm;
2386 LLVMBuilderRef builder = gallivm->builder;
2387 const struct tgsi_full_instruction * inst = emit_data->inst;
2388 unsigned opcode = inst->Instruction.Opcode;
2389 unsigned target = inst->Texture.Texture;
2390 LLVMValueRef coords[5], derivs[6];
2391 LLVMValueRef address[16];
2392 int ref_pos;
2393 unsigned num_coords = tgsi_util_get_texture_coord_dim(target, &ref_pos);
2394 unsigned count = 0;
2395 unsigned chan;
2396 unsigned num_deriv_channels = 0;
2397 bool has_offset = inst->Texture.NumOffsets > 0;
2398 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2399 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2400 unsigned dmask = 0xf;
2401
2402 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2403
2404 if (opcode == TGSI_OPCODE_TXQ) {
2405 if (target == TGSI_TEXTURE_BUFFER) {
2406 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2407
2408 /* Read the size from the buffer descriptor directly. */
2409 LLVMValueRef res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2410 LLVMValueRef size = LLVMBuildExtractElement(builder, res,
2411 lp_build_const_int32(gallivm, 6), "");
2412
2413 if (si_shader_ctx->screen->b.chip_class >= VI) {
2414 /* On VI, the descriptor contains the size in bytes,
2415 * but TXQ must return the size in elements.
2416 * The stride is always non-zero for resources using TXQ.
2417 */
2418 LLVMValueRef stride =
2419 LLVMBuildExtractElement(builder, res,
2420 lp_build_const_int32(gallivm, 5), "");
2421 stride = LLVMBuildLShr(builder, stride,
2422 lp_build_const_int32(gallivm, 16), "");
2423 stride = LLVMBuildAnd(builder, stride,
2424 lp_build_const_int32(gallivm, 0x3FFF), "");
2425
2426 size = LLVMBuildUDiv(builder, size, stride, "");
2427 }
2428
2429 emit_data->args[0] = size;
2430 return;
2431 }
2432
2433 /* Textures - set the mip level. */
2434 address[count++] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
2435
2436 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2437 NULL, address, count, 0xf);
2438 return;
2439 }
2440
2441 if (target == TGSI_TEXTURE_BUFFER) {
2442 LLVMTypeRef i128 = LLVMIntTypeInContext(gallivm->context, 128);
2443 LLVMTypeRef v2i128 = LLVMVectorType(i128, 2);
2444 LLVMTypeRef i8 = LLVMInt8TypeInContext(gallivm->context);
2445 LLVMTypeRef v16i8 = LLVMVectorType(i8, 16);
2446
2447 /* Bitcast and truncate v8i32 to v16i8. */
2448 LLVMValueRef res = res_ptr;
2449 res = LLVMBuildBitCast(gallivm->builder, res, v2i128, "");
2450 res = LLVMBuildExtractElement(gallivm->builder, res, bld_base->uint_bld.one, "");
2451 res = LLVMBuildBitCast(gallivm->builder, res, v16i8, "");
2452
2453 emit_data->dst_type = LLVMVectorType(bld_base->base.elem_type, 4);
2454 emit_data->args[0] = res;
2455 emit_data->args[1] = bld_base->uint_bld.zero;
2456 emit_data->args[2] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, 0);
2457 emit_data->arg_count = 3;
2458 return;
2459 }
2460
2461 /* Fetch and project texture coordinates */
2462 coords[3] = lp_build_emit_fetch(bld_base, emit_data->inst, 0, TGSI_CHAN_W);
2463 for (chan = 0; chan < 3; chan++ ) {
2464 coords[chan] = lp_build_emit_fetch(bld_base,
2465 emit_data->inst, 0,
2466 chan);
2467 if (opcode == TGSI_OPCODE_TXP)
2468 coords[chan] = lp_build_emit_llvm_binary(bld_base,
2469 TGSI_OPCODE_DIV,
2470 coords[chan],
2471 coords[3]);
2472 }
2473
2474 if (opcode == TGSI_OPCODE_TXP)
2475 coords[3] = bld_base->base.one;
2476
2477 /* Pack offsets. */
2478 if (has_offset && opcode != TGSI_OPCODE_TXF) {
2479 /* The offsets are six-bit signed integers packed like this:
2480 * X=[5:0], Y=[13:8], and Z=[21:16].
2481 */
2482 LLVMValueRef offset[3], pack;
2483
2484 assert(inst->Texture.NumOffsets == 1);
2485
2486 for (chan = 0; chan < 3; chan++) {
2487 offset[chan] = lp_build_emit_fetch_texoffset(bld_base,
2488 emit_data->inst, 0, chan);
2489 offset[chan] = LLVMBuildAnd(gallivm->builder, offset[chan],
2490 lp_build_const_int32(gallivm, 0x3f), "");
2491 if (chan)
2492 offset[chan] = LLVMBuildShl(gallivm->builder, offset[chan],
2493 lp_build_const_int32(gallivm, chan*8), "");
2494 }
2495
2496 pack = LLVMBuildOr(gallivm->builder, offset[0], offset[1], "");
2497 pack = LLVMBuildOr(gallivm->builder, pack, offset[2], "");
2498 address[count++] = pack;
2499 }
2500
2501 /* Pack LOD bias value */
2502 if (opcode == TGSI_OPCODE_TXB)
2503 address[count++] = coords[3];
2504 if (opcode == TGSI_OPCODE_TXB2)
2505 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2506
2507 /* Pack depth comparison value */
2508 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
2509 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
2510 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2511 } else {
2512 assert(ref_pos >= 0);
2513 address[count++] = coords[ref_pos];
2514 }
2515 }
2516
2517 /* Pack user derivatives */
2518 if (opcode == TGSI_OPCODE_TXD) {
2519 int param, num_src_deriv_channels;
2520
2521 switch (target) {
2522 case TGSI_TEXTURE_3D:
2523 num_src_deriv_channels = 3;
2524 num_deriv_channels = 3;
2525 break;
2526 case TGSI_TEXTURE_2D:
2527 case TGSI_TEXTURE_SHADOW2D:
2528 case TGSI_TEXTURE_RECT:
2529 case TGSI_TEXTURE_SHADOWRECT:
2530 case TGSI_TEXTURE_2D_ARRAY:
2531 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2532 num_src_deriv_channels = 2;
2533 num_deriv_channels = 2;
2534 break;
2535 case TGSI_TEXTURE_CUBE:
2536 case TGSI_TEXTURE_SHADOWCUBE:
2537 case TGSI_TEXTURE_CUBE_ARRAY:
2538 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
2539 /* Cube derivatives will be converted to 2D. */
2540 num_src_deriv_channels = 3;
2541 num_deriv_channels = 2;
2542 break;
2543 case TGSI_TEXTURE_1D:
2544 case TGSI_TEXTURE_SHADOW1D:
2545 case TGSI_TEXTURE_1D_ARRAY:
2546 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2547 num_src_deriv_channels = 1;
2548 num_deriv_channels = 1;
2549 break;
2550 default:
2551 unreachable("invalid target");
2552 }
2553
2554 for (param = 0; param < 2; param++)
2555 for (chan = 0; chan < num_src_deriv_channels; chan++)
2556 derivs[param * num_src_deriv_channels + chan] =
2557 lp_build_emit_fetch(bld_base, inst, param+1, chan);
2558 }
2559
2560 if (target == TGSI_TEXTURE_CUBE ||
2561 target == TGSI_TEXTURE_CUBE_ARRAY ||
2562 target == TGSI_TEXTURE_SHADOWCUBE ||
2563 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)
2564 radeon_llvm_emit_prepare_cube_coords(bld_base, emit_data, coords, derivs);
2565
2566 if (opcode == TGSI_OPCODE_TXD)
2567 for (int i = 0; i < num_deriv_channels * 2; i++)
2568 address[count++] = derivs[i];
2569
2570 /* Pack texture coordinates */
2571 address[count++] = coords[0];
2572 if (num_coords > 1)
2573 address[count++] = coords[1];
2574 if (num_coords > 2)
2575 address[count++] = coords[2];
2576
2577 /* Pack LOD or sample index */
2578 if (opcode == TGSI_OPCODE_TXL || opcode == TGSI_OPCODE_TXF)
2579 address[count++] = coords[3];
2580 else if (opcode == TGSI_OPCODE_TXL2)
2581 address[count++] = lp_build_emit_fetch(bld_base, inst, 1, 0);
2582
2583 if (count > 16) {
2584 assert(!"Cannot handle more than 16 texture address parameters");
2585 count = 16;
2586 }
2587
2588 for (chan = 0; chan < count; chan++ ) {
2589 address[chan] = LLVMBuildBitCast(gallivm->builder,
2590 address[chan], i32, "");
2591 }
2592
2593 /* Adjust the sample index according to FMASK.
2594 *
2595 * For uncompressed MSAA surfaces, FMASK should return 0x76543210,
2596 * which is the identity mapping. Each nibble says which physical sample
2597 * should be fetched to get that sample.
2598 *
2599 * For example, 0x11111100 means there are only 2 samples stored and
2600 * the second sample covers 3/4 of the pixel. When reading samples 0
2601 * and 1, return physical sample 0 (determined by the first two 0s
2602 * in FMASK), otherwise return physical sample 1.
2603 *
2604 * The sample index should be adjusted as follows:
2605 * sample_index = (fmask >> (sample_index * 4)) & 0xF;
2606 */
2607 if (target == TGSI_TEXTURE_2D_MSAA ||
2608 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
2609 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2610 struct lp_build_emit_data txf_emit_data = *emit_data;
2611 LLVMValueRef txf_address[4];
2612 unsigned txf_count = count;
2613 struct tgsi_full_instruction inst = {};
2614
2615 memcpy(txf_address, address, sizeof(txf_address));
2616
2617 if (target == TGSI_TEXTURE_2D_MSAA) {
2618 txf_address[2] = bld_base->uint_bld.zero;
2619 }
2620 txf_address[3] = bld_base->uint_bld.zero;
2621
2622 /* Read FMASK using TXF. */
2623 inst.Instruction.Opcode = TGSI_OPCODE_TXF;
2624 inst.Texture.Texture = target;
2625 txf_emit_data.inst = &inst;
2626 txf_emit_data.chan = 0;
2627 set_tex_fetch_args(gallivm, &txf_emit_data, TGSI_OPCODE_TXF,
2628 target, fmask_ptr, NULL,
2629 txf_address, txf_count, 0xf);
2630 build_tex_intrinsic(&tex_action, bld_base, &txf_emit_data);
2631
2632 /* Initialize some constants. */
2633 LLVMValueRef four = LLVMConstInt(uint_bld->elem_type, 4, 0);
2634 LLVMValueRef F = LLVMConstInt(uint_bld->elem_type, 0xF, 0);
2635
2636 /* Apply the formula. */
2637 LLVMValueRef fmask =
2638 LLVMBuildExtractElement(gallivm->builder,
2639 txf_emit_data.output[0],
2640 uint_bld->zero, "");
2641
2642 unsigned sample_chan = target == TGSI_TEXTURE_2D_MSAA ? 2 : 3;
2643
2644 LLVMValueRef sample_index4 =
2645 LLVMBuildMul(gallivm->builder, address[sample_chan], four, "");
2646
2647 LLVMValueRef shifted_fmask =
2648 LLVMBuildLShr(gallivm->builder, fmask, sample_index4, "");
2649
2650 LLVMValueRef final_sample =
2651 LLVMBuildAnd(gallivm->builder, shifted_fmask, F, "");
2652
2653 /* Don't rewrite the sample index if WORD1.DATA_FORMAT of the FMASK
2654 * resource descriptor is 0 (invalid),
2655 */
2656 LLVMValueRef fmask_desc =
2657 LLVMBuildBitCast(gallivm->builder, fmask_ptr,
2658 LLVMVectorType(uint_bld->elem_type, 8), "");
2659
2660 LLVMValueRef fmask_word1 =
2661 LLVMBuildExtractElement(gallivm->builder, fmask_desc,
2662 uint_bld->one, "");
2663
2664 LLVMValueRef word1_is_nonzero =
2665 LLVMBuildICmp(gallivm->builder, LLVMIntNE,
2666 fmask_word1, uint_bld->zero, "");
2667
2668 /* Replace the MSAA sample index. */
2669 address[sample_chan] =
2670 LLVMBuildSelect(gallivm->builder, word1_is_nonzero,
2671 final_sample, address[sample_chan], "");
2672 }
2673
2674 if (opcode == TGSI_OPCODE_TXF) {
2675 /* add tex offsets */
2676 if (inst->Texture.NumOffsets) {
2677 struct lp_build_context *uint_bld = &bld_base->uint_bld;
2678 struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
2679 const struct tgsi_texture_offset * off = inst->TexOffsets;
2680
2681 assert(inst->Texture.NumOffsets == 1);
2682
2683 switch (target) {
2684 case TGSI_TEXTURE_3D:
2685 address[2] = lp_build_add(uint_bld, address[2],
2686 bld->immediates[off->Index][off->SwizzleZ]);
2687 /* fall through */
2688 case TGSI_TEXTURE_2D:
2689 case TGSI_TEXTURE_SHADOW2D:
2690 case TGSI_TEXTURE_RECT:
2691 case TGSI_TEXTURE_SHADOWRECT:
2692 case TGSI_TEXTURE_2D_ARRAY:
2693 case TGSI_TEXTURE_SHADOW2D_ARRAY:
2694 address[1] =
2695 lp_build_add(uint_bld, address[1],
2696 bld->immediates[off->Index][off->SwizzleY]);
2697 /* fall through */
2698 case TGSI_TEXTURE_1D:
2699 case TGSI_TEXTURE_SHADOW1D:
2700 case TGSI_TEXTURE_1D_ARRAY:
2701 case TGSI_TEXTURE_SHADOW1D_ARRAY:
2702 address[0] =
2703 lp_build_add(uint_bld, address[0],
2704 bld->immediates[off->Index][off->SwizzleX]);
2705 break;
2706 /* texture offsets do not apply to other texture targets */
2707 }
2708 }
2709 }
2710
2711 if (opcode == TGSI_OPCODE_TG4) {
2712 unsigned gather_comp = 0;
2713
2714 /* DMASK was repurposed for GATHER4. 4 components are always
2715 * returned and DMASK works like a swizzle - it selects
2716 * the component to fetch. The only valid DMASK values are
2717 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
2718 * (red,red,red,red) etc.) The ISA document doesn't mention
2719 * this.
2720 */
2721
2722 /* Get the component index from src1.x for Gather4. */
2723 if (!tgsi_is_shadow_target(target)) {
2724 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
2725 LLVMValueRef comp_imm;
2726 struct tgsi_src_register src1 = inst->Src[1].Register;
2727
2728 assert(src1.File == TGSI_FILE_IMMEDIATE);
2729
2730 comp_imm = imms[src1.Index][src1.SwizzleX];
2731 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
2732 gather_comp = CLAMP(gather_comp, 0, 3);
2733 }
2734
2735 dmask = 1 << gather_comp;
2736 }
2737
2738 set_tex_fetch_args(gallivm, emit_data, opcode, target, res_ptr,
2739 samp_ptr, address, count, dmask);
2740 }
2741
2742 static void build_tex_intrinsic(const struct lp_build_tgsi_action * action,
2743 struct lp_build_tgsi_context * bld_base,
2744 struct lp_build_emit_data * emit_data)
2745 {
2746 struct lp_build_context * base = &bld_base->base;
2747 unsigned opcode = emit_data->inst->Instruction.Opcode;
2748 unsigned target = emit_data->inst->Texture.Texture;
2749 char intr_name[127];
2750 bool has_offset = emit_data->inst->Texture.NumOffsets > 0;
2751 bool is_shadow = tgsi_is_shadow_target(target);
2752 char type[64];
2753 const char *name = "llvm.SI.image.sample";
2754 const char *infix = "";
2755
2756 if (opcode == TGSI_OPCODE_TXQ && target == TGSI_TEXTURE_BUFFER) {
2757 /* Just return the buffer size. */
2758 emit_data->output[emit_data->chan] = emit_data->args[0];
2759 return;
2760 }
2761
2762 if (target == TGSI_TEXTURE_BUFFER) {
2763 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2764 base->gallivm->builder,
2765 "llvm.SI.vs.load.input", emit_data->dst_type,
2766 emit_data->args, emit_data->arg_count,
2767 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2768 return;
2769 }
2770
2771 switch (opcode) {
2772 case TGSI_OPCODE_TXF:
2773 name = target == TGSI_TEXTURE_2D_MSAA ||
2774 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
2775 "llvm.SI.image.load" :
2776 "llvm.SI.image.load.mip";
2777 is_shadow = false;
2778 has_offset = false;
2779 break;
2780 case TGSI_OPCODE_TXQ:
2781 name = "llvm.SI.getresinfo";
2782 is_shadow = false;
2783 has_offset = false;
2784 break;
2785 case TGSI_OPCODE_LODQ:
2786 name = "llvm.SI.getlod";
2787 is_shadow = false;
2788 has_offset = false;
2789 break;
2790 case TGSI_OPCODE_TEX:
2791 case TGSI_OPCODE_TEX2:
2792 case TGSI_OPCODE_TXP:
2793 break;
2794 case TGSI_OPCODE_TXB:
2795 case TGSI_OPCODE_TXB2:
2796 infix = ".b";
2797 break;
2798 case TGSI_OPCODE_TXL:
2799 case TGSI_OPCODE_TXL2:
2800 infix = ".l";
2801 break;
2802 case TGSI_OPCODE_TXD:
2803 infix = ".d";
2804 break;
2805 case TGSI_OPCODE_TG4:
2806 name = "llvm.SI.gather4";
2807 break;
2808 default:
2809 assert(0);
2810 return;
2811 }
2812
2813 if (LLVMGetTypeKind(LLVMTypeOf(emit_data->args[0])) == LLVMVectorTypeKind)
2814 sprintf(type, ".v%ui32",
2815 LLVMGetVectorSize(LLVMTypeOf(emit_data->args[0])));
2816 else
2817 strcpy(type, ".i32");
2818
2819 /* Add the type and suffixes .c, .o if needed. */
2820 sprintf(intr_name, "%s%s%s%s%s",
2821 name, is_shadow ? ".c" : "", infix,
2822 has_offset ? ".o" : "", type);
2823
2824 emit_data->output[emit_data->chan] = lp_build_intrinsic(
2825 base->gallivm->builder, intr_name, emit_data->dst_type,
2826 emit_data->args, emit_data->arg_count,
2827 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
2828
2829 /* Divide the number of layers by 6 to get the number of cubes. */
2830 if (opcode == TGSI_OPCODE_TXQ &&
2831 (target == TGSI_TEXTURE_CUBE_ARRAY ||
2832 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY)) {
2833 LLVMBuilderRef builder = bld_base->base.gallivm->builder;
2834 LLVMValueRef two = lp_build_const_int32(bld_base->base.gallivm, 2);
2835 LLVMValueRef six = lp_build_const_int32(bld_base->base.gallivm, 6);
2836
2837 LLVMValueRef v4 = emit_data->output[emit_data->chan];
2838 LLVMValueRef z = LLVMBuildExtractElement(builder, v4, two, "");
2839 z = LLVMBuildSDiv(builder, z, six, "");
2840
2841 emit_data->output[emit_data->chan] =
2842 LLVMBuildInsertElement(builder, v4, z, two, "");
2843 }
2844 }
2845
2846 static void si_llvm_emit_txqs(
2847 const struct lp_build_tgsi_action * action,
2848 struct lp_build_tgsi_context * bld_base,
2849 struct lp_build_emit_data * emit_data)
2850 {
2851 struct gallivm_state *gallivm = bld_base->base.gallivm;
2852 LLVMBuilderRef builder = gallivm->builder;
2853 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
2854 LLVMTypeRef v8i32 = LLVMVectorType(i32, 8);
2855 LLVMValueRef res, samples;
2856 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
2857
2858 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
2859
2860
2861 /* Read the samples from the descriptor directly. */
2862 res = LLVMBuildBitCast(builder, res_ptr, v8i32, "");
2863 samples = LLVMBuildExtractElement(
2864 builder, res,
2865 lp_build_const_int32(gallivm, 3), "");
2866 samples = LLVMBuildLShr(builder, samples,
2867 lp_build_const_int32(gallivm, 16), "");
2868 samples = LLVMBuildAnd(builder, samples,
2869 lp_build_const_int32(gallivm, 0xf), "");
2870 samples = LLVMBuildShl(builder, lp_build_const_int32(gallivm, 1),
2871 samples, "");
2872
2873 emit_data->output[emit_data->chan] = samples;
2874 }
2875
2876 /*
2877 * SI implements derivatives using the local data store (LDS)
2878 * All writes to the LDS happen in all executing threads at
2879 * the same time. TID is the Thread ID for the current
2880 * thread and is a value between 0 and 63, representing
2881 * the thread's position in the wavefront.
2882 *
2883 * For the pixel shader threads are grouped into quads of four pixels.
2884 * The TIDs of the pixels of a quad are:
2885 *
2886 * +------+------+
2887 * |4n + 0|4n + 1|
2888 * +------+------+
2889 * |4n + 2|4n + 3|
2890 * +------+------+
2891 *
2892 * So, masking the TID with 0xfffffffc yields the TID of the top left pixel
2893 * of the quad, masking with 0xfffffffd yields the TID of the top pixel of
2894 * the current pixel's column, and masking with 0xfffffffe yields the TID
2895 * of the left pixel of the current pixel's row.
2896 *
2897 * Adding 1 yields the TID of the pixel to the right of the left pixel, and
2898 * adding 2 yields the TID of the pixel below the top pixel.
2899 */
2900 /* masks for thread ID. */
2901 #define TID_MASK_TOP_LEFT 0xfffffffc
2902 #define TID_MASK_TOP 0xfffffffd
2903 #define TID_MASK_LEFT 0xfffffffe
2904
2905 static void si_llvm_emit_ddxy(
2906 const struct lp_build_tgsi_action * action,
2907 struct lp_build_tgsi_context * bld_base,
2908 struct lp_build_emit_data * emit_data)
2909 {
2910 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2911 struct gallivm_state *gallivm = bld_base->base.gallivm;
2912 struct lp_build_context * base = &bld_base->base;
2913 const struct tgsi_full_instruction *inst = emit_data->inst;
2914 unsigned opcode = inst->Instruction.Opcode;
2915 LLVMValueRef indices[2];
2916 LLVMValueRef store_ptr, load_ptr0, load_ptr1;
2917 LLVMValueRef tl, trbl, result[4];
2918 LLVMTypeRef i32;
2919 unsigned swizzle[4];
2920 unsigned c;
2921 int idx;
2922 unsigned mask;
2923
2924 i32 = LLVMInt32TypeInContext(gallivm->context);
2925
2926 indices[0] = bld_base->uint_bld.zero;
2927 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
2928 NULL, 0, LLVMReadNoneAttribute);
2929 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2930 indices, 2, "");
2931
2932 if (opcode == TGSI_OPCODE_DDX_FINE)
2933 mask = TID_MASK_LEFT;
2934 else if (opcode == TGSI_OPCODE_DDY_FINE)
2935 mask = TID_MASK_TOP;
2936 else
2937 mask = TID_MASK_TOP_LEFT;
2938
2939 indices[1] = LLVMBuildAnd(gallivm->builder, indices[1],
2940 lp_build_const_int32(gallivm, mask), "");
2941 load_ptr0 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2942 indices, 2, "");
2943
2944 /* for DDX we want to next X pixel, DDY next Y pixel. */
2945 idx = (opcode == TGSI_OPCODE_DDX || opcode == TGSI_OPCODE_DDX_FINE) ? 1 : 2;
2946 indices[1] = LLVMBuildAdd(gallivm->builder, indices[1],
2947 lp_build_const_int32(gallivm, idx), "");
2948 load_ptr1 = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
2949 indices, 2, "");
2950
2951 for (c = 0; c < 4; ++c) {
2952 unsigned i;
2953
2954 swizzle[c] = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], c);
2955 for (i = 0; i < c; ++i) {
2956 if (swizzle[i] == swizzle[c]) {
2957 result[c] = result[i];
2958 break;
2959 }
2960 }
2961 if (i != c)
2962 continue;
2963
2964 LLVMBuildStore(gallivm->builder,
2965 LLVMBuildBitCast(gallivm->builder,
2966 lp_build_emit_fetch(bld_base, inst, 0, c),
2967 i32, ""),
2968 store_ptr);
2969
2970 tl = LLVMBuildLoad(gallivm->builder, load_ptr0, "");
2971 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
2972
2973 trbl = LLVMBuildLoad(gallivm->builder, load_ptr1, "");
2974 trbl = LLVMBuildBitCast(gallivm->builder, trbl, base->elem_type, "");
2975
2976 result[c] = LLVMBuildFSub(gallivm->builder, trbl, tl, "");
2977 }
2978
2979 emit_data->output[0] = lp_build_gather_values(gallivm, result, 4);
2980 }
2981
2982 /*
2983 * this takes an I,J coordinate pair,
2984 * and works out the X and Y derivatives.
2985 * it returns DDX(I), DDX(J), DDY(I), DDY(J).
2986 */
2987 static LLVMValueRef si_llvm_emit_ddxy_interp(
2988 struct lp_build_tgsi_context *bld_base,
2989 LLVMValueRef interp_ij)
2990 {
2991 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
2992 struct gallivm_state *gallivm = bld_base->base.gallivm;
2993 struct lp_build_context *base = &bld_base->base;
2994 LLVMValueRef indices[2];
2995 LLVMValueRef store_ptr, load_ptr_x, load_ptr_y, load_ptr_ddx, load_ptr_ddy, temp, temp2;
2996 LLVMValueRef tl, tr, bl, result[4];
2997 LLVMTypeRef i32;
2998 unsigned c;
2999
3000 i32 = LLVMInt32TypeInContext(gallivm->context);
3001
3002 indices[0] = bld_base->uint_bld.zero;
3003 indices[1] = lp_build_intrinsic(gallivm->builder, "llvm.SI.tid", i32,
3004 NULL, 0, LLVMReadNoneAttribute);
3005 store_ptr = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3006 indices, 2, "");
3007
3008 temp = LLVMBuildAnd(gallivm->builder, indices[1],
3009 lp_build_const_int32(gallivm, TID_MASK_LEFT), "");
3010
3011 temp2 = LLVMBuildAnd(gallivm->builder, indices[1],
3012 lp_build_const_int32(gallivm, TID_MASK_TOP), "");
3013
3014 indices[1] = temp;
3015 load_ptr_x = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3016 indices, 2, "");
3017
3018 indices[1] = temp2;
3019 load_ptr_y = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3020 indices, 2, "");
3021
3022 indices[1] = LLVMBuildAdd(gallivm->builder, temp,
3023 lp_build_const_int32(gallivm, 1), "");
3024 load_ptr_ddx = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3025 indices, 2, "");
3026
3027 indices[1] = LLVMBuildAdd(gallivm->builder, temp2,
3028 lp_build_const_int32(gallivm, 2), "");
3029 load_ptr_ddy = LLVMBuildGEP(gallivm->builder, si_shader_ctx->lds,
3030 indices, 2, "");
3031
3032 for (c = 0; c < 2; ++c) {
3033 LLVMValueRef store_val;
3034 LLVMValueRef c_ll = lp_build_const_int32(gallivm, c);
3035
3036 store_val = LLVMBuildExtractElement(gallivm->builder,
3037 interp_ij, c_ll, "");
3038 LLVMBuildStore(gallivm->builder,
3039 store_val,
3040 store_ptr);
3041
3042 tl = LLVMBuildLoad(gallivm->builder, load_ptr_x, "");
3043 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3044
3045 tr = LLVMBuildLoad(gallivm->builder, load_ptr_ddx, "");
3046 tr = LLVMBuildBitCast(gallivm->builder, tr, base->elem_type, "");
3047
3048 result[c] = LLVMBuildFSub(gallivm->builder, tr, tl, "");
3049
3050 tl = LLVMBuildLoad(gallivm->builder, load_ptr_y, "");
3051 tl = LLVMBuildBitCast(gallivm->builder, tl, base->elem_type, "");
3052
3053 bl = LLVMBuildLoad(gallivm->builder, load_ptr_ddy, "");
3054 bl = LLVMBuildBitCast(gallivm->builder, bl, base->elem_type, "");
3055
3056 result[c + 2] = LLVMBuildFSub(gallivm->builder, bl, tl, "");
3057 }
3058
3059 return lp_build_gather_values(gallivm, result, 4);
3060 }
3061
3062 static void interp_fetch_args(
3063 struct lp_build_tgsi_context *bld_base,
3064 struct lp_build_emit_data *emit_data)
3065 {
3066 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3067 struct gallivm_state *gallivm = bld_base->base.gallivm;
3068 const struct tgsi_full_instruction *inst = emit_data->inst;
3069
3070 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET) {
3071 /* offset is in second src, first two channels */
3072 emit_data->args[0] = lp_build_emit_fetch(bld_base,
3073 emit_data->inst, 1,
3074 0);
3075 emit_data->args[1] = lp_build_emit_fetch(bld_base,
3076 emit_data->inst, 1,
3077 1);
3078 emit_data->arg_count = 2;
3079 } else if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3080 LLVMValueRef sample_position;
3081 LLVMValueRef sample_id;
3082 LLVMValueRef halfval = lp_build_const_float(gallivm, 0.5f);
3083
3084 /* fetch sample ID, then fetch its sample position,
3085 * and place into first two channels.
3086 */
3087 sample_id = lp_build_emit_fetch(bld_base,
3088 emit_data->inst, 1, 0);
3089 sample_id = LLVMBuildBitCast(gallivm->builder, sample_id,
3090 LLVMInt32TypeInContext(gallivm->context),
3091 "");
3092 sample_position = load_sample_position(&si_shader_ctx->radeon_bld, sample_id);
3093
3094 emit_data->args[0] = LLVMBuildExtractElement(gallivm->builder,
3095 sample_position,
3096 lp_build_const_int32(gallivm, 0), "");
3097
3098 emit_data->args[0] = LLVMBuildFSub(gallivm->builder, emit_data->args[0], halfval, "");
3099 emit_data->args[1] = LLVMBuildExtractElement(gallivm->builder,
3100 sample_position,
3101 lp_build_const_int32(gallivm, 1), "");
3102 emit_data->args[1] = LLVMBuildFSub(gallivm->builder, emit_data->args[1], halfval, "");
3103 emit_data->arg_count = 2;
3104 }
3105 }
3106
3107 static void build_interp_intrinsic(const struct lp_build_tgsi_action *action,
3108 struct lp_build_tgsi_context *bld_base,
3109 struct lp_build_emit_data *emit_data)
3110 {
3111 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3112 struct si_shader *shader = si_shader_ctx->shader;
3113 struct gallivm_state *gallivm = bld_base->base.gallivm;
3114 LLVMValueRef interp_param;
3115 const struct tgsi_full_instruction *inst = emit_data->inst;
3116 const char *intr_name;
3117 int input_index;
3118 int chan;
3119 int i;
3120 LLVMValueRef attr_number;
3121 LLVMTypeRef input_type = LLVMFloatTypeInContext(gallivm->context);
3122 LLVMValueRef params = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_PRIM_MASK);
3123 int interp_param_idx;
3124 unsigned location;
3125
3126 assert(inst->Src[0].Register.File == TGSI_FILE_INPUT);
3127 input_index = inst->Src[0].Register.Index;
3128
3129 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3130 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE)
3131 location = TGSI_INTERPOLATE_LOC_CENTER;
3132 else
3133 location = TGSI_INTERPOLATE_LOC_CENTROID;
3134
3135 interp_param_idx = lookup_interp_param_index(shader->ps_input_interpolate[input_index],
3136 location);
3137 if (interp_param_idx == -1)
3138 return;
3139 else if (interp_param_idx)
3140 interp_param = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, interp_param_idx);
3141 else
3142 interp_param = NULL;
3143
3144 attr_number = lp_build_const_int32(gallivm,
3145 shader->ps_input_param_offset[input_index]);
3146
3147 if (inst->Instruction.Opcode == TGSI_OPCODE_INTERP_OFFSET ||
3148 inst->Instruction.Opcode == TGSI_OPCODE_INTERP_SAMPLE) {
3149 LLVMValueRef ij_out[2];
3150 LLVMValueRef ddxy_out = si_llvm_emit_ddxy_interp(bld_base, interp_param);
3151
3152 /*
3153 * take the I then J parameters, and the DDX/Y for it, and
3154 * calculate the IJ inputs for the interpolator.
3155 * temp1 = ddx * offset/sample.x + I;
3156 * interp_param.I = ddy * offset/sample.y + temp1;
3157 * temp1 = ddx * offset/sample.x + J;
3158 * interp_param.J = ddy * offset/sample.y + temp1;
3159 */
3160 for (i = 0; i < 2; i++) {
3161 LLVMValueRef ix_ll = lp_build_const_int32(gallivm, i);
3162 LLVMValueRef iy_ll = lp_build_const_int32(gallivm, i + 2);
3163 LLVMValueRef ddx_el = LLVMBuildExtractElement(gallivm->builder,
3164 ddxy_out, ix_ll, "");
3165 LLVMValueRef ddy_el = LLVMBuildExtractElement(gallivm->builder,
3166 ddxy_out, iy_ll, "");
3167 LLVMValueRef interp_el = LLVMBuildExtractElement(gallivm->builder,
3168 interp_param, ix_ll, "");
3169 LLVMValueRef temp1, temp2;
3170
3171 interp_el = LLVMBuildBitCast(gallivm->builder, interp_el,
3172 LLVMFloatTypeInContext(gallivm->context), "");
3173
3174 temp1 = LLVMBuildFMul(gallivm->builder, ddx_el, emit_data->args[0], "");
3175
3176 temp1 = LLVMBuildFAdd(gallivm->builder, temp1, interp_el, "");
3177
3178 temp2 = LLVMBuildFMul(gallivm->builder, ddy_el, emit_data->args[1], "");
3179
3180 temp2 = LLVMBuildFAdd(gallivm->builder, temp2, temp1, "");
3181
3182 ij_out[i] = LLVMBuildBitCast(gallivm->builder,
3183 temp2,
3184 LLVMIntTypeInContext(gallivm->context, 32), "");
3185 }
3186 interp_param = lp_build_gather_values(bld_base->base.gallivm, ij_out, 2);
3187 }
3188
3189 intr_name = interp_param ? "llvm.SI.fs.interp" : "llvm.SI.fs.constant";
3190 for (chan = 0; chan < 2; chan++) {
3191 LLVMValueRef args[4];
3192 LLVMValueRef llvm_chan;
3193 unsigned schan;
3194
3195 schan = tgsi_util_get_full_src_register_swizzle(&inst->Src[0], chan);
3196 llvm_chan = lp_build_const_int32(gallivm, schan);
3197
3198 args[0] = llvm_chan;
3199 args[1] = attr_number;
3200 args[2] = params;
3201 args[3] = interp_param;
3202
3203 emit_data->output[chan] =
3204 lp_build_intrinsic(gallivm->builder, intr_name,
3205 input_type, args, args[3] ? 4 : 3,
3206 LLVMReadNoneAttribute | LLVMNoUnwindAttribute);
3207 }
3208 }
3209
3210 static unsigned si_llvm_get_stream(struct lp_build_tgsi_context *bld_base,
3211 struct lp_build_emit_data *emit_data)
3212 {
3213 LLVMValueRef (*imms)[4] = lp_soa_context(bld_base)->immediates;
3214 struct tgsi_src_register src0 = emit_data->inst->Src[0].Register;
3215 unsigned stream;
3216
3217 assert(src0.File == TGSI_FILE_IMMEDIATE);
3218
3219 stream = LLVMConstIntGetZExtValue(imms[src0.Index][src0.SwizzleX]) & 0x3;
3220 return stream;
3221 }
3222
3223 /* Emit one vertex from the geometry shader */
3224 static void si_llvm_emit_vertex(
3225 const struct lp_build_tgsi_action *action,
3226 struct lp_build_tgsi_context *bld_base,
3227 struct lp_build_emit_data *emit_data)
3228 {
3229 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3230 struct lp_build_context *uint = &bld_base->uint_bld;
3231 struct si_shader *shader = si_shader_ctx->shader;
3232 struct tgsi_shader_info *info = &shader->selector->info;
3233 struct gallivm_state *gallivm = bld_base->base.gallivm;
3234 LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm->context);
3235 LLVMValueRef soffset = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3236 SI_PARAM_GS2VS_OFFSET);
3237 LLVMValueRef gs_next_vertex;
3238 LLVMValueRef can_emit, kill;
3239 LLVMValueRef args[2];
3240 unsigned chan;
3241 int i;
3242 unsigned stream;
3243
3244 stream = si_llvm_get_stream(bld_base, emit_data);
3245
3246 /* Write vertex attribute values to GSVS ring */
3247 gs_next_vertex = LLVMBuildLoad(gallivm->builder,
3248 si_shader_ctx->gs_next_vertex[stream],
3249 "");
3250
3251 /* If this thread has already emitted the declared maximum number of
3252 * vertices, kill it: excessive vertex emissions are not supposed to
3253 * have any effect, and GS threads have no externally observable
3254 * effects other than emitting vertices.
3255 */
3256 can_emit = LLVMBuildICmp(gallivm->builder, LLVMIntULE, gs_next_vertex,
3257 lp_build_const_int32(gallivm,
3258 shader->selector->gs_max_out_vertices), "");
3259 kill = lp_build_select(&bld_base->base, can_emit,
3260 lp_build_const_float(gallivm, 1.0f),
3261 lp_build_const_float(gallivm, -1.0f));
3262
3263 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.kill",
3264 LLVMVoidTypeInContext(gallivm->context), &kill, 1, 0);
3265
3266 for (i = 0; i < info->num_outputs; i++) {
3267 LLVMValueRef *out_ptr =
3268 si_shader_ctx->radeon_bld.soa.outputs[i];
3269
3270 for (chan = 0; chan < 4; chan++) {
3271 LLVMValueRef out_val = LLVMBuildLoad(gallivm->builder, out_ptr[chan], "");
3272 LLVMValueRef voffset =
3273 lp_build_const_int32(gallivm, (i * 4 + chan) *
3274 shader->selector->gs_max_out_vertices);
3275
3276 voffset = lp_build_add(uint, voffset, gs_next_vertex);
3277 voffset = lp_build_mul_imm(uint, voffset, 4);
3278
3279 out_val = LLVMBuildBitCast(gallivm->builder, out_val, i32, "");
3280
3281 build_tbuffer_store(si_shader_ctx,
3282 si_shader_ctx->gsvs_ring[stream],
3283 out_val, 1,
3284 voffset, soffset, 0,
3285 V_008F0C_BUF_DATA_FORMAT_32,
3286 V_008F0C_BUF_NUM_FORMAT_UINT,
3287 1, 0, 1, 1, 0);
3288 }
3289 }
3290 gs_next_vertex = lp_build_add(uint, gs_next_vertex,
3291 lp_build_const_int32(gallivm, 1));
3292
3293 LLVMBuildStore(gallivm->builder, gs_next_vertex, si_shader_ctx->gs_next_vertex[stream]);
3294
3295 /* Signal vertex emission */
3296 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_EMIT | SENDMSG_GS | (stream << 8));
3297 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3298 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3299 LLVMVoidTypeInContext(gallivm->context), args, 2,
3300 LLVMNoUnwindAttribute);
3301 }
3302
3303 /* Cut one primitive from the geometry shader */
3304 static void si_llvm_emit_primitive(
3305 const struct lp_build_tgsi_action *action,
3306 struct lp_build_tgsi_context *bld_base,
3307 struct lp_build_emit_data *emit_data)
3308 {
3309 struct si_shader_context *si_shader_ctx = si_shader_context(bld_base);
3310 struct gallivm_state *gallivm = bld_base->base.gallivm;
3311 LLVMValueRef args[2];
3312 unsigned stream;
3313
3314 /* Signal primitive cut */
3315 stream = si_llvm_get_stream(bld_base, emit_data);
3316 args[0] = lp_build_const_int32(gallivm, SENDMSG_GS_OP_CUT | SENDMSG_GS | (stream << 8));
3317 args[1] = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_GS_WAVE_ID);
3318 lp_build_intrinsic(gallivm->builder, "llvm.SI.sendmsg",
3319 LLVMVoidTypeInContext(gallivm->context), args, 2,
3320 LLVMNoUnwindAttribute);
3321 }
3322
3323 static void si_llvm_emit_barrier(const struct lp_build_tgsi_action *action,
3324 struct lp_build_tgsi_context *bld_base,
3325 struct lp_build_emit_data *emit_data)
3326 {
3327 struct gallivm_state *gallivm = bld_base->base.gallivm;
3328
3329 lp_build_intrinsic(gallivm->builder, "llvm.AMDGPU.barrier.local",
3330 LLVMVoidTypeInContext(gallivm->context), NULL, 0,
3331 LLVMNoUnwindAttribute);
3332 }
3333
3334 static const struct lp_build_tgsi_action tex_action = {
3335 .fetch_args = tex_fetch_args,
3336 .emit = build_tex_intrinsic,
3337 };
3338
3339 static const struct lp_build_tgsi_action interp_action = {
3340 .fetch_args = interp_fetch_args,
3341 .emit = build_interp_intrinsic,
3342 };
3343
3344 static void create_meta_data(struct si_shader_context *si_shader_ctx)
3345 {
3346 struct gallivm_state *gallivm = si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3347 LLVMValueRef args[3];
3348
3349 args[0] = LLVMMDStringInContext(gallivm->context, "const", 5);
3350 args[1] = 0;
3351 args[2] = lp_build_const_int32(gallivm, 1);
3352
3353 si_shader_ctx->const_md = LLVMMDNodeInContext(gallivm->context, args, 3);
3354 }
3355
3356 static LLVMTypeRef const_array(LLVMTypeRef elem_type, int num_elements)
3357 {
3358 return LLVMPointerType(LLVMArrayType(elem_type, num_elements),
3359 CONST_ADDR_SPACE);
3360 }
3361
3362 static void declare_streamout_params(struct si_shader_context *si_shader_ctx,
3363 struct pipe_stream_output_info *so,
3364 LLVMTypeRef *params, LLVMTypeRef i32,
3365 unsigned *num_params)
3366 {
3367 int i;
3368
3369 /* Streamout SGPRs. */
3370 if (so->num_outputs) {
3371 params[si_shader_ctx->param_streamout_config = (*num_params)++] = i32;
3372 params[si_shader_ctx->param_streamout_write_index = (*num_params)++] = i32;
3373 }
3374 /* A streamout buffer offset is loaded if the stride is non-zero. */
3375 for (i = 0; i < 4; i++) {
3376 if (!so->stride[i])
3377 continue;
3378
3379 params[si_shader_ctx->param_streamout_offset[i] = (*num_params)++] = i32;
3380 }
3381 }
3382
3383 static void create_function(struct si_shader_context *si_shader_ctx)
3384 {
3385 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3386 struct gallivm_state *gallivm = bld_base->base.gallivm;
3387 struct si_shader *shader = si_shader_ctx->shader;
3388 LLVMTypeRef params[SI_NUM_PARAMS], f32, i8, i32, v2i32, v3i32, v16i8, v4i32, v8i32;
3389 unsigned i, last_array_pointer, last_sgpr, num_params;
3390
3391 i8 = LLVMInt8TypeInContext(gallivm->context);
3392 i32 = LLVMInt32TypeInContext(gallivm->context);
3393 f32 = LLVMFloatTypeInContext(gallivm->context);
3394 v2i32 = LLVMVectorType(i32, 2);
3395 v3i32 = LLVMVectorType(i32, 3);
3396 v4i32 = LLVMVectorType(i32, 4);
3397 v8i32 = LLVMVectorType(i32, 8);
3398 v16i8 = LLVMVectorType(i8, 16);
3399
3400 params[SI_PARAM_RW_BUFFERS] = const_array(v16i8, SI_NUM_RW_BUFFERS);
3401 params[SI_PARAM_CONST_BUFFERS] = const_array(v16i8, SI_NUM_CONST_BUFFERS);
3402 params[SI_PARAM_SAMPLER_STATES] = const_array(v4i32, SI_NUM_SAMPLER_STATES);
3403 params[SI_PARAM_SAMPLER_VIEWS] = const_array(v8i32, SI_NUM_SAMPLER_VIEWS);
3404 last_array_pointer = SI_PARAM_SAMPLER_VIEWS;
3405
3406 switch (si_shader_ctx->type) {
3407 case TGSI_PROCESSOR_VERTEX:
3408 params[SI_PARAM_VERTEX_BUFFERS] = const_array(v16i8, SI_NUM_VERTEX_BUFFERS);
3409 last_array_pointer = SI_PARAM_VERTEX_BUFFERS;
3410 params[SI_PARAM_BASE_VERTEX] = i32;
3411 params[SI_PARAM_START_INSTANCE] = i32;
3412 num_params = SI_PARAM_START_INSTANCE+1;
3413
3414 if (shader->key.vs.as_es) {
3415 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3416 } else if (shader->key.vs.as_ls) {
3417 params[SI_PARAM_LS_OUT_LAYOUT] = i32;
3418 num_params = SI_PARAM_LS_OUT_LAYOUT+1;
3419 } else {
3420 if (shader->is_gs_copy_shader) {
3421 last_array_pointer = SI_PARAM_CONST_BUFFERS;
3422 num_params = SI_PARAM_CONST_BUFFERS+1;
3423 } else {
3424 params[SI_PARAM_VS_STATE_BITS] = i32;
3425 num_params = SI_PARAM_VS_STATE_BITS+1;
3426 }
3427
3428 /* The locations of the other parameters are assigned dynamically. */
3429 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3430 params, i32, &num_params);
3431 }
3432
3433 last_sgpr = num_params-1;
3434
3435 /* VGPRs */
3436 params[si_shader_ctx->param_vertex_id = num_params++] = i32;
3437 params[si_shader_ctx->param_rel_auto_id = num_params++] = i32;
3438 params[si_shader_ctx->param_vs_prim_id = num_params++] = i32;
3439 params[si_shader_ctx->param_instance_id = num_params++] = i32;
3440 break;
3441
3442 case TGSI_PROCESSOR_TESS_CTRL:
3443 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3444 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3445 params[SI_PARAM_TCS_IN_LAYOUT] = i32;
3446 params[SI_PARAM_TESS_FACTOR_OFFSET] = i32;
3447 last_sgpr = SI_PARAM_TESS_FACTOR_OFFSET;
3448
3449 /* VGPRs */
3450 params[SI_PARAM_PATCH_ID] = i32;
3451 params[SI_PARAM_REL_IDS] = i32;
3452 num_params = SI_PARAM_REL_IDS+1;
3453 break;
3454
3455 case TGSI_PROCESSOR_TESS_EVAL:
3456 params[SI_PARAM_TCS_OUT_OFFSETS] = i32;
3457 params[SI_PARAM_TCS_OUT_LAYOUT] = i32;
3458 num_params = SI_PARAM_TCS_OUT_LAYOUT+1;
3459
3460 if (shader->key.tes.as_es) {
3461 params[si_shader_ctx->param_es2gs_offset = num_params++] = i32;
3462 } else {
3463 declare_streamout_params(si_shader_ctx, &shader->selector->so,
3464 params, i32, &num_params);
3465 }
3466 last_sgpr = num_params - 1;
3467
3468 /* VGPRs */
3469 params[si_shader_ctx->param_tes_u = num_params++] = f32;
3470 params[si_shader_ctx->param_tes_v = num_params++] = f32;
3471 params[si_shader_ctx->param_tes_rel_patch_id = num_params++] = i32;
3472 params[si_shader_ctx->param_tes_patch_id = num_params++] = i32;
3473 break;
3474
3475 case TGSI_PROCESSOR_GEOMETRY:
3476 params[SI_PARAM_GS2VS_OFFSET] = i32;
3477 params[SI_PARAM_GS_WAVE_ID] = i32;
3478 last_sgpr = SI_PARAM_GS_WAVE_ID;
3479
3480 /* VGPRs */
3481 params[SI_PARAM_VTX0_OFFSET] = i32;
3482 params[SI_PARAM_VTX1_OFFSET] = i32;
3483 params[SI_PARAM_PRIMITIVE_ID] = i32;
3484 params[SI_PARAM_VTX2_OFFSET] = i32;
3485 params[SI_PARAM_VTX3_OFFSET] = i32;
3486 params[SI_PARAM_VTX4_OFFSET] = i32;
3487 params[SI_PARAM_VTX5_OFFSET] = i32;
3488 params[SI_PARAM_GS_INSTANCE_ID] = i32;
3489 num_params = SI_PARAM_GS_INSTANCE_ID+1;
3490 break;
3491
3492 case TGSI_PROCESSOR_FRAGMENT:
3493 params[SI_PARAM_ALPHA_REF] = f32;
3494 params[SI_PARAM_PS_STATE_BITS] = i32;
3495 params[SI_PARAM_PRIM_MASK] = i32;
3496 last_sgpr = SI_PARAM_PRIM_MASK;
3497 params[SI_PARAM_PERSP_SAMPLE] = v2i32;
3498 params[SI_PARAM_PERSP_CENTER] = v2i32;
3499 params[SI_PARAM_PERSP_CENTROID] = v2i32;
3500 params[SI_PARAM_PERSP_PULL_MODEL] = v3i32;
3501 params[SI_PARAM_LINEAR_SAMPLE] = v2i32;
3502 params[SI_PARAM_LINEAR_CENTER] = v2i32;
3503 params[SI_PARAM_LINEAR_CENTROID] = v2i32;
3504 params[SI_PARAM_LINE_STIPPLE_TEX] = f32;
3505 params[SI_PARAM_POS_X_FLOAT] = f32;
3506 params[SI_PARAM_POS_Y_FLOAT] = f32;
3507 params[SI_PARAM_POS_Z_FLOAT] = f32;
3508 params[SI_PARAM_POS_W_FLOAT] = f32;
3509 params[SI_PARAM_FRONT_FACE] = f32;
3510 params[SI_PARAM_ANCILLARY] = i32;
3511 params[SI_PARAM_SAMPLE_COVERAGE] = f32;
3512 params[SI_PARAM_POS_FIXED_PT] = f32;
3513 num_params = SI_PARAM_POS_FIXED_PT+1;
3514 break;
3515
3516 default:
3517 assert(0 && "unimplemented shader");
3518 return;
3519 }
3520
3521 assert(num_params <= Elements(params));
3522 radeon_llvm_create_func(&si_shader_ctx->radeon_bld, params, num_params);
3523 radeon_llvm_shader_type(si_shader_ctx->radeon_bld.main_fn, si_shader_ctx->type);
3524
3525 if (shader->dx10_clamp_mode)
3526 LLVMAddTargetDependentFunctionAttr(si_shader_ctx->radeon_bld.main_fn,
3527 "enable-no-nans-fp-math", "true");
3528
3529 for (i = 0; i <= last_sgpr; ++i) {
3530 LLVMValueRef P = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
3531
3532 /* We tell llvm that array inputs are passed by value to allow Sinking pass
3533 * to move load. Inputs are constant so this is fine. */
3534 if (i <= last_array_pointer)
3535 LLVMAddAttribute(P, LLVMByValAttribute);
3536 else
3537 LLVMAddAttribute(P, LLVMInRegAttribute);
3538 }
3539
3540 if (bld_base->info &&
3541 (bld_base->info->opcode_count[TGSI_OPCODE_DDX] > 0 ||
3542 bld_base->info->opcode_count[TGSI_OPCODE_DDY] > 0 ||
3543 bld_base->info->opcode_count[TGSI_OPCODE_DDX_FINE] > 0 ||
3544 bld_base->info->opcode_count[TGSI_OPCODE_DDY_FINE] > 0 ||
3545 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_OFFSET] > 0 ||
3546 bld_base->info->opcode_count[TGSI_OPCODE_INTERP_SAMPLE] > 0))
3547 si_shader_ctx->lds =
3548 LLVMAddGlobalInAddressSpace(gallivm->module,
3549 LLVMArrayType(i32, 64),
3550 "ddxy_lds",
3551 LOCAL_ADDR_SPACE);
3552
3553 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX && shader->key.vs.as_ls) ||
3554 si_shader_ctx->type == TGSI_PROCESSOR_TESS_CTRL ||
3555 si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL) {
3556 /* This is the upper bound, maximum is 32 inputs times 32 vertices */
3557 unsigned vertex_data_dw_size = 32*32*4;
3558 unsigned patch_data_dw_size = 32*4;
3559 /* The formula is: TCS inputs + TCS outputs + TCS patch outputs. */
3560 unsigned patch_dw_size = vertex_data_dw_size*2 + patch_data_dw_size;
3561 unsigned lds_dwords = patch_dw_size;
3562
3563 /* The actual size is computed outside of the shader to reduce
3564 * the number of shader variants. */
3565 si_shader_ctx->lds =
3566 LLVMAddGlobalInAddressSpace(gallivm->module,
3567 LLVMArrayType(i32, lds_dwords),
3568 "tess_lds",
3569 LOCAL_ADDR_SPACE);
3570 }
3571 }
3572
3573 static void preload_constants(struct si_shader_context *si_shader_ctx)
3574 {
3575 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3576 struct gallivm_state * gallivm = bld_base->base.gallivm;
3577 const struct tgsi_shader_info * info = bld_base->info;
3578 unsigned buf;
3579 LLVMValueRef ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_CONST_BUFFERS);
3580
3581 for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
3582 unsigned i, num_const = info->const_file_max[buf] + 1;
3583
3584 if (num_const == 0)
3585 continue;
3586
3587 /* Allocate space for the constant values */
3588 si_shader_ctx->constants[buf] = CALLOC(num_const * 4, sizeof(LLVMValueRef));
3589
3590 /* Load the resource descriptor */
3591 si_shader_ctx->const_buffers[buf] =
3592 build_indexed_load_const(si_shader_ctx, ptr, lp_build_const_int32(gallivm, buf));
3593
3594 /* Load the constants, we rely on the code sinking to do the rest */
3595 for (i = 0; i < num_const * 4; ++i) {
3596 si_shader_ctx->constants[buf][i] =
3597 buffer_load_const(gallivm->builder,
3598 si_shader_ctx->const_buffers[buf],
3599 lp_build_const_int32(gallivm, i * 4),
3600 bld_base->base.elem_type);
3601 }
3602 }
3603 }
3604
3605 static void preload_samplers(struct si_shader_context *si_shader_ctx)
3606 {
3607 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3608 struct gallivm_state * gallivm = bld_base->base.gallivm;
3609 const struct tgsi_shader_info * info = bld_base->info;
3610
3611 unsigned i, num_samplers = info->file_max[TGSI_FILE_SAMPLER] + 1;
3612
3613 LLVMValueRef res_ptr, samp_ptr;
3614 LLVMValueRef offset;
3615
3616 if (num_samplers == 0)
3617 return;
3618
3619 res_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_VIEWS);
3620 samp_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, SI_PARAM_SAMPLER_STATES);
3621
3622 /* Load the resources and samplers, we rely on the code sinking to do the rest */
3623 for (i = 0; i < num_samplers; ++i) {
3624 /* Resource */
3625 offset = lp_build_const_int32(gallivm, i);
3626 si_shader_ctx->sampler_views[i] = build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3627
3628 /* Sampler */
3629 offset = lp_build_const_int32(gallivm, i);
3630 si_shader_ctx->sampler_states[i] = build_indexed_load_const(si_shader_ctx, samp_ptr, offset);
3631
3632 /* FMASK resource */
3633 if (info->is_msaa_sampler[i]) {
3634 offset = lp_build_const_int32(gallivm, SI_FMASK_TEX_OFFSET + i);
3635 si_shader_ctx->sampler_views[SI_FMASK_TEX_OFFSET + i] =
3636 build_indexed_load_const(si_shader_ctx, res_ptr, offset);
3637 }
3638 }
3639 }
3640
3641 static void preload_streamout_buffers(struct si_shader_context *si_shader_ctx)
3642 {
3643 struct lp_build_tgsi_context * bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3644 struct gallivm_state * gallivm = bld_base->base.gallivm;
3645 unsigned i;
3646
3647 /* Streamout can only be used if the shader is compiled as VS. */
3648 if (!si_shader_ctx->shader->selector->so.num_outputs ||
3649 (si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3650 (si_shader_ctx->shader->key.vs.as_es ||
3651 si_shader_ctx->shader->key.vs.as_ls)) ||
3652 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3653 si_shader_ctx->shader->key.tes.as_es))
3654 return;
3655
3656 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3657 SI_PARAM_RW_BUFFERS);
3658
3659 /* Load the resources, we rely on the code sinking to do the rest */
3660 for (i = 0; i < 4; ++i) {
3661 if (si_shader_ctx->shader->selector->so.stride[i]) {
3662 LLVMValueRef offset = lp_build_const_int32(gallivm,
3663 SI_SO_BUF_OFFSET + i);
3664
3665 si_shader_ctx->so_buffers[i] = build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3666 }
3667 }
3668 }
3669
3670 /**
3671 * Load ESGS and GSVS ring buffer resource descriptors and save the variables
3672 * for later use.
3673 */
3674 static void preload_ring_buffers(struct si_shader_context *si_shader_ctx)
3675 {
3676 struct gallivm_state *gallivm =
3677 si_shader_ctx->radeon_bld.soa.bld_base.base.gallivm;
3678
3679 LLVMValueRef buf_ptr = LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3680 SI_PARAM_RW_BUFFERS);
3681
3682 if ((si_shader_ctx->type == TGSI_PROCESSOR_VERTEX &&
3683 si_shader_ctx->shader->key.vs.as_es) ||
3684 (si_shader_ctx->type == TGSI_PROCESSOR_TESS_EVAL &&
3685 si_shader_ctx->shader->key.tes.as_es) ||
3686 si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3687 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_ESGS);
3688
3689 si_shader_ctx->esgs_ring =
3690 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3691 }
3692
3693 if (si_shader_ctx->shader->is_gs_copy_shader) {
3694 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS);
3695
3696 si_shader_ctx->gsvs_ring[0] =
3697 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3698 }
3699 if (si_shader_ctx->type == TGSI_PROCESSOR_GEOMETRY) {
3700 int i;
3701 for (i = 0; i < 4; i++) {
3702 LLVMValueRef offset = lp_build_const_int32(gallivm, SI_RING_GSVS + i);
3703
3704 si_shader_ctx->gsvs_ring[i] =
3705 build_indexed_load_const(si_shader_ctx, buf_ptr, offset);
3706 }
3707 }
3708 }
3709
3710 void si_shader_binary_read_config(struct radeon_shader_binary *binary,
3711 struct si_shader_config *conf,
3712 unsigned symbol_offset)
3713 {
3714 unsigned i;
3715 const unsigned char *config =
3716 radeon_shader_binary_config_start(binary, symbol_offset);
3717
3718 /* XXX: We may be able to emit some of these values directly rather than
3719 * extracting fields to be emitted later.
3720 */
3721
3722 for (i = 0; i < binary->config_size_per_symbol; i+= 8) {
3723 unsigned reg = util_le32_to_cpu(*(uint32_t*)(config + i));
3724 unsigned value = util_le32_to_cpu(*(uint32_t*)(config + i + 4));
3725 switch (reg) {
3726 case R_00B028_SPI_SHADER_PGM_RSRC1_PS:
3727 case R_00B128_SPI_SHADER_PGM_RSRC1_VS:
3728 case R_00B228_SPI_SHADER_PGM_RSRC1_GS:
3729 case R_00B848_COMPUTE_PGM_RSRC1:
3730 conf->num_sgprs = MAX2(conf->num_sgprs, (G_00B028_SGPRS(value) + 1) * 8);
3731 conf->num_vgprs = MAX2(conf->num_vgprs, (G_00B028_VGPRS(value) + 1) * 4);
3732 conf->float_mode = G_00B028_FLOAT_MODE(value);
3733 conf->rsrc1 = value;
3734 break;
3735 case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
3736 conf->lds_size = MAX2(conf->lds_size, G_00B02C_EXTRA_LDS_SIZE(value));
3737 break;
3738 case R_00B84C_COMPUTE_PGM_RSRC2:
3739 conf->lds_size = MAX2(conf->lds_size, G_00B84C_LDS_SIZE(value));
3740 conf->rsrc2 = value;
3741 break;
3742 case R_0286CC_SPI_PS_INPUT_ENA:
3743 conf->spi_ps_input_ena = value;
3744 break;
3745 case R_0286E8_SPI_TMPRING_SIZE:
3746 case R_00B860_COMPUTE_TMPRING_SIZE:
3747 /* WAVESIZE is in units of 256 dwords. */
3748 conf->scratch_bytes_per_wave =
3749 G_00B860_WAVESIZE(value) * 256 * 4 * 1;
3750 break;
3751 default:
3752 fprintf(stderr, "Warning: Compiler emitted unknown "
3753 "config register: 0x%x\n", reg);
3754 break;
3755 }
3756 }
3757 }
3758
3759 void si_shader_apply_scratch_relocs(struct si_context *sctx,
3760 struct si_shader *shader,
3761 uint64_t scratch_va)
3762 {
3763 unsigned i;
3764 uint32_t scratch_rsrc_dword0 = scratch_va;
3765 uint32_t scratch_rsrc_dword1 =
3766 S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
3767 | S_008F04_STRIDE(shader->config.scratch_bytes_per_wave / 64);
3768
3769 for (i = 0 ; i < shader->binary.reloc_count; i++) {
3770 const struct radeon_shader_reloc *reloc =
3771 &shader->binary.relocs[i];
3772 if (!strcmp(scratch_rsrc_dword0_symbol, reloc->name)) {
3773 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3774 &scratch_rsrc_dword0, 4);
3775 } else if (!strcmp(scratch_rsrc_dword1_symbol, reloc->name)) {
3776 util_memcpy_cpu_to_le32(shader->binary.code + reloc->offset,
3777 &scratch_rsrc_dword1, 4);
3778 }
3779 }
3780 }
3781
3782 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader *shader)
3783 {
3784 const struct radeon_shader_binary *binary = &shader->binary;
3785 unsigned code_size = binary->code_size + binary->rodata_size;
3786 unsigned char *ptr;
3787
3788 r600_resource_reference(&shader->bo, NULL);
3789 shader->bo = si_resource_create_custom(&sscreen->b.b,
3790 PIPE_USAGE_IMMUTABLE,
3791 code_size);
3792 if (!shader->bo)
3793 return -ENOMEM;
3794
3795 ptr = sscreen->b.ws->buffer_map(shader->bo->buf, NULL,
3796 PIPE_TRANSFER_READ_WRITE);
3797 util_memcpy_cpu_to_le32(ptr, binary->code, binary->code_size);
3798 if (binary->rodata_size > 0) {
3799 ptr += binary->code_size;
3800 util_memcpy_cpu_to_le32(ptr, binary->rodata,
3801 binary->rodata_size);
3802 }
3803
3804 sscreen->b.ws->buffer_unmap(shader->bo->buf);
3805 return 0;
3806 }
3807
3808 static void si_shader_dump_disassembly(const struct radeon_shader_binary *binary,
3809 struct pipe_debug_callback *debug)
3810 {
3811 char *line, *p;
3812 unsigned i, count;
3813
3814 if (binary->disasm_string) {
3815 fprintf(stderr, "\nShader Disassembly:\n\n");
3816 fprintf(stderr, "%s\n", binary->disasm_string);
3817
3818 if (debug && debug->debug_message) {
3819 /* Very long debug messages are cut off, so send the
3820 * disassembly one line at a time. This causes more
3821 * overhead, but on the plus side it simplifies
3822 * parsing of resulting logs.
3823 */
3824 pipe_debug_message(debug, SHADER_INFO,
3825 "Shader Disassembly Begin");
3826
3827 line = binary->disasm_string;
3828 while (*line) {
3829 p = strchrnul(line, '\n');
3830 count = p - line;
3831
3832 if (count) {
3833 pipe_debug_message(debug, SHADER_INFO,
3834 "%.*s", count, line);
3835 }
3836
3837 if (!*p)
3838 break;
3839 line = p + 1;
3840 }
3841
3842 pipe_debug_message(debug, SHADER_INFO,
3843 "Shader Disassembly End");
3844 }
3845 } else {
3846 fprintf(stderr, "SI CODE:\n");
3847 for (i = 0; i < binary->code_size; i += 4) {
3848 fprintf(stderr, "@0x%x: %02x%02x%02x%02x\n", i,
3849 binary->code[i + 3], binary->code[i + 2],
3850 binary->code[i + 1], binary->code[i]);
3851 }
3852 }
3853 }
3854
3855 static void si_shader_dump_stats(struct si_screen *sscreen,
3856 struct si_shader_config *conf,
3857 unsigned code_size,
3858 struct pipe_debug_callback *debug,
3859 unsigned processor)
3860 {
3861 if (r600_can_dump_shader(&sscreen->b, processor)) {
3862 fprintf(stderr, "*** SHADER STATS ***\n"
3863 "SGPRS: %d\nVGPRS: %d\nCode Size: %d bytes\nLDS: %d blocks\n"
3864 "Scratch: %d bytes per wave\n********************\n",
3865 conf->num_sgprs, conf->num_vgprs, code_size,
3866 conf->lds_size, conf->scratch_bytes_per_wave);
3867 }
3868
3869 pipe_debug_message(debug, SHADER_INFO,
3870 "Shader Stats: SGPRS: %d VGPRS: %d Code Size: %d LDS: %d Scratch: %d",
3871 conf->num_sgprs, conf->num_vgprs, code_size,
3872 conf->lds_size, conf->scratch_bytes_per_wave);
3873 }
3874
3875 static void si_shader_dump(struct si_screen *sscreen,
3876 struct radeon_shader_binary *binary,
3877 struct si_shader_config *conf,
3878 struct pipe_debug_callback *debug,
3879 unsigned processor)
3880 {
3881 if (r600_can_dump_shader(&sscreen->b, processor))
3882 if (!(sscreen->b.debug_flags & DBG_NO_ASM))
3883 si_shader_dump_disassembly(binary, debug);
3884
3885 si_shader_dump_stats(sscreen, conf, binary->code_size, debug, processor);
3886 }
3887
3888 void si_shader_binary_read(struct si_screen *sscreen,
3889 struct radeon_shader_binary *binary,
3890 struct si_shader_config *conf,
3891 struct pipe_debug_callback *debug,
3892 unsigned processor)
3893 {
3894 si_shader_binary_read_config(binary, conf, 0);
3895 si_shader_dump(sscreen, binary, conf, debug, processor);
3896 }
3897
3898 int si_compile_llvm(struct si_screen *sscreen,
3899 struct radeon_shader_binary *binary,
3900 struct si_shader_config *conf,
3901 LLVMTargetMachineRef tm,
3902 LLVMModuleRef mod,
3903 struct pipe_debug_callback *debug,
3904 unsigned processor)
3905 {
3906 int r = 0;
3907 unsigned count = p_atomic_inc_return(&sscreen->b.num_compilations);
3908
3909 if (r600_can_dump_shader(&sscreen->b, processor)) {
3910 fprintf(stderr, "radeonsi: Compiling shader %d\n", count);
3911
3912 if (!(sscreen->b.debug_flags & DBG_NO_IR))
3913 LLVMDumpModule(mod);
3914 }
3915
3916 if (!si_replace_shader(count, binary)) {
3917 r = radeon_llvm_compile(mod, binary,
3918 r600_get_llvm_processor_name(sscreen->b.family), tm,
3919 debug);
3920 if (r)
3921 return r;
3922 }
3923
3924 si_shader_binary_read(sscreen, binary, conf, debug, processor);
3925
3926 FREE(binary->config);
3927 FREE(binary->global_symbol_offsets);
3928 binary->config = NULL;
3929 binary->global_symbol_offsets = NULL;
3930 return r;
3931 }
3932
3933 /* Generate code for the hardware VS shader stage to go with a geometry shader */
3934 static int si_generate_gs_copy_shader(struct si_screen *sscreen,
3935 struct si_shader_context *si_shader_ctx,
3936 struct si_shader *gs, bool dump,
3937 struct pipe_debug_callback *debug)
3938 {
3939 struct gallivm_state *gallivm = &si_shader_ctx->radeon_bld.gallivm;
3940 struct lp_build_tgsi_context *bld_base = &si_shader_ctx->radeon_bld.soa.bld_base;
3941 struct lp_build_context *base = &bld_base->base;
3942 struct lp_build_context *uint = &bld_base->uint_bld;
3943 struct si_shader *shader = si_shader_ctx->shader;
3944 struct si_shader_output_values *outputs;
3945 struct tgsi_shader_info *gsinfo = &gs->selector->info;
3946 LLVMValueRef args[9];
3947 int i, r;
3948
3949 outputs = MALLOC(gsinfo->num_outputs * sizeof(outputs[0]));
3950
3951 si_shader_ctx->type = TGSI_PROCESSOR_VERTEX;
3952 shader->is_gs_copy_shader = true;
3953
3954 radeon_llvm_context_init(&si_shader_ctx->radeon_bld);
3955
3956 create_meta_data(si_shader_ctx);
3957 create_function(si_shader_ctx);
3958 preload_streamout_buffers(si_shader_ctx);
3959 preload_ring_buffers(si_shader_ctx);
3960
3961 args[0] = si_shader_ctx->gsvs_ring[0];
3962 args[1] = lp_build_mul_imm(uint,
3963 LLVMGetParam(si_shader_ctx->radeon_bld.main_fn,
3964 si_shader_ctx->param_vertex_id),
3965 4);
3966 args[3] = uint->zero;
3967 args[4] = uint->one; /* OFFEN */
3968 args[5] = uint->zero; /* IDXEN */
3969 args[6] = uint->one; /* GLC */
3970 args[7] = uint->one; /* SLC */
3971 args[8] = uint->zero; /* TFE */
3972
3973 /* Fetch vertex data from GSVS ring */
3974 for (i = 0; i < gsinfo->num_outputs; ++i) {
3975 unsigned chan;
3976
3977 outputs[i].name = gsinfo->output_semantic_name[i];
3978 outputs[i].sid = gsinfo->output_semantic_index[i];
3979
3980 for (chan = 0; chan < 4; chan++) {
3981 args[2] = lp_build_const_int32(gallivm,
3982 (i * 4 + chan) *
3983 gs->selector->gs_max_out_vertices * 16 * 4);
3984
3985 outputs[i].values[chan] =
3986 LLVMBuildBitCast(gallivm->builder,
3987 lp_build_intrinsic(gallivm->builder,
3988 "llvm.SI.buffer.load.dword.i32.i32",
3989 LLVMInt32TypeInContext(gallivm->context),
3990 args, 9,
3991 LLVMReadOnlyAttribute | LLVMNoUnwindAttribute),
3992 base->elem_type, "");
3993 }
3994 }
3995
3996 si_llvm_export_vs(bld_base, outputs, gsinfo->num_outputs);
3997
3998 radeon_llvm_finalize_module(&si_shader_ctx->radeon_bld);
3999
4000 if (dump)
4001 fprintf(stderr, "Copy Vertex Shader for Geometry Shader:\n\n");
4002
4003 r = si_compile_llvm(sscreen, &si_shader_ctx->shader->binary,
4004 &si_shader_ctx->shader->config, si_shader_ctx->tm,
4005 bld_base->base.gallivm->module,
4006 debug, TGSI_PROCESSOR_GEOMETRY);
4007 if (!r)
4008 r = si_shader_binary_upload(sscreen, si_shader_ctx->shader);
4009
4010 radeon_llvm_dispose(&si_shader_ctx->radeon_bld);
4011
4012 FREE(outputs);
4013 return r;
4014 }
4015
4016 void si_dump_shader_key(unsigned shader, union si_shader_key *key, FILE *f)
4017 {
4018 int i;
4019
4020 fprintf(f, "SHADER KEY\n");
4021
4022 switch (shader) {
4023 case PIPE_SHADER_VERTEX:
4024 fprintf(f, " instance_divisors = {");
4025 for (i = 0; i < Elements(key->vs.instance_divisors); i++)
4026 fprintf(f, !i ? "%u" : ", %u",
4027 key->vs.instance_divisors[i]);
4028 fprintf(f, "}\n");
4029 fprintf(f, " as_es = %u\n", key->vs.as_es);
4030 fprintf(f, " as_ls = %u\n", key->vs.as_ls);
4031 fprintf(f, " export_prim_id = %u\n", key->vs.export_prim_id);
4032 break;
4033
4034 case PIPE_SHADER_TESS_CTRL:
4035 fprintf(f, " prim_mode = %u\n", key->tcs.prim_mode);
4036 break;
4037
4038 case PIPE_SHADER_TESS_EVAL:
4039 fprintf(f, " as_es = %u\n", key->tes.as_es);
4040 fprintf(f, " export_prim_id = %u\n", key->tes.export_prim_id);
4041 break;
4042
4043 case PIPE_SHADER_GEOMETRY:
4044 break;
4045
4046 case PIPE_SHADER_FRAGMENT:
4047 fprintf(f, " export_16bpc = 0x%X\n", key->ps.export_16bpc);
4048 fprintf(f, " last_cbuf = %u\n", key->ps.last_cbuf);
4049 fprintf(f, " color_two_side = %u\n", key->ps.color_two_side);
4050 fprintf(f, " alpha_func = %u\n", key->ps.alpha_func);
4051 fprintf(f, " alpha_to_one = %u\n", key->ps.alpha_to_one);
4052 fprintf(f, " poly_stipple = %u\n", key->ps.poly_stipple);
4053 fprintf(f, " clamp_color = %u\n", key->ps.clamp_color);
4054 break;
4055
4056 default:
4057 assert(0);
4058 }
4059 }
4060
4061 int si_shader_create(struct si_screen *sscreen, LLVMTargetMachineRef tm,
4062 struct si_shader *shader,
4063 struct pipe_debug_callback *debug)
4064 {
4065 struct si_shader_selector *sel = shader->selector;
4066 struct tgsi_token *tokens = sel->tokens;
4067 struct si_shader_context si_shader_ctx;
4068 struct lp_build_tgsi_context * bld_base;
4069 struct tgsi_shader_info stipple_shader_info;
4070 LLVMModuleRef mod;
4071 int r = 0;
4072 bool poly_stipple = sel->type == PIPE_SHADER_FRAGMENT &&
4073 shader->key.ps.poly_stipple;
4074 bool dump = r600_can_dump_shader(&sscreen->b, sel->info.processor);
4075
4076 if (poly_stipple) {
4077 tokens = util_pstipple_create_fragment_shader(tokens, NULL,
4078 SI_POLY_STIPPLE_SAMPLER);
4079 tgsi_scan_shader(tokens, &stipple_shader_info);
4080 }
4081
4082 /* Dump TGSI code before doing TGSI->LLVM conversion in case the
4083 * conversion fails. */
4084 if (dump && !(sscreen->b.debug_flags & DBG_NO_TGSI)) {
4085 si_dump_shader_key(sel->type, &shader->key, stderr);
4086 tgsi_dump(tokens, 0);
4087 si_dump_streamout(&sel->so);
4088 }
4089
4090 assert(shader->nparam == 0);
4091
4092 memset(&si_shader_ctx, 0, sizeof(si_shader_ctx));
4093 radeon_llvm_context_init(&si_shader_ctx.radeon_bld);
4094 bld_base = &si_shader_ctx.radeon_bld.soa.bld_base;
4095
4096 if (sel->type != PIPE_SHADER_COMPUTE)
4097 shader->dx10_clamp_mode = true;
4098
4099 shader->uses_instanceid = sel->info.uses_instanceid;
4100 bld_base->info = poly_stipple ? &stipple_shader_info : &sel->info;
4101 bld_base->emit_fetch_funcs[TGSI_FILE_CONSTANT] = fetch_constant;
4102
4103 bld_base->op_actions[TGSI_OPCODE_INTERP_CENTROID] = interp_action;
4104 bld_base->op_actions[TGSI_OPCODE_INTERP_SAMPLE] = interp_action;
4105 bld_base->op_actions[TGSI_OPCODE_INTERP_OFFSET] = interp_action;
4106
4107 bld_base->op_actions[TGSI_OPCODE_TEX] = tex_action;
4108 bld_base->op_actions[TGSI_OPCODE_TEX2] = tex_action;
4109 bld_base->op_actions[TGSI_OPCODE_TXB] = tex_action;
4110 bld_base->op_actions[TGSI_OPCODE_TXB2] = tex_action;
4111 bld_base->op_actions[TGSI_OPCODE_TXD] = tex_action;
4112 bld_base->op_actions[TGSI_OPCODE_TXF] = tex_action;
4113 bld_base->op_actions[TGSI_OPCODE_TXL] = tex_action;
4114 bld_base->op_actions[TGSI_OPCODE_TXL2] = tex_action;
4115 bld_base->op_actions[TGSI_OPCODE_TXP] = tex_action;
4116 bld_base->op_actions[TGSI_OPCODE_TXQ] = tex_action;
4117 bld_base->op_actions[TGSI_OPCODE_TG4] = tex_action;
4118 bld_base->op_actions[TGSI_OPCODE_LODQ] = tex_action;
4119 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
4120
4121 bld_base->op_actions[TGSI_OPCODE_DDX].emit = si_llvm_emit_ddxy;
4122 bld_base->op_actions[TGSI_OPCODE_DDY].emit = si_llvm_emit_ddxy;
4123 bld_base->op_actions[TGSI_OPCODE_DDX_FINE].emit = si_llvm_emit_ddxy;
4124 bld_base->op_actions[TGSI_OPCODE_DDY_FINE].emit = si_llvm_emit_ddxy;
4125
4126 bld_base->op_actions[TGSI_OPCODE_EMIT].emit = si_llvm_emit_vertex;
4127 bld_base->op_actions[TGSI_OPCODE_ENDPRIM].emit = si_llvm_emit_primitive;
4128 bld_base->op_actions[TGSI_OPCODE_BARRIER].emit = si_llvm_emit_barrier;
4129
4130 if (HAVE_LLVM >= 0x0306) {
4131 bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
4132 bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.maxnum.f32";
4133 bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
4134 bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.minnum.f32";
4135 }
4136
4137 si_shader_ctx.radeon_bld.load_system_value = declare_system_value;
4138 si_shader_ctx.shader = shader;
4139 si_shader_ctx.type = tgsi_get_processor_type(tokens);
4140 si_shader_ctx.screen = sscreen;
4141 si_shader_ctx.tm = tm;
4142
4143 switch (si_shader_ctx.type) {
4144 case TGSI_PROCESSOR_VERTEX:
4145 si_shader_ctx.radeon_bld.load_input = declare_input_vs;
4146 if (shader->key.vs.as_ls)
4147 bld_base->emit_epilogue = si_llvm_emit_ls_epilogue;
4148 else if (shader->key.vs.as_es)
4149 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4150 else
4151 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4152 break;
4153 case TGSI_PROCESSOR_TESS_CTRL:
4154 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
4155 bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
4156 bld_base->emit_store = store_output_tcs;
4157 bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
4158 break;
4159 case TGSI_PROCESSOR_TESS_EVAL:
4160 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
4161 if (shader->key.tes.as_es)
4162 bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
4163 else
4164 bld_base->emit_epilogue = si_llvm_emit_vs_epilogue;
4165 break;
4166 case TGSI_PROCESSOR_GEOMETRY:
4167 bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
4168 bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
4169 break;
4170 case TGSI_PROCESSOR_FRAGMENT:
4171 si_shader_ctx.radeon_bld.load_input = declare_input_fs;
4172 bld_base->emit_epilogue = si_llvm_emit_fs_epilogue;
4173 break;
4174 default:
4175 assert(!"Unsupported shader type");
4176 return -1;
4177 }
4178
4179 create_meta_data(&si_shader_ctx);
4180 create_function(&si_shader_ctx);
4181 preload_constants(&si_shader_ctx);
4182 preload_samplers(&si_shader_ctx);
4183 preload_streamout_buffers(&si_shader_ctx);
4184 preload_ring_buffers(&si_shader_ctx);
4185
4186 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4187 int i;
4188 for (i = 0; i < 4; i++) {
4189 si_shader_ctx.gs_next_vertex[i] =
4190 lp_build_alloca(bld_base->base.gallivm,
4191 bld_base->uint_bld.elem_type, "");
4192 }
4193 }
4194
4195 if (!lp_build_tgsi_llvm(bld_base, tokens)) {
4196 fprintf(stderr, "Failed to translate shader from TGSI to LLVM\n");
4197 goto out;
4198 }
4199
4200 radeon_llvm_finalize_module(&si_shader_ctx.radeon_bld);
4201
4202 mod = bld_base->base.gallivm->module;
4203 r = si_compile_llvm(sscreen, &shader->binary, &shader->config, tm,
4204 mod, debug, si_shader_ctx.type);
4205 if (r) {
4206 fprintf(stderr, "LLVM failed to compile shader\n");
4207 goto out;
4208 }
4209
4210 r = si_shader_binary_upload(sscreen, shader);
4211 if (r) {
4212 fprintf(stderr, "LLVM failed to upload shader\n");
4213 goto out;
4214 }
4215
4216 radeon_llvm_dispose(&si_shader_ctx.radeon_bld);
4217
4218 if (si_shader_ctx.type == TGSI_PROCESSOR_GEOMETRY) {
4219 shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
4220 shader->gs_copy_shader->selector = shader->selector;
4221 shader->gs_copy_shader->key = shader->key;
4222 si_shader_ctx.shader = shader->gs_copy_shader;
4223 if ((r = si_generate_gs_copy_shader(sscreen, &si_shader_ctx,
4224 shader, dump, debug))) {
4225 free(shader->gs_copy_shader);
4226 shader->gs_copy_shader = NULL;
4227 goto out;
4228 }
4229 }
4230
4231 out:
4232 for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
4233 FREE(si_shader_ctx.constants[i]);
4234 if (poly_stipple)
4235 tgsi_free_tokens(tokens);
4236 return r;
4237 }
4238
4239 void si_shader_destroy_binary(struct radeon_shader_binary *binary)
4240 {
4241 FREE(binary->code);
4242 FREE(binary->rodata);
4243 FREE(binary->relocs);
4244 FREE(binary->disasm_string);
4245 }
4246
4247 void si_shader_destroy(struct si_shader *shader)
4248 {
4249 if (shader->gs_copy_shader) {
4250 si_shader_destroy(shader->gs_copy_shader);
4251 FREE(shader->gs_copy_shader);
4252 }
4253
4254 if (shader->scratch_bo)
4255 r600_resource_reference(&shader->scratch_bo, NULL);
4256
4257 r600_resource_reference(&shader->bo, NULL);
4258 si_shader_destroy_binary(&shader->binary);
4259 }