src/gallium/drivers/radeonsi/si_shader_internal.h

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #ifndef SI_SHADER_PRIVATE_H
  25 #define SI_SHADER_PRIVATE_H
  26
  27 #include "si_shader.h"
  28 #include "gallivm/lp_bld_init.h"
  29 #include "gallivm/lp_bld_tgsi.h"
  30 #include "tgsi/tgsi_parse.h"
  31
  32 #include <llvm-c/Core.h>
  33 #include <llvm-c/TargetMachine.h>
  34
  35 struct pipe_debug_callback;
  36 struct radeon_shader_binary;
  37
  38 #define RADEON_LLVM_MAX_INPUT_SLOTS 32
  39 #define RADEON_LLVM_MAX_INPUTS 32 * 4
  40 #define RADEON_LLVM_MAX_OUTPUTS 32 * 4
  41
  42 #define RADEON_LLVM_INITIAL_CF_DEPTH 4
  43
  44 #define RADEON_LLVM_MAX_SYSTEM_VALUES 4
  45
  46 struct si_llvm_flow;
  47
  48 struct si_shader_context {
  49         struct lp_build_tgsi_soa_context soa;
  50         struct gallivm_state gallivm;
  51         struct si_shader *shader;
  52         struct si_screen *screen;
  53
  54         unsigned type; /* PIPE_SHADER_* specifies the type of shader. */
  55         bool is_gs_copy_shader;
  56         /* Whether to generate the optimized shader variant compiled as a whole
  57          * (without a prolog and epilog)
  58          */
  59         bool is_monolithic;
  60
  61         /** This function is responsible for initilizing the inputs array and will be
  62           * called once for each input declared in the TGSI shader.
  63           */
  64         void (*load_input)(struct si_shader_context *,
  65                            unsigned input_index,
  66                            const struct tgsi_full_declaration *decl,
  67                            LLVMValueRef out[4]);
  68
  69         void (*load_system_value)(struct si_shader_context *,
  70                                   unsigned index,
  71                                   const struct tgsi_full_declaration *decl);
  72
  73         void (*declare_memory_region)(struct si_shader_context *,
  74                                       const struct tgsi_full_declaration *decl);
  75
  76         /** This array contains the input values for the shader.  Typically these
  77           * values will be in the form of a target intrinsic that will inform the
  78           * backend how to load the actual inputs to the shader.
  79           */
  80         struct tgsi_full_declaration input_decls[RADEON_LLVM_MAX_INPUT_SLOTS];
  81         LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS];
  82         LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS][TGSI_NUM_CHANNELS];
  83
  84         /** This pointer is used to contain the temporary values.
  85           * The amount of temporary used in tgsi can't be bound to a max value and
  86           * thus we must allocate this array at runtime.
  87           */
  88         LLVMValueRef *temps;
  89         unsigned temps_count;
  90         LLVMValueRef system_values[RADEON_LLVM_MAX_SYSTEM_VALUES];
  91
  92         struct si_llvm_flow *flow;
  93         unsigned flow_depth;
  94         unsigned flow_depth_max;
  95
  96         struct tgsi_array_info *temp_arrays;
  97         LLVMValueRef *temp_array_allocas;
  98
  99         LLVMValueRef undef_alloca;
 100
 101         LLVMValueRef main_fn;
 102         LLVMTypeRef return_type;
 103
 104         int param_streamout_config;
 105         int param_streamout_write_index;
 106         int param_streamout_offset[4];
 107         int param_vertex_id;
 108         int param_rel_auto_id;
 109         int param_vs_prim_id;
 110         int param_instance_id;
 111         int param_vertex_index0;
 112         int param_tes_u;
 113         int param_tes_v;
 114         int param_tes_rel_patch_id;
 115         int param_tes_patch_id;
 116         int param_es2gs_offset;
 117         int param_oc_lds;
 118
 119         /* Sets a bit if the dynamic HS control word was 0x80000000. The bit is
 120          * 0x800000 for VS, 0x1 for ES.
 121          */
 122         int param_tess_offchip;
 123
 124         LLVMTargetMachineRef tm;
 125
 126         unsigned invariant_load_md_kind;
 127         unsigned range_md_kind;
 128         unsigned uniform_md_kind;
 129         unsigned fpmath_md_kind;
 130         LLVMValueRef fpmath_md_2p5_ulp;
 131         LLVMValueRef empty_md;
 132
 133         /* Preloaded descriptors. */
 134         LLVMValueRef esgs_ring;
 135         LLVMValueRef gsvs_ring[4];
 136
 137         LLVMValueRef lds;
 138         LLVMValueRef gs_next_vertex[4];
 139         LLVMValueRef return_value;
 140
 141         LLVMTypeRef voidt;
 142         LLVMTypeRef i1;
 143         LLVMTypeRef i8;
 144         LLVMTypeRef i32;
 145         LLVMTypeRef i64;
 146         LLVMTypeRef i128;
 147         LLVMTypeRef f32;
 148         LLVMTypeRef v16i8;
 149         LLVMTypeRef v2i32;
 150         LLVMTypeRef v4i32;
 151         LLVMTypeRef v4f32;
 152         LLVMTypeRef v8i32;
 153
 154         LLVMValueRef shared_memory;
 155 };
 156
 157 static inline struct si_shader_context *
 158 si_shader_context(struct lp_build_tgsi_context *bld_base)
 159 {
 160         return (struct si_shader_context*)bld_base;
 161 }
 162
 163 void si_llvm_add_attribute(LLVMValueRef F, const char *name, int value);
 164 void si_llvm_shader_type(LLVMValueRef F, unsigned type);
 165
 166 LLVMTargetRef si_llvm_get_amdgpu_target(const char *triple);
 167
 168 unsigned si_llvm_compile(LLVMModuleRef M, struct radeon_shader_binary *binary,
 169                          LLVMTargetMachineRef tm,
 170                          struct pipe_debug_callback *debug);
 171
 172 LLVMTypeRef tgsi2llvmtype(struct lp_build_tgsi_context *bld_base,
 173                           enum tgsi_opcode_type type);
 174
 175 LLVMValueRef bitcast(struct lp_build_tgsi_context *bld_base,
 176                      enum tgsi_opcode_type type, LLVMValueRef value);
 177
 178 LLVMValueRef si_llvm_bound_index(struct si_shader_context *ctx,
 179                                  LLVMValueRef index,
 180                                  unsigned num);
 181
 182 void si_llvm_context_init(struct si_shader_context *ctx,
 183                           const char *triple,
 184                           const struct tgsi_shader_info *info,
 185                           const struct tgsi_token *tokens);
 186
 187 void si_llvm_create_func(struct si_shader_context *ctx,
 188                          LLVMTypeRef *return_types, unsigned num_return_elems,
 189                          LLVMTypeRef *ParamTypes, unsigned ParamCount);
 190
 191 void si_llvm_dispose(struct si_shader_context *ctx);
 192
 193 void si_llvm_finalize_module(struct si_shader_context *ctx,
 194                              bool run_verifier);
 195
 196 LLVMValueRef si_llvm_emit_fetch_64bit(struct lp_build_tgsi_context *bld_base,
 197                                       enum tgsi_opcode_type type,
 198                                       LLVMValueRef ptr,
 199                                       LLVMValueRef ptr2);
 200
 201 LLVMValueRef si_llvm_saturate(struct lp_build_tgsi_context *bld_base,
 202                               LLVMValueRef value);
 203
 204 LLVMValueRef si_llvm_emit_fetch(struct lp_build_tgsi_context *bld_base,
 205                                 const struct tgsi_full_src_register *reg,
 206                                 enum tgsi_opcode_type type,
 207                                 unsigned swizzle);
 208
 209 void si_llvm_emit_store(struct lp_build_tgsi_context *bld_base,
 210                         const struct tgsi_full_instruction *inst,
 211                         const struct tgsi_opcode_info *info,
 212                         LLVMValueRef dst[4]);
 213
 214 void si_shader_context_init_alu(struct lp_build_tgsi_context *bld_base);
 215 void si_prepare_cube_coords(struct lp_build_tgsi_context *bld_base,
 216                             struct lp_build_emit_data *emit_data,
 217                             LLVMValueRef *coords_arg,
 218                             LLVMValueRef *derivs_arg);
 219
 220 #endif