2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "ac_nir_to_llvm.h"
26 #include "compiler/nir/nir.h"
27 #include "compiler/nir/nir_builder.h"
28 #include "compiler/nir/nir_deref.h"
29 #include "compiler/nir_types.h"
31 #include "si_shader_internal.h"
32 #include "tgsi/tgsi_from_mesa.h"
34 static const nir_deref_instr
*tex_get_texture_deref(nir_tex_instr
*instr
)
36 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
37 switch (instr
->src
[i
].src_type
) {
38 case nir_tex_src_texture_deref
:
39 return nir_src_as_deref(instr
->src
[i
].src
);
48 static void scan_io_usage(struct si_shader_info
*info
, nir_intrinsic_instr
*intr
,
51 unsigned interp
= TGSI_INTERPOLATE_CONSTANT
; /* load_input uses flat shading */
53 if (intr
->intrinsic
== nir_intrinsic_load_interpolated_input
) {
54 nir_intrinsic_instr
*baryc
= nir_instr_as_intrinsic(intr
->src
[0].ssa
->parent_instr
);
57 if (nir_intrinsic_infos
[baryc
->intrinsic
].index_map
[NIR_INTRINSIC_INTERP_MODE
] > 0)
58 interp
= tgsi_get_interp_mode(nir_intrinsic_interp_mode(baryc
), false);
60 unreachable("unknown barycentric intrinsic");
62 unreachable("unknown barycentric expression");
66 unsigned mask
, bit_size
;
69 if (nir_intrinsic_infos
[intr
->intrinsic
].index_map
[NIR_INTRINSIC_WRMASK
] > 0) {
70 mask
= nir_intrinsic_write_mask(intr
); /* store */
71 bit_size
= nir_src_bit_size(intr
->src
[0]);
72 dual_slot
= bit_size
== 64 && nir_src_num_components(intr
->src
[0]) >= 3;
74 mask
= nir_ssa_def_components_read(&intr
->dest
.ssa
); /* load */
75 bit_size
= intr
->dest
.ssa
.bit_size
;
76 dual_slot
= bit_size
== 64 && intr
->dest
.ssa
.num_components
>= 3;
79 /* Convert the 64-bit component mask to a 32-bit component mask. */
81 unsigned new_mask
= 0;
82 for (unsigned i
= 0; i
< 4; i
++) {
84 new_mask
|= 0x3 << (2 * i
);
89 /* Convert the 16-bit component mask to a 32-bit component mask. */
91 unsigned new_mask
= 0;
92 for (unsigned i
= 0; i
< 4; i
++) {
94 new_mask
|= 0x1 << (i
/ 2);
99 mask
<<= nir_intrinsic_component(intr
);
101 unsigned name
, index
;
102 if (info
->processor
== PIPE_SHADER_VERTEX
&& is_input
) {
103 /* VS doesn't have semantics. */
106 } else if (info
->processor
== PIPE_SHADER_FRAGMENT
&& !is_input
) {
107 tgsi_get_gl_frag_result_semantic(nir_intrinsic_io_semantics(intr
).location
,
109 /* Adjust for dual source blending. */
110 if (nir_intrinsic_io_semantics(intr
).dual_source_blend_index
)
113 tgsi_get_gl_varying_semantic(nir_intrinsic_io_semantics(intr
).location
,
114 true, &name
, &index
);
117 nir_src offset
= *nir_get_io_offset_src(intr
);
118 bool indirect
= !nir_src_is_const(offset
);
120 assert(nir_src_as_uint(offset
) == 0);
122 unsigned driver_location
= nir_intrinsic_base(intr
);
123 unsigned num_slots
= indirect
? nir_intrinsic_io_semantics(intr
).num_slots
: (1 + dual_slot
);
126 assert(driver_location
+ num_slots
<= ARRAY_SIZE(info
->input_usage_mask
));
128 for (unsigned i
= 0; i
< num_slots
; i
++) {
129 unsigned loc
= driver_location
+ i
;
130 unsigned slot_mask
= (dual_slot
&& i
% 2 ? mask
>> 4 : mask
) & 0xf;
132 info
->input_semantic_name
[loc
] = name
;
133 info
->input_semantic_index
[loc
] = index
+ i
;
134 info
->input_interpolate
[loc
] = interp
;
137 info
->input_usage_mask
[loc
] |= slot_mask
;
138 info
->num_inputs
= MAX2(info
->num_inputs
, loc
+ 1);
140 if (name
== TGSI_SEMANTIC_PRIMID
)
141 info
->uses_primid
= true;
146 assert(driver_location
+ num_slots
<= ARRAY_SIZE(info
->output_usagemask
));
148 for (unsigned i
= 0; i
< num_slots
; i
++) {
149 unsigned loc
= driver_location
+ i
;
150 unsigned slot_mask
= (dual_slot
&& i
% 2 ? mask
>> 4 : mask
) & 0xf;
152 info
->output_semantic_name
[loc
] = name
;
153 info
->output_semantic_index
[loc
] = index
+ i
;
156 if (info
->processor
== PIPE_SHADER_GEOMETRY
) {
157 unsigned gs_streams
= (uint32_t)nir_intrinsic_io_semantics(intr
).gs_streams
<<
158 (nir_intrinsic_component(intr
) * 2);
159 unsigned new_mask
= slot_mask
& ~info
->output_usagemask
[loc
];
161 for (unsigned i
= 0; i
< 4; i
++) {
162 unsigned stream
= (gs_streams
>> (i
* 2)) & 0x3;
164 if (new_mask
& (1 << i
)) {
165 info
->output_streams
[loc
] |= stream
<< (i
* 2);
166 info
->num_stream_output_components
[stream
]++;
171 info
->output_usagemask
[loc
] |= slot_mask
;
172 info
->num_outputs
= MAX2(info
->num_outputs
, loc
+ 1);
175 case TGSI_SEMANTIC_PRIMID
:
176 info
->writes_primid
= true;
178 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
179 info
->writes_viewport_index
= true;
181 case TGSI_SEMANTIC_LAYER
:
182 info
->writes_layer
= true;
184 case TGSI_SEMANTIC_PSIZE
:
185 info
->writes_psize
= true;
187 case TGSI_SEMANTIC_CLIPVERTEX
:
188 info
->writes_clipvertex
= true;
190 case TGSI_SEMANTIC_COLOR
:
191 info
->colors_written
|= 1 << (index
+ i
);
193 if (info
->processor
== PIPE_SHADER_FRAGMENT
&&
194 nir_intrinsic_io_semantics(intr
).location
== FRAG_RESULT_COLOR
)
195 info
->properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] = true;
197 case TGSI_SEMANTIC_STENCIL
:
198 info
->writes_stencil
= true;
200 case TGSI_SEMANTIC_SAMPLEMASK
:
201 info
->writes_samplemask
= true;
203 case TGSI_SEMANTIC_EDGEFLAG
:
204 info
->writes_edgeflag
= true;
206 case TGSI_SEMANTIC_POSITION
:
207 if (info
->processor
== PIPE_SHADER_FRAGMENT
)
208 info
->writes_z
= true;
210 info
->writes_position
= true;
218 static void scan_instruction(const struct nir_shader
*nir
, struct si_shader_info
*info
,
221 if (instr
->type
== nir_instr_type_alu
) {
222 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
227 case nir_op_fddx_fine
:
228 case nir_op_fddy_fine
:
229 case nir_op_fddx_coarse
:
230 case nir_op_fddy_coarse
:
231 info
->uses_derivatives
= true;
236 } else if (instr
->type
== nir_instr_type_tex
) {
237 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
238 const nir_deref_instr
*deref
= tex_get_texture_deref(tex
);
239 nir_variable
*var
= deref
? nir_deref_instr_get_variable(deref
) : NULL
;
242 info
->samplers_declared
|= u_bit_consecutive(tex
->sampler_index
, 1);
244 if (deref
->mode
!= nir_var_uniform
|| var
->data
.bindless
)
245 info
->uses_bindless_samplers
= true;
252 info
->uses_derivatives
= true;
257 } else if (instr
->type
== nir_instr_type_intrinsic
) {
258 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
260 switch (intr
->intrinsic
) {
261 case nir_intrinsic_load_front_face
:
262 info
->uses_frontface
= 1;
264 case nir_intrinsic_load_instance_id
:
265 info
->uses_instanceid
= 1;
267 case nir_intrinsic_load_invocation_id
:
268 info
->uses_invocationid
= true;
270 case nir_intrinsic_load_num_work_groups
:
271 info
->uses_grid_size
= true;
273 case nir_intrinsic_load_local_invocation_index
:
274 case nir_intrinsic_load_subgroup_id
:
275 case nir_intrinsic_load_num_subgroups
:
276 info
->uses_subgroup_info
= true;
278 case nir_intrinsic_load_local_group_size
:
279 /* The block size is translated to IMM with a fixed block size. */
280 if (info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] == 0)
281 info
->uses_block_size
= true;
283 case nir_intrinsic_load_local_invocation_id
:
284 case nir_intrinsic_load_work_group_id
: {
285 unsigned mask
= nir_ssa_def_components_read(&intr
->dest
.ssa
);
287 unsigned i
= u_bit_scan(&mask
);
289 if (intr
->intrinsic
== nir_intrinsic_load_work_group_id
)
290 info
->uses_block_id
[i
] = true;
292 info
->uses_thread_id
[i
] = true;
296 case nir_intrinsic_load_vertex_id
:
297 info
->uses_vertexid
= 1;
299 case nir_intrinsic_load_vertex_id_zero_base
:
300 info
->uses_vertexid_nobase
= 1;
302 case nir_intrinsic_load_base_vertex
:
303 info
->uses_basevertex
= 1;
305 case nir_intrinsic_load_draw_id
:
306 info
->uses_drawid
= 1;
308 case nir_intrinsic_load_primitive_id
:
309 info
->uses_primid
= 1;
311 case nir_intrinsic_load_sample_mask_in
:
312 info
->reads_samplemask
= true;
314 case nir_intrinsic_load_tess_level_inner
:
315 case nir_intrinsic_load_tess_level_outer
:
316 info
->reads_tess_factors
= true;
318 case nir_intrinsic_bindless_image_load
:
319 case nir_intrinsic_bindless_image_size
:
320 case nir_intrinsic_bindless_image_samples
:
321 info
->uses_bindless_images
= true;
323 case nir_intrinsic_bindless_image_store
:
324 info
->uses_bindless_images
= true;
325 info
->writes_memory
= true;
326 info
->num_memory_instructions
++; /* we only care about stores */
328 case nir_intrinsic_image_deref_store
:
329 info
->writes_memory
= true;
330 info
->num_memory_instructions
++; /* we only care about stores */
332 case nir_intrinsic_bindless_image_atomic_add
:
333 case nir_intrinsic_bindless_image_atomic_imin
:
334 case nir_intrinsic_bindless_image_atomic_umin
:
335 case nir_intrinsic_bindless_image_atomic_imax
:
336 case nir_intrinsic_bindless_image_atomic_umax
:
337 case nir_intrinsic_bindless_image_atomic_and
:
338 case nir_intrinsic_bindless_image_atomic_or
:
339 case nir_intrinsic_bindless_image_atomic_xor
:
340 case nir_intrinsic_bindless_image_atomic_exchange
:
341 case nir_intrinsic_bindless_image_atomic_comp_swap
:
342 info
->uses_bindless_images
= true;
343 info
->writes_memory
= true;
344 info
->num_memory_instructions
++; /* we only care about stores */
346 case nir_intrinsic_image_deref_atomic_add
:
347 case nir_intrinsic_image_deref_atomic_imin
:
348 case nir_intrinsic_image_deref_atomic_umin
:
349 case nir_intrinsic_image_deref_atomic_imax
:
350 case nir_intrinsic_image_deref_atomic_umax
:
351 case nir_intrinsic_image_deref_atomic_and
:
352 case nir_intrinsic_image_deref_atomic_or
:
353 case nir_intrinsic_image_deref_atomic_xor
:
354 case nir_intrinsic_image_deref_atomic_exchange
:
355 case nir_intrinsic_image_deref_atomic_comp_swap
:
356 case nir_intrinsic_image_deref_atomic_inc_wrap
:
357 case nir_intrinsic_image_deref_atomic_dec_wrap
:
358 info
->writes_memory
= true;
359 info
->num_memory_instructions
++; /* we only care about stores */
361 case nir_intrinsic_store_ssbo
:
362 case nir_intrinsic_ssbo_atomic_add
:
363 case nir_intrinsic_ssbo_atomic_imin
:
364 case nir_intrinsic_ssbo_atomic_umin
:
365 case nir_intrinsic_ssbo_atomic_imax
:
366 case nir_intrinsic_ssbo_atomic_umax
:
367 case nir_intrinsic_ssbo_atomic_and
:
368 case nir_intrinsic_ssbo_atomic_or
:
369 case nir_intrinsic_ssbo_atomic_xor
:
370 case nir_intrinsic_ssbo_atomic_exchange
:
371 case nir_intrinsic_ssbo_atomic_comp_swap
:
372 info
->writes_memory
= true;
373 info
->num_memory_instructions
++; /* we only care about stores */
375 case nir_intrinsic_load_color0
:
376 case nir_intrinsic_load_color1
: {
377 unsigned index
= intr
->intrinsic
== nir_intrinsic_load_color1
;
378 uint8_t mask
= nir_ssa_def_components_read(&intr
->dest
.ssa
);
379 info
->colors_read
|= mask
<< (index
* 4);
382 case nir_intrinsic_load_barycentric_pixel
:
383 case nir_intrinsic_load_barycentric_centroid
:
384 case nir_intrinsic_load_barycentric_sample
:
385 case nir_intrinsic_load_barycentric_at_offset
: /* uses center */
386 case nir_intrinsic_load_barycentric_at_sample
: { /* uses center */
387 unsigned mode
= nir_intrinsic_interp_mode(intr
);
389 if (mode
== INTERP_MODE_FLAT
)
392 if (mode
== INTERP_MODE_NOPERSPECTIVE
) {
393 if (intr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
394 info
->uses_linear_sample
= true;
395 else if (intr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
396 info
->uses_linear_centroid
= true;
398 info
->uses_linear_center
= true;
400 if (intr
->intrinsic
== nir_intrinsic_load_barycentric_at_sample
)
401 info
->uses_linear_opcode_interp_sample
= true;
403 if (intr
->intrinsic
== nir_intrinsic_load_barycentric_sample
)
404 info
->uses_persp_sample
= true;
405 else if (intr
->intrinsic
== nir_intrinsic_load_barycentric_centroid
)
406 info
->uses_persp_centroid
= true;
408 info
->uses_persp_center
= true;
410 if (intr
->intrinsic
== nir_intrinsic_load_barycentric_at_sample
)
411 info
->uses_persp_opcode_interp_sample
= true;
415 case nir_intrinsic_load_input
:
416 case nir_intrinsic_load_per_vertex_input
:
417 case nir_intrinsic_load_input_vertex
:
418 case nir_intrinsic_load_interpolated_input
:
419 scan_io_usage(info
, intr
, true);
421 case nir_intrinsic_store_output
:
422 case nir_intrinsic_store_per_vertex_output
:
423 scan_io_usage(info
, intr
, false);
425 case nir_intrinsic_load_output
: {
426 unsigned location
= nir_intrinsic_io_semantics(intr
).location
;
428 if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
429 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
430 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
431 info
->reads_tessfactor_outputs
= true;
433 info
->reads_perpatch_outputs
= true;
434 } else if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
435 if (nir_intrinsic_io_semantics(intr
).fb_fetch_output
)
436 info
->uses_fbfetch
= true;
440 case nir_intrinsic_load_per_vertex_output
:
441 info
->reads_pervertex_outputs
= true;
443 case nir_intrinsic_load_deref
:
444 case nir_intrinsic_store_deref
:
445 case nir_intrinsic_interp_deref_at_centroid
:
446 case nir_intrinsic_interp_deref_at_sample
:
447 case nir_intrinsic_interp_deref_at_offset
:
448 unreachable("these opcodes should have been lowered");
456 void si_nir_scan_shader(const struct nir_shader
*nir
, struct si_shader_info
*info
)
460 info
->processor
= pipe_shader_type_from_mesa(nir
->info
.stage
);
462 info
->properties
[TGSI_PROPERTY_NEXT_SHADER
] = pipe_shader_type_from_mesa(nir
->info
.next_stage
);
464 if (nir
->info
.stage
== MESA_SHADER_VERTEX
) {
465 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] = nir
->info
.vs
.window_space_position
;
466 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
] = nir
->info
.vs
.blit_sgprs_amd
;
469 if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
470 info
->properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] = nir
->info
.tess
.tcs_vertices_out
;
473 if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
474 if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
)
475 info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
] = PIPE_PRIM_LINES
;
477 info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
] = nir
->info
.tess
.primitive_mode
;
479 STATIC_ASSERT((TESS_SPACING_EQUAL
+ 1) % 3 == PIPE_TESS_SPACING_EQUAL
);
480 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD
+ 1) % 3 == PIPE_TESS_SPACING_FRACTIONAL_ODD
);
481 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN
+ 1) % 3 == PIPE_TESS_SPACING_FRACTIONAL_EVEN
);
483 info
->properties
[TGSI_PROPERTY_TES_SPACING
] = (nir
->info
.tess
.spacing
+ 1) % 3;
484 info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
] = !nir
->info
.tess
.ccw
;
485 info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
] = nir
->info
.tess
.point_mode
;
488 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
489 info
->properties
[TGSI_PROPERTY_GS_INPUT_PRIM
] = nir
->info
.gs
.input_primitive
;
490 info
->properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
] = nir
->info
.gs
.output_primitive
;
491 info
->properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
] = nir
->info
.gs
.vertices_out
;
492 info
->properties
[TGSI_PROPERTY_GS_INVOCATIONS
] = nir
->info
.gs
.invocations
;
495 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
496 info
->properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] =
497 nir
->info
.fs
.early_fragment_tests
| nir
->info
.fs
.post_depth_coverage
;
498 info
->properties
[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
] = nir
->info
.fs
.post_depth_coverage
;
500 if (nir
->info
.fs
.pixel_center_integer
) {
501 info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] = TGSI_FS_COORD_PIXEL_CENTER_INTEGER
;
504 if (nir
->info
.fs
.depth_layout
!= FRAG_DEPTH_LAYOUT_NONE
) {
505 switch (nir
->info
.fs
.depth_layout
) {
506 case FRAG_DEPTH_LAYOUT_ANY
:
507 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_ANY
;
509 case FRAG_DEPTH_LAYOUT_GREATER
:
510 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_GREATER
;
512 case FRAG_DEPTH_LAYOUT_LESS
:
513 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_LESS
;
515 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
516 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED
;
519 unreachable("Unknow depth layout");
523 info
->color_interpolate
[0] = tgsi_get_interp_mode(nir
->info
.fs
.color0_interp
, true);
524 info
->color_interpolate
[1] = tgsi_get_interp_mode(nir
->info
.fs
.color1_interp
, true);
525 info
->color_interpolate_loc
[0] = nir
->info
.fs
.color0_sample
? TGSI_INTERPOLATE_LOC_SAMPLE
:
526 nir
->info
.fs
.color0_centroid
? TGSI_INTERPOLATE_LOC_CENTROID
:
527 TGSI_INTERPOLATE_LOC_CENTER
;
528 info
->color_interpolate_loc
[1] = nir
->info
.fs
.color1_sample
? TGSI_INTERPOLATE_LOC_SAMPLE
:
529 nir
->info
.fs
.color1_centroid
? TGSI_INTERPOLATE_LOC_CENTROID
:
530 TGSI_INTERPOLATE_LOC_CENTER
;
533 if (gl_shader_stage_is_compute(nir
->info
.stage
)) {
534 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] = nir
->info
.cs
.local_size
[0];
535 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
] = nir
->info
.cs
.local_size
[1];
536 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
] = nir
->info
.cs
.local_size
[2];
537 info
->properties
[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD
] =
538 nir
->info
.cs
.user_data_components_amd
;
541 info
->constbuf0_num_slots
= nir
->num_uniforms
;
542 info
->shader_buffers_declared
= u_bit_consecutive(0, nir
->info
.num_ssbos
);
543 info
->const_buffers_declared
= u_bit_consecutive(0, nir
->info
.num_ubos
);
544 info
->images_declared
= u_bit_consecutive(0, nir
->info
.num_images
);
545 info
->msaa_images_declared
= nir
->info
.msaa_images
;
546 info
->image_buffers
= nir
->info
.image_buffers
;
547 info
->samplers_declared
= nir
->info
.textures_used
;
549 info
->num_written_clipdistance
= nir
->info
.clip_distance_array_size
;
550 info
->num_written_culldistance
= nir
->info
.cull_distance_array_size
;
551 info
->clipdist_writemask
= u_bit_consecutive(0, info
->num_written_clipdistance
);
552 info
->culldist_writemask
= u_bit_consecutive(0, info
->num_written_culldistance
);
554 if (info
->processor
== PIPE_SHADER_FRAGMENT
)
555 info
->uses_kill
= nir
->info
.fs
.uses_discard
;
557 if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
558 info
->tessfactors_are_def_in_all_invocs
= ac_are_tessfactors_def_in_all_invocs(nir
);
561 func
= (struct nir_function
*)exec_list_get_head_const(&nir
->functions
);
562 nir_foreach_block (block
, func
->impl
) {
563 nir_foreach_instr (instr
, block
)
564 scan_instruction(nir
, info
, instr
);
567 /* Add color inputs to the list of inputs. */
568 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
569 for (unsigned i
= 0; i
< 2; i
++) {
570 if ((info
->colors_read
>> (i
* 4)) & 0xf) {
571 info
->input_semantic_name
[info
->num_inputs
] = TGSI_SEMANTIC_COLOR
;
572 info
->input_semantic_index
[info
->num_inputs
] = i
;
573 info
->input_interpolate
[info
->num_inputs
] = info
->color_interpolate
[i
];
574 info
->input_usage_mask
[info
->num_inputs
] = info
->colors_read
>> (i
* 4);
581 static void si_nir_opts(struct nir_shader
*nir
, bool first
)
585 NIR_PASS_V(nir
, nir_lower_vars_to_ssa
);
586 NIR_PASS_V(nir
, nir_lower_alu_to_scalar
, NULL
, NULL
);
587 NIR_PASS_V(nir
, nir_lower_phis_to_scalar
);
591 bool lower_alu_to_scalar
= false;
592 bool lower_phis_to_scalar
= false;
595 bool opt_find_array_copies
= false;
597 NIR_PASS(progress
, nir
, nir_split_array_vars
, nir_var_function_temp
);
598 NIR_PASS(lower_alu_to_scalar
, nir
, nir_shrink_vec_array_vars
, nir_var_function_temp
);
599 NIR_PASS(opt_find_array_copies
, nir
, nir_opt_find_array_copies
);
600 NIR_PASS(progress
, nir
, nir_opt_copy_prop_vars
);
602 /* Call nir_lower_var_copies() to remove any copies introduced
603 * by nir_opt_find_array_copies().
605 if (opt_find_array_copies
)
606 NIR_PASS(progress
, nir
, nir_lower_var_copies
);
607 progress
|= opt_find_array_copies
;
609 NIR_PASS(progress
, nir
, nir_opt_copy_prop_vars
);
612 NIR_PASS(progress
, nir
, nir_opt_dead_write_vars
);
614 NIR_PASS(lower_alu_to_scalar
, nir
, nir_opt_trivial_continues
);
615 /* (Constant) copy propagation is needed for txf with offsets. */
616 NIR_PASS(progress
, nir
, nir_copy_prop
);
617 NIR_PASS(progress
, nir
, nir_opt_remove_phis
);
618 NIR_PASS(progress
, nir
, nir_opt_dce
);
619 NIR_PASS(lower_phis_to_scalar
, nir
, nir_opt_if
, true);
620 NIR_PASS(progress
, nir
, nir_opt_dead_cf
);
622 if (lower_alu_to_scalar
)
623 NIR_PASS_V(nir
, nir_lower_alu_to_scalar
, NULL
, NULL
);
624 if (lower_phis_to_scalar
)
625 NIR_PASS_V(nir
, nir_lower_phis_to_scalar
);
626 progress
|= lower_alu_to_scalar
| lower_phis_to_scalar
;
628 NIR_PASS(progress
, nir
, nir_opt_cse
);
629 NIR_PASS(progress
, nir
, nir_opt_peephole_select
, 8, true, true);
631 /* Needed for algebraic lowering */
632 NIR_PASS(progress
, nir
, nir_opt_algebraic
);
633 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
635 if (!nir
->info
.flrp_lowered
) {
636 unsigned lower_flrp
= (nir
->options
->lower_flrp16
? 16 : 0) |
637 (nir
->options
->lower_flrp32
? 32 : 0) |
638 (nir
->options
->lower_flrp64
? 64 : 0);
640 bool lower_flrp_progress
= false;
642 NIR_PASS(lower_flrp_progress
, nir
, nir_lower_flrp
, lower_flrp
, false /* always_precise */,
643 nir
->options
->lower_ffma
);
644 if (lower_flrp_progress
) {
645 NIR_PASS(progress
, nir
, nir_opt_constant_folding
);
649 /* Nothing should rematerialize any flrps, so we only
650 * need to do this lowering once.
652 nir
->info
.flrp_lowered
= true;
655 NIR_PASS(progress
, nir
, nir_opt_undef
);
656 NIR_PASS(progress
, nir
, nir_opt_conditional_discard
);
657 if (nir
->options
->max_unroll_iterations
) {
658 NIR_PASS(progress
, nir
, nir_opt_loop_unroll
, 0);
663 static int type_size_vec4(const struct glsl_type
*type
, bool bindless
)
665 return glsl_count_attribute_slots(type
, false);
668 static void si_nir_lower_color(nir_shader
*nir
)
670 nir_function_impl
*entrypoint
= nir_shader_get_entrypoint(nir
);
673 nir_builder_init(&b
, entrypoint
);
675 nir_foreach_block (block
, entrypoint
) {
676 nir_foreach_instr_safe (instr
, block
) {
677 if (instr
->type
!= nir_instr_type_intrinsic
)
680 nir_intrinsic_instr
*intrin
= nir_instr_as_intrinsic(instr
);
682 if (intrin
->intrinsic
!= nir_intrinsic_load_deref
)
685 nir_deref_instr
*deref
= nir_src_as_deref(intrin
->src
[0]);
686 if (deref
->mode
!= nir_var_shader_in
)
689 b
.cursor
= nir_before_instr(instr
);
690 nir_variable
*var
= nir_deref_instr_get_variable(deref
);
693 if (var
->data
.location
== VARYING_SLOT_COL0
) {
694 def
= nir_load_color0(&b
);
695 nir
->info
.fs
.color0_interp
= var
->data
.interpolation
;
696 nir
->info
.fs
.color0_sample
= var
->data
.sample
;
697 nir
->info
.fs
.color0_centroid
= var
->data
.centroid
;
698 } else if (var
->data
.location
== VARYING_SLOT_COL1
) {
699 def
= nir_load_color1(&b
);
700 nir
->info
.fs
.color1_interp
= var
->data
.interpolation
;
701 nir
->info
.fs
.color1_sample
= var
->data
.sample
;
702 nir
->info
.fs
.color1_centroid
= var
->data
.centroid
;
707 nir_ssa_def_rewrite_uses(&intrin
->dest
.ssa
, nir_src_for_ssa(def
));
708 nir_instr_remove(instr
);
713 static void si_lower_io(struct nir_shader
*nir
)
715 /* HW supports indirect indexing for: | Enabled in driver
716 * -------------------------------------------------------
721 * -------------------------------------------------------
722 * VS outputs before TCS | No
723 * VS outputs before GS | No
725 * TES outputs before GS | No
727 bool has_indirect_inputs
= nir
->info
.stage
== MESA_SHADER_TESS_CTRL
||
728 nir
->info
.stage
== MESA_SHADER_TESS_EVAL
;
729 bool has_indirect_outputs
= nir
->info
.stage
== MESA_SHADER_TESS_CTRL
;
731 if (!has_indirect_inputs
|| !has_indirect_outputs
) {
732 NIR_PASS_V(nir
, nir_lower_io_to_temporaries
, nir_shader_get_entrypoint(nir
),
733 !has_indirect_outputs
, !has_indirect_inputs
);
735 /* Since we're doing nir_lower_io_to_temporaries late, we need
736 * to lower all the copy_deref's introduced by
737 * lower_io_to_temporaries before calling nir_lower_io.
739 NIR_PASS_V(nir
, nir_split_var_copies
);
740 NIR_PASS_V(nir
, nir_lower_var_copies
);
741 NIR_PASS_V(nir
, nir_lower_global_vars_to_local
);
744 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
)
745 si_nir_lower_color(nir
);
747 NIR_PASS_V(nir
, nir_lower_io
, nir_var_shader_out
| nir_var_shader_in
,
749 nir
->info
.io_lowered
= true;
751 /* This pass needs actual constants */
752 NIR_PASS_V(nir
, nir_opt_constant_folding
);
753 NIR_PASS_V(nir
, nir_io_add_const_offset_to_base
, nir_var_shader_in
);
754 NIR_PASS_V(nir
, nir_io_add_const_offset_to_base
, nir_var_shader_out
);
758 * Perform "lowering" operations on the NIR that are run once when the shader
759 * selector is created.
761 static void si_lower_nir(struct si_screen
*sscreen
, struct nir_shader
*nir
)
763 /* Perform lowerings (and optimizations) of code.
765 * Performance considerations aside, we must:
766 * - lower certain ALU operations
767 * - ensure constant offsets for texture instructions are folded
768 * and copy-propagated
771 static const struct nir_lower_tex_options lower_tex_options
= {
774 NIR_PASS_V(nir
, nir_lower_tex
, &lower_tex_options
);
776 const nir_lower_subgroups_options subgroups_options
= {
778 .ballot_bit_size
= 64,
779 .lower_to_scalar
= true,
780 .lower_subgroup_masks
= true,
781 .lower_vote_trivial
= false,
782 .lower_vote_eq_to_ballot
= true,
784 NIR_PASS_V(nir
, nir_lower_subgroups
, &subgroups_options
);
786 /* Lower load constants to scalar and then clean up the mess */
787 NIR_PASS_V(nir
, nir_lower_load_const_to_scalar
);
788 NIR_PASS_V(nir
, nir_lower_var_copies
);
789 NIR_PASS_V(nir
, nir_lower_pack
);
790 NIR_PASS_V(nir
, nir_opt_access
);
791 si_nir_opts(nir
, true);
793 /* Lower large variables that are always constant with load_constant
794 * intrinsics, which get turned into PC-relative loads from a data
795 * section next to the shader.
797 * st/mesa calls finalize_nir twice, but we can't call this pass twice.
799 bool changed
= false;
800 if (!nir
->constant_data
) {
801 /* The pass crashes if there are dead temps of lowered IO interface types. */
802 NIR_PASS_V(nir
, nir_remove_dead_variables
, nir_var_function_temp
, NULL
);
803 NIR_PASS(changed
, nir
, nir_opt_large_constants
, glsl_get_natural_size_align_bytes
, 16);
806 changed
|= ac_lower_indirect_derefs(nir
, sscreen
->info
.chip_class
);
808 si_nir_opts(nir
, false);
810 NIR_PASS_V(nir
, nir_lower_bool_to_int32
);
811 NIR_PASS_V(nir
, nir_remove_dead_variables
, nir_var_function_temp
, NULL
);
813 if (sscreen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
))
814 NIR_PASS_V(nir
, nir_lower_discard_to_demote
);
817 void si_finalize_nir(struct pipe_screen
*screen
, void *nirptr
, bool optimize
)
819 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
820 struct nir_shader
*nir
= (struct nir_shader
*)nirptr
;
822 nir_shader_gather_info(nir
, nir_shader_get_entrypoint(nir
));
824 si_lower_nir(sscreen
, nir
);