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9c0379a997be7ffd6be70f5d979481510bfda113
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 #include "tgsi/tgsi_from_mesa.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34 #include "compiler/nir/nir_builder.h"
35
36 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
37 {
38 for (unsigned i = 0; i < instr->num_srcs; i++) {
39 switch (instr->src[i].src_type) {
40 case nir_tex_src_texture_deref:
41 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
42 default:
43 break;
44 }
45 }
46
47 return NULL;
48 }
49
50 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
51 {
52 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
53 }
54
55 static void gather_intrinsic_load_deref_input_info(const nir_shader *nir,
56 const nir_intrinsic_instr *instr,
57 nir_variable *var,
58 struct tgsi_shader_info *info)
59 {
60 assert(var && var->data.mode == nir_var_shader_in);
61
62 switch (nir->info.stage) {
63 case MESA_SHADER_VERTEX: {
64 unsigned i = var->data.driver_location;
65 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
66 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
67
68 for (unsigned j = 0; j < attrib_count; j++, i++) {
69 if (glsl_type_is_64bit(glsl_without_array(var->type))) {
70 unsigned dmask = mask;
71
72 if (glsl_type_is_dual_slot(glsl_without_array(var->type)) && j % 2)
73 dmask >>= 2;
74
75 dmask <<= var->data.location_frac / 2;
76
77 if (dmask & 0x1)
78 info->input_usage_mask[i] |= TGSI_WRITEMASK_XY;
79 if (dmask & 0x2)
80 info->input_usage_mask[i] |= TGSI_WRITEMASK_ZW;
81 } else {
82 info->input_usage_mask[i] |=
83 (mask << var->data.location_frac) & 0xf;
84 }
85 }
86 break;
87 }
88 default:;
89 }
90 }
91
92 static void gather_intrinsic_load_deref_output_info(const nir_shader *nir,
93 const nir_intrinsic_instr *instr,
94 nir_variable *var,
95 struct tgsi_shader_info *info)
96 {
97 assert(var && var->data.mode == nir_var_shader_out);
98
99 switch (nir->info.stage) {
100 case MESA_SHADER_TESS_CTRL:
101 if (var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
102 var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
103 info->reads_tessfactor_outputs = true;
104 else if (var->data.patch)
105 info->reads_perpatch_outputs = true;
106 else
107 info->reads_pervertex_outputs = true;
108 break;
109
110 case MESA_SHADER_FRAGMENT:
111 if (var->data.fb_fetch_output)
112 info->uses_fbfetch = true;
113 break;
114 default:;
115 }
116 }
117
118 static void gather_intrinsic_store_deref_output_info(const nir_shader *nir,
119 const nir_intrinsic_instr *instr,
120 nir_variable *var,
121 struct tgsi_shader_info *info)
122 {
123 assert(var && var->data.mode == nir_var_shader_out);
124
125 switch (nir->info.stage) {
126 case MESA_SHADER_VERTEX: /* needed by LS, ES */
127 case MESA_SHADER_TESS_EVAL: /* needed by ES */
128 case MESA_SHADER_GEOMETRY: {
129 unsigned i = var->data.driver_location;
130 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
131 unsigned mask = nir_intrinsic_write_mask(instr);
132
133 assert(!var->data.compact);
134
135 for (unsigned j = 0; j < attrib_count; j++, i++) {
136 if (glsl_type_is_64bit(glsl_without_array(var->type))) {
137 unsigned dmask = mask;
138
139 if (glsl_type_is_dual_slot(glsl_without_array(var->type)) && j % 2)
140 dmask >>= 2;
141
142 dmask <<= var->data.location_frac / 2;
143
144 if (dmask & 0x1)
145 info->output_usagemask[i] |= TGSI_WRITEMASK_XY;
146 if (dmask & 0x2)
147 info->output_usagemask[i] |= TGSI_WRITEMASK_ZW;
148 } else {
149 info->output_usagemask[i] |=
150 (mask << var->data.location_frac) & 0xf;
151 }
152
153 }
154 break;
155 }
156 default:;
157 }
158 }
159
160 static void scan_instruction(const struct nir_shader *nir,
161 struct tgsi_shader_info *info,
162 nir_instr *instr)
163 {
164 if (instr->type == nir_instr_type_alu) {
165 nir_alu_instr *alu = nir_instr_as_alu(instr);
166
167 switch (alu->op) {
168 case nir_op_fddx:
169 case nir_op_fddy:
170 case nir_op_fddx_fine:
171 case nir_op_fddy_fine:
172 case nir_op_fddx_coarse:
173 case nir_op_fddy_coarse:
174 info->uses_derivatives = true;
175 break;
176 default:
177 break;
178 }
179 } else if (instr->type == nir_instr_type_tex) {
180 nir_tex_instr *tex = nir_instr_as_tex(instr);
181 nir_variable *texture = tex_get_texture_var(tex);
182
183 if (!texture) {
184 info->samplers_declared |=
185 u_bit_consecutive(tex->sampler_index, 1);
186 } else {
187 if (texture->data.bindless)
188 info->uses_bindless_samplers = true;
189 }
190
191 switch (tex->op) {
192 case nir_texop_tex:
193 case nir_texop_txb:
194 case nir_texop_lod:
195 info->uses_derivatives = true;
196 break;
197 default:
198 break;
199 }
200 } else if (instr->type == nir_instr_type_intrinsic) {
201 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
202
203 switch (intr->intrinsic) {
204 case nir_intrinsic_load_front_face:
205 info->uses_frontface = 1;
206 break;
207 case nir_intrinsic_load_instance_id:
208 info->uses_instanceid = 1;
209 break;
210 case nir_intrinsic_load_invocation_id:
211 info->uses_invocationid = true;
212 break;
213 case nir_intrinsic_load_num_work_groups:
214 info->uses_grid_size = true;
215 break;
216 case nir_intrinsic_load_local_group_size:
217 /* The block size is translated to IMM with a fixed block size. */
218 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
219 info->uses_block_size = true;
220 break;
221 case nir_intrinsic_load_local_invocation_id:
222 case nir_intrinsic_load_work_group_id: {
223 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
224 while (mask) {
225 unsigned i = u_bit_scan(&mask);
226
227 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
228 info->uses_block_id[i] = true;
229 else
230 info->uses_thread_id[i] = true;
231 }
232 break;
233 }
234 case nir_intrinsic_load_vertex_id:
235 info->uses_vertexid = 1;
236 break;
237 case nir_intrinsic_load_vertex_id_zero_base:
238 info->uses_vertexid_nobase = 1;
239 break;
240 case nir_intrinsic_load_base_vertex:
241 info->uses_basevertex = 1;
242 break;
243 case nir_intrinsic_load_draw_id:
244 info->uses_drawid = 1;
245 break;
246 case nir_intrinsic_load_primitive_id:
247 info->uses_primid = 1;
248 break;
249 case nir_intrinsic_load_sample_mask_in:
250 info->reads_samplemask = true;
251 break;
252 case nir_intrinsic_load_tess_level_inner:
253 case nir_intrinsic_load_tess_level_outer:
254 info->reads_tess_factors = true;
255 break;
256 case nir_intrinsic_bindless_image_load:
257 info->uses_bindless_images = true;
258
259 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
260 info->uses_bindless_buffer_load = true;
261 else
262 info->uses_bindless_image_load = true;
263 break;
264 case nir_intrinsic_bindless_image_size:
265 case nir_intrinsic_bindless_image_samples:
266 info->uses_bindless_images = true;
267 break;
268 case nir_intrinsic_bindless_image_store:
269 info->uses_bindless_images = true;
270
271 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
272 info->uses_bindless_buffer_store = true;
273 else
274 info->uses_bindless_image_store = true;
275
276 info->writes_memory = true;
277 info->num_memory_instructions++; /* we only care about stores */
278 break;
279 case nir_intrinsic_image_deref_store:
280 info->writes_memory = true;
281 info->num_memory_instructions++; /* we only care about stores */
282 break;
283 case nir_intrinsic_bindless_image_atomic_add:
284 case nir_intrinsic_bindless_image_atomic_min:
285 case nir_intrinsic_bindless_image_atomic_max:
286 case nir_intrinsic_bindless_image_atomic_and:
287 case nir_intrinsic_bindless_image_atomic_or:
288 case nir_intrinsic_bindless_image_atomic_xor:
289 case nir_intrinsic_bindless_image_atomic_exchange:
290 case nir_intrinsic_bindless_image_atomic_comp_swap:
291 info->uses_bindless_images = true;
292
293 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
294 info->uses_bindless_buffer_atomic = true;
295 else
296 info->uses_bindless_image_atomic = true;
297
298 info->writes_memory = true;
299 info->num_memory_instructions++; /* we only care about stores */
300 break;
301 case nir_intrinsic_image_deref_atomic_add:
302 case nir_intrinsic_image_deref_atomic_min:
303 case nir_intrinsic_image_deref_atomic_max:
304 case nir_intrinsic_image_deref_atomic_and:
305 case nir_intrinsic_image_deref_atomic_or:
306 case nir_intrinsic_image_deref_atomic_xor:
307 case nir_intrinsic_image_deref_atomic_exchange:
308 case nir_intrinsic_image_deref_atomic_comp_swap:
309 case nir_intrinsic_image_deref_atomic_inc_wrap:
310 case nir_intrinsic_image_deref_atomic_dec_wrap:
311 info->writes_memory = true;
312 info->num_memory_instructions++; /* we only care about stores */
313 break;
314 case nir_intrinsic_store_ssbo:
315 case nir_intrinsic_ssbo_atomic_add:
316 case nir_intrinsic_ssbo_atomic_imin:
317 case nir_intrinsic_ssbo_atomic_umin:
318 case nir_intrinsic_ssbo_atomic_imax:
319 case nir_intrinsic_ssbo_atomic_umax:
320 case nir_intrinsic_ssbo_atomic_and:
321 case nir_intrinsic_ssbo_atomic_or:
322 case nir_intrinsic_ssbo_atomic_xor:
323 case nir_intrinsic_ssbo_atomic_exchange:
324 case nir_intrinsic_ssbo_atomic_comp_swap:
325 info->writes_memory = true;
326 info->num_memory_instructions++; /* we only care about stores */
327 break;
328 case nir_intrinsic_load_color0:
329 case nir_intrinsic_load_color1: {
330 unsigned index = intr->intrinsic == nir_intrinsic_load_color1;
331 uint8_t mask = nir_ssa_def_components_read(&intr->dest.ssa);
332 info->colors_read |= mask << (index * 4);
333 break;
334 }
335 case nir_intrinsic_load_barycentric_pixel:
336 case nir_intrinsic_load_barycentric_centroid:
337 case nir_intrinsic_load_barycentric_sample:
338 case nir_intrinsic_load_barycentric_at_offset: /* uses center */
339 case nir_intrinsic_load_barycentric_at_sample: { /* uses center */
340 unsigned mode = nir_intrinsic_interp_mode(intr);
341
342 if (mode == INTERP_MODE_FLAT)
343 break;
344
345 if (mode == INTERP_MODE_NOPERSPECTIVE) {
346 if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
347 info->uses_linear_sample = true;
348 else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
349 info->uses_linear_centroid = true;
350 else
351 info->uses_linear_center = true;
352
353 if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
354 info->uses_linear_opcode_interp_sample = true;
355 } else {
356 if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
357 info->uses_persp_sample = true;
358 else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
359 info->uses_persp_centroid = true;
360 else
361 info->uses_persp_center = true;
362
363 if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
364 info->uses_persp_opcode_interp_sample = true;
365 }
366 break;
367 }
368 case nir_intrinsic_load_deref: {
369 nir_variable *var = intrinsic_get_var(intr);
370 nir_variable_mode mode = var->data.mode;
371
372 if (mode == nir_var_shader_in) {
373 /* PS inputs use the interpolated load intrinsics. */
374 assert(nir->info.stage != MESA_SHADER_FRAGMENT);
375 gather_intrinsic_load_deref_input_info(nir, intr, var, info);
376 } else if (mode == nir_var_shader_out) {
377 gather_intrinsic_load_deref_output_info(nir, intr, var, info);
378 }
379 break;
380 }
381 case nir_intrinsic_store_deref: {
382 nir_variable *var = intrinsic_get_var(intr);
383
384 if (var->data.mode == nir_var_shader_out)
385 gather_intrinsic_store_deref_output_info(nir, intr, var, info);
386 break;
387 }
388 case nir_intrinsic_interp_deref_at_centroid:
389 case nir_intrinsic_interp_deref_at_sample:
390 case nir_intrinsic_interp_deref_at_offset:
391 unreachable("interp opcodes should have been lowered");
392 break;
393 default:
394 break;
395 }
396 }
397 }
398
399 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
400 struct tgsi_tessctrl_info *out)
401 {
402 memset(out, 0, sizeof(*out));
403
404 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
405 return;
406
407 out->tessfactors_are_def_in_all_invocs =
408 ac_are_tessfactors_def_in_all_invocs(nir);
409 }
410
411 void si_nir_scan_shader(const struct nir_shader *nir,
412 struct tgsi_shader_info *info)
413 {
414 nir_function *func;
415 unsigned i;
416
417 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
418 info->num_tokens = 2; /* indicate that the shader is non-empty */
419 info->num_instructions = 2;
420
421 info->properties[TGSI_PROPERTY_NEXT_SHADER] =
422 pipe_shader_type_from_mesa(nir->info.next_stage);
423
424 if (nir->info.stage == MESA_SHADER_VERTEX) {
425 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
426 nir->info.vs.window_space_position;
427 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] =
428 nir->info.vs.blit_sgprs_amd;
429 }
430
431 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
432 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
433 nir->info.tess.tcs_vertices_out;
434 }
435
436 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
437 if (nir->info.tess.primitive_mode == GL_ISOLINES)
438 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
439 else
440 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
441
442 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
443 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
444 PIPE_TESS_SPACING_FRACTIONAL_ODD);
445 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
446 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
447
448 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
449 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
450 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
451 }
452
453 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
454 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
455 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
456 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
457 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
458 }
459
460 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
461 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
462 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
463 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
464
465 if (nir->info.fs.pixel_center_integer) {
466 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
467 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
468 }
469
470 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
471 switch (nir->info.fs.depth_layout) {
472 case FRAG_DEPTH_LAYOUT_ANY:
473 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
474 break;
475 case FRAG_DEPTH_LAYOUT_GREATER:
476 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
477 break;
478 case FRAG_DEPTH_LAYOUT_LESS:
479 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
480 break;
481 case FRAG_DEPTH_LAYOUT_UNCHANGED:
482 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
483 break;
484 default:
485 unreachable("Unknow depth layout");
486 }
487 }
488 }
489
490 if (gl_shader_stage_is_compute(nir->info.stage)) {
491 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
492 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
493 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
494 info->properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD] = nir->info.cs.user_data_components_amd;
495 }
496
497 i = 0;
498 uint64_t processed_inputs = 0;
499 unsigned num_inputs = 0;
500 nir_foreach_variable(variable, &nir->inputs) {
501 unsigned semantic_name, semantic_index;
502
503 const struct glsl_type *type = variable->type;
504 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
505 assert(glsl_type_is_array(type));
506 type = glsl_get_array_element(type);
507 }
508
509 unsigned attrib_count = glsl_count_attribute_slots(type,
510 nir->info.stage == MESA_SHADER_VERTEX);
511
512 i = variable->data.driver_location;
513
514 /* Vertex shader inputs don't have semantics. The state
515 * tracker has already mapped them to attributes via
516 * variable->data.driver_location.
517 */
518 if (nir->info.stage == MESA_SHADER_VERTEX) {
519 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)))
520 num_inputs++;
521
522 num_inputs++;
523 continue;
524 }
525
526 for (unsigned j = 0; j < attrib_count; j++, i++) {
527
528 if (processed_inputs & ((uint64_t)1 << i))
529 continue;
530
531 processed_inputs |= ((uint64_t)1 << i);
532 num_inputs++;
533
534 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
535 &semantic_name, &semantic_index);
536
537 info->input_semantic_name[i] = semantic_name;
538 info->input_semantic_index[i] = semantic_index;
539
540 if (semantic_name == TGSI_SEMANTIC_PRIMID)
541 info->uses_primid = true;
542
543 if (semantic_name == TGSI_SEMANTIC_COLOR) {
544 /* We only need this for color inputs. */
545 if (variable->data.sample)
546 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
547 else if (variable->data.centroid)
548 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
549 else
550 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
551 }
552
553 enum glsl_base_type base_type =
554 glsl_get_base_type(glsl_without_array(variable->type));
555
556 switch (variable->data.interpolation) {
557 case INTERP_MODE_NONE:
558 if (glsl_base_type_is_integer(base_type)) {
559 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
560 break;
561 }
562
563 if (semantic_name == TGSI_SEMANTIC_COLOR) {
564 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
565 break;
566 }
567 /* fall-through */
568
569 case INTERP_MODE_SMOOTH:
570 assert(!glsl_base_type_is_integer(base_type));
571
572 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
573 break;
574
575 case INTERP_MODE_NOPERSPECTIVE:
576 assert(!glsl_base_type_is_integer(base_type));
577
578 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
579 break;
580
581 case INTERP_MODE_FLAT:
582 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
583 break;
584 }
585 }
586 }
587
588 info->num_inputs = num_inputs;
589
590 i = 0;
591 uint64_t processed_outputs = 0;
592 unsigned num_outputs = 0;
593 nir_foreach_variable(variable, &nir->outputs) {
594 unsigned semantic_name, semantic_index;
595
596 i = variable->data.driver_location;
597
598 const struct glsl_type *type = variable->type;
599 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
600 assert(glsl_type_is_array(type));
601 type = glsl_get_array_element(type);
602 }
603
604 unsigned attrib_count = glsl_count_attribute_slots(type, false);
605 for (unsigned k = 0; k < attrib_count; k++, i++) {
606
607 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
608 tgsi_get_gl_frag_result_semantic(variable->data.location + k,
609 &semantic_name, &semantic_index);
610
611 /* Adjust for dual source blending */
612 if (variable->data.index > 0) {
613 semantic_index++;
614 }
615 } else {
616 tgsi_get_gl_varying_semantic(variable->data.location + k, true,
617 &semantic_name, &semantic_index);
618 }
619
620 unsigned num_components = 4;
621 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
622 if (vector_elements)
623 num_components = vector_elements;
624
625 unsigned component = variable->data.location_frac;
626 if (glsl_type_is_64bit(glsl_without_array(variable->type))) {
627 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)) && k % 2) {
628 num_components = (num_components * 2) - 4;
629 component = 0;
630 } else {
631 num_components = MIN2(num_components * 2, 4);
632 }
633 }
634
635 ubyte usagemask = 0;
636 for (unsigned j = component; j < num_components + component; j++) {
637 switch (j) {
638 case 0:
639 usagemask |= TGSI_WRITEMASK_X;
640 break;
641 case 1:
642 usagemask |= TGSI_WRITEMASK_Y;
643 break;
644 case 2:
645 usagemask |= TGSI_WRITEMASK_Z;
646 break;
647 case 3:
648 usagemask |= TGSI_WRITEMASK_W;
649 break;
650 default:
651 unreachable("error calculating component index");
652 }
653 }
654
655 unsigned gs_out_streams;
656 if (variable->data.stream & (1u << 31)) {
657 gs_out_streams = variable->data.stream & ~(1u << 31);
658 } else {
659 assert(variable->data.stream < 4);
660 gs_out_streams = 0;
661 for (unsigned j = 0; j < num_components; ++j)
662 gs_out_streams |= variable->data.stream << (2 * (component + j));
663 }
664
665 unsigned streamx = gs_out_streams & 3;
666 unsigned streamy = (gs_out_streams >> 2) & 3;
667 unsigned streamz = (gs_out_streams >> 4) & 3;
668 unsigned streamw = (gs_out_streams >> 6) & 3;
669
670 if (usagemask & TGSI_WRITEMASK_X) {
671 info->output_streams[i] |= streamx;
672 info->num_stream_output_components[streamx]++;
673 }
674 if (usagemask & TGSI_WRITEMASK_Y) {
675 info->output_streams[i] |= streamy << 2;
676 info->num_stream_output_components[streamy]++;
677 }
678 if (usagemask & TGSI_WRITEMASK_Z) {
679 info->output_streams[i] |= streamz << 4;
680 info->num_stream_output_components[streamz]++;
681 }
682 if (usagemask & TGSI_WRITEMASK_W) {
683 info->output_streams[i] |= streamw << 6;
684 info->num_stream_output_components[streamw]++;
685 }
686
687 /* make sure we only count this location once against
688 * the num_outputs counter.
689 */
690 if (processed_outputs & ((uint64_t)1 << i))
691 continue;
692
693 processed_outputs |= ((uint64_t)1 << i);
694 num_outputs++;
695
696 info->output_semantic_name[i] = semantic_name;
697 info->output_semantic_index[i] = semantic_index;
698
699 switch (semantic_name) {
700 case TGSI_SEMANTIC_PRIMID:
701 info->writes_primid = true;
702 break;
703 case TGSI_SEMANTIC_VIEWPORT_INDEX:
704 info->writes_viewport_index = true;
705 break;
706 case TGSI_SEMANTIC_LAYER:
707 info->writes_layer = true;
708 break;
709 case TGSI_SEMANTIC_PSIZE:
710 info->writes_psize = true;
711 break;
712 case TGSI_SEMANTIC_CLIPVERTEX:
713 info->writes_clipvertex = true;
714 break;
715 case TGSI_SEMANTIC_COLOR:
716 info->colors_written |= 1 << semantic_index;
717 break;
718 case TGSI_SEMANTIC_STENCIL:
719 info->writes_stencil = true;
720 break;
721 case TGSI_SEMANTIC_SAMPLEMASK:
722 info->writes_samplemask = true;
723 break;
724 case TGSI_SEMANTIC_EDGEFLAG:
725 info->writes_edgeflag = true;
726 break;
727 case TGSI_SEMANTIC_POSITION:
728 if (info->processor == PIPE_SHADER_FRAGMENT)
729 info->writes_z = true;
730 else
731 info->writes_position = true;
732 break;
733 }
734 }
735
736 unsigned loc = variable->data.location;
737 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
738 loc == FRAG_RESULT_COLOR &&
739 nir->info.outputs_written & (1ull << loc)) {
740 assert(attrib_count == 1);
741 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
742 }
743 }
744
745 info->num_outputs = num_outputs;
746
747 struct set *ubo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
748 _mesa_key_pointer_equal);
749 struct set *ssbo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
750 _mesa_key_pointer_equal);
751
752 /* Intialise const_file_max[0] */
753 info->const_file_max[0] = -1;
754
755 /* The first 8 are reserved for atomic counters using ssbo */
756 unsigned ssbo_idx = 8;
757
758 unsigned ubo_idx = 1;
759 nir_foreach_variable(variable, &nir->uniforms) {
760 const struct glsl_type *type = variable->type;
761 enum glsl_base_type base_type =
762 glsl_get_base_type(glsl_without_array(type));
763 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
764 unsigned loc = variable->data.driver_location / 4;
765 int slot_count = glsl_count_attribute_slots(type, false);
766 int max_slot = MAX2(info->const_file_max[0], (int) loc) + slot_count;
767
768 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
769 * really use the mask (other than ubo_idx == 1 for regular
770 * uniforms) its really only used for getting the buffer count
771 * so we don't need to worry about the ordering.
772 */
773 if (variable->interface_type != NULL) {
774 if (variable->data.mode == nir_var_uniform ||
775 variable->data.mode == nir_var_mem_ubo ||
776 variable->data.mode == nir_var_mem_ssbo) {
777
778 struct set *buf_set = variable->data.mode == nir_var_mem_ssbo ?
779 ssbo_set : ubo_set;
780
781 unsigned block_count;
782 if (base_type != GLSL_TYPE_INTERFACE) {
783 struct set_entry *entry =
784 _mesa_set_search(buf_set, variable->interface_type);
785
786 /* Check if we have already processed
787 * a member from this ubo.
788 */
789 if (entry)
790 continue;
791
792 block_count = 1;
793 } else {
794 block_count = aoa_size;
795 }
796
797 if (variable->data.mode == nir_var_uniform ||
798 variable->data.mode == nir_var_mem_ubo) {
799 info->const_buffers_declared |= u_bit_consecutive(ubo_idx, block_count);
800 ubo_idx += block_count;
801 } else {
802 assert(variable->data.mode == nir_var_mem_ssbo);
803
804 info->shader_buffers_declared |= u_bit_consecutive(ssbo_idx, block_count);
805 ssbo_idx += block_count;
806 }
807
808 _mesa_set_add(buf_set, variable->interface_type);
809 }
810
811 continue;
812 }
813
814 /* We rely on the fact that nir_lower_samplers_as_deref has
815 * eliminated struct dereferences.
816 */
817 if (base_type == GLSL_TYPE_SAMPLER && !variable->data.bindless) {
818 info->samplers_declared |=
819 u_bit_consecutive(variable->data.binding, aoa_size);
820 } else if (base_type == GLSL_TYPE_IMAGE && !variable->data.bindless) {
821 info->images_declared |=
822 u_bit_consecutive(variable->data.binding, aoa_size);
823 } else if (base_type != GLSL_TYPE_ATOMIC_UINT) {
824 info->const_buffers_declared |= 1;
825 info->const_file_max[0] = max_slot;
826 }
827 }
828
829 _mesa_set_destroy(ubo_set, NULL);
830 _mesa_set_destroy(ssbo_set, NULL);
831
832 info->num_written_clipdistance = nir->info.clip_distance_array_size;
833 info->num_written_culldistance = nir->info.cull_distance_array_size;
834 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
835 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
836
837 if (info->processor == PIPE_SHADER_FRAGMENT)
838 info->uses_kill = nir->info.fs.uses_discard;
839
840 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
841 nir_foreach_block(block, func->impl) {
842 nir_foreach_instr(instr, block)
843 scan_instruction(nir, info, instr);
844 }
845 }
846
847 void
848 si_nir_opts(struct nir_shader *nir)
849 {
850 bool progress;
851 unsigned lower_flrp =
852 (nir->options->lower_flrp16 ? 16 : 0) |
853 (nir->options->lower_flrp32 ? 32 : 0) |
854 (nir->options->lower_flrp64 ? 64 : 0);
855
856 do {
857 progress = false;
858
859 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
860
861 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
862 NIR_PASS(progress, nir, nir_opt_dead_write_vars);
863
864 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL);
865 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
866
867 /* (Constant) copy propagation is needed for txf with offsets. */
868 NIR_PASS(progress, nir, nir_copy_prop);
869 NIR_PASS(progress, nir, nir_opt_remove_phis);
870 NIR_PASS(progress, nir, nir_opt_dce);
871 if (nir_opt_trivial_continues(nir)) {
872 progress = true;
873 NIR_PASS(progress, nir, nir_copy_prop);
874 NIR_PASS(progress, nir, nir_opt_dce);
875 }
876 NIR_PASS(progress, nir, nir_opt_if, true);
877 NIR_PASS(progress, nir, nir_opt_dead_cf);
878 NIR_PASS(progress, nir, nir_opt_cse);
879 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
880
881 /* Needed for algebraic lowering */
882 NIR_PASS(progress, nir, nir_opt_algebraic);
883 NIR_PASS(progress, nir, nir_opt_constant_folding);
884
885 if (lower_flrp != 0) {
886 bool lower_flrp_progress = false;
887
888 NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp,
889 lower_flrp,
890 false /* always_precise */,
891 nir->options->lower_ffma);
892 if (lower_flrp_progress) {
893 NIR_PASS(progress, nir,
894 nir_opt_constant_folding);
895 progress = true;
896 }
897
898 /* Nothing should rematerialize any flrps, so we only
899 * need to do this lowering once.
900 */
901 lower_flrp = 0;
902 }
903
904 NIR_PASS(progress, nir, nir_opt_undef);
905 NIR_PASS(progress, nir, nir_opt_conditional_discard);
906 if (nir->options->max_unroll_iterations) {
907 NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
908 }
909 } while (progress);
910 }
911
912 static int
913 type_size_vec4(const struct glsl_type *type, bool bindless)
914 {
915 return glsl_count_attribute_slots(type, false);
916 }
917
918 static void
919 si_nir_lower_color(nir_shader *nir)
920 {
921 nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
922
923 nir_builder b;
924 nir_builder_init(&b, entrypoint);
925
926 nir_foreach_block(block, entrypoint) {
927 nir_foreach_instr_safe(instr, block) {
928 if (instr->type != nir_instr_type_intrinsic)
929 continue;
930
931 nir_intrinsic_instr *intrin =
932 nir_instr_as_intrinsic(instr);
933
934 if (intrin->intrinsic != nir_intrinsic_load_deref)
935 continue;
936
937 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
938 if (deref->mode != nir_var_shader_in)
939 continue;
940
941 b.cursor = nir_before_instr(instr);
942 nir_variable *var = nir_deref_instr_get_variable(deref);
943 nir_ssa_def *def;
944
945 if (var->data.location == VARYING_SLOT_COL0) {
946 def = nir_load_color0(&b);
947 } else if (var->data.location == VARYING_SLOT_COL1) {
948 def = nir_load_color1(&b);
949 } else {
950 continue;
951 }
952
953 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(def));
954 nir_instr_remove(instr);
955 }
956 }
957 }
958
959 void si_nir_lower_ps_inputs(struct nir_shader *nir)
960 {
961 if (nir->info.stage != MESA_SHADER_FRAGMENT)
962 return;
963
964 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
965 nir_shader_get_entrypoint(nir), false, true);
966
967 /* Since we're doing nir_lower_io_to_temporaries late, we need
968 * to lower all the copy_deref's introduced by
969 * lower_io_to_temporaries before calling nir_lower_io.
970 */
971 NIR_PASS_V(nir, nir_split_var_copies);
972 NIR_PASS_V(nir, nir_lower_var_copies);
973 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
974
975 si_nir_lower_color(nir);
976 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
977
978 /* This pass needs actual constants */
979 NIR_PASS_V(nir, nir_opt_constant_folding);
980 NIR_PASS_V(nir, nir_io_add_const_offset_to_base,
981 nir_var_shader_in);
982 }
983
984 /**
985 * Perform "lowering" operations on the NIR that are run once when the shader
986 * selector is created.
987 */
988 void
989 si_lower_nir(struct si_shader_selector* sel, unsigned wave_size)
990 {
991 /* Adjust the driver location of inputs and outputs. The state tracker
992 * interprets them as slots, while the ac/nir backend interprets them
993 * as individual components.
994 */
995 if (sel->nir->info.stage != MESA_SHADER_FRAGMENT) {
996 nir_foreach_variable(variable, &sel->nir->inputs)
997 variable->data.driver_location *= 4;
998 }
999
1000 nir_foreach_variable(variable, &sel->nir->outputs) {
1001 variable->data.driver_location *= 4;
1002
1003 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
1004 if (variable->data.location == FRAG_RESULT_DEPTH)
1005 variable->data.driver_location += 2;
1006 else if (variable->data.location == FRAG_RESULT_STENCIL)
1007 variable->data.driver_location += 1;
1008 }
1009 }
1010
1011 /* Perform lowerings (and optimizations) of code.
1012 *
1013 * Performance considerations aside, we must:
1014 * - lower certain ALU operations
1015 * - ensure constant offsets for texture instructions are folded
1016 * and copy-propagated
1017 */
1018
1019 static const struct nir_lower_tex_options lower_tex_options = {
1020 .lower_txp = ~0u,
1021 };
1022 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
1023
1024 const nir_lower_subgroups_options subgroups_options = {
1025 .subgroup_size = wave_size,
1026 .ballot_bit_size = wave_size,
1027 .lower_to_scalar = true,
1028 .lower_subgroup_masks = true,
1029 .lower_vote_trivial = false,
1030 .lower_vote_eq_to_ballot = true,
1031 };
1032 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
1033
1034 ac_lower_indirect_derefs(sel->nir, sel->screen->info.chip_class);
1035
1036 si_nir_opts(sel->nir);
1037
1038 NIR_PASS_V(sel->nir, nir_lower_bool_to_int32);
1039
1040 /* Strip the resulting shader so that the shader cache is more likely
1041 * to hit from other similar shaders.
1042 */
1043 nir_strip(sel->nir);
1044 }
1045
1046 static void declare_nir_input_vs(struct si_shader_context *ctx,
1047 struct nir_variable *variable,
1048 unsigned input_index,
1049 LLVMValueRef out[4])
1050 {
1051 si_llvm_load_input_vs(ctx, input_index, out);
1052 }
1053
1054 LLVMValueRef
1055 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
1056 enum glsl_interp_mode interp, unsigned location)
1057 {
1058 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1059 int interp_param_idx = -1;
1060
1061 switch (interp) {
1062 case INTERP_MODE_FLAT:
1063 return NULL;
1064 case INTERP_MODE_SMOOTH:
1065 case INTERP_MODE_NONE:
1066 if (location == INTERP_CENTER)
1067 interp_param_idx = SI_PARAM_PERSP_CENTER;
1068 else if (location == INTERP_CENTROID)
1069 interp_param_idx = SI_PARAM_PERSP_CENTROID;
1070 else if (location == INTERP_SAMPLE)
1071 interp_param_idx = SI_PARAM_PERSP_SAMPLE;
1072 break;
1073 case INTERP_MODE_NOPERSPECTIVE:
1074 if (location == INTERP_CENTER)
1075 interp_param_idx = SI_PARAM_LINEAR_CENTER;
1076 else if (location == INTERP_CENTROID)
1077 interp_param_idx = SI_PARAM_LINEAR_CENTROID;
1078 else if (location == INTERP_SAMPLE)
1079 interp_param_idx = SI_PARAM_LINEAR_SAMPLE;
1080 break;
1081 default:
1082 assert(!"Unhandled interpolation mode.");
1083 return NULL;
1084 }
1085
1086 return interp_param_idx != -1 ?
1087 LLVMGetParam(ctx->main_fn, interp_param_idx) : NULL;
1088 }
1089
1090 static LLVMValueRef
1091 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
1092 unsigned descriptor_set, unsigned base_index,
1093 unsigned constant_index, LLVMValueRef dynamic_index,
1094 enum ac_descriptor_type desc_type, bool image,
1095 bool write, bool bindless)
1096 {
1097 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1098 LLVMBuilderRef builder = ctx->ac.builder;
1099 unsigned const_index = base_index + constant_index;
1100
1101 assert(!descriptor_set);
1102 assert(!image || desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
1103
1104 if (bindless) {
1105 LLVMValueRef list =
1106 LLVMGetParam(ctx->main_fn, ctx->param_bindless_samplers_and_images);
1107
1108 /* dynamic_index is the bindless handle */
1109 if (image) {
1110 /* For simplicity, bindless image descriptors use fixed
1111 * 16-dword slots for now.
1112 */
1113 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1114 LLVMConstInt(ctx->i64, 2, 0), "");
1115
1116 return si_load_image_desc(ctx, list, dynamic_index, desc_type,
1117 write, true);
1118 }
1119
1120 /* Since bindless handle arithmetic can contain an unsigned integer
1121 * wraparound and si_load_sampler_desc assumes there isn't any,
1122 * use GEP without "inbounds" (inside ac_build_pointer_add)
1123 * to prevent incorrect code generation and hangs.
1124 */
1125 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1126 LLVMConstInt(ctx->i64, 2, 0), "");
1127 list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
1128 return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
1129 }
1130
1131 unsigned num_slots = image ? ctx->num_images : ctx->num_samplers;
1132 assert(const_index < num_slots || dynamic_index);
1133
1134 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1135 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, const_index, false);
1136
1137 if (dynamic_index) {
1138 index = LLVMBuildAdd(builder, index, dynamic_index, "");
1139
1140 /* From the GL_ARB_shader_image_load_store extension spec:
1141 *
1142 * If a shader performs an image load, store, or atomic
1143 * operation using an image variable declared as an array,
1144 * and if the index used to select an individual element is
1145 * negative or greater than or equal to the size of the
1146 * array, the results of the operation are undefined but may
1147 * not lead to termination.
1148 */
1149 index = si_llvm_bound_index(ctx, index, num_slots);
1150 }
1151
1152 if (image) {
1153 index = LLVMBuildSub(ctx->ac.builder,
1154 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
1155 index, "");
1156 return si_load_image_desc(ctx, list, index, desc_type, write, false);
1157 }
1158
1159 index = LLVMBuildAdd(ctx->ac.builder, index,
1160 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1161 return si_load_sampler_desc(ctx, list, index, desc_type);
1162 }
1163
1164 static void bitcast_inputs(struct si_shader_context *ctx,
1165 LLVMValueRef data[4],
1166 unsigned input_idx)
1167 {
1168 for (unsigned chan = 0; chan < 4; chan++) {
1169 ctx->inputs[input_idx + chan] =
1170 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
1171 }
1172 }
1173
1174 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
1175 {
1176 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1177
1178 if (nir->info.stage == MESA_SHADER_VERTEX) {
1179 uint64_t processed_inputs = 0;
1180 nir_foreach_variable(variable, &nir->inputs) {
1181 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
1182 true);
1183 unsigned input_idx = variable->data.driver_location;
1184
1185 LLVMValueRef data[4];
1186 unsigned loc = variable->data.location;
1187
1188 for (unsigned i = 0; i < attrib_count; i++) {
1189 /* Packed components share the same location so skip
1190 * them if we have already processed the location.
1191 */
1192 if (processed_inputs & ((uint64_t)1 << (loc + i))) {
1193 input_idx += 4;
1194 continue;
1195 }
1196
1197 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1198 bitcast_inputs(ctx, data, input_idx);
1199 if (glsl_type_is_dual_slot(variable->type)) {
1200 input_idx += 4;
1201 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1202 bitcast_inputs(ctx, data, input_idx);
1203 }
1204
1205 processed_inputs |= ((uint64_t)1 << (loc + i));
1206 input_idx += 4;
1207 }
1208 }
1209 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1210 unsigned colors_read =
1211 ctx->shader->selector->info.colors_read;
1212 LLVMValueRef main_fn = ctx->main_fn;
1213
1214 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1215
1216 unsigned offset = SI_PARAM_POS_FIXED_PT + 1;
1217
1218 if (colors_read & 0x0f) {
1219 unsigned mask = colors_read & 0x0f;
1220 LLVMValueRef values[4];
1221 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1222 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1223 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1224 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1225 ctx->abi.color0 =
1226 ac_to_integer(&ctx->ac,
1227 ac_build_gather_values(&ctx->ac, values, 4));
1228 }
1229 if (colors_read & 0xf0) {
1230 unsigned mask = (colors_read & 0xf0) >> 4;
1231 LLVMValueRef values[4];
1232 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1233 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1234 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1235 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1236 ctx->abi.color1 =
1237 ac_to_integer(&ctx->ac,
1238 ac_build_gather_values(&ctx->ac, values, 4));
1239 }
1240
1241 ctx->abi.interp_at_sample_force_center =
1242 ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center;
1243 } else if (nir->info.stage == MESA_SHADER_COMPUTE) {
1244 if (nir->info.cs.user_data_components_amd) {
1245 ctx->abi.user_data = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
1246 ctx->abi.user_data = ac_build_expand_to_vec4(&ctx->ac, ctx->abi.user_data,
1247 nir->info.cs.user_data_components_amd);
1248 }
1249 }
1250
1251 ctx->abi.inputs = &ctx->inputs[0];
1252 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
1253 ctx->abi.clamp_shadow_reference = true;
1254 ctx->abi.robust_buffer_access = true;
1255
1256 ctx->num_samplers = util_last_bit(info->samplers_declared);
1257 ctx->num_images = util_last_bit(info->images_declared);
1258
1259 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
1260 assert(gl_shader_stage_is_compute(nir->info.stage));
1261 si_declare_compute_memory(ctx);
1262 }
1263 ac_nir_translate(&ctx->ac, &ctx->abi, nir);
1264
1265 return true;
1266 }