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[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 #include "tgsi/tgsi_from_mesa.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34 #include "compiler/nir/nir_builder.h"
35 #include "compiler/nir/nir_deref.h"
36
37 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
38 {
39 for (unsigned i = 0; i < instr->num_srcs; i++) {
40 switch (instr->src[i].src_type) {
41 case nir_tex_src_texture_deref:
42 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
43 default:
44 break;
45 }
46 }
47
48 return NULL;
49 }
50
51 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
52 {
53 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
54 }
55
56 static void gather_usage_helper(const nir_deref_instr **deref_ptr,
57 unsigned location,
58 uint8_t mask,
59 uint8_t *usage_mask)
60 {
61 for (; *deref_ptr; deref_ptr++) {
62 const nir_deref_instr *deref = *deref_ptr;
63 switch (deref->deref_type) {
64 case nir_deref_type_array: {
65 unsigned elem_size =
66 glsl_count_attribute_slots(deref->type, false);
67 if (nir_src_is_const(deref->arr.index)) {
68 location += elem_size * nir_src_as_uint(deref->arr.index);
69 } else {
70 unsigned array_elems =
71 glsl_get_length(deref_ptr[-1]->type);
72 for (unsigned i = 0; i < array_elems; i++) {
73 gather_usage_helper(deref_ptr + 1,
74 location + elem_size * i,
75 mask, usage_mask);
76 }
77 return;
78 }
79 break;
80 }
81 case nir_deref_type_struct: {
82 const struct glsl_type *parent_type =
83 deref_ptr[-1]->type;
84 unsigned index = deref->strct.index;
85 for (unsigned i = 0; i < index; i++) {
86 const struct glsl_type *ft = glsl_get_struct_field(parent_type, i);
87 location += glsl_count_attribute_slots(ft, false);
88 }
89 break;
90 }
91 default:
92 unreachable("Unhandled deref type in gather_components_used_helper");
93 }
94 }
95
96 usage_mask[location] |= mask & 0xf;
97 if (mask & 0xf0)
98 usage_mask[location + 1] |= (mask >> 4) & 0xf;
99 }
100
101 static void gather_usage(const nir_deref_instr *deref,
102 uint8_t mask,
103 uint8_t *usage_mask)
104 {
105 nir_deref_path path;
106 nir_deref_path_init(&path, (nir_deref_instr *)deref, NULL);
107
108 unsigned location_frac = path.path[0]->var->data.location_frac;
109 if (glsl_type_is_64bit(deref->type)) {
110 uint8_t new_mask = 0;
111 for (unsigned i = 0; i < 4; i++) {
112 if (mask & (1 << i))
113 new_mask |= 0x3 << (2 * i);
114 }
115 mask = new_mask << location_frac;
116 } else {
117 mask <<= location_frac;
118 mask &= 0xf;
119 }
120
121 gather_usage_helper((const nir_deref_instr **)&path.path[1],
122 path.path[0]->var->data.driver_location,
123 mask, usage_mask);
124
125 nir_deref_path_finish(&path);
126 }
127
128 static void gather_intrinsic_load_deref_input_info(const nir_shader *nir,
129 const nir_intrinsic_instr *instr,
130 const nir_deref_instr *deref,
131 struct tgsi_shader_info *info)
132 {
133 switch (nir->info.stage) {
134 case MESA_SHADER_VERTEX:
135 gather_usage(deref, nir_ssa_def_components_read(&instr->dest.ssa),
136 info->input_usage_mask);
137 default:;
138 }
139 }
140
141 static void gather_intrinsic_load_deref_output_info(const nir_shader *nir,
142 const nir_intrinsic_instr *instr,
143 nir_variable *var,
144 struct tgsi_shader_info *info)
145 {
146 assert(var && var->data.mode == nir_var_shader_out);
147
148 switch (nir->info.stage) {
149 case MESA_SHADER_TESS_CTRL:
150 if (var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
151 var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
152 info->reads_tessfactor_outputs = true;
153 else if (var->data.patch)
154 info->reads_perpatch_outputs = true;
155 else
156 info->reads_pervertex_outputs = true;
157 break;
158
159 case MESA_SHADER_FRAGMENT:
160 if (var->data.fb_fetch_output)
161 info->uses_fbfetch = true;
162 break;
163 default:;
164 }
165 }
166
167 static void gather_intrinsic_store_deref_output_info(const nir_shader *nir,
168 const nir_intrinsic_instr *instr,
169 const nir_deref_instr *deref,
170 struct tgsi_shader_info *info)
171 {
172 switch (nir->info.stage) {
173 case MESA_SHADER_VERTEX: /* needed by LS, ES */
174 case MESA_SHADER_TESS_EVAL: /* needed by ES */
175 case MESA_SHADER_GEOMETRY:
176 gather_usage(deref, nir_intrinsic_write_mask(instr),
177 info->output_usagemask);
178 break;
179 default:;
180 }
181 }
182
183 static void scan_instruction(const struct nir_shader *nir,
184 struct tgsi_shader_info *info,
185 nir_instr *instr)
186 {
187 if (instr->type == nir_instr_type_alu) {
188 nir_alu_instr *alu = nir_instr_as_alu(instr);
189
190 switch (alu->op) {
191 case nir_op_fddx:
192 case nir_op_fddy:
193 case nir_op_fddx_fine:
194 case nir_op_fddy_fine:
195 case nir_op_fddx_coarse:
196 case nir_op_fddy_coarse:
197 info->uses_derivatives = true;
198 break;
199 default:
200 break;
201 }
202 } else if (instr->type == nir_instr_type_tex) {
203 nir_tex_instr *tex = nir_instr_as_tex(instr);
204 nir_variable *texture = tex_get_texture_var(tex);
205
206 if (!texture) {
207 info->samplers_declared |=
208 u_bit_consecutive(tex->sampler_index, 1);
209 } else {
210 if (texture->data.bindless)
211 info->uses_bindless_samplers = true;
212 }
213
214 switch (tex->op) {
215 case nir_texop_tex:
216 case nir_texop_txb:
217 case nir_texop_lod:
218 info->uses_derivatives = true;
219 break;
220 default:
221 break;
222 }
223 } else if (instr->type == nir_instr_type_intrinsic) {
224 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
225
226 switch (intr->intrinsic) {
227 case nir_intrinsic_load_front_face:
228 info->uses_frontface = 1;
229 break;
230 case nir_intrinsic_load_instance_id:
231 info->uses_instanceid = 1;
232 break;
233 case nir_intrinsic_load_invocation_id:
234 info->uses_invocationid = true;
235 break;
236 case nir_intrinsic_load_num_work_groups:
237 info->uses_grid_size = true;
238 break;
239 case nir_intrinsic_load_local_group_size:
240 /* The block size is translated to IMM with a fixed block size. */
241 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
242 info->uses_block_size = true;
243 break;
244 case nir_intrinsic_load_local_invocation_id:
245 case nir_intrinsic_load_work_group_id: {
246 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
247 while (mask) {
248 unsigned i = u_bit_scan(&mask);
249
250 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
251 info->uses_block_id[i] = true;
252 else
253 info->uses_thread_id[i] = true;
254 }
255 break;
256 }
257 case nir_intrinsic_load_vertex_id:
258 info->uses_vertexid = 1;
259 break;
260 case nir_intrinsic_load_vertex_id_zero_base:
261 info->uses_vertexid_nobase = 1;
262 break;
263 case nir_intrinsic_load_base_vertex:
264 info->uses_basevertex = 1;
265 break;
266 case nir_intrinsic_load_draw_id:
267 info->uses_drawid = 1;
268 break;
269 case nir_intrinsic_load_primitive_id:
270 info->uses_primid = 1;
271 break;
272 case nir_intrinsic_load_sample_mask_in:
273 info->reads_samplemask = true;
274 break;
275 case nir_intrinsic_load_tess_level_inner:
276 case nir_intrinsic_load_tess_level_outer:
277 info->reads_tess_factors = true;
278 break;
279 case nir_intrinsic_bindless_image_load:
280 info->uses_bindless_images = true;
281
282 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
283 info->uses_bindless_buffer_load = true;
284 else
285 info->uses_bindless_image_load = true;
286 break;
287 case nir_intrinsic_bindless_image_size:
288 case nir_intrinsic_bindless_image_samples:
289 info->uses_bindless_images = true;
290 break;
291 case nir_intrinsic_bindless_image_store:
292 info->uses_bindless_images = true;
293
294 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
295 info->uses_bindless_buffer_store = true;
296 else
297 info->uses_bindless_image_store = true;
298
299 info->writes_memory = true;
300 info->num_memory_instructions++; /* we only care about stores */
301 break;
302 case nir_intrinsic_image_deref_store:
303 info->writes_memory = true;
304 info->num_memory_instructions++; /* we only care about stores */
305 break;
306 case nir_intrinsic_bindless_image_atomic_add:
307 case nir_intrinsic_bindless_image_atomic_imin:
308 case nir_intrinsic_bindless_image_atomic_umin:
309 case nir_intrinsic_bindless_image_atomic_imax:
310 case nir_intrinsic_bindless_image_atomic_umax:
311 case nir_intrinsic_bindless_image_atomic_and:
312 case nir_intrinsic_bindless_image_atomic_or:
313 case nir_intrinsic_bindless_image_atomic_xor:
314 case nir_intrinsic_bindless_image_atomic_exchange:
315 case nir_intrinsic_bindless_image_atomic_comp_swap:
316 info->uses_bindless_images = true;
317
318 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
319 info->uses_bindless_buffer_atomic = true;
320 else
321 info->uses_bindless_image_atomic = true;
322
323 info->writes_memory = true;
324 info->num_memory_instructions++; /* we only care about stores */
325 break;
326 case nir_intrinsic_image_deref_atomic_add:
327 case nir_intrinsic_image_deref_atomic_imin:
328 case nir_intrinsic_image_deref_atomic_umin:
329 case nir_intrinsic_image_deref_atomic_imax:
330 case nir_intrinsic_image_deref_atomic_umax:
331 case nir_intrinsic_image_deref_atomic_and:
332 case nir_intrinsic_image_deref_atomic_or:
333 case nir_intrinsic_image_deref_atomic_xor:
334 case nir_intrinsic_image_deref_atomic_exchange:
335 case nir_intrinsic_image_deref_atomic_comp_swap:
336 case nir_intrinsic_image_deref_atomic_inc_wrap:
337 case nir_intrinsic_image_deref_atomic_dec_wrap:
338 info->writes_memory = true;
339 info->num_memory_instructions++; /* we only care about stores */
340 break;
341 case nir_intrinsic_store_ssbo:
342 case nir_intrinsic_ssbo_atomic_add:
343 case nir_intrinsic_ssbo_atomic_imin:
344 case nir_intrinsic_ssbo_atomic_umin:
345 case nir_intrinsic_ssbo_atomic_imax:
346 case nir_intrinsic_ssbo_atomic_umax:
347 case nir_intrinsic_ssbo_atomic_and:
348 case nir_intrinsic_ssbo_atomic_or:
349 case nir_intrinsic_ssbo_atomic_xor:
350 case nir_intrinsic_ssbo_atomic_exchange:
351 case nir_intrinsic_ssbo_atomic_comp_swap:
352 info->writes_memory = true;
353 info->num_memory_instructions++; /* we only care about stores */
354 break;
355 case nir_intrinsic_load_color0:
356 case nir_intrinsic_load_color1: {
357 unsigned index = intr->intrinsic == nir_intrinsic_load_color1;
358 uint8_t mask = nir_ssa_def_components_read(&intr->dest.ssa);
359 info->colors_read |= mask << (index * 4);
360 break;
361 }
362 case nir_intrinsic_load_barycentric_pixel:
363 case nir_intrinsic_load_barycentric_centroid:
364 case nir_intrinsic_load_barycentric_sample:
365 case nir_intrinsic_load_barycentric_at_offset: /* uses center */
366 case nir_intrinsic_load_barycentric_at_sample: { /* uses center */
367 unsigned mode = nir_intrinsic_interp_mode(intr);
368
369 if (mode == INTERP_MODE_FLAT)
370 break;
371
372 if (mode == INTERP_MODE_NOPERSPECTIVE) {
373 if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
374 info->uses_linear_sample = true;
375 else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
376 info->uses_linear_centroid = true;
377 else
378 info->uses_linear_center = true;
379
380 if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
381 info->uses_linear_opcode_interp_sample = true;
382 } else {
383 if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
384 info->uses_persp_sample = true;
385 else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
386 info->uses_persp_centroid = true;
387 else
388 info->uses_persp_center = true;
389
390 if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
391 info->uses_persp_opcode_interp_sample = true;
392 }
393 break;
394 }
395 case nir_intrinsic_load_deref: {
396 nir_variable *var = intrinsic_get_var(intr);
397 nir_variable_mode mode = var->data.mode;
398
399 if (mode == nir_var_shader_in) {
400 /* PS inputs use the interpolated load intrinsics. */
401 assert(nir->info.stage != MESA_SHADER_FRAGMENT);
402 gather_intrinsic_load_deref_input_info(nir, intr,
403 nir_src_as_deref(intr->src[0]), info);
404 } else if (mode == nir_var_shader_out) {
405 gather_intrinsic_load_deref_output_info(nir, intr, var, info);
406 }
407 break;
408 }
409 case nir_intrinsic_store_deref: {
410 nir_variable *var = intrinsic_get_var(intr);
411
412 if (var->data.mode == nir_var_shader_out)
413 gather_intrinsic_store_deref_output_info(nir, intr,
414 nir_src_as_deref(intr->src[0]), info);
415 break;
416 }
417 case nir_intrinsic_interp_deref_at_centroid:
418 case nir_intrinsic_interp_deref_at_sample:
419 case nir_intrinsic_interp_deref_at_offset:
420 unreachable("interp opcodes should have been lowered");
421 break;
422 default:
423 break;
424 }
425 }
426 }
427
428 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
429 struct tgsi_tessctrl_info *out)
430 {
431 memset(out, 0, sizeof(*out));
432
433 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
434 return;
435
436 out->tessfactors_are_def_in_all_invocs =
437 ac_are_tessfactors_def_in_all_invocs(nir);
438 }
439
440 static void scan_output_slot(const nir_variable *var,
441 unsigned var_idx,
442 unsigned component, unsigned num_components,
443 struct tgsi_shader_info *info)
444 {
445 assert(component + num_components <= 4);
446 assert(component < 4);
447
448 unsigned semantic_name, semantic_index;
449
450 unsigned location = var->data.location + var_idx;
451 unsigned drv_location = var->data.driver_location + var_idx;
452
453 if (info->processor == PIPE_SHADER_FRAGMENT) {
454 tgsi_get_gl_frag_result_semantic(location,
455 &semantic_name, &semantic_index);
456
457 /* Adjust for dual source blending */
458 if (var->data.index > 0) {
459 semantic_index++;
460 }
461 } else {
462 tgsi_get_gl_varying_semantic(location, true,
463 &semantic_name, &semantic_index);
464 }
465
466 ubyte usagemask = ((1 << num_components) - 1) << component;
467
468 unsigned gs_out_streams;
469 if (var->data.stream & (1u << 31)) {
470 gs_out_streams = var->data.stream & ~(1u << 31);
471 } else {
472 assert(var->data.stream < 4);
473 gs_out_streams = 0;
474 for (unsigned j = 0; j < num_components; ++j)
475 gs_out_streams |= var->data.stream << (2 * (component + j));
476 }
477
478 unsigned streamx = gs_out_streams & 3;
479 unsigned streamy = (gs_out_streams >> 2) & 3;
480 unsigned streamz = (gs_out_streams >> 4) & 3;
481 unsigned streamw = (gs_out_streams >> 6) & 3;
482
483 if (usagemask & TGSI_WRITEMASK_X) {
484 info->output_streams[drv_location] |= streamx;
485 info->num_stream_output_components[streamx]++;
486 }
487 if (usagemask & TGSI_WRITEMASK_Y) {
488 info->output_streams[drv_location] |= streamy << 2;
489 info->num_stream_output_components[streamy]++;
490 }
491 if (usagemask & TGSI_WRITEMASK_Z) {
492 info->output_streams[drv_location] |= streamz << 4;
493 info->num_stream_output_components[streamz]++;
494 }
495 if (usagemask & TGSI_WRITEMASK_W) {
496 info->output_streams[drv_location] |= streamw << 6;
497 info->num_stream_output_components[streamw]++;
498 }
499
500 info->output_semantic_name[drv_location] = semantic_name;
501 info->output_semantic_index[drv_location] = semantic_index;
502
503 switch (semantic_name) {
504 case TGSI_SEMANTIC_PRIMID:
505 info->writes_primid = true;
506 break;
507 case TGSI_SEMANTIC_VIEWPORT_INDEX:
508 info->writes_viewport_index = true;
509 break;
510 case TGSI_SEMANTIC_LAYER:
511 info->writes_layer = true;
512 break;
513 case TGSI_SEMANTIC_PSIZE:
514 info->writes_psize = true;
515 break;
516 case TGSI_SEMANTIC_CLIPVERTEX:
517 info->writes_clipvertex = true;
518 break;
519 case TGSI_SEMANTIC_COLOR:
520 info->colors_written |= 1 << semantic_index;
521 break;
522 case TGSI_SEMANTIC_STENCIL:
523 info->writes_stencil = true;
524 break;
525 case TGSI_SEMANTIC_SAMPLEMASK:
526 info->writes_samplemask = true;
527 break;
528 case TGSI_SEMANTIC_EDGEFLAG:
529 info->writes_edgeflag = true;
530 break;
531 case TGSI_SEMANTIC_POSITION:
532 if (info->processor == PIPE_SHADER_FRAGMENT)
533 info->writes_z = true;
534 else
535 info->writes_position = true;
536 break;
537 }
538 }
539
540 static void scan_output_helper(const nir_variable *var,
541 unsigned location,
542 const struct glsl_type *type,
543 struct tgsi_shader_info *info)
544 {
545 if (glsl_type_is_struct(type)) {
546 for (unsigned i = 0; i < glsl_get_length(type); i++) {
547 const struct glsl_type *ft = glsl_get_struct_field(type, i);
548 scan_output_helper(var, location, ft, info);
549 location += glsl_count_attribute_slots(ft, false);
550 }
551 } else if (glsl_type_is_array_or_matrix(type)) {
552 const struct glsl_type *elem_type =
553 glsl_get_array_element(type);
554 unsigned num_elems = glsl_get_length(type);
555 if (var->data.compact) {
556 assert(glsl_type_is_scalar(elem_type));
557 assert(glsl_get_bit_size(elem_type) == 32);
558 unsigned component = var->data.location_frac;
559 scan_output_slot(var, location, component,
560 MIN2(num_elems, 4 - component), info);
561 if (component + num_elems > 4) {
562 scan_output_slot(var, location + 1, 0,
563 component + num_elems - 4, info);
564 }
565
566 } else {
567 unsigned elem_count = glsl_count_attribute_slots(elem_type, false);
568 for (unsigned i = 0; i < num_elems; i++) {
569 scan_output_helper(var, location, elem_type, info);
570 location += elem_count;
571 }
572 }
573 } else if (glsl_type_is_dual_slot(type)) {
574 unsigned component = var->data.location_frac;
575 scan_output_slot(var, location, component, 4 - component, info);
576 scan_output_slot(var, location + 1, 0, component + 2 * glsl_get_components(type) - 4,
577 info);
578 } else {
579 unsigned component = var->data.location_frac;
580 assert(glsl_type_is_vector_or_scalar(type));
581 unsigned num_components = glsl_get_components(type);
582 if (glsl_type_is_64bit(type))
583 num_components *= 2;
584 scan_output_slot(var, location, component, num_components, info);
585 }
586 }
587
588 void si_nir_scan_shader(const struct nir_shader *nir,
589 struct tgsi_shader_info *info)
590 {
591 nir_function *func;
592 unsigned i;
593
594 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
595 info->num_tokens = 2; /* indicate that the shader is non-empty */
596 info->num_instructions = 2;
597
598 info->properties[TGSI_PROPERTY_NEXT_SHADER] =
599 pipe_shader_type_from_mesa(nir->info.next_stage);
600
601 if (nir->info.stage == MESA_SHADER_VERTEX) {
602 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
603 nir->info.vs.window_space_position;
604 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] =
605 nir->info.vs.blit_sgprs_amd;
606 }
607
608 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
609 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
610 nir->info.tess.tcs_vertices_out;
611 }
612
613 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
614 if (nir->info.tess.primitive_mode == GL_ISOLINES)
615 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
616 else
617 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
618
619 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
620 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
621 PIPE_TESS_SPACING_FRACTIONAL_ODD);
622 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
623 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
624
625 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
626 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
627 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
628 }
629
630 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
631 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
632 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
633 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
634 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
635 }
636
637 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
638 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
639 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
640 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
641
642 if (nir->info.fs.pixel_center_integer) {
643 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
644 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
645 }
646
647 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
648 switch (nir->info.fs.depth_layout) {
649 case FRAG_DEPTH_LAYOUT_ANY:
650 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
651 break;
652 case FRAG_DEPTH_LAYOUT_GREATER:
653 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
654 break;
655 case FRAG_DEPTH_LAYOUT_LESS:
656 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
657 break;
658 case FRAG_DEPTH_LAYOUT_UNCHANGED:
659 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
660 break;
661 default:
662 unreachable("Unknow depth layout");
663 }
664 }
665 }
666
667 if (gl_shader_stage_is_compute(nir->info.stage)) {
668 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
669 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
670 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
671 info->properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD] = nir->info.cs.user_data_components_amd;
672 }
673
674 i = 0;
675 uint64_t processed_inputs = 0;
676 nir_foreach_variable(variable, &nir->inputs) {
677 unsigned semantic_name, semantic_index;
678
679 const struct glsl_type *type = variable->type;
680 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
681 assert(glsl_type_is_array(type));
682 type = glsl_get_array_element(type);
683 }
684
685 unsigned attrib_count = glsl_count_attribute_slots(type,
686 nir->info.stage == MESA_SHADER_VERTEX);
687
688 i = variable->data.driver_location;
689
690 /* Vertex shader inputs don't have semantics. The state
691 * tracker has already mapped them to attributes via
692 * variable->data.driver_location.
693 */
694 if (nir->info.stage == MESA_SHADER_VERTEX)
695 continue;
696
697 for (unsigned j = 0; j < attrib_count; j++, i++) {
698
699 if (processed_inputs & ((uint64_t)1 << i))
700 continue;
701
702 processed_inputs |= ((uint64_t)1 << i);
703
704 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
705 &semantic_name, &semantic_index);
706
707 info->input_semantic_name[i] = semantic_name;
708 info->input_semantic_index[i] = semantic_index;
709
710 if (semantic_name == TGSI_SEMANTIC_PRIMID)
711 info->uses_primid = true;
712
713 if (semantic_name == TGSI_SEMANTIC_COLOR) {
714 /* We only need this for color inputs. */
715 if (variable->data.sample)
716 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
717 else if (variable->data.centroid)
718 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
719 else
720 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
721 }
722
723 enum glsl_base_type base_type =
724 glsl_get_base_type(glsl_without_array(variable->type));
725
726 switch (variable->data.interpolation) {
727 case INTERP_MODE_NONE:
728 if (glsl_base_type_is_integer(base_type)) {
729 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
730 break;
731 }
732
733 if (semantic_name == TGSI_SEMANTIC_COLOR) {
734 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
735 break;
736 }
737 /* fall-through */
738
739 case INTERP_MODE_SMOOTH:
740 assert(!glsl_base_type_is_integer(base_type));
741
742 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
743 break;
744
745 case INTERP_MODE_NOPERSPECTIVE:
746 assert(!glsl_base_type_is_integer(base_type));
747
748 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
749 break;
750
751 case INTERP_MODE_FLAT:
752 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
753 break;
754 }
755 }
756 }
757
758 nir_foreach_variable(variable, &nir->outputs) {
759 const struct glsl_type *type = variable->type;
760 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
761 assert(glsl_type_is_array(type));
762 type = glsl_get_array_element(type);
763 }
764
765 ASSERTED unsigned attrib_count = glsl_count_attribute_slots(type, false);
766 scan_output_helper(variable, 0, type, info);
767
768 unsigned loc = variable->data.location;
769 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
770 loc == FRAG_RESULT_COLOR &&
771 nir->info.outputs_written & (1ull << loc)) {
772 assert(attrib_count == 1);
773 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
774 }
775 }
776
777 info->num_inputs = nir->num_inputs;
778 info->num_outputs = nir->num_outputs;
779
780 struct set *ubo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
781 _mesa_key_pointer_equal);
782 struct set *ssbo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
783 _mesa_key_pointer_equal);
784
785 /* Intialise const_file_max[0] */
786 info->const_file_max[0] = -1;
787
788 /* The first 8 are reserved for atomic counters using ssbo */
789 unsigned ssbo_idx = 8;
790
791 unsigned ubo_idx = 1;
792 nir_foreach_variable(variable, &nir->uniforms) {
793 const struct glsl_type *type = variable->type;
794 enum glsl_base_type base_type =
795 glsl_get_base_type(glsl_without_array(type));
796 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
797 unsigned loc = variable->data.driver_location / 4;
798 int slot_count = glsl_count_attribute_slots(type, false);
799 int max_slot = MAX2(info->const_file_max[0], (int) loc) + slot_count;
800
801 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
802 * really use the mask (other than ubo_idx == 1 for regular
803 * uniforms) its really only used for getting the buffer count
804 * so we don't need to worry about the ordering.
805 */
806 if (variable->interface_type != NULL) {
807 if (variable->data.mode == nir_var_uniform ||
808 variable->data.mode == nir_var_mem_ubo ||
809 variable->data.mode == nir_var_mem_ssbo) {
810
811 struct set *buf_set = variable->data.mode == nir_var_mem_ssbo ?
812 ssbo_set : ubo_set;
813
814 unsigned block_count;
815 if (base_type != GLSL_TYPE_INTERFACE) {
816 struct set_entry *entry =
817 _mesa_set_search(buf_set, variable->interface_type);
818
819 /* Check if we have already processed
820 * a member from this ubo.
821 */
822 if (entry)
823 continue;
824
825 block_count = 1;
826 } else {
827 block_count = aoa_size;
828 }
829
830 if (variable->data.mode == nir_var_uniform ||
831 variable->data.mode == nir_var_mem_ubo) {
832 info->const_buffers_declared |= u_bit_consecutive(ubo_idx, block_count);
833 ubo_idx += block_count;
834 } else {
835 assert(variable->data.mode == nir_var_mem_ssbo);
836
837 info->shader_buffers_declared |= u_bit_consecutive(ssbo_idx, block_count);
838 ssbo_idx += block_count;
839 }
840
841 _mesa_set_add(buf_set, variable->interface_type);
842 }
843
844 continue;
845 }
846
847 /* We rely on the fact that nir_lower_samplers_as_deref has
848 * eliminated struct dereferences.
849 */
850 if (base_type == GLSL_TYPE_SAMPLER && !variable->data.bindless) {
851 info->samplers_declared |=
852 u_bit_consecutive(variable->data.binding, aoa_size);
853 } else if (base_type == GLSL_TYPE_IMAGE && !variable->data.bindless) {
854 info->images_declared |=
855 u_bit_consecutive(variable->data.binding, aoa_size);
856 } else if (base_type != GLSL_TYPE_ATOMIC_UINT) {
857 info->const_buffers_declared |= 1;
858 info->const_file_max[0] = max_slot;
859 }
860 }
861
862 _mesa_set_destroy(ubo_set, NULL);
863 _mesa_set_destroy(ssbo_set, NULL);
864
865 info->num_written_clipdistance = nir->info.clip_distance_array_size;
866 info->num_written_culldistance = nir->info.cull_distance_array_size;
867 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
868 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
869
870 if (info->processor == PIPE_SHADER_FRAGMENT)
871 info->uses_kill = nir->info.fs.uses_discard;
872
873 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
874 nir_foreach_block(block, func->impl) {
875 nir_foreach_instr(instr, block)
876 scan_instruction(nir, info, instr);
877 }
878 }
879
880 void
881 si_nir_opts(struct nir_shader *nir)
882 {
883 bool progress;
884 unsigned lower_flrp =
885 (nir->options->lower_flrp16 ? 16 : 0) |
886 (nir->options->lower_flrp32 ? 32 : 0) |
887 (nir->options->lower_flrp64 ? 64 : 0);
888
889 do {
890 progress = false;
891
892 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
893
894 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
895 NIR_PASS(progress, nir, nir_opt_dead_write_vars);
896
897 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL);
898 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
899
900 /* (Constant) copy propagation is needed for txf with offsets. */
901 NIR_PASS(progress, nir, nir_copy_prop);
902 NIR_PASS(progress, nir, nir_opt_remove_phis);
903 NIR_PASS(progress, nir, nir_opt_dce);
904 if (nir_opt_trivial_continues(nir)) {
905 progress = true;
906 NIR_PASS(progress, nir, nir_copy_prop);
907 NIR_PASS(progress, nir, nir_opt_dce);
908 }
909 NIR_PASS(progress, nir, nir_opt_if, true);
910 NIR_PASS(progress, nir, nir_opt_dead_cf);
911 NIR_PASS(progress, nir, nir_opt_cse);
912 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
913
914 /* Needed for algebraic lowering */
915 NIR_PASS(progress, nir, nir_opt_algebraic);
916 NIR_PASS(progress, nir, nir_opt_constant_folding);
917
918 if (lower_flrp != 0) {
919 bool lower_flrp_progress = false;
920
921 NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp,
922 lower_flrp,
923 false /* always_precise */,
924 nir->options->lower_ffma);
925 if (lower_flrp_progress) {
926 NIR_PASS(progress, nir,
927 nir_opt_constant_folding);
928 progress = true;
929 }
930
931 /* Nothing should rematerialize any flrps, so we only
932 * need to do this lowering once.
933 */
934 lower_flrp = 0;
935 }
936
937 NIR_PASS(progress, nir, nir_opt_undef);
938 NIR_PASS(progress, nir, nir_opt_conditional_discard);
939 if (nir->options->max_unroll_iterations) {
940 NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
941 }
942 } while (progress);
943 }
944
945 static int
946 type_size_vec4(const struct glsl_type *type, bool bindless)
947 {
948 return glsl_count_attribute_slots(type, false);
949 }
950
951 static void
952 si_nir_lower_color(nir_shader *nir)
953 {
954 nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
955
956 nir_builder b;
957 nir_builder_init(&b, entrypoint);
958
959 nir_foreach_block(block, entrypoint) {
960 nir_foreach_instr_safe(instr, block) {
961 if (instr->type != nir_instr_type_intrinsic)
962 continue;
963
964 nir_intrinsic_instr *intrin =
965 nir_instr_as_intrinsic(instr);
966
967 if (intrin->intrinsic != nir_intrinsic_load_deref)
968 continue;
969
970 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
971 if (deref->mode != nir_var_shader_in)
972 continue;
973
974 b.cursor = nir_before_instr(instr);
975 nir_variable *var = nir_deref_instr_get_variable(deref);
976 nir_ssa_def *def;
977
978 if (var->data.location == VARYING_SLOT_COL0) {
979 def = nir_load_color0(&b);
980 } else if (var->data.location == VARYING_SLOT_COL1) {
981 def = nir_load_color1(&b);
982 } else {
983 continue;
984 }
985
986 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(def));
987 nir_instr_remove(instr);
988 }
989 }
990 }
991
992 void si_nir_lower_ps_inputs(struct nir_shader *nir)
993 {
994 if (nir->info.stage != MESA_SHADER_FRAGMENT)
995 return;
996
997 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
998 nir_shader_get_entrypoint(nir), false, true);
999
1000 /* Since we're doing nir_lower_io_to_temporaries late, we need
1001 * to lower all the copy_deref's introduced by
1002 * lower_io_to_temporaries before calling nir_lower_io.
1003 */
1004 NIR_PASS_V(nir, nir_split_var_copies);
1005 NIR_PASS_V(nir, nir_lower_var_copies);
1006 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
1007
1008 si_nir_lower_color(nir);
1009 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
1010
1011 /* This pass needs actual constants */
1012 NIR_PASS_V(nir, nir_opt_constant_folding);
1013 NIR_PASS_V(nir, nir_io_add_const_offset_to_base,
1014 nir_var_shader_in);
1015 }
1016
1017 /**
1018 * Perform "lowering" operations on the NIR that are run once when the shader
1019 * selector is created.
1020 */
1021 void si_lower_nir(struct si_shader_selector *sel)
1022 {
1023 /* Adjust the driver location of inputs and outputs. The state tracker
1024 * interprets them as slots, while the ac/nir backend interprets them
1025 * as individual components.
1026 */
1027 if (sel->nir->info.stage != MESA_SHADER_FRAGMENT) {
1028 nir_foreach_variable(variable, &sel->nir->inputs)
1029 variable->data.driver_location *= 4;
1030 }
1031
1032 nir_foreach_variable(variable, &sel->nir->outputs) {
1033 variable->data.driver_location *= 4;
1034
1035 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
1036 if (variable->data.location == FRAG_RESULT_DEPTH)
1037 variable->data.driver_location += 2;
1038 else if (variable->data.location == FRAG_RESULT_STENCIL)
1039 variable->data.driver_location += 1;
1040 }
1041 }
1042
1043 /* Perform lowerings (and optimizations) of code.
1044 *
1045 * Performance considerations aside, we must:
1046 * - lower certain ALU operations
1047 * - ensure constant offsets for texture instructions are folded
1048 * and copy-propagated
1049 */
1050
1051 static const struct nir_lower_tex_options lower_tex_options = {
1052 .lower_txp = ~0u,
1053 };
1054 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
1055
1056 const nir_lower_subgroups_options subgroups_options = {
1057 .subgroup_size = 64,
1058 .ballot_bit_size = 64,
1059 .lower_to_scalar = true,
1060 .lower_subgroup_masks = true,
1061 .lower_vote_trivial = false,
1062 .lower_vote_eq_to_ballot = true,
1063 };
1064 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
1065
1066 ac_lower_indirect_derefs(sel->nir, sel->screen->info.chip_class);
1067
1068 si_nir_opts(sel->nir);
1069
1070 NIR_PASS_V(sel->nir, nir_lower_bool_to_int32);
1071
1072 /* Strip the resulting shader so that the shader cache is more likely
1073 * to hit from other similar shaders.
1074 */
1075 nir_strip(sel->nir);
1076 }
1077
1078 static void declare_nir_input_vs(struct si_shader_context *ctx,
1079 struct nir_variable *variable,
1080 unsigned input_index,
1081 LLVMValueRef out[4])
1082 {
1083 si_llvm_load_input_vs(ctx, input_index, out);
1084 }
1085
1086 LLVMValueRef
1087 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
1088 enum glsl_interp_mode interp, unsigned location)
1089 {
1090 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1091
1092 switch (interp) {
1093 case INTERP_MODE_FLAT:
1094 return NULL;
1095 case INTERP_MODE_SMOOTH:
1096 case INTERP_MODE_NONE:
1097 if (location == INTERP_CENTER)
1098 return ctx->abi.persp_center;
1099 else if (location == INTERP_CENTROID)
1100 return ctx->abi.persp_centroid;
1101 else if (location == INTERP_SAMPLE)
1102 return ctx->abi.persp_sample;
1103 break;
1104 case INTERP_MODE_NOPERSPECTIVE:
1105 if (location == INTERP_CENTER)
1106 return ctx->abi.linear_center;
1107 else if (location == INTERP_CENTROID)
1108 return ctx->abi.linear_centroid;
1109 else if (location == INTERP_SAMPLE)
1110 return ctx->abi.linear_sample;
1111 break;
1112 default:
1113 assert(!"Unhandled interpolation mode.");
1114 }
1115 return NULL;
1116 }
1117
1118 static LLVMValueRef
1119 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
1120 unsigned descriptor_set, unsigned base_index,
1121 unsigned constant_index, LLVMValueRef dynamic_index,
1122 enum ac_descriptor_type desc_type, bool image,
1123 bool write, bool bindless)
1124 {
1125 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1126 LLVMBuilderRef builder = ctx->ac.builder;
1127 unsigned const_index = base_index + constant_index;
1128
1129 assert(!descriptor_set);
1130 assert(!image || desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
1131
1132 if (bindless) {
1133 LLVMValueRef list =
1134 LLVMGetParam(ctx->main_fn, ctx->param_bindless_samplers_and_images);
1135
1136 /* dynamic_index is the bindless handle */
1137 if (image) {
1138 /* For simplicity, bindless image descriptors use fixed
1139 * 16-dword slots for now.
1140 */
1141 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1142 LLVMConstInt(ctx->i64, 2, 0), "");
1143
1144 return si_load_image_desc(ctx, list, dynamic_index, desc_type,
1145 write, true);
1146 }
1147
1148 /* Since bindless handle arithmetic can contain an unsigned integer
1149 * wraparound and si_load_sampler_desc assumes there isn't any,
1150 * use GEP without "inbounds" (inside ac_build_pointer_add)
1151 * to prevent incorrect code generation and hangs.
1152 */
1153 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1154 LLVMConstInt(ctx->i64, 2, 0), "");
1155 list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
1156 return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
1157 }
1158
1159 unsigned num_slots = image ? ctx->num_images : ctx->num_samplers;
1160 assert(const_index < num_slots || dynamic_index);
1161
1162 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1163 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, const_index, false);
1164
1165 if (dynamic_index) {
1166 index = LLVMBuildAdd(builder, index, dynamic_index, "");
1167
1168 /* From the GL_ARB_shader_image_load_store extension spec:
1169 *
1170 * If a shader performs an image load, store, or atomic
1171 * operation using an image variable declared as an array,
1172 * and if the index used to select an individual element is
1173 * negative or greater than or equal to the size of the
1174 * array, the results of the operation are undefined but may
1175 * not lead to termination.
1176 */
1177 index = si_llvm_bound_index(ctx, index, num_slots);
1178 }
1179
1180 if (image) {
1181 index = LLVMBuildSub(ctx->ac.builder,
1182 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
1183 index, "");
1184 return si_load_image_desc(ctx, list, index, desc_type, write, false);
1185 }
1186
1187 index = LLVMBuildAdd(ctx->ac.builder, index,
1188 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1189 return si_load_sampler_desc(ctx, list, index, desc_type);
1190 }
1191
1192 static void bitcast_inputs(struct si_shader_context *ctx,
1193 LLVMValueRef data[4],
1194 unsigned input_idx)
1195 {
1196 for (unsigned chan = 0; chan < 4; chan++) {
1197 ctx->inputs[input_idx + chan] =
1198 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
1199 }
1200 }
1201
1202 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
1203 {
1204 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1205
1206 if (nir->info.stage == MESA_SHADER_VERTEX) {
1207 uint64_t processed_inputs = 0;
1208 nir_foreach_variable(variable, &nir->inputs) {
1209 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
1210 true);
1211 unsigned input_idx = variable->data.driver_location;
1212
1213 LLVMValueRef data[4];
1214 unsigned loc = variable->data.location;
1215
1216 for (unsigned i = 0; i < attrib_count; i++) {
1217 /* Packed components share the same location so skip
1218 * them if we have already processed the location.
1219 */
1220 if (processed_inputs & ((uint64_t)1 << (loc + i))) {
1221 input_idx += 4;
1222 continue;
1223 }
1224
1225 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1226 bitcast_inputs(ctx, data, input_idx);
1227 if (glsl_type_is_dual_slot(variable->type)) {
1228 input_idx += 4;
1229 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1230 bitcast_inputs(ctx, data, input_idx);
1231 }
1232
1233 processed_inputs |= ((uint64_t)1 << (loc + i));
1234 input_idx += 4;
1235 }
1236 }
1237 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1238 unsigned colors_read =
1239 ctx->shader->selector->info.colors_read;
1240 LLVMValueRef main_fn = ctx->main_fn;
1241
1242 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1243
1244 unsigned offset = SI_PARAM_POS_FIXED_PT + 1;
1245
1246 if (colors_read & 0x0f) {
1247 unsigned mask = colors_read & 0x0f;
1248 LLVMValueRef values[4];
1249 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1250 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1251 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1252 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1253 ctx->abi.color0 =
1254 ac_to_integer(&ctx->ac,
1255 ac_build_gather_values(&ctx->ac, values, 4));
1256 }
1257 if (colors_read & 0xf0) {
1258 unsigned mask = (colors_read & 0xf0) >> 4;
1259 LLVMValueRef values[4];
1260 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1261 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1262 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1263 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1264 ctx->abi.color1 =
1265 ac_to_integer(&ctx->ac,
1266 ac_build_gather_values(&ctx->ac, values, 4));
1267 }
1268
1269 ctx->abi.interp_at_sample_force_center =
1270 ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center;
1271 } else if (nir->info.stage == MESA_SHADER_COMPUTE) {
1272 if (nir->info.cs.user_data_components_amd) {
1273 ctx->abi.user_data = LLVMGetParam(ctx->main_fn, ctx->param_cs_user_data);
1274 ctx->abi.user_data = ac_build_expand_to_vec4(&ctx->ac, ctx->abi.user_data,
1275 nir->info.cs.user_data_components_amd);
1276 }
1277 }
1278
1279 ctx->abi.inputs = &ctx->inputs[0];
1280 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
1281 ctx->abi.clamp_shadow_reference = true;
1282 ctx->abi.robust_buffer_access = true;
1283
1284 ctx->num_samplers = util_last_bit(info->samplers_declared);
1285 ctx->num_images = util_last_bit(info->images_declared);
1286
1287 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
1288 assert(gl_shader_stage_is_compute(nir->info.stage));
1289 si_declare_compute_memory(ctx);
1290 }
1291 ac_nir_translate(&ctx->ac, &ctx->abi, nir);
1292
1293 return true;
1294 }