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[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 #include "tgsi/tgsi_from_mesa.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34 #include "compiler/nir/nir_builder.h"
35
36 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
37 {
38 for (unsigned i = 0; i < instr->num_srcs; i++) {
39 switch (instr->src[i].src_type) {
40 case nir_tex_src_texture_deref:
41 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
42 default:
43 break;
44 }
45 }
46
47 return NULL;
48 }
49
50 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
51 {
52 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
53 }
54
55 static void gather_intrinsic_load_deref_input_info(const nir_shader *nir,
56 const nir_intrinsic_instr *instr,
57 nir_variable *var,
58 struct tgsi_shader_info *info)
59 {
60 assert(var && var->data.mode == nir_var_shader_in);
61
62 switch (nir->info.stage) {
63 case MESA_SHADER_VERTEX: {
64 unsigned i = var->data.driver_location;
65 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
66 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
67
68 for (unsigned j = 0; j < attrib_count; j++, i++) {
69 if (glsl_type_is_64bit(glsl_without_array(var->type))) {
70 unsigned dmask = mask;
71
72 if (glsl_type_is_dual_slot(glsl_without_array(var->type)) && j % 2)
73 dmask >>= 2;
74
75 dmask <<= var->data.location_frac / 2;
76
77 if (dmask & 0x1)
78 info->input_usage_mask[i] |= TGSI_WRITEMASK_XY;
79 if (dmask & 0x2)
80 info->input_usage_mask[i] |= TGSI_WRITEMASK_ZW;
81 } else {
82 info->input_usage_mask[i] |=
83 (mask << var->data.location_frac) & 0xf;
84 }
85 }
86 break;
87 }
88 default:;
89 }
90 }
91
92 static void gather_intrinsic_load_deref_output_info(const nir_shader *nir,
93 const nir_intrinsic_instr *instr,
94 nir_variable *var,
95 struct tgsi_shader_info *info)
96 {
97 assert(var && var->data.mode == nir_var_shader_out);
98
99 switch (nir->info.stage) {
100 case MESA_SHADER_TESS_CTRL:
101 if (var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
102 var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
103 info->reads_tessfactor_outputs = true;
104 else if (var->data.patch)
105 info->reads_perpatch_outputs = true;
106 else
107 info->reads_pervertex_outputs = true;
108 break;
109
110 case MESA_SHADER_FRAGMENT:
111 if (var->data.fb_fetch_output)
112 info->uses_fbfetch = true;
113 break;
114 default:;
115 }
116 }
117
118 static void gather_intrinsic_store_deref_output_info(const nir_shader *nir,
119 const nir_intrinsic_instr *instr,
120 nir_variable *var,
121 struct tgsi_shader_info *info)
122 {
123 assert(var && var->data.mode == nir_var_shader_out);
124
125 switch (nir->info.stage) {
126 case MESA_SHADER_VERTEX: /* needed by LS, ES */
127 case MESA_SHADER_TESS_EVAL: /* needed by ES */
128 case MESA_SHADER_GEOMETRY: {
129 unsigned i = var->data.driver_location;
130 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
131 unsigned mask = nir_intrinsic_write_mask(instr);
132
133 assert(!var->data.compact);
134
135 for (unsigned j = 0; j < attrib_count; j++, i++) {
136 if (glsl_type_is_64bit(glsl_without_array(var->type))) {
137 unsigned dmask = mask;
138
139 if (glsl_type_is_dual_slot(glsl_without_array(var->type)) && j % 2)
140 dmask >>= 2;
141
142 dmask <<= var->data.location_frac / 2;
143
144 if (dmask & 0x1)
145 info->output_usagemask[i] |= TGSI_WRITEMASK_XY;
146 if (dmask & 0x2)
147 info->output_usagemask[i] |= TGSI_WRITEMASK_ZW;
148 } else {
149 info->output_usagemask[i] |=
150 (mask << var->data.location_frac) & 0xf;
151 }
152
153 }
154 break;
155 }
156 default:;
157 }
158 }
159
160 static void scan_instruction(const struct nir_shader *nir,
161 struct tgsi_shader_info *info,
162 nir_instr *instr)
163 {
164 if (instr->type == nir_instr_type_alu) {
165 nir_alu_instr *alu = nir_instr_as_alu(instr);
166
167 switch (alu->op) {
168 case nir_op_fddx:
169 case nir_op_fddy:
170 case nir_op_fddx_fine:
171 case nir_op_fddy_fine:
172 case nir_op_fddx_coarse:
173 case nir_op_fddy_coarse:
174 info->uses_derivatives = true;
175 break;
176 default:
177 break;
178 }
179 } else if (instr->type == nir_instr_type_tex) {
180 nir_tex_instr *tex = nir_instr_as_tex(instr);
181 nir_variable *texture = tex_get_texture_var(tex);
182
183 if (!texture) {
184 info->samplers_declared |=
185 u_bit_consecutive(tex->sampler_index, 1);
186 } else {
187 if (texture->data.bindless)
188 info->uses_bindless_samplers = true;
189 }
190
191 switch (tex->op) {
192 case nir_texop_tex:
193 case nir_texop_txb:
194 case nir_texop_lod:
195 info->uses_derivatives = true;
196 break;
197 default:
198 break;
199 }
200 } else if (instr->type == nir_instr_type_intrinsic) {
201 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
202
203 switch (intr->intrinsic) {
204 case nir_intrinsic_load_front_face:
205 info->uses_frontface = 1;
206 break;
207 case nir_intrinsic_load_instance_id:
208 info->uses_instanceid = 1;
209 break;
210 case nir_intrinsic_load_invocation_id:
211 info->uses_invocationid = true;
212 break;
213 case nir_intrinsic_load_num_work_groups:
214 info->uses_grid_size = true;
215 break;
216 case nir_intrinsic_load_local_group_size:
217 /* The block size is translated to IMM with a fixed block size. */
218 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
219 info->uses_block_size = true;
220 break;
221 case nir_intrinsic_load_local_invocation_id:
222 case nir_intrinsic_load_work_group_id: {
223 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
224 while (mask) {
225 unsigned i = u_bit_scan(&mask);
226
227 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
228 info->uses_block_id[i] = true;
229 else
230 info->uses_thread_id[i] = true;
231 }
232 break;
233 }
234 case nir_intrinsic_load_vertex_id:
235 info->uses_vertexid = 1;
236 break;
237 case nir_intrinsic_load_vertex_id_zero_base:
238 info->uses_vertexid_nobase = 1;
239 break;
240 case nir_intrinsic_load_base_vertex:
241 info->uses_basevertex = 1;
242 break;
243 case nir_intrinsic_load_draw_id:
244 info->uses_drawid = 1;
245 break;
246 case nir_intrinsic_load_primitive_id:
247 info->uses_primid = 1;
248 break;
249 case nir_intrinsic_load_sample_mask_in:
250 info->reads_samplemask = true;
251 break;
252 case nir_intrinsic_load_tess_level_inner:
253 case nir_intrinsic_load_tess_level_outer:
254 info->reads_tess_factors = true;
255 break;
256 case nir_intrinsic_bindless_image_load:
257 info->uses_bindless_images = true;
258
259 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
260 info->uses_bindless_buffer_load = true;
261 else
262 info->uses_bindless_image_load = true;
263 break;
264 case nir_intrinsic_bindless_image_size:
265 case nir_intrinsic_bindless_image_samples:
266 info->uses_bindless_images = true;
267 break;
268 case nir_intrinsic_bindless_image_store:
269 info->uses_bindless_images = true;
270
271 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
272 info->uses_bindless_buffer_store = true;
273 else
274 info->uses_bindless_image_store = true;
275
276 info->writes_memory = true;
277 info->num_memory_instructions++; /* we only care about stores */
278 break;
279 case nir_intrinsic_image_deref_store:
280 info->writes_memory = true;
281 info->num_memory_instructions++; /* we only care about stores */
282 break;
283 case nir_intrinsic_bindless_image_atomic_add:
284 case nir_intrinsic_bindless_image_atomic_min:
285 case nir_intrinsic_bindless_image_atomic_max:
286 case nir_intrinsic_bindless_image_atomic_and:
287 case nir_intrinsic_bindless_image_atomic_or:
288 case nir_intrinsic_bindless_image_atomic_xor:
289 case nir_intrinsic_bindless_image_atomic_exchange:
290 case nir_intrinsic_bindless_image_atomic_comp_swap:
291 info->uses_bindless_images = true;
292
293 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
294 info->uses_bindless_buffer_atomic = true;
295 else
296 info->uses_bindless_image_atomic = true;
297
298 info->writes_memory = true;
299 info->num_memory_instructions++; /* we only care about stores */
300 break;
301 case nir_intrinsic_image_deref_atomic_add:
302 case nir_intrinsic_image_deref_atomic_min:
303 case nir_intrinsic_image_deref_atomic_max:
304 case nir_intrinsic_image_deref_atomic_and:
305 case nir_intrinsic_image_deref_atomic_or:
306 case nir_intrinsic_image_deref_atomic_xor:
307 case nir_intrinsic_image_deref_atomic_exchange:
308 case nir_intrinsic_image_deref_atomic_comp_swap:
309 info->writes_memory = true;
310 info->num_memory_instructions++; /* we only care about stores */
311 break;
312 case nir_intrinsic_store_ssbo:
313 case nir_intrinsic_ssbo_atomic_add:
314 case nir_intrinsic_ssbo_atomic_imin:
315 case nir_intrinsic_ssbo_atomic_umin:
316 case nir_intrinsic_ssbo_atomic_imax:
317 case nir_intrinsic_ssbo_atomic_umax:
318 case nir_intrinsic_ssbo_atomic_and:
319 case nir_intrinsic_ssbo_atomic_or:
320 case nir_intrinsic_ssbo_atomic_xor:
321 case nir_intrinsic_ssbo_atomic_exchange:
322 case nir_intrinsic_ssbo_atomic_comp_swap:
323 info->writes_memory = true;
324 info->num_memory_instructions++; /* we only care about stores */
325 break;
326 case nir_intrinsic_load_color0:
327 case nir_intrinsic_load_color1: {
328 unsigned index = intr->intrinsic == nir_intrinsic_load_color1;
329 uint8_t mask = nir_ssa_def_components_read(&intr->dest.ssa);
330 info->colors_read |= mask << (index * 4);
331 break;
332 }
333 case nir_intrinsic_load_barycentric_pixel:
334 case nir_intrinsic_load_barycentric_centroid:
335 case nir_intrinsic_load_barycentric_sample:
336 case nir_intrinsic_load_barycentric_at_offset: /* uses center */
337 case nir_intrinsic_load_barycentric_at_sample: { /* uses center */
338 unsigned mode = nir_intrinsic_interp_mode(intr);
339
340 if (mode == INTERP_MODE_FLAT)
341 break;
342
343 if (mode == INTERP_MODE_NOPERSPECTIVE) {
344 if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
345 info->uses_linear_sample = true;
346 else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
347 info->uses_linear_centroid = true;
348 else
349 info->uses_linear_center = true;
350
351 if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
352 info->uses_linear_opcode_interp_sample = true;
353 } else {
354 if (intr->intrinsic == nir_intrinsic_load_barycentric_sample)
355 info->uses_persp_sample = true;
356 else if (intr->intrinsic == nir_intrinsic_load_barycentric_centroid)
357 info->uses_persp_centroid = true;
358 else
359 info->uses_persp_center = true;
360
361 if (intr->intrinsic == nir_intrinsic_load_barycentric_at_sample)
362 info->uses_persp_opcode_interp_sample = true;
363 }
364 break;
365 }
366 case nir_intrinsic_load_deref: {
367 nir_variable *var = intrinsic_get_var(intr);
368 nir_variable_mode mode = var->data.mode;
369
370 if (mode == nir_var_shader_in) {
371 /* PS inputs use the interpolated load intrinsics. */
372 assert(nir->info.stage != MESA_SHADER_FRAGMENT);
373 gather_intrinsic_load_deref_input_info(nir, intr, var, info);
374 } else if (mode == nir_var_shader_out) {
375 gather_intrinsic_load_deref_output_info(nir, intr, var, info);
376 }
377 break;
378 }
379 case nir_intrinsic_store_deref: {
380 nir_variable *var = intrinsic_get_var(intr);
381
382 if (var->data.mode == nir_var_shader_out)
383 gather_intrinsic_store_deref_output_info(nir, intr, var, info);
384 break;
385 }
386 case nir_intrinsic_interp_deref_at_centroid:
387 case nir_intrinsic_interp_deref_at_sample:
388 case nir_intrinsic_interp_deref_at_offset:
389 unreachable("interp opcodes should have been lowered");
390 break;
391 default:
392 break;
393 }
394 }
395 }
396
397 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
398 struct tgsi_tessctrl_info *out)
399 {
400 memset(out, 0, sizeof(*out));
401
402 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
403 return;
404
405 out->tessfactors_are_def_in_all_invocs =
406 ac_are_tessfactors_def_in_all_invocs(nir);
407 }
408
409 void si_nir_scan_shader(const struct nir_shader *nir,
410 struct tgsi_shader_info *info)
411 {
412 nir_function *func;
413 unsigned i;
414
415 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
416 info->num_tokens = 2; /* indicate that the shader is non-empty */
417 info->num_instructions = 2;
418
419 info->properties[TGSI_PROPERTY_NEXT_SHADER] =
420 pipe_shader_type_from_mesa(nir->info.next_stage);
421
422 if (nir->info.stage == MESA_SHADER_VERTEX) {
423 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
424 nir->info.vs.window_space_position;
425 }
426
427 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
428 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
429 nir->info.tess.tcs_vertices_out;
430 }
431
432 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
433 if (nir->info.tess.primitive_mode == GL_ISOLINES)
434 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
435 else
436 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
437
438 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
439 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
440 PIPE_TESS_SPACING_FRACTIONAL_ODD);
441 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
442 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
443
444 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
445 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
446 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
447 }
448
449 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
450 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
451 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
452 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
453 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
454 }
455
456 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
457 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
458 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
459 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
460
461 if (nir->info.fs.pixel_center_integer) {
462 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
463 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
464 }
465
466 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
467 switch (nir->info.fs.depth_layout) {
468 case FRAG_DEPTH_LAYOUT_ANY:
469 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
470 break;
471 case FRAG_DEPTH_LAYOUT_GREATER:
472 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
473 break;
474 case FRAG_DEPTH_LAYOUT_LESS:
475 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
476 break;
477 case FRAG_DEPTH_LAYOUT_UNCHANGED:
478 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
479 break;
480 default:
481 unreachable("Unknow depth layout");
482 }
483 }
484 }
485
486 if (gl_shader_stage_is_compute(nir->info.stage)) {
487 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
488 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
489 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
490 }
491
492 i = 0;
493 uint64_t processed_inputs = 0;
494 unsigned num_inputs = 0;
495 nir_foreach_variable(variable, &nir->inputs) {
496 unsigned semantic_name, semantic_index;
497
498 const struct glsl_type *type = variable->type;
499 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
500 assert(glsl_type_is_array(type));
501 type = glsl_get_array_element(type);
502 }
503
504 unsigned attrib_count = glsl_count_attribute_slots(type,
505 nir->info.stage == MESA_SHADER_VERTEX);
506
507 i = variable->data.driver_location;
508
509 /* Vertex shader inputs don't have semantics. The state
510 * tracker has already mapped them to attributes via
511 * variable->data.driver_location.
512 */
513 if (nir->info.stage == MESA_SHADER_VERTEX) {
514 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)))
515 num_inputs++;
516
517 num_inputs++;
518 continue;
519 }
520
521 for (unsigned j = 0; j < attrib_count; j++, i++) {
522
523 if (processed_inputs & ((uint64_t)1 << i))
524 continue;
525
526 processed_inputs |= ((uint64_t)1 << i);
527 num_inputs++;
528
529 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
530 &semantic_name, &semantic_index);
531
532 info->input_semantic_name[i] = semantic_name;
533 info->input_semantic_index[i] = semantic_index;
534
535 if (semantic_name == TGSI_SEMANTIC_PRIMID)
536 info->uses_primid = true;
537
538 if (semantic_name == TGSI_SEMANTIC_COLOR) {
539 /* We only need this for color inputs. */
540 if (variable->data.sample)
541 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
542 else if (variable->data.centroid)
543 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
544 else
545 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
546 }
547
548 enum glsl_base_type base_type =
549 glsl_get_base_type(glsl_without_array(variable->type));
550
551 switch (variable->data.interpolation) {
552 case INTERP_MODE_NONE:
553 if (glsl_base_type_is_integer(base_type)) {
554 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
555 break;
556 }
557
558 if (semantic_name == TGSI_SEMANTIC_COLOR) {
559 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
560 break;
561 }
562 /* fall-through */
563
564 case INTERP_MODE_SMOOTH:
565 assert(!glsl_base_type_is_integer(base_type));
566
567 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
568 break;
569
570 case INTERP_MODE_NOPERSPECTIVE:
571 assert(!glsl_base_type_is_integer(base_type));
572
573 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
574 break;
575
576 case INTERP_MODE_FLAT:
577 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
578 break;
579 }
580 }
581 }
582
583 info->num_inputs = num_inputs;
584
585 i = 0;
586 uint64_t processed_outputs = 0;
587 unsigned num_outputs = 0;
588 nir_foreach_variable(variable, &nir->outputs) {
589 unsigned semantic_name, semantic_index;
590
591 i = variable->data.driver_location;
592
593 const struct glsl_type *type = variable->type;
594 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
595 assert(glsl_type_is_array(type));
596 type = glsl_get_array_element(type);
597 }
598
599 unsigned attrib_count = glsl_count_attribute_slots(type, false);
600 for (unsigned k = 0; k < attrib_count; k++, i++) {
601
602 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
603 tgsi_get_gl_frag_result_semantic(variable->data.location + k,
604 &semantic_name, &semantic_index);
605
606 /* Adjust for dual source blending */
607 if (variable->data.index > 0) {
608 semantic_index++;
609 }
610 } else {
611 tgsi_get_gl_varying_semantic(variable->data.location + k, true,
612 &semantic_name, &semantic_index);
613 }
614
615 unsigned num_components = 4;
616 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
617 if (vector_elements)
618 num_components = vector_elements;
619
620 unsigned component = variable->data.location_frac;
621 if (glsl_type_is_64bit(glsl_without_array(variable->type))) {
622 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)) && k % 2) {
623 num_components = (num_components * 2) - 4;
624 component = 0;
625 } else {
626 num_components = MIN2(num_components * 2, 4);
627 }
628 }
629
630 ubyte usagemask = 0;
631 for (unsigned j = component; j < num_components + component; j++) {
632 switch (j) {
633 case 0:
634 usagemask |= TGSI_WRITEMASK_X;
635 break;
636 case 1:
637 usagemask |= TGSI_WRITEMASK_Y;
638 break;
639 case 2:
640 usagemask |= TGSI_WRITEMASK_Z;
641 break;
642 case 3:
643 usagemask |= TGSI_WRITEMASK_W;
644 break;
645 default:
646 unreachable("error calculating component index");
647 }
648 }
649
650 unsigned gs_out_streams;
651 if (variable->data.stream & (1u << 31)) {
652 gs_out_streams = variable->data.stream & ~(1u << 31);
653 } else {
654 assert(variable->data.stream < 4);
655 gs_out_streams = 0;
656 for (unsigned j = 0; j < num_components; ++j)
657 gs_out_streams |= variable->data.stream << (2 * (component + j));
658 }
659
660 unsigned streamx = gs_out_streams & 3;
661 unsigned streamy = (gs_out_streams >> 2) & 3;
662 unsigned streamz = (gs_out_streams >> 4) & 3;
663 unsigned streamw = (gs_out_streams >> 6) & 3;
664
665 if (usagemask & TGSI_WRITEMASK_X) {
666 info->output_streams[i] |= streamx;
667 info->num_stream_output_components[streamx]++;
668 }
669 if (usagemask & TGSI_WRITEMASK_Y) {
670 info->output_streams[i] |= streamy << 2;
671 info->num_stream_output_components[streamy]++;
672 }
673 if (usagemask & TGSI_WRITEMASK_Z) {
674 info->output_streams[i] |= streamz << 4;
675 info->num_stream_output_components[streamz]++;
676 }
677 if (usagemask & TGSI_WRITEMASK_W) {
678 info->output_streams[i] |= streamw << 6;
679 info->num_stream_output_components[streamw]++;
680 }
681
682 /* make sure we only count this location once against
683 * the num_outputs counter.
684 */
685 if (processed_outputs & ((uint64_t)1 << i))
686 continue;
687
688 processed_outputs |= ((uint64_t)1 << i);
689 num_outputs++;
690
691 info->output_semantic_name[i] = semantic_name;
692 info->output_semantic_index[i] = semantic_index;
693
694 switch (semantic_name) {
695 case TGSI_SEMANTIC_PRIMID:
696 info->writes_primid = true;
697 break;
698 case TGSI_SEMANTIC_VIEWPORT_INDEX:
699 info->writes_viewport_index = true;
700 break;
701 case TGSI_SEMANTIC_LAYER:
702 info->writes_layer = true;
703 break;
704 case TGSI_SEMANTIC_PSIZE:
705 info->writes_psize = true;
706 break;
707 case TGSI_SEMANTIC_CLIPVERTEX:
708 info->writes_clipvertex = true;
709 break;
710 case TGSI_SEMANTIC_COLOR:
711 info->colors_written |= 1 << semantic_index;
712 break;
713 case TGSI_SEMANTIC_STENCIL:
714 info->writes_stencil = true;
715 break;
716 case TGSI_SEMANTIC_SAMPLEMASK:
717 info->writes_samplemask = true;
718 break;
719 case TGSI_SEMANTIC_EDGEFLAG:
720 info->writes_edgeflag = true;
721 break;
722 case TGSI_SEMANTIC_POSITION:
723 if (info->processor == PIPE_SHADER_FRAGMENT)
724 info->writes_z = true;
725 else
726 info->writes_position = true;
727 break;
728 }
729 }
730
731 unsigned loc = variable->data.location;
732 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
733 loc == FRAG_RESULT_COLOR &&
734 nir->info.outputs_written & (1ull << loc)) {
735 assert(attrib_count == 1);
736 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
737 }
738 }
739
740 info->num_outputs = num_outputs;
741
742 struct set *ubo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
743 _mesa_key_pointer_equal);
744 struct set *ssbo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
745 _mesa_key_pointer_equal);
746
747 /* Intialise const_file_max[0] */
748 info->const_file_max[0] = -1;
749
750 /* The first 8 are reserved for atomic counters using ssbo */
751 unsigned ssbo_idx = 8;
752
753 unsigned ubo_idx = 1;
754 nir_foreach_variable(variable, &nir->uniforms) {
755 const struct glsl_type *type = variable->type;
756 enum glsl_base_type base_type =
757 glsl_get_base_type(glsl_without_array(type));
758 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
759 unsigned loc = variable->data.driver_location / 4;
760 int slot_count = glsl_count_attribute_slots(type, false);
761 int max_slot = MAX2(info->const_file_max[0], (int) loc) + slot_count;
762
763 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
764 * really use the mask (other than ubo_idx == 1 for regular
765 * uniforms) its really only used for getting the buffer count
766 * so we don't need to worry about the ordering.
767 */
768 if (variable->interface_type != NULL) {
769 if (variable->data.mode == nir_var_uniform ||
770 variable->data.mode == nir_var_mem_ubo ||
771 variable->data.mode == nir_var_mem_ssbo) {
772
773 struct set *buf_set = variable->data.mode == nir_var_mem_ssbo ?
774 ssbo_set : ubo_set;
775
776 unsigned block_count;
777 if (base_type != GLSL_TYPE_INTERFACE) {
778 struct set_entry *entry =
779 _mesa_set_search(buf_set, variable->interface_type);
780
781 /* Check if we have already processed
782 * a member from this ubo.
783 */
784 if (entry)
785 continue;
786
787 block_count = 1;
788 } else {
789 block_count = aoa_size;
790 }
791
792 if (variable->data.mode == nir_var_uniform ||
793 variable->data.mode == nir_var_mem_ubo) {
794 info->const_buffers_declared |= u_bit_consecutive(ubo_idx, block_count);
795 ubo_idx += block_count;
796 } else {
797 assert(variable->data.mode == nir_var_mem_ssbo);
798
799 info->shader_buffers_declared |= u_bit_consecutive(ssbo_idx, block_count);
800 ssbo_idx += block_count;
801 }
802
803 _mesa_set_add(buf_set, variable->interface_type);
804 }
805
806 continue;
807 }
808
809 /* We rely on the fact that nir_lower_samplers_as_deref has
810 * eliminated struct dereferences.
811 */
812 if (base_type == GLSL_TYPE_SAMPLER && !variable->data.bindless) {
813 info->samplers_declared |=
814 u_bit_consecutive(variable->data.binding, aoa_size);
815 } else if (base_type == GLSL_TYPE_IMAGE && !variable->data.bindless) {
816 info->images_declared |=
817 u_bit_consecutive(variable->data.binding, aoa_size);
818 } else if (base_type != GLSL_TYPE_ATOMIC_UINT) {
819 info->const_buffers_declared |= 1;
820 info->const_file_max[0] = max_slot;
821 }
822 }
823
824 _mesa_set_destroy(ubo_set, NULL);
825 _mesa_set_destroy(ssbo_set, NULL);
826
827 info->num_written_clipdistance = nir->info.clip_distance_array_size;
828 info->num_written_culldistance = nir->info.cull_distance_array_size;
829 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
830 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
831
832 if (info->processor == PIPE_SHADER_FRAGMENT)
833 info->uses_kill = nir->info.fs.uses_discard;
834
835 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
836 nir_foreach_block(block, func->impl) {
837 nir_foreach_instr(instr, block)
838 scan_instruction(nir, info, instr);
839 }
840 }
841
842 void
843 si_nir_opts(struct nir_shader *nir)
844 {
845 bool progress;
846 unsigned lower_flrp =
847 (nir->options->lower_flrp16 ? 16 : 0) |
848 (nir->options->lower_flrp32 ? 32 : 0) |
849 (nir->options->lower_flrp64 ? 64 : 0);
850
851 do {
852 progress = false;
853
854 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
855
856 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
857 NIR_PASS(progress, nir, nir_opt_dead_write_vars);
858
859 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL);
860 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
861
862 /* (Constant) copy propagation is needed for txf with offsets. */
863 NIR_PASS(progress, nir, nir_copy_prop);
864 NIR_PASS(progress, nir, nir_opt_remove_phis);
865 NIR_PASS(progress, nir, nir_opt_dce);
866 if (nir_opt_trivial_continues(nir)) {
867 progress = true;
868 NIR_PASS(progress, nir, nir_copy_prop);
869 NIR_PASS(progress, nir, nir_opt_dce);
870 }
871 NIR_PASS(progress, nir, nir_opt_if, true);
872 NIR_PASS(progress, nir, nir_opt_dead_cf);
873 NIR_PASS(progress, nir, nir_opt_cse);
874 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
875
876 /* Needed for algebraic lowering */
877 NIR_PASS(progress, nir, nir_opt_algebraic);
878 NIR_PASS(progress, nir, nir_opt_constant_folding);
879
880 if (lower_flrp != 0) {
881 bool lower_flrp_progress = false;
882
883 NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp,
884 lower_flrp,
885 false /* always_precise */,
886 nir->options->lower_ffma);
887 if (lower_flrp_progress) {
888 NIR_PASS(progress, nir,
889 nir_opt_constant_folding);
890 progress = true;
891 }
892
893 /* Nothing should rematerialize any flrps, so we only
894 * need to do this lowering once.
895 */
896 lower_flrp = 0;
897 }
898
899 NIR_PASS(progress, nir, nir_opt_undef);
900 NIR_PASS(progress, nir, nir_opt_conditional_discard);
901 if (nir->options->max_unroll_iterations) {
902 NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
903 }
904 } while (progress);
905 }
906
907 static int
908 type_size_vec4(const struct glsl_type *type, bool bindless)
909 {
910 return glsl_count_attribute_slots(type, false);
911 }
912
913 static void
914 si_nir_lower_color(nir_shader *nir)
915 {
916 nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
917
918 nir_builder b;
919 nir_builder_init(&b, entrypoint);
920
921 nir_foreach_block(block, entrypoint) {
922 nir_foreach_instr_safe(instr, block) {
923 if (instr->type != nir_instr_type_intrinsic)
924 continue;
925
926 nir_intrinsic_instr *intrin =
927 nir_instr_as_intrinsic(instr);
928
929 if (intrin->intrinsic != nir_intrinsic_load_deref)
930 continue;
931
932 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
933 if (deref->mode != nir_var_shader_in)
934 continue;
935
936 b.cursor = nir_before_instr(instr);
937 nir_variable *var = nir_deref_instr_get_variable(deref);
938 nir_ssa_def *def;
939
940 if (var->data.location == VARYING_SLOT_COL0) {
941 def = nir_load_color0(&b);
942 } else if (var->data.location == VARYING_SLOT_COL1) {
943 def = nir_load_color1(&b);
944 } else {
945 continue;
946 }
947
948 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(def));
949 nir_instr_remove(instr);
950 }
951 }
952 }
953
954 void si_nir_lower_ps_inputs(struct nir_shader *nir)
955 {
956 if (nir->info.stage != MESA_SHADER_FRAGMENT)
957 return;
958
959 NIR_PASS_V(nir, nir_lower_io_to_temporaries,
960 nir_shader_get_entrypoint(nir), false, true);
961
962 /* Since we're doing nir_lower_io_to_temporaries late, we need
963 * to lower all the copy_deref's introduced by
964 * lower_io_to_temporaries before calling nir_lower_io.
965 */
966 NIR_PASS_V(nir, nir_split_var_copies);
967 NIR_PASS_V(nir, nir_lower_var_copies);
968 NIR_PASS_V(nir, nir_lower_global_vars_to_local);
969
970 si_nir_lower_color(nir);
971 NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
972
973 /* This pass needs actual constants */
974 NIR_PASS_V(nir, nir_opt_constant_folding);
975 NIR_PASS_V(nir, nir_io_add_const_offset_to_base,
976 nir_var_shader_in);
977 }
978
979 /**
980 * Perform "lowering" operations on the NIR that are run once when the shader
981 * selector is created.
982 */
983 void
984 si_lower_nir(struct si_shader_selector* sel, unsigned wave_size)
985 {
986 /* Adjust the driver location of inputs and outputs. The state tracker
987 * interprets them as slots, while the ac/nir backend interprets them
988 * as individual components.
989 */
990 if (sel->nir->info.stage != MESA_SHADER_FRAGMENT) {
991 nir_foreach_variable(variable, &sel->nir->inputs)
992 variable->data.driver_location *= 4;
993 }
994
995 nir_foreach_variable(variable, &sel->nir->outputs) {
996 variable->data.driver_location *= 4;
997
998 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
999 if (variable->data.location == FRAG_RESULT_DEPTH)
1000 variable->data.driver_location += 2;
1001 else if (variable->data.location == FRAG_RESULT_STENCIL)
1002 variable->data.driver_location += 1;
1003 }
1004 }
1005
1006 /* Perform lowerings (and optimizations) of code.
1007 *
1008 * Performance considerations aside, we must:
1009 * - lower certain ALU operations
1010 * - ensure constant offsets for texture instructions are folded
1011 * and copy-propagated
1012 */
1013
1014 static const struct nir_lower_tex_options lower_tex_options = {
1015 .lower_txp = ~0u,
1016 };
1017 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
1018
1019 const nir_lower_subgroups_options subgroups_options = {
1020 .subgroup_size = wave_size,
1021 .ballot_bit_size = wave_size,
1022 .lower_to_scalar = true,
1023 .lower_subgroup_masks = true,
1024 .lower_vote_trivial = false,
1025 .lower_vote_eq_to_ballot = true,
1026 };
1027 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
1028
1029 ac_lower_indirect_derefs(sel->nir, sel->screen->info.chip_class);
1030
1031 si_nir_opts(sel->nir);
1032
1033 NIR_PASS_V(sel->nir, nir_lower_bool_to_int32);
1034
1035 /* Strip the resulting shader so that the shader cache is more likely
1036 * to hit from other similar shaders.
1037 */
1038 nir_strip(sel->nir);
1039 }
1040
1041 static void declare_nir_input_vs(struct si_shader_context *ctx,
1042 struct nir_variable *variable,
1043 unsigned input_index,
1044 LLVMValueRef out[4])
1045 {
1046 si_llvm_load_input_vs(ctx, input_index, out);
1047 }
1048
1049 LLVMValueRef
1050 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
1051 enum glsl_interp_mode interp, unsigned location)
1052 {
1053 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1054 int interp_param_idx = -1;
1055
1056 switch (interp) {
1057 case INTERP_MODE_FLAT:
1058 return NULL;
1059 case INTERP_MODE_SMOOTH:
1060 case INTERP_MODE_NONE:
1061 if (location == INTERP_CENTER)
1062 interp_param_idx = SI_PARAM_PERSP_CENTER;
1063 else if (location == INTERP_CENTROID)
1064 interp_param_idx = SI_PARAM_PERSP_CENTROID;
1065 else if (location == INTERP_SAMPLE)
1066 interp_param_idx = SI_PARAM_PERSP_SAMPLE;
1067 break;
1068 case INTERP_MODE_NOPERSPECTIVE:
1069 if (location == INTERP_CENTER)
1070 interp_param_idx = SI_PARAM_LINEAR_CENTER;
1071 else if (location == INTERP_CENTROID)
1072 interp_param_idx = SI_PARAM_LINEAR_CENTROID;
1073 else if (location == INTERP_SAMPLE)
1074 interp_param_idx = SI_PARAM_LINEAR_SAMPLE;
1075 break;
1076 default:
1077 assert(!"Unhandled interpolation mode.");
1078 return NULL;
1079 }
1080
1081 return interp_param_idx != -1 ?
1082 LLVMGetParam(ctx->main_fn, interp_param_idx) : NULL;
1083 }
1084
1085 static LLVMValueRef
1086 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
1087 unsigned descriptor_set, unsigned base_index,
1088 unsigned constant_index, LLVMValueRef dynamic_index,
1089 enum ac_descriptor_type desc_type, bool image,
1090 bool write, bool bindless)
1091 {
1092 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1093 LLVMBuilderRef builder = ctx->ac.builder;
1094 unsigned const_index = base_index + constant_index;
1095
1096 assert(!descriptor_set);
1097 assert(!image || desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
1098
1099 if (bindless) {
1100 LLVMValueRef list =
1101 LLVMGetParam(ctx->main_fn, ctx->param_bindless_samplers_and_images);
1102
1103 /* dynamic_index is the bindless handle */
1104 if (image) {
1105 /* For simplicity, bindless image descriptors use fixed
1106 * 16-dword slots for now.
1107 */
1108 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1109 LLVMConstInt(ctx->i64, 2, 0), "");
1110
1111 return si_load_image_desc(ctx, list, dynamic_index, desc_type,
1112 write, true);
1113 }
1114
1115 /* Since bindless handle arithmetic can contain an unsigned integer
1116 * wraparound and si_load_sampler_desc assumes there isn't any,
1117 * use GEP without "inbounds" (inside ac_build_pointer_add)
1118 * to prevent incorrect code generation and hangs.
1119 */
1120 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1121 LLVMConstInt(ctx->i64, 2, 0), "");
1122 list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
1123 return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
1124 }
1125
1126 unsigned num_slots = image ? ctx->num_images : ctx->num_samplers;
1127 assert(const_index < num_slots);
1128
1129 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1130 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, const_index, false);
1131
1132 if (dynamic_index) {
1133 index = LLVMBuildAdd(builder, index, dynamic_index, "");
1134
1135 /* From the GL_ARB_shader_image_load_store extension spec:
1136 *
1137 * If a shader performs an image load, store, or atomic
1138 * operation using an image variable declared as an array,
1139 * and if the index used to select an individual element is
1140 * negative or greater than or equal to the size of the
1141 * array, the results of the operation are undefined but may
1142 * not lead to termination.
1143 */
1144 index = si_llvm_bound_index(ctx, index, num_slots);
1145 }
1146
1147 if (image) {
1148 index = LLVMBuildSub(ctx->ac.builder,
1149 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
1150 index, "");
1151 return si_load_image_desc(ctx, list, index, desc_type, write, false);
1152 }
1153
1154 index = LLVMBuildAdd(ctx->ac.builder, index,
1155 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1156 return si_load_sampler_desc(ctx, list, index, desc_type);
1157 }
1158
1159 static void bitcast_inputs(struct si_shader_context *ctx,
1160 LLVMValueRef data[4],
1161 unsigned input_idx)
1162 {
1163 for (unsigned chan = 0; chan < 4; chan++) {
1164 ctx->inputs[input_idx + chan] =
1165 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
1166 }
1167 }
1168
1169 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
1170 {
1171 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1172
1173 if (nir->info.stage == MESA_SHADER_VERTEX) {
1174 uint64_t processed_inputs = 0;
1175 nir_foreach_variable(variable, &nir->inputs) {
1176 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
1177 true);
1178 unsigned input_idx = variable->data.driver_location;
1179
1180 LLVMValueRef data[4];
1181 unsigned loc = variable->data.location;
1182
1183 for (unsigned i = 0; i < attrib_count; i++) {
1184 /* Packed components share the same location so skip
1185 * them if we have already processed the location.
1186 */
1187 if (processed_inputs & ((uint64_t)1 << (loc + i))) {
1188 input_idx += 4;
1189 continue;
1190 }
1191
1192 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1193 bitcast_inputs(ctx, data, input_idx);
1194 if (glsl_type_is_dual_slot(variable->type)) {
1195 input_idx += 4;
1196 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1197 bitcast_inputs(ctx, data, input_idx);
1198 }
1199
1200 processed_inputs |= ((uint64_t)1 << (loc + i));
1201 input_idx += 4;
1202 }
1203 }
1204 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1205 unsigned colors_read =
1206 ctx->shader->selector->info.colors_read;
1207 LLVMValueRef main_fn = ctx->main_fn;
1208
1209 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1210
1211 unsigned offset = SI_PARAM_POS_FIXED_PT + 1;
1212
1213 if (colors_read & 0x0f) {
1214 unsigned mask = colors_read & 0x0f;
1215 LLVMValueRef values[4];
1216 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1217 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1218 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1219 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1220 ctx->abi.color0 =
1221 ac_to_integer(&ctx->ac,
1222 ac_build_gather_values(&ctx->ac, values, 4));
1223 }
1224 if (colors_read & 0xf0) {
1225 unsigned mask = (colors_read & 0xf0) >> 4;
1226 LLVMValueRef values[4];
1227 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1228 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1229 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1230 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1231 ctx->abi.color1 =
1232 ac_to_integer(&ctx->ac,
1233 ac_build_gather_values(&ctx->ac, values, 4));
1234 }
1235
1236 ctx->abi.interp_at_sample_force_center =
1237 ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center;
1238 }
1239
1240 ctx->abi.inputs = &ctx->inputs[0];
1241 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
1242 ctx->abi.clamp_shadow_reference = true;
1243 ctx->abi.robust_buffer_access = true;
1244
1245 ctx->num_samplers = util_last_bit(info->samplers_declared);
1246 ctx->num_images = util_last_bit(info->images_declared);
1247
1248 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
1249 assert(gl_shader_stage_is_compute(nir->info.stage));
1250 si_declare_compute_memory(ctx);
1251 }
1252 ac_nir_translate(&ctx->ac, &ctx->abi, nir);
1253
1254 return true;
1255 }