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radeonsi/gfx10: enable image stores with DCC
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 #include "tgsi/tgsi_from_mesa.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34 #include "compiler/nir/nir_builder.h"
35
36 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
37 {
38 for (unsigned i = 0; i < instr->num_srcs; i++) {
39 switch (instr->src[i].src_type) {
40 case nir_tex_src_texture_deref:
41 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
42 default:
43 break;
44 }
45 }
46
47 return NULL;
48 }
49
50 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
51 {
52 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
53 }
54
55 static void gather_intrinsic_load_deref_info(const nir_shader *nir,
56 const nir_intrinsic_instr *instr,
57 nir_variable *var,
58 struct tgsi_shader_info *info)
59 {
60 assert(var && var->data.mode == nir_var_shader_in);
61
62 switch (nir->info.stage) {
63 case MESA_SHADER_VERTEX: {
64 unsigned i = var->data.driver_location;
65 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
66
67 for (unsigned j = 0; j < attrib_count; j++, i++) {
68 if (glsl_type_is_64bit(glsl_without_array(var->type))) {
69 /* TODO: set usage mask more accurately for doubles */
70 info->input_usage_mask[i] = TGSI_WRITEMASK_XYZW;
71 } else {
72 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
73 info->input_usage_mask[i] |= mask << var->data.location_frac;
74 }
75 }
76 break;
77 }
78 default: {
79 unsigned semantic_name, semantic_index;
80 tgsi_get_gl_varying_semantic(var->data.location, true,
81 &semantic_name, &semantic_index);
82
83 if (semantic_name == TGSI_SEMANTIC_COLOR) {
84 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
85 info->colors_read |= mask << (semantic_index * 4);
86 }
87 break;
88 }
89 }
90 }
91
92 static void scan_instruction(const struct nir_shader *nir,
93 struct tgsi_shader_info *info,
94 nir_instr *instr)
95 {
96 if (instr->type == nir_instr_type_alu) {
97 nir_alu_instr *alu = nir_instr_as_alu(instr);
98
99 switch (alu->op) {
100 case nir_op_fddx:
101 case nir_op_fddy:
102 case nir_op_fddx_fine:
103 case nir_op_fddy_fine:
104 case nir_op_fddx_coarse:
105 case nir_op_fddy_coarse:
106 info->uses_derivatives = true;
107 break;
108 default:
109 break;
110 }
111 } else if (instr->type == nir_instr_type_tex) {
112 nir_tex_instr *tex = nir_instr_as_tex(instr);
113 nir_variable *texture = tex_get_texture_var(tex);
114
115 if (!texture) {
116 info->samplers_declared |=
117 u_bit_consecutive(tex->sampler_index, 1);
118 } else {
119 if (texture->data.bindless)
120 info->uses_bindless_samplers = true;
121 }
122
123 switch (tex->op) {
124 case nir_texop_tex:
125 case nir_texop_txb:
126 case nir_texop_lod:
127 info->uses_derivatives = true;
128 break;
129 default:
130 break;
131 }
132 } else if (instr->type == nir_instr_type_intrinsic) {
133 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
134
135 switch (intr->intrinsic) {
136 case nir_intrinsic_load_front_face:
137 info->uses_frontface = 1;
138 break;
139 case nir_intrinsic_load_instance_id:
140 info->uses_instanceid = 1;
141 break;
142 case nir_intrinsic_load_invocation_id:
143 info->uses_invocationid = true;
144 break;
145 case nir_intrinsic_load_num_work_groups:
146 info->uses_grid_size = true;
147 break;
148 case nir_intrinsic_load_local_group_size:
149 /* The block size is translated to IMM with a fixed block size. */
150 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
151 info->uses_block_size = true;
152 break;
153 case nir_intrinsic_load_local_invocation_id:
154 case nir_intrinsic_load_work_group_id: {
155 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
156 while (mask) {
157 unsigned i = u_bit_scan(&mask);
158
159 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
160 info->uses_block_id[i] = true;
161 else
162 info->uses_thread_id[i] = true;
163 }
164 break;
165 }
166 case nir_intrinsic_load_vertex_id:
167 info->uses_vertexid = 1;
168 break;
169 case nir_intrinsic_load_vertex_id_zero_base:
170 info->uses_vertexid_nobase = 1;
171 break;
172 case nir_intrinsic_load_base_vertex:
173 info->uses_basevertex = 1;
174 break;
175 case nir_intrinsic_load_draw_id:
176 info->uses_drawid = 1;
177 break;
178 case nir_intrinsic_load_primitive_id:
179 info->uses_primid = 1;
180 break;
181 case nir_intrinsic_load_sample_mask_in:
182 info->reads_samplemask = true;
183 break;
184 case nir_intrinsic_load_tess_level_inner:
185 case nir_intrinsic_load_tess_level_outer:
186 info->reads_tess_factors = true;
187 break;
188 case nir_intrinsic_bindless_image_load:
189 info->uses_bindless_images = true;
190
191 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
192 info->uses_bindless_buffer_load = true;
193 else
194 info->uses_bindless_image_load = true;
195 break;
196 case nir_intrinsic_bindless_image_size:
197 case nir_intrinsic_bindless_image_samples:
198 info->uses_bindless_images = true;
199 break;
200 case nir_intrinsic_bindless_image_store:
201 info->uses_bindless_images = true;
202
203 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
204 info->uses_bindless_buffer_store = true;
205 else
206 info->uses_bindless_image_store = true;
207
208 info->writes_memory = true;
209 break;
210 case nir_intrinsic_image_deref_store:
211 info->writes_memory = true;
212 break;
213 case nir_intrinsic_bindless_image_atomic_add:
214 case nir_intrinsic_bindless_image_atomic_min:
215 case nir_intrinsic_bindless_image_atomic_max:
216 case nir_intrinsic_bindless_image_atomic_and:
217 case nir_intrinsic_bindless_image_atomic_or:
218 case nir_intrinsic_bindless_image_atomic_xor:
219 case nir_intrinsic_bindless_image_atomic_exchange:
220 case nir_intrinsic_bindless_image_atomic_comp_swap:
221 info->uses_bindless_images = true;
222
223 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
224 info->uses_bindless_buffer_atomic = true;
225 else
226 info->uses_bindless_image_atomic = true;
227
228 info->writes_memory = true;
229 break;
230 case nir_intrinsic_image_deref_atomic_add:
231 case nir_intrinsic_image_deref_atomic_min:
232 case nir_intrinsic_image_deref_atomic_max:
233 case nir_intrinsic_image_deref_atomic_and:
234 case nir_intrinsic_image_deref_atomic_or:
235 case nir_intrinsic_image_deref_atomic_xor:
236 case nir_intrinsic_image_deref_atomic_exchange:
237 case nir_intrinsic_image_deref_atomic_comp_swap:
238 info->writes_memory = true;
239 break;
240 case nir_intrinsic_store_ssbo:
241 case nir_intrinsic_ssbo_atomic_add:
242 case nir_intrinsic_ssbo_atomic_imin:
243 case nir_intrinsic_ssbo_atomic_umin:
244 case nir_intrinsic_ssbo_atomic_imax:
245 case nir_intrinsic_ssbo_atomic_umax:
246 case nir_intrinsic_ssbo_atomic_and:
247 case nir_intrinsic_ssbo_atomic_or:
248 case nir_intrinsic_ssbo_atomic_xor:
249 case nir_intrinsic_ssbo_atomic_exchange:
250 case nir_intrinsic_ssbo_atomic_comp_swap:
251 info->writes_memory = true;
252 break;
253 case nir_intrinsic_load_deref: {
254 nir_variable *var = intrinsic_get_var(intr);
255 nir_variable_mode mode = var->data.mode;
256 enum glsl_base_type base_type =
257 glsl_get_base_type(glsl_without_array(var->type));
258
259 if (mode == nir_var_shader_in) {
260 gather_intrinsic_load_deref_info(nir, intr, var, info);
261
262 switch (var->data.interpolation) {
263 case INTERP_MODE_NONE:
264 if (glsl_base_type_is_integer(base_type))
265 break;
266
267 /* fall-through */
268 case INTERP_MODE_SMOOTH:
269 if (var->data.sample)
270 info->uses_persp_sample = true;
271 else if (var->data.centroid)
272 info->uses_persp_centroid = true;
273 else
274 info->uses_persp_center = true;
275 break;
276
277 case INTERP_MODE_NOPERSPECTIVE:
278 if (var->data.sample)
279 info->uses_linear_sample = true;
280 else if (var->data.centroid)
281 info->uses_linear_centroid = true;
282 else
283 info->uses_linear_center = true;
284 break;
285 }
286 }
287 break;
288 }
289 case nir_intrinsic_interp_deref_at_centroid:
290 case nir_intrinsic_interp_deref_at_sample:
291 case nir_intrinsic_interp_deref_at_offset: {
292 enum glsl_interp_mode interp = intrinsic_get_var(intr)->data.interpolation;
293 switch (interp) {
294 case INTERP_MODE_SMOOTH:
295 case INTERP_MODE_NONE:
296 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
297 info->uses_persp_opcode_interp_centroid = true;
298 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
299 info->uses_persp_opcode_interp_sample = true;
300 else
301 info->uses_persp_opcode_interp_offset = true;
302 break;
303 case INTERP_MODE_NOPERSPECTIVE:
304 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
305 info->uses_linear_opcode_interp_centroid = true;
306 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
307 info->uses_linear_opcode_interp_sample = true;
308 else
309 info->uses_linear_opcode_interp_offset = true;
310 break;
311 case INTERP_MODE_FLAT:
312 break;
313 default:
314 unreachable("Unsupported interpoation type");
315 }
316 break;
317 }
318 default:
319 break;
320 }
321 }
322 }
323
324 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
325 struct tgsi_tessctrl_info *out)
326 {
327 memset(out, 0, sizeof(*out));
328
329 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
330 return;
331
332 out->tessfactors_are_def_in_all_invocs =
333 ac_are_tessfactors_def_in_all_invocs(nir);
334 }
335
336 void si_nir_scan_shader(const struct nir_shader *nir,
337 struct tgsi_shader_info *info)
338 {
339 nir_function *func;
340 unsigned i;
341
342 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
343 info->num_tokens = 2; /* indicate that the shader is non-empty */
344 info->num_instructions = 2;
345
346 info->properties[TGSI_PROPERTY_NEXT_SHADER] =
347 pipe_shader_type_from_mesa(nir->info.next_stage);
348
349 if (nir->info.stage == MESA_SHADER_VERTEX) {
350 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
351 nir->info.vs.window_space_position;
352 }
353
354 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
355 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
356 nir->info.tess.tcs_vertices_out;
357 }
358
359 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
360 if (nir->info.tess.primitive_mode == GL_ISOLINES)
361 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
362 else
363 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
364
365 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
366 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
367 PIPE_TESS_SPACING_FRACTIONAL_ODD);
368 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
369 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
370
371 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
372 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
373 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
374 }
375
376 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
377 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
378 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
379 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
380 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
381 }
382
383 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
384 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
385 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
386 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
387
388 if (nir->info.fs.pixel_center_integer) {
389 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
390 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
391 }
392
393 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
394 switch (nir->info.fs.depth_layout) {
395 case FRAG_DEPTH_LAYOUT_ANY:
396 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
397 break;
398 case FRAG_DEPTH_LAYOUT_GREATER:
399 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
400 break;
401 case FRAG_DEPTH_LAYOUT_LESS:
402 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
403 break;
404 case FRAG_DEPTH_LAYOUT_UNCHANGED:
405 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
406 break;
407 default:
408 unreachable("Unknow depth layout");
409 }
410 }
411 }
412
413 if (gl_shader_stage_is_compute(nir->info.stage)) {
414 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
415 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
416 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
417 }
418
419 i = 0;
420 uint64_t processed_inputs = 0;
421 unsigned num_inputs = 0;
422 nir_foreach_variable(variable, &nir->inputs) {
423 unsigned semantic_name, semantic_index;
424
425 const struct glsl_type *type = variable->type;
426 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
427 assert(glsl_type_is_array(type));
428 type = glsl_get_array_element(type);
429 }
430
431 unsigned attrib_count = glsl_count_attribute_slots(type,
432 nir->info.stage == MESA_SHADER_VERTEX);
433
434 i = variable->data.driver_location;
435
436 /* Vertex shader inputs don't have semantics. The state
437 * tracker has already mapped them to attributes via
438 * variable->data.driver_location.
439 */
440 if (nir->info.stage == MESA_SHADER_VERTEX) {
441 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)))
442 num_inputs++;
443
444 num_inputs++;
445 continue;
446 }
447
448 for (unsigned j = 0; j < attrib_count; j++, i++) {
449
450 if (processed_inputs & ((uint64_t)1 << i))
451 continue;
452
453 processed_inputs |= ((uint64_t)1 << i);
454 num_inputs++;
455
456 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
457 &semantic_name, &semantic_index);
458
459 info->input_semantic_name[i] = semantic_name;
460 info->input_semantic_index[i] = semantic_index;
461
462 if (semantic_name == TGSI_SEMANTIC_PRIMID)
463 info->uses_primid = true;
464
465 enum glsl_base_type base_type =
466 glsl_get_base_type(glsl_without_array(variable->type));
467
468 switch (variable->data.interpolation) {
469 case INTERP_MODE_NONE:
470 if (glsl_base_type_is_integer(base_type)) {
471 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
472 break;
473 }
474
475 if (semantic_name == TGSI_SEMANTIC_COLOR) {
476 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
477 break;
478 }
479 /* fall-through */
480
481 case INTERP_MODE_SMOOTH:
482 assert(!glsl_base_type_is_integer(base_type));
483
484 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
485 break;
486
487 case INTERP_MODE_NOPERSPECTIVE:
488 assert(!glsl_base_type_is_integer(base_type));
489
490 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
491 break;
492
493 case INTERP_MODE_FLAT:
494 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
495 break;
496 }
497 }
498 }
499
500 info->num_inputs = num_inputs;
501
502 i = 0;
503 uint64_t processed_outputs = 0;
504 unsigned num_outputs = 0;
505 nir_foreach_variable(variable, &nir->outputs) {
506 unsigned semantic_name, semantic_index;
507
508 i = variable->data.driver_location;
509
510 const struct glsl_type *type = variable->type;
511 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
512 assert(glsl_type_is_array(type));
513 type = glsl_get_array_element(type);
514 }
515
516 unsigned attrib_count = glsl_count_attribute_slots(type, false);
517 for (unsigned k = 0; k < attrib_count; k++, i++) {
518
519 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
520 tgsi_get_gl_frag_result_semantic(variable->data.location + k,
521 &semantic_name, &semantic_index);
522
523 /* Adjust for dual source blending */
524 if (variable->data.index > 0) {
525 semantic_index++;
526 }
527 } else {
528 tgsi_get_gl_varying_semantic(variable->data.location + k, true,
529 &semantic_name, &semantic_index);
530 }
531
532 unsigned num_components = 4;
533 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
534 if (vector_elements)
535 num_components = vector_elements;
536
537 unsigned component = variable->data.location_frac;
538 if (glsl_type_is_64bit(glsl_without_array(variable->type))) {
539 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)) && k % 2) {
540 num_components = (num_components * 2) - 4;
541 component = 0;
542 } else {
543 num_components = MIN2(num_components * 2, 4);
544 }
545 }
546
547 ubyte usagemask = 0;
548 for (unsigned j = component; j < num_components + component; j++) {
549 switch (j) {
550 case 0:
551 usagemask |= TGSI_WRITEMASK_X;
552 break;
553 case 1:
554 usagemask |= TGSI_WRITEMASK_Y;
555 break;
556 case 2:
557 usagemask |= TGSI_WRITEMASK_Z;
558 break;
559 case 3:
560 usagemask |= TGSI_WRITEMASK_W;
561 break;
562 default:
563 unreachable("error calculating component index");
564 }
565 }
566
567 unsigned gs_out_streams;
568 if (variable->data.stream & (1u << 31)) {
569 gs_out_streams = variable->data.stream & ~(1u << 31);
570 } else {
571 assert(variable->data.stream < 4);
572 gs_out_streams = 0;
573 for (unsigned j = 0; j < num_components; ++j)
574 gs_out_streams |= variable->data.stream << (2 * (component + j));
575 }
576
577 unsigned streamx = gs_out_streams & 3;
578 unsigned streamy = (gs_out_streams >> 2) & 3;
579 unsigned streamz = (gs_out_streams >> 4) & 3;
580 unsigned streamw = (gs_out_streams >> 6) & 3;
581
582 if (usagemask & TGSI_WRITEMASK_X) {
583 info->output_usagemask[i] |= TGSI_WRITEMASK_X;
584 info->output_streams[i] |= streamx;
585 info->num_stream_output_components[streamx]++;
586 }
587 if (usagemask & TGSI_WRITEMASK_Y) {
588 info->output_usagemask[i] |= TGSI_WRITEMASK_Y;
589 info->output_streams[i] |= streamy << 2;
590 info->num_stream_output_components[streamy]++;
591 }
592 if (usagemask & TGSI_WRITEMASK_Z) {
593 info->output_usagemask[i] |= TGSI_WRITEMASK_Z;
594 info->output_streams[i] |= streamz << 4;
595 info->num_stream_output_components[streamz]++;
596 }
597 if (usagemask & TGSI_WRITEMASK_W) {
598 info->output_usagemask[i] |= TGSI_WRITEMASK_W;
599 info->output_streams[i] |= streamw << 6;
600 info->num_stream_output_components[streamw]++;
601 }
602
603 /* make sure we only count this location once against
604 * the num_outputs counter.
605 */
606 if (processed_outputs & ((uint64_t)1 << i))
607 continue;
608
609 processed_outputs |= ((uint64_t)1 << i);
610 num_outputs++;
611
612 info->output_semantic_name[i] = semantic_name;
613 info->output_semantic_index[i] = semantic_index;
614
615 switch (semantic_name) {
616 case TGSI_SEMANTIC_PRIMID:
617 info->writes_primid = true;
618 break;
619 case TGSI_SEMANTIC_VIEWPORT_INDEX:
620 info->writes_viewport_index = true;
621 break;
622 case TGSI_SEMANTIC_LAYER:
623 info->writes_layer = true;
624 break;
625 case TGSI_SEMANTIC_PSIZE:
626 info->writes_psize = true;
627 break;
628 case TGSI_SEMANTIC_CLIPVERTEX:
629 info->writes_clipvertex = true;
630 break;
631 case TGSI_SEMANTIC_COLOR:
632 info->colors_written |= 1 << semantic_index;
633 break;
634 case TGSI_SEMANTIC_STENCIL:
635 info->writes_stencil = true;
636 break;
637 case TGSI_SEMANTIC_SAMPLEMASK:
638 info->writes_samplemask = true;
639 break;
640 case TGSI_SEMANTIC_EDGEFLAG:
641 info->writes_edgeflag = true;
642 break;
643 case TGSI_SEMANTIC_POSITION:
644 if (info->processor == PIPE_SHADER_FRAGMENT)
645 info->writes_z = true;
646 else
647 info->writes_position = true;
648 break;
649 }
650
651 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
652 switch (semantic_name) {
653 case TGSI_SEMANTIC_PATCH:
654 info->reads_perpatch_outputs = true;
655 break;
656 case TGSI_SEMANTIC_TESSINNER:
657 case TGSI_SEMANTIC_TESSOUTER:
658 info->reads_tessfactor_outputs = true;
659 break;
660 default:
661 info->reads_pervertex_outputs = true;
662 }
663 }
664 }
665
666 unsigned loc = variable->data.location;
667 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
668 loc == FRAG_RESULT_COLOR &&
669 nir->info.outputs_written & (1ull << loc)) {
670 assert(attrib_count == 1);
671 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
672 }
673 }
674
675 info->num_outputs = num_outputs;
676
677 struct set *ubo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
678 _mesa_key_pointer_equal);
679 struct set *ssbo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
680 _mesa_key_pointer_equal);
681
682 /* Intialise const_file_max[0] */
683 info->const_file_max[0] = -1;
684
685 /* The first 8 are reserved for atomic counters using ssbo */
686 unsigned ssbo_idx = 8;
687
688 unsigned ubo_idx = 1;
689 nir_foreach_variable(variable, &nir->uniforms) {
690 const struct glsl_type *type = variable->type;
691 enum glsl_base_type base_type =
692 glsl_get_base_type(glsl_without_array(type));
693 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
694 unsigned loc = variable->data.driver_location / 4;
695 int slot_count = glsl_count_attribute_slots(type, false);
696 int max_slot = MAX2(info->const_file_max[0], (int) loc) + slot_count;
697
698 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
699 * really use the mask (other than ubo_idx == 1 for regular
700 * uniforms) its really only used for getting the buffer count
701 * so we don't need to worry about the ordering.
702 */
703 if (variable->interface_type != NULL) {
704 if (variable->data.mode == nir_var_uniform ||
705 variable->data.mode == nir_var_mem_ubo ||
706 variable->data.mode == nir_var_mem_ssbo) {
707
708 struct set *buf_set = variable->data.mode == nir_var_mem_ssbo ?
709 ssbo_set : ubo_set;
710
711 unsigned block_count;
712 if (base_type != GLSL_TYPE_INTERFACE) {
713 struct set_entry *entry =
714 _mesa_set_search(buf_set, variable->interface_type);
715
716 /* Check if we have already processed
717 * a member from this ubo.
718 */
719 if (entry)
720 continue;
721
722 block_count = 1;
723 } else {
724 block_count = aoa_size;
725 }
726
727 if (variable->data.mode == nir_var_uniform ||
728 variable->data.mode == nir_var_mem_ubo) {
729 info->const_buffers_declared |= u_bit_consecutive(ubo_idx, block_count);
730 ubo_idx += block_count;
731 } else {
732 assert(variable->data.mode == nir_var_mem_ssbo);
733
734 info->shader_buffers_declared |= u_bit_consecutive(ssbo_idx, block_count);
735 ssbo_idx += block_count;
736 }
737
738 _mesa_set_add(buf_set, variable->interface_type);
739 }
740
741 continue;
742 }
743
744 /* We rely on the fact that nir_lower_samplers_as_deref has
745 * eliminated struct dereferences.
746 */
747 if (base_type == GLSL_TYPE_SAMPLER) {
748 if (variable->data.bindless) {
749 info->const_buffers_declared |= 1;
750 info->const_file_max[0] = max_slot;
751 } else {
752 info->samplers_declared |=
753 u_bit_consecutive(variable->data.binding, aoa_size);
754 }
755 } else if (base_type == GLSL_TYPE_IMAGE) {
756 if (variable->data.bindless) {
757 info->const_buffers_declared |= 1;
758 info->const_file_max[0] = max_slot;
759 } else {
760 info->images_declared |=
761 u_bit_consecutive(variable->data.binding, aoa_size);
762 }
763 } else if (base_type != GLSL_TYPE_ATOMIC_UINT) {
764 info->const_buffers_declared |= 1;
765 info->const_file_max[0] = max_slot;
766 }
767 }
768
769 _mesa_set_destroy(ubo_set, NULL);
770 _mesa_set_destroy(ssbo_set, NULL);
771
772 info->num_written_clipdistance = nir->info.clip_distance_array_size;
773 info->num_written_culldistance = nir->info.cull_distance_array_size;
774 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
775 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
776
777 if (info->processor == PIPE_SHADER_FRAGMENT)
778 info->uses_kill = nir->info.fs.uses_discard;
779
780 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
781 nir_foreach_block(block, func->impl) {
782 nir_foreach_instr(instr, block)
783 scan_instruction(nir, info, instr);
784 }
785 }
786
787 void
788 si_nir_opts(struct nir_shader *nir)
789 {
790 bool progress;
791 unsigned lower_flrp =
792 (nir->options->lower_flrp16 ? 16 : 0) |
793 (nir->options->lower_flrp32 ? 32 : 0) |
794 (nir->options->lower_flrp64 ? 64 : 0);
795
796 do {
797 progress = false;
798
799 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
800
801 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
802 NIR_PASS(progress, nir, nir_opt_dead_write_vars);
803
804 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL);
805 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
806
807 /* (Constant) copy propagation is needed for txf with offsets. */
808 NIR_PASS(progress, nir, nir_copy_prop);
809 NIR_PASS(progress, nir, nir_opt_remove_phis);
810 NIR_PASS(progress, nir, nir_opt_dce);
811 if (nir_opt_trivial_continues(nir)) {
812 progress = true;
813 NIR_PASS(progress, nir, nir_copy_prop);
814 NIR_PASS(progress, nir, nir_opt_dce);
815 }
816 NIR_PASS(progress, nir, nir_opt_if, true);
817 NIR_PASS(progress, nir, nir_opt_dead_cf);
818 NIR_PASS(progress, nir, nir_opt_cse);
819 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
820
821 /* Needed for algebraic lowering */
822 NIR_PASS(progress, nir, nir_opt_algebraic);
823 NIR_PASS(progress, nir, nir_opt_constant_folding);
824
825 if (lower_flrp != 0) {
826 bool lower_flrp_progress = false;
827
828 NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp,
829 lower_flrp,
830 false /* always_precise */,
831 nir->options->lower_ffma);
832 if (lower_flrp_progress) {
833 NIR_PASS(progress, nir,
834 nir_opt_constant_folding);
835 progress = true;
836 }
837
838 /* Nothing should rematerialize any flrps, so we only
839 * need to do this lowering once.
840 */
841 lower_flrp = 0;
842 }
843
844 NIR_PASS(progress, nir, nir_opt_undef);
845 NIR_PASS(progress, nir, nir_opt_conditional_discard);
846 if (nir->options->max_unroll_iterations) {
847 NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
848 }
849 } while (progress);
850 }
851
852 static int
853 type_size_vec4(const struct glsl_type *type, bool bindless)
854 {
855 return glsl_count_attribute_slots(type, false);
856 }
857
858 static void
859 si_nir_lower_color(nir_shader *nir)
860 {
861 nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
862
863 nir_builder b;
864 nir_builder_init(&b, entrypoint);
865
866 nir_foreach_block(block, entrypoint) {
867 nir_foreach_instr_safe(instr, block) {
868 if (instr->type != nir_instr_type_intrinsic)
869 continue;
870
871 nir_intrinsic_instr *intrin =
872 nir_instr_as_intrinsic(instr);
873
874 if (intrin->intrinsic != nir_intrinsic_load_deref)
875 continue;
876
877 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
878 if (deref->mode != nir_var_shader_in)
879 continue;
880
881 b.cursor = nir_before_instr(instr);
882 nir_variable *var = nir_deref_instr_get_variable(deref);
883 nir_ssa_def *def;
884
885 if (var->data.location == VARYING_SLOT_COL0) {
886 def = nir_load_color0(&b);
887 } else if (var->data.location == VARYING_SLOT_COL1) {
888 def = nir_load_color1(&b);
889 } else {
890 continue;
891 }
892
893 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(def));
894 nir_instr_remove(instr);
895 }
896 }
897 }
898
899 /**
900 * Perform "lowering" operations on the NIR that are run once when the shader
901 * selector is created.
902 */
903 void
904 si_lower_nir(struct si_shader_selector* sel)
905 {
906 /* Adjust the driver location of inputs and outputs. The state tracker
907 * interprets them as slots, while the ac/nir backend interprets them
908 * as individual components.
909 */
910 if (sel->nir->info.stage != MESA_SHADER_FRAGMENT) {
911 nir_foreach_variable(variable, &sel->nir->inputs)
912 variable->data.driver_location *= 4;
913 } else {
914 NIR_PASS_V(sel->nir, nir_lower_io_to_temporaries,
915 nir_shader_get_entrypoint(sel->nir), false, true);
916
917 /* Since we're doing nir_lower_io_to_temporaries late, we need
918 * to lower all the copy_deref's introduced by
919 * lower_io_to_temporaries before calling nir_lower_io.
920 */
921 NIR_PASS_V(sel->nir, nir_split_var_copies);
922 NIR_PASS_V(sel->nir, nir_lower_var_copies);
923 NIR_PASS_V(sel->nir, nir_lower_global_vars_to_local);
924
925 si_nir_lower_color(sel->nir);
926 NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
927
928 /* This pass needs actual constants */
929 NIR_PASS_V(sel->nir, nir_opt_constant_folding);
930 NIR_PASS_V(sel->nir, nir_io_add_const_offset_to_base,
931 nir_var_shader_in);
932 }
933
934 nir_foreach_variable(variable, &sel->nir->outputs) {
935 variable->data.driver_location *= 4;
936
937 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
938 if (variable->data.location == FRAG_RESULT_DEPTH)
939 variable->data.driver_location += 2;
940 else if (variable->data.location == FRAG_RESULT_STENCIL)
941 variable->data.driver_location += 1;
942 }
943 }
944
945 /* Perform lowerings (and optimizations) of code.
946 *
947 * Performance considerations aside, we must:
948 * - lower certain ALU operations
949 * - ensure constant offsets for texture instructions are folded
950 * and copy-propagated
951 */
952
953 static const struct nir_lower_tex_options lower_tex_options = {
954 .lower_txp = ~0u,
955 };
956 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
957
958 const nir_lower_subgroups_options subgroups_options = {
959 .subgroup_size = 64,
960 .ballot_bit_size = 64,
961 .lower_to_scalar = true,
962 .lower_subgroup_masks = true,
963 .lower_vote_trivial = false,
964 .lower_vote_eq_to_ballot = true,
965 };
966 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
967
968 ac_lower_indirect_derefs(sel->nir, sel->screen->info.chip_class);
969
970 si_nir_opts(sel->nir);
971
972 NIR_PASS_V(sel->nir, nir_lower_bool_to_int32);
973
974 /* Strip the resulting shader so that the shader cache is more likely
975 * to hit from other similar shaders.
976 */
977 nir_strip(sel->nir);
978 }
979
980 static void declare_nir_input_vs(struct si_shader_context *ctx,
981 struct nir_variable *variable,
982 unsigned input_index,
983 LLVMValueRef out[4])
984 {
985 si_llvm_load_input_vs(ctx, input_index, out);
986 }
987
988 LLVMValueRef
989 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
990 enum glsl_interp_mode interp, unsigned location)
991 {
992 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
993 int interp_param_idx = -1;
994
995 switch (interp) {
996 case INTERP_MODE_FLAT:
997 return NULL;
998 case INTERP_MODE_SMOOTH:
999 case INTERP_MODE_NONE:
1000 if (location == INTERP_CENTER)
1001 interp_param_idx = SI_PARAM_PERSP_CENTER;
1002 else if (location == INTERP_CENTROID)
1003 interp_param_idx = SI_PARAM_PERSP_CENTROID;
1004 else if (location == INTERP_SAMPLE)
1005 interp_param_idx = SI_PARAM_PERSP_SAMPLE;
1006 break;
1007 case INTERP_MODE_NOPERSPECTIVE:
1008 if (location == INTERP_CENTER)
1009 interp_param_idx = SI_PARAM_LINEAR_CENTER;
1010 else if (location == INTERP_CENTROID)
1011 interp_param_idx = SI_PARAM_LINEAR_CENTROID;
1012 else if (location == INTERP_SAMPLE)
1013 interp_param_idx = SI_PARAM_LINEAR_SAMPLE;
1014 break;
1015 default:
1016 assert(!"Unhandled interpolation mode.");
1017 return NULL;
1018 }
1019
1020 return interp_param_idx != -1 ?
1021 LLVMGetParam(ctx->main_fn, interp_param_idx) : NULL;
1022 }
1023
1024 static LLVMValueRef
1025 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
1026 unsigned descriptor_set, unsigned base_index,
1027 unsigned constant_index, LLVMValueRef dynamic_index,
1028 enum ac_descriptor_type desc_type, bool image,
1029 bool write, bool bindless)
1030 {
1031 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1032 LLVMBuilderRef builder = ctx->ac.builder;
1033 unsigned const_index = base_index + constant_index;
1034
1035 assert(!descriptor_set);
1036 assert(!image || desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
1037
1038 if (bindless) {
1039 LLVMValueRef list =
1040 LLVMGetParam(ctx->main_fn, ctx->param_bindless_samplers_and_images);
1041
1042 /* dynamic_index is the bindless handle */
1043 if (image) {
1044 /* For simplicity, bindless image descriptors use fixed
1045 * 16-dword slots for now.
1046 */
1047 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1048 LLVMConstInt(ctx->i64, 2, 0), "");
1049
1050 return si_load_image_desc(ctx, list, dynamic_index, desc_type,
1051 write, true);
1052 }
1053
1054 /* Since bindless handle arithmetic can contain an unsigned integer
1055 * wraparound and si_load_sampler_desc assumes there isn't any,
1056 * use GEP without "inbounds" (inside ac_build_pointer_add)
1057 * to prevent incorrect code generation and hangs.
1058 */
1059 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1060 LLVMConstInt(ctx->i64, 2, 0), "");
1061 list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
1062 return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
1063 }
1064
1065 unsigned num_slots = image ? ctx->num_images : ctx->num_samplers;
1066 assert(const_index < num_slots);
1067
1068 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1069 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, const_index, false);
1070
1071 if (dynamic_index) {
1072 index = LLVMBuildAdd(builder, index, dynamic_index, "");
1073
1074 /* From the GL_ARB_shader_image_load_store extension spec:
1075 *
1076 * If a shader performs an image load, store, or atomic
1077 * operation using an image variable declared as an array,
1078 * and if the index used to select an individual element is
1079 * negative or greater than or equal to the size of the
1080 * array, the results of the operation are undefined but may
1081 * not lead to termination.
1082 */
1083 index = si_llvm_bound_index(ctx, index, num_slots);
1084 }
1085
1086 if (image) {
1087 index = LLVMBuildSub(ctx->ac.builder,
1088 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
1089 index, "");
1090 return si_load_image_desc(ctx, list, index, desc_type, write, false);
1091 }
1092
1093 index = LLVMBuildAdd(ctx->ac.builder, index,
1094 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1095 return si_load_sampler_desc(ctx, list, index, desc_type);
1096 }
1097
1098 static void bitcast_inputs(struct si_shader_context *ctx,
1099 LLVMValueRef data[4],
1100 unsigned input_idx)
1101 {
1102 for (unsigned chan = 0; chan < 4; chan++) {
1103 ctx->inputs[input_idx + chan] =
1104 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
1105 }
1106 }
1107
1108 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
1109 {
1110 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1111
1112 if (nir->info.stage == MESA_SHADER_VERTEX) {
1113 uint64_t processed_inputs = 0;
1114 nir_foreach_variable(variable, &nir->inputs) {
1115 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
1116 true);
1117 unsigned input_idx = variable->data.driver_location;
1118
1119 LLVMValueRef data[4];
1120 unsigned loc = variable->data.location;
1121
1122 for (unsigned i = 0; i < attrib_count; i++) {
1123 /* Packed components share the same location so skip
1124 * them if we have already processed the location.
1125 */
1126 if (processed_inputs & ((uint64_t)1 << (loc + i))) {
1127 input_idx += 4;
1128 continue;
1129 }
1130
1131 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1132 bitcast_inputs(ctx, data, input_idx);
1133 if (glsl_type_is_dual_slot(variable->type)) {
1134 input_idx += 4;
1135 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1136 bitcast_inputs(ctx, data, input_idx);
1137 }
1138
1139 processed_inputs |= ((uint64_t)1 << (loc + i));
1140 input_idx += 4;
1141 }
1142 }
1143 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1144 unsigned colors_read =
1145 ctx->shader->selector->info.colors_read;
1146 LLVMValueRef main_fn = ctx->main_fn;
1147
1148 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1149
1150 unsigned offset = SI_PARAM_POS_FIXED_PT + 1;
1151
1152 if (colors_read & 0x0f) {
1153 unsigned mask = colors_read & 0x0f;
1154 LLVMValueRef values[4];
1155 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1156 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1157 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1158 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1159 ctx->abi.color0 =
1160 ac_to_integer(&ctx->ac,
1161 ac_build_gather_values(&ctx->ac, values, 4));
1162 }
1163 if (colors_read & 0xf0) {
1164 unsigned mask = (colors_read & 0xf0) >> 4;
1165 LLVMValueRef values[4];
1166 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1167 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1168 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1169 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1170 ctx->abi.color1 =
1171 ac_to_integer(&ctx->ac,
1172 ac_build_gather_values(&ctx->ac, values, 4));
1173 }
1174 }
1175
1176 ctx->abi.inputs = &ctx->inputs[0];
1177 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
1178 ctx->abi.clamp_shadow_reference = true;
1179
1180 ctx->num_samplers = util_last_bit(info->samplers_declared);
1181 ctx->num_images = util_last_bit(info->images_declared);
1182
1183 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
1184 assert(gl_shader_stage_is_compute(nir->info.stage));
1185 si_declare_compute_memory(ctx);
1186 }
1187 ac_nir_translate(&ctx->ac, &ctx->abi, nir);
1188
1189 return true;
1190 }