2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 #include "si_shader.h"
25 #include "si_shader_internal.h"
27 #include "ac_nir_to_llvm.h"
29 #include "tgsi/tgsi_from_mesa.h"
31 #include "compiler/nir/nir.h"
32 #include "compiler/nir_types.h"
36 type_size(const struct glsl_type
*type
)
38 return glsl_count_attribute_slots(type
, false);
41 static void scan_instruction(struct tgsi_shader_info
*info
,
44 if (instr
->type
== nir_instr_type_alu
) {
45 nir_alu_instr
*alu
= nir_instr_as_alu(instr
);
50 case nir_op_fddx_fine
:
51 case nir_op_fddy_fine
:
52 case nir_op_fddx_coarse
:
53 case nir_op_fddy_coarse
:
54 info
->uses_derivatives
= true;
59 } else if (instr
->type
== nir_instr_type_tex
) {
60 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
63 info
->samplers_declared
|=
64 u_bit_consecutive(tex
->sampler_index
, 1);
71 info
->uses_derivatives
= true;
76 } else if (instr
->type
== nir_instr_type_intrinsic
) {
77 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
79 switch (intr
->intrinsic
) {
80 case nir_intrinsic_load_front_face
:
81 info
->uses_frontface
= 1;
83 case nir_intrinsic_load_instance_id
:
84 info
->uses_instanceid
= 1;
86 case nir_intrinsic_load_invocation_id
:
87 info
->uses_invocationid
= true;
89 case nir_intrinsic_load_num_work_groups
:
90 info
->uses_grid_size
= true;
92 case nir_intrinsic_load_local_group_size
:
93 /* The block size is translated to IMM with a fixed block size. */
94 if (info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] == 0)
95 info
->uses_block_size
= true;
97 case nir_intrinsic_load_local_invocation_id
:
98 case nir_intrinsic_load_work_group_id
: {
99 unsigned mask
= nir_ssa_def_components_read(&intr
->dest
.ssa
);
101 unsigned i
= u_bit_scan(&mask
);
103 if (intr
->intrinsic
== nir_intrinsic_load_work_group_id
)
104 info
->uses_block_id
[i
] = true;
106 info
->uses_thread_id
[i
] = true;
110 case nir_intrinsic_load_vertex_id
:
111 info
->uses_vertexid
= 1;
113 case nir_intrinsic_load_vertex_id_zero_base
:
114 info
->uses_vertexid_nobase
= 1;
116 case nir_intrinsic_load_base_vertex
:
117 info
->uses_basevertex
= 1;
119 case nir_intrinsic_load_primitive_id
:
120 info
->uses_primid
= 1;
122 case nir_intrinsic_load_sample_mask_in
:
123 info
->reads_samplemask
= true;
125 case nir_intrinsic_load_tess_level_inner
:
126 case nir_intrinsic_load_tess_level_outer
:
127 info
->reads_tess_factors
= true;
129 case nir_intrinsic_image_store
:
130 case nir_intrinsic_image_atomic_add
:
131 case nir_intrinsic_image_atomic_min
:
132 case nir_intrinsic_image_atomic_max
:
133 case nir_intrinsic_image_atomic_and
:
134 case nir_intrinsic_image_atomic_or
:
135 case nir_intrinsic_image_atomic_xor
:
136 case nir_intrinsic_image_atomic_exchange
:
137 case nir_intrinsic_image_atomic_comp_swap
:
138 case nir_intrinsic_store_ssbo
:
139 case nir_intrinsic_ssbo_atomic_add
:
140 case nir_intrinsic_ssbo_atomic_imin
:
141 case nir_intrinsic_ssbo_atomic_umin
:
142 case nir_intrinsic_ssbo_atomic_imax
:
143 case nir_intrinsic_ssbo_atomic_umax
:
144 case nir_intrinsic_ssbo_atomic_and
:
145 case nir_intrinsic_ssbo_atomic_or
:
146 case nir_intrinsic_ssbo_atomic_xor
:
147 case nir_intrinsic_ssbo_atomic_exchange
:
148 case nir_intrinsic_ssbo_atomic_comp_swap
:
149 info
->writes_memory
= true;
151 case nir_intrinsic_load_var
: {
152 nir_variable
*var
= intr
->variables
[0]->var
;
153 nir_variable_mode mode
= var
->data
.mode
;
154 enum glsl_base_type base_type
=
155 glsl_get_base_type(glsl_without_array(var
->type
));
157 if (mode
== nir_var_shader_in
) {
158 switch (var
->data
.interpolation
) {
159 case INTERP_MODE_NONE
:
160 if (glsl_base_type_is_integer(base_type
))
164 case INTERP_MODE_SMOOTH
:
165 if (var
->data
.sample
)
166 info
->uses_persp_sample
= true;
167 else if (var
->data
.centroid
)
168 info
->uses_persp_centroid
= true;
170 info
->uses_persp_center
= true;
173 case INTERP_MODE_NOPERSPECTIVE
:
174 if (var
->data
.sample
)
175 info
->uses_linear_sample
= true;
176 else if (var
->data
.centroid
)
177 info
->uses_linear_centroid
= true;
179 info
->uses_linear_center
= true;
185 case nir_intrinsic_interp_var_at_centroid
:
186 case nir_intrinsic_interp_var_at_sample
:
187 case nir_intrinsic_interp_var_at_offset
: {
188 enum glsl_interp_mode interp
=
189 intr
->variables
[0]->var
->data
.interpolation
;
191 case INTERP_MODE_SMOOTH
:
192 case INTERP_MODE_NONE
:
193 if (intr
->intrinsic
== nir_intrinsic_interp_var_at_centroid
)
194 info
->uses_persp_opcode_interp_centroid
= true;
195 else if (intr
->intrinsic
== nir_intrinsic_interp_var_at_sample
)
196 info
->uses_persp_opcode_interp_sample
= true;
198 info
->uses_persp_opcode_interp_offset
= true;
200 case INTERP_MODE_NOPERSPECTIVE
:
201 if (intr
->intrinsic
== nir_intrinsic_interp_var_at_centroid
)
202 info
->uses_linear_opcode_interp_centroid
= true;
203 else if (intr
->intrinsic
== nir_intrinsic_interp_var_at_sample
)
204 info
->uses_linear_opcode_interp_sample
= true;
206 info
->uses_linear_opcode_interp_offset
= true;
208 case INTERP_MODE_FLAT
:
211 unreachable("Unsupported interpoation type");
221 void si_nir_scan_tess_ctrl(const struct nir_shader
*nir
,
222 const struct tgsi_shader_info
*info
,
223 struct tgsi_tessctrl_info
*out
)
225 memset(out
, 0, sizeof(*out
));
227 if (nir
->info
.stage
!= MESA_SHADER_TESS_CTRL
)
230 /* Initial value = true. Here the pass will accumulate results from
231 * multiple segments surrounded by barriers. If tess factors aren't
232 * written at all, it's a shader bug and we don't care if this will be
235 out
->tessfactors_are_def_in_all_invocs
= true;
237 /* TODO: Implement scanning of tess factors, see tgsi backend. */
240 void si_nir_scan_shader(const struct nir_shader
*nir
,
241 struct tgsi_shader_info
*info
)
246 info
->processor
= pipe_shader_type_from_mesa(nir
->info
.stage
);
247 info
->num_tokens
= 2; /* indicate that the shader is non-empty */
248 info
->num_instructions
= 2;
250 if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
251 info
->properties
[TGSI_PROPERTY_TCS_VERTICES_OUT
] =
252 nir
->info
.tess
.tcs_vertices_out
;
255 if (nir
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
256 if (nir
->info
.tess
.primitive_mode
== GL_ISOLINES
)
257 info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
] = PIPE_PRIM_LINES
;
259 info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
] = nir
->info
.tess
.primitive_mode
;
261 STATIC_ASSERT((TESS_SPACING_EQUAL
+ 1) % 3 == PIPE_TESS_SPACING_EQUAL
);
262 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD
+ 1) % 3 ==
263 PIPE_TESS_SPACING_FRACTIONAL_ODD
);
264 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN
+ 1) % 3 ==
265 PIPE_TESS_SPACING_FRACTIONAL_EVEN
);
267 info
->properties
[TGSI_PROPERTY_TES_SPACING
] = (nir
->info
.tess
.spacing
+ 1) % 3;
268 info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
] = !nir
->info
.tess
.ccw
;
269 info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
] = nir
->info
.tess
.point_mode
;
272 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
) {
273 info
->properties
[TGSI_PROPERTY_GS_INPUT_PRIM
] = nir
->info
.gs
.input_primitive
;
274 info
->properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
] = nir
->info
.gs
.output_primitive
;
275 info
->properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
] = nir
->info
.gs
.vertices_out
;
276 info
->properties
[TGSI_PROPERTY_GS_INVOCATIONS
] = nir
->info
.gs
.invocations
;
279 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
280 info
->properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] =
281 nir
->info
.fs
.early_fragment_tests
| nir
->info
.fs
.post_depth_coverage
;
282 info
->properties
[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
] = nir
->info
.fs
.post_depth_coverage
;
284 if (nir
->info
.fs
.depth_layout
!= FRAG_DEPTH_LAYOUT_NONE
) {
285 switch (nir
->info
.fs
.depth_layout
) {
286 case FRAG_DEPTH_LAYOUT_ANY
:
287 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_ANY
;
289 case FRAG_DEPTH_LAYOUT_GREATER
:
290 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_GREATER
;
292 case FRAG_DEPTH_LAYOUT_LESS
:
293 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_LESS
;
295 case FRAG_DEPTH_LAYOUT_UNCHANGED
:
296 info
->properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED
;
299 unreachable("Unknow depth layout");
304 if (nir
->info
.stage
== MESA_SHADER_COMPUTE
) {
305 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH
] = nir
->info
.cs
.local_size
[0];
306 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT
] = nir
->info
.cs
.local_size
[1];
307 info
->properties
[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH
] = nir
->info
.cs
.local_size
[2];
311 uint64_t processed_inputs
= 0;
312 unsigned num_inputs
= 0;
313 nir_foreach_variable(variable
, &nir
->inputs
) {
314 unsigned semantic_name
, semantic_index
;
316 const struct glsl_type
*type
= variable
->type
;
317 if (nir_is_per_vertex_io(variable
, nir
->info
.stage
)) {
318 assert(glsl_type_is_array(type
));
319 type
= glsl_get_array_element(type
);
322 unsigned attrib_count
= glsl_count_attribute_slots(type
,
323 nir
->info
.stage
== MESA_SHADER_VERTEX
);
325 i
= variable
->data
.driver_location
;
327 /* Vertex shader inputs don't have semantics. The state
328 * tracker has already mapped them to attributes via
329 * variable->data.driver_location.
331 if (nir
->info
.stage
== MESA_SHADER_VERTEX
) {
332 /* TODO: gather the actual input useage and remove this. */
333 info
->input_usage_mask
[i
] = TGSI_WRITEMASK_XYZW
;
335 if (glsl_type_is_dual_slot(variable
->type
)) {
338 /* TODO: gather the actual input useage and remove this. */
339 info
->input_usage_mask
[i
+1] = TGSI_WRITEMASK_XYZW
;
345 /* Fragment shader position is a system value. */
346 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
&&
347 variable
->data
.location
== VARYING_SLOT_POS
) {
348 if (variable
->data
.pixel_center_integer
)
349 info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] =
350 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
;
356 for (unsigned j
= 0; j
< attrib_count
; j
++, i
++) {
358 if (processed_inputs
& ((uint64_t)1 << i
))
361 processed_inputs
|= ((uint64_t)1 << i
);
364 tgsi_get_gl_varying_semantic(variable
->data
.location
+ j
, true,
365 &semantic_name
, &semantic_index
);
367 info
->input_semantic_name
[i
] = semantic_name
;
368 info
->input_semantic_index
[i
] = semantic_index
;
370 if (semantic_name
== TGSI_SEMANTIC_PRIMID
)
371 info
->uses_primid
= true;
373 if (variable
->data
.sample
)
374 info
->input_interpolate_loc
[i
] = TGSI_INTERPOLATE_LOC_SAMPLE
;
375 else if (variable
->data
.centroid
)
376 info
->input_interpolate_loc
[i
] = TGSI_INTERPOLATE_LOC_CENTROID
;
378 info
->input_interpolate_loc
[i
] = TGSI_INTERPOLATE_LOC_CENTER
;
380 enum glsl_base_type base_type
=
381 glsl_get_base_type(glsl_without_array(variable
->type
));
383 switch (variable
->data
.interpolation
) {
384 case INTERP_MODE_NONE
:
385 if (glsl_base_type_is_integer(base_type
)) {
386 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_CONSTANT
;
390 if (semantic_name
== TGSI_SEMANTIC_COLOR
) {
391 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_COLOR
;
396 case INTERP_MODE_SMOOTH
:
397 assert(!glsl_base_type_is_integer(base_type
));
399 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_PERSPECTIVE
;
402 case INTERP_MODE_NOPERSPECTIVE
:
403 assert(!glsl_base_type_is_integer(base_type
));
405 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_LINEAR
;
408 case INTERP_MODE_FLAT
:
409 info
->input_interpolate
[i
] = TGSI_INTERPOLATE_CONSTANT
;
413 /* TODO make this more precise */
414 if (variable
->data
.location
== VARYING_SLOT_COL0
)
415 info
->colors_read
|= 0x0f;
416 else if (variable
->data
.location
== VARYING_SLOT_COL1
)
417 info
->colors_read
|= 0xf0;
421 info
->num_inputs
= num_inputs
;
425 uint64_t processed_outputs
= 0;
426 unsigned num_outputs
= 0;
427 nir_foreach_variable(variable
, &nir
->outputs
) {
428 unsigned semantic_name
, semantic_index
;
430 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
431 tgsi_get_gl_frag_result_semantic(variable
->data
.location
,
432 &semantic_name
, &semantic_index
);
434 /* Adjust for dual source blending */
435 if (variable
->data
.index
> 0) {
439 tgsi_get_gl_varying_semantic(variable
->data
.location
, true,
440 &semantic_name
, &semantic_index
);
443 i
= variable
->data
.driver_location
;
444 if (processed_outputs
& ((uint64_t)1 << i
))
447 processed_outputs
|= ((uint64_t)1 << i
);
450 info
->output_semantic_name
[i
] = semantic_name
;
451 info
->output_semantic_index
[i
] = semantic_index
;
452 info
->output_usagemask
[i
] = TGSI_WRITEMASK_XYZW
;
454 unsigned num_components
= 4;
455 unsigned vector_elements
= glsl_get_vector_elements(glsl_without_array(variable
->type
));
457 num_components
= vector_elements
;
459 unsigned gs_out_streams
;
460 if (variable
->data
.stream
& (1u << 31)) {
461 gs_out_streams
= variable
->data
.stream
& ~(1u << 31);
463 assert(variable
->data
.stream
< 4);
465 for (unsigned j
= 0; j
< num_components
; ++j
)
466 gs_out_streams
|= variable
->data
.stream
<< (2 * (variable
->data
.location_frac
+ j
));
469 unsigned streamx
= gs_out_streams
& 3;
470 unsigned streamy
= (gs_out_streams
>> 2) & 3;
471 unsigned streamz
= (gs_out_streams
>> 4) & 3;
472 unsigned streamw
= (gs_out_streams
>> 6) & 3;
474 if (info
->output_usagemask
[i
] & TGSI_WRITEMASK_X
) {
475 info
->output_streams
[i
] |= streamx
;
476 info
->num_stream_output_components
[streamx
]++;
478 if (info
->output_usagemask
[i
] & TGSI_WRITEMASK_Y
) {
479 info
->output_streams
[i
] |= streamy
<< 2;
480 info
->num_stream_output_components
[streamy
]++;
482 if (info
->output_usagemask
[i
] & TGSI_WRITEMASK_Z
) {
483 info
->output_streams
[i
] |= streamz
<< 4;
484 info
->num_stream_output_components
[streamz
]++;
486 if (info
->output_usagemask
[i
] & TGSI_WRITEMASK_W
) {
487 info
->output_streams
[i
] |= streamw
<< 6;
488 info
->num_stream_output_components
[streamw
]++;
491 switch (semantic_name
) {
492 case TGSI_SEMANTIC_PRIMID
:
493 info
->writes_primid
= true;
495 case TGSI_SEMANTIC_VIEWPORT_INDEX
:
496 info
->writes_viewport_index
= true;
498 case TGSI_SEMANTIC_LAYER
:
499 info
->writes_layer
= true;
501 case TGSI_SEMANTIC_PSIZE
:
502 info
->writes_psize
= true;
504 case TGSI_SEMANTIC_CLIPVERTEX
:
505 info
->writes_clipvertex
= true;
507 case TGSI_SEMANTIC_COLOR
:
508 info
->colors_written
|= 1 << semantic_index
;
510 case TGSI_SEMANTIC_STENCIL
:
511 info
->writes_stencil
= true;
513 case TGSI_SEMANTIC_SAMPLEMASK
:
514 info
->writes_samplemask
= true;
516 case TGSI_SEMANTIC_EDGEFLAG
:
517 info
->writes_edgeflag
= true;
519 case TGSI_SEMANTIC_POSITION
:
520 if (info
->processor
== PIPE_SHADER_FRAGMENT
)
521 info
->writes_z
= true;
523 info
->writes_position
= true;
527 if (nir
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
528 switch (semantic_name
) {
529 case TGSI_SEMANTIC_PATCH
:
530 info
->reads_perpatch_outputs
= true;
532 case TGSI_SEMANTIC_TESSINNER
:
533 case TGSI_SEMANTIC_TESSOUTER
:
534 info
->reads_tessfactor_outputs
= true;
537 info
->reads_pervertex_outputs
= true;
541 unsigned loc
= variable
->data
.location
;
542 if (loc
== FRAG_RESULT_COLOR
&&
543 nir
->info
.outputs_written
& (1ull << loc
)) {
544 info
->properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] = true;
548 info
->num_outputs
= num_outputs
;
550 nir_foreach_variable(variable
, &nir
->uniforms
) {
551 const struct glsl_type
*type
= variable
->type
;
552 enum glsl_base_type base_type
=
553 glsl_get_base_type(glsl_without_array(type
));
554 unsigned aoa_size
= MAX2(1, glsl_get_aoa_size(type
));
556 /* We rely on the fact that nir_lower_samplers_as_deref has
557 * eliminated struct dereferences.
559 if (base_type
== GLSL_TYPE_SAMPLER
)
560 info
->samplers_declared
|=
561 u_bit_consecutive(variable
->data
.binding
, aoa_size
);
562 else if (base_type
== GLSL_TYPE_IMAGE
)
563 info
->images_declared
|=
564 u_bit_consecutive(variable
->data
.binding
, aoa_size
);
567 info
->num_written_clipdistance
= nir
->info
.clip_distance_array_size
;
568 info
->num_written_culldistance
= nir
->info
.cull_distance_array_size
;
569 info
->clipdist_writemask
= u_bit_consecutive(0, info
->num_written_clipdistance
);
570 info
->culldist_writemask
= u_bit_consecutive(0, info
->num_written_culldistance
);
572 if (info
->processor
== PIPE_SHADER_FRAGMENT
)
573 info
->uses_kill
= nir
->info
.fs
.uses_discard
;
575 /* TODO make this more accurate */
576 info
->const_buffers_declared
= u_bit_consecutive(0, SI_NUM_CONST_BUFFERS
);
577 info
->shader_buffers_declared
= u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS
);
579 func
= (struct nir_function
*)exec_list_get_head_const(&nir
->functions
);
580 nir_foreach_block(block
, func
->impl
) {
581 nir_foreach_instr(instr
, block
)
582 scan_instruction(info
, instr
);
587 * Perform "lowering" operations on the NIR that are run once when the shader
588 * selector is created.
591 si_lower_nir(struct si_shader_selector
* sel
)
593 /* Adjust the driver location of inputs and outputs. The state tracker
594 * interprets them as slots, while the ac/nir backend interprets them
595 * as individual components.
597 nir_foreach_variable(variable
, &sel
->nir
->inputs
)
598 variable
->data
.driver_location
*= 4;
600 nir_foreach_variable(variable
, &sel
->nir
->outputs
) {
601 variable
->data
.driver_location
*= 4;
603 if (sel
->nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
604 if (variable
->data
.location
== FRAG_RESULT_DEPTH
)
605 variable
->data
.driver_location
+= 2;
606 else if (variable
->data
.location
== FRAG_RESULT_STENCIL
)
607 variable
->data
.driver_location
+= 1;
611 /* Perform lowerings (and optimizations) of code.
613 * Performance considerations aside, we must:
614 * - lower certain ALU operations
615 * - ensure constant offsets for texture instructions are folded
616 * and copy-propagated
618 NIR_PASS_V(sel
->nir
, nir_lower_io
, nir_var_uniform
, type_size
,
619 (nir_lower_io_options
)0);
620 NIR_PASS_V(sel
->nir
, nir_lower_uniforms_to_ubo
);
622 NIR_PASS_V(sel
->nir
, nir_lower_returns
);
623 NIR_PASS_V(sel
->nir
, nir_lower_vars_to_ssa
);
624 NIR_PASS_V(sel
->nir
, nir_lower_alu_to_scalar
);
625 NIR_PASS_V(sel
->nir
, nir_lower_phis_to_scalar
);
627 static const struct nir_lower_tex_options lower_tex_options
= {
630 NIR_PASS_V(sel
->nir
, nir_lower_tex
, &lower_tex_options
);
632 const nir_lower_subgroups_options subgroups_options
= {
634 .ballot_bit_size
= 64,
635 .lower_to_scalar
= true,
636 .lower_subgroup_masks
= true,
637 .lower_vote_trivial
= false,
639 NIR_PASS_V(sel
->nir
, nir_lower_subgroups
, &subgroups_options
);
645 /* (Constant) copy propagation is needed for txf with offsets. */
646 NIR_PASS(progress
, sel
->nir
, nir_copy_prop
);
647 NIR_PASS(progress
, sel
->nir
, nir_opt_remove_phis
);
648 NIR_PASS(progress
, sel
->nir
, nir_opt_dce
);
649 if (nir_opt_trivial_continues(sel
->nir
)) {
651 NIR_PASS(progress
, sel
->nir
, nir_copy_prop
);
652 NIR_PASS(progress
, sel
->nir
, nir_opt_dce
);
654 NIR_PASS(progress
, sel
->nir
, nir_opt_if
);
655 NIR_PASS(progress
, sel
->nir
, nir_opt_dead_cf
);
656 NIR_PASS(progress
, sel
->nir
, nir_opt_cse
);
657 NIR_PASS(progress
, sel
->nir
, nir_opt_peephole_select
, 8);
659 /* Needed for algebraic lowering */
660 NIR_PASS(progress
, sel
->nir
, nir_opt_algebraic
);
661 NIR_PASS(progress
, sel
->nir
, nir_opt_constant_folding
);
663 NIR_PASS(progress
, sel
->nir
, nir_opt_undef
);
664 NIR_PASS(progress
, sel
->nir
, nir_opt_conditional_discard
);
665 if (sel
->nir
->options
->max_unroll_iterations
) {
666 NIR_PASS(progress
, sel
->nir
, nir_opt_loop_unroll
, 0);
671 static void declare_nir_input_vs(struct si_shader_context
*ctx
,
672 struct nir_variable
*variable
,
673 unsigned input_index
,
676 si_llvm_load_input_vs(ctx
, input_index
, out
);
679 static void declare_nir_input_fs(struct si_shader_context
*ctx
,
680 struct nir_variable
*variable
,
681 unsigned input_index
,
684 unsigned slot
= variable
->data
.location
;
685 if (slot
== VARYING_SLOT_POS
) {
686 out
[0] = LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_X_FLOAT
);
687 out
[1] = LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Y_FLOAT
);
688 out
[2] = LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_Z_FLOAT
);
689 out
[3] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
,
690 LLVMGetParam(ctx
->main_fn
, SI_PARAM_POS_W_FLOAT
));
694 si_llvm_load_input_fs(ctx
, input_index
, out
);
697 LLVMValueRef
si_nir_load_input_gs(struct ac_shader_abi
*abi
,
699 unsigned driver_location
,
701 unsigned num_components
,
702 unsigned vertex_index
,
703 unsigned const_index
,
706 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
708 LLVMValueRef value
[4];
709 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
710 value
[i
] = si_llvm_load_input_gs(&ctx
->abi
, driver_location
/ 4,
711 vertex_index
, type
, i
);
714 return ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
718 si_nir_lookup_interp_param(struct ac_shader_abi
*abi
,
719 enum glsl_interp_mode interp
, unsigned location
)
721 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
722 int interp_param_idx
= -1;
725 case INTERP_MODE_FLAT
:
727 case INTERP_MODE_SMOOTH
:
728 case INTERP_MODE_NONE
:
729 if (location
== INTERP_CENTER
)
730 interp_param_idx
= SI_PARAM_PERSP_CENTER
;
731 else if (location
== INTERP_CENTROID
)
732 interp_param_idx
= SI_PARAM_PERSP_CENTROID
;
733 else if (location
== INTERP_SAMPLE
)
734 interp_param_idx
= SI_PARAM_PERSP_SAMPLE
;
736 case INTERP_MODE_NOPERSPECTIVE
:
737 if (location
== INTERP_CENTER
)
738 interp_param_idx
= SI_PARAM_LINEAR_CENTER
;
739 else if (location
== INTERP_CENTROID
)
740 interp_param_idx
= SI_PARAM_LINEAR_CENTROID
;
741 else if (location
== INTERP_SAMPLE
)
742 interp_param_idx
= SI_PARAM_LINEAR_SAMPLE
;
745 assert(!"Unhandled interpolation mode.");
749 return interp_param_idx
!= -1 ?
750 LLVMGetParam(ctx
->main_fn
, interp_param_idx
) : NULL
;
754 si_nir_load_sampler_desc(struct ac_shader_abi
*abi
,
755 unsigned descriptor_set
, unsigned base_index
,
756 unsigned constant_index
, LLVMValueRef dynamic_index
,
757 enum ac_descriptor_type desc_type
, bool image
,
760 struct si_shader_context
*ctx
= si_shader_context_from_abi(abi
);
761 LLVMBuilderRef builder
= ctx
->ac
.builder
;
762 LLVMValueRef list
= LLVMGetParam(ctx
->main_fn
, ctx
->param_samplers_and_images
);
763 LLVMValueRef index
= dynamic_index
;
765 assert(!descriptor_set
);
768 index
= ctx
->ac
.i32_0
;
770 index
= LLVMBuildAdd(builder
, index
,
771 LLVMConstInt(ctx
->ac
.i32
, base_index
+ constant_index
, false),
775 assert(desc_type
== AC_DESC_IMAGE
|| desc_type
== AC_DESC_BUFFER
);
776 assert(base_index
+ constant_index
< ctx
->num_images
);
779 index
= si_llvm_bound_index(ctx
, index
, ctx
->num_images
);
781 index
= LLVMBuildSub(ctx
->gallivm
.builder
,
782 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
- 1, 0),
785 /* TODO: be smarter about when we use dcc_off */
786 return si_load_image_desc(ctx
, list
, index
, desc_type
, write
);
789 assert(base_index
+ constant_index
< ctx
->num_samplers
);
792 index
= si_llvm_bound_index(ctx
, index
, ctx
->num_samplers
);
794 index
= LLVMBuildAdd(ctx
->gallivm
.builder
, index
,
795 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
/ 2, 0), "");
797 return si_load_sampler_desc(ctx
, list
, index
, desc_type
);
800 static void bitcast_inputs(struct si_shader_context
*ctx
,
801 LLVMValueRef data
[4],
804 for (unsigned chan
= 0; chan
< 4; chan
++) {
805 ctx
->inputs
[input_idx
+ chan
] =
806 LLVMBuildBitCast(ctx
->ac
.builder
, data
[chan
], ctx
->ac
.i32
, "");
810 bool si_nir_build_llvm(struct si_shader_context
*ctx
, struct nir_shader
*nir
)
812 struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
814 if (nir
->info
.stage
== MESA_SHADER_VERTEX
||
815 nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
816 uint64_t processed_inputs
= 0;
817 nir_foreach_variable(variable
, &nir
->inputs
) {
818 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
,
819 nir
->info
.stage
== MESA_SHADER_VERTEX
);
820 unsigned input_idx
= variable
->data
.driver_location
;
822 LLVMValueRef data
[4];
823 unsigned loc
= variable
->data
.location
;
825 for (unsigned i
= 0; i
< attrib_count
; i
++) {
826 /* Packed components share the same location so skip
827 * them if we have already processed the location.
829 if (processed_inputs
& ((uint64_t)1 << loc
)) {
834 if (nir
->info
.stage
== MESA_SHADER_VERTEX
) {
835 declare_nir_input_vs(ctx
, variable
, input_idx
/ 4, data
);
836 bitcast_inputs(ctx
, data
, input_idx
);
837 if (glsl_type_is_dual_slot(variable
->type
)) {
839 declare_nir_input_vs(ctx
, variable
, input_idx
/ 4, data
);
840 bitcast_inputs(ctx
, data
, input_idx
);
842 } else if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
843 declare_nir_input_fs(ctx
, variable
, input_idx
/ 4, data
);
844 bitcast_inputs(ctx
, data
, input_idx
);
847 processed_inputs
|= ((uint64_t)1 << loc
);
854 ctx
->abi
.inputs
= &ctx
->inputs
[0];
855 ctx
->abi
.load_sampler_desc
= si_nir_load_sampler_desc
;
856 ctx
->abi
.clamp_shadow_reference
= true;
858 ctx
->num_samplers
= util_last_bit(info
->samplers_declared
);
859 ctx
->num_images
= util_last_bit(info
->images_declared
);
861 if (ctx
->shader
->selector
->local_size
) {
862 assert(nir
->info
.stage
== MESA_SHADER_COMPUTE
);
863 si_declare_compute_memory(ctx
);
865 ac_nir_translate(&ctx
->ac
, &ctx
->abi
, nir
);