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radeonsi/nir: clean up gather_intrinsic_load_deref_input_info
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 #include "tgsi/tgsi_from_mesa.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34 #include "compiler/nir/nir_builder.h"
35
36 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
37 {
38 for (unsigned i = 0; i < instr->num_srcs; i++) {
39 switch (instr->src[i].src_type) {
40 case nir_tex_src_texture_deref:
41 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
42 default:
43 break;
44 }
45 }
46
47 return NULL;
48 }
49
50 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
51 {
52 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
53 }
54
55 static void gather_intrinsic_load_deref_input_info(const nir_shader *nir,
56 const nir_intrinsic_instr *instr,
57 nir_variable *var,
58 struct tgsi_shader_info *info)
59 {
60 assert(var && var->data.mode == nir_var_shader_in);
61
62 switch (nir->info.stage) {
63 case MESA_SHADER_VERTEX: {
64 unsigned i = var->data.driver_location;
65 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
66
67 for (unsigned j = 0; j < attrib_count; j++, i++) {
68 if (glsl_type_is_64bit(glsl_without_array(var->type))) {
69 /* TODO: set usage mask more accurately for doubles */
70 info->input_usage_mask[i] = TGSI_WRITEMASK_XYZW;
71 } else {
72 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
73 info->input_usage_mask[i] |= mask << var->data.location_frac;
74 }
75 }
76 break;
77 }
78 case MESA_SHADER_FRAGMENT:
79 if (var->data.location == VARYING_SLOT_COL0 ||
80 var->data.location == VARYING_SLOT_COL1) {
81 unsigned index = var->data.location == VARYING_SLOT_COL1;
82 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
83 info->colors_read |= mask << (index * 4);
84 }
85 break;
86 default:;
87 }
88 }
89
90 static void gather_intrinsic_load_deref_output_info(const nir_shader *nir,
91 const nir_intrinsic_instr *instr,
92 nir_variable *var,
93 struct tgsi_shader_info *info)
94 {
95 assert(var && var->data.mode == nir_var_shader_out);
96
97 switch (nir->info.stage) {
98 case MESA_SHADER_FRAGMENT:
99 if (var->data.fb_fetch_output)
100 info->uses_fbfetch = true;
101 break;
102 default:;
103 }
104 }
105
106 static void scan_instruction(const struct nir_shader *nir,
107 struct tgsi_shader_info *info,
108 nir_instr *instr)
109 {
110 if (instr->type == nir_instr_type_alu) {
111 nir_alu_instr *alu = nir_instr_as_alu(instr);
112
113 switch (alu->op) {
114 case nir_op_fddx:
115 case nir_op_fddy:
116 case nir_op_fddx_fine:
117 case nir_op_fddy_fine:
118 case nir_op_fddx_coarse:
119 case nir_op_fddy_coarse:
120 info->uses_derivatives = true;
121 break;
122 default:
123 break;
124 }
125 } else if (instr->type == nir_instr_type_tex) {
126 nir_tex_instr *tex = nir_instr_as_tex(instr);
127 nir_variable *texture = tex_get_texture_var(tex);
128
129 if (!texture) {
130 info->samplers_declared |=
131 u_bit_consecutive(tex->sampler_index, 1);
132 } else {
133 if (texture->data.bindless)
134 info->uses_bindless_samplers = true;
135 }
136
137 switch (tex->op) {
138 case nir_texop_tex:
139 case nir_texop_txb:
140 case nir_texop_lod:
141 info->uses_derivatives = true;
142 break;
143 default:
144 break;
145 }
146 } else if (instr->type == nir_instr_type_intrinsic) {
147 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
148
149 switch (intr->intrinsic) {
150 case nir_intrinsic_load_front_face:
151 info->uses_frontface = 1;
152 break;
153 case nir_intrinsic_load_instance_id:
154 info->uses_instanceid = 1;
155 break;
156 case nir_intrinsic_load_invocation_id:
157 info->uses_invocationid = true;
158 break;
159 case nir_intrinsic_load_num_work_groups:
160 info->uses_grid_size = true;
161 break;
162 case nir_intrinsic_load_local_group_size:
163 /* The block size is translated to IMM with a fixed block size. */
164 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
165 info->uses_block_size = true;
166 break;
167 case nir_intrinsic_load_local_invocation_id:
168 case nir_intrinsic_load_work_group_id: {
169 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
170 while (mask) {
171 unsigned i = u_bit_scan(&mask);
172
173 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
174 info->uses_block_id[i] = true;
175 else
176 info->uses_thread_id[i] = true;
177 }
178 break;
179 }
180 case nir_intrinsic_load_vertex_id:
181 info->uses_vertexid = 1;
182 break;
183 case nir_intrinsic_load_vertex_id_zero_base:
184 info->uses_vertexid_nobase = 1;
185 break;
186 case nir_intrinsic_load_base_vertex:
187 info->uses_basevertex = 1;
188 break;
189 case nir_intrinsic_load_draw_id:
190 info->uses_drawid = 1;
191 break;
192 case nir_intrinsic_load_primitive_id:
193 info->uses_primid = 1;
194 break;
195 case nir_intrinsic_load_sample_mask_in:
196 info->reads_samplemask = true;
197 break;
198 case nir_intrinsic_load_tess_level_inner:
199 case nir_intrinsic_load_tess_level_outer:
200 info->reads_tess_factors = true;
201 break;
202 case nir_intrinsic_bindless_image_load:
203 info->uses_bindless_images = true;
204
205 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
206 info->uses_bindless_buffer_load = true;
207 else
208 info->uses_bindless_image_load = true;
209 break;
210 case nir_intrinsic_bindless_image_size:
211 case nir_intrinsic_bindless_image_samples:
212 info->uses_bindless_images = true;
213 break;
214 case nir_intrinsic_bindless_image_store:
215 info->uses_bindless_images = true;
216
217 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
218 info->uses_bindless_buffer_store = true;
219 else
220 info->uses_bindless_image_store = true;
221
222 info->writes_memory = true;
223 break;
224 case nir_intrinsic_image_deref_store:
225 info->writes_memory = true;
226 break;
227 case nir_intrinsic_bindless_image_atomic_add:
228 case nir_intrinsic_bindless_image_atomic_min:
229 case nir_intrinsic_bindless_image_atomic_max:
230 case nir_intrinsic_bindless_image_atomic_and:
231 case nir_intrinsic_bindless_image_atomic_or:
232 case nir_intrinsic_bindless_image_atomic_xor:
233 case nir_intrinsic_bindless_image_atomic_exchange:
234 case nir_intrinsic_bindless_image_atomic_comp_swap:
235 info->uses_bindless_images = true;
236
237 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
238 info->uses_bindless_buffer_atomic = true;
239 else
240 info->uses_bindless_image_atomic = true;
241
242 info->writes_memory = true;
243 break;
244 case nir_intrinsic_image_deref_atomic_add:
245 case nir_intrinsic_image_deref_atomic_min:
246 case nir_intrinsic_image_deref_atomic_max:
247 case nir_intrinsic_image_deref_atomic_and:
248 case nir_intrinsic_image_deref_atomic_or:
249 case nir_intrinsic_image_deref_atomic_xor:
250 case nir_intrinsic_image_deref_atomic_exchange:
251 case nir_intrinsic_image_deref_atomic_comp_swap:
252 info->writes_memory = true;
253 break;
254 case nir_intrinsic_store_ssbo:
255 case nir_intrinsic_ssbo_atomic_add:
256 case nir_intrinsic_ssbo_atomic_imin:
257 case nir_intrinsic_ssbo_atomic_umin:
258 case nir_intrinsic_ssbo_atomic_imax:
259 case nir_intrinsic_ssbo_atomic_umax:
260 case nir_intrinsic_ssbo_atomic_and:
261 case nir_intrinsic_ssbo_atomic_or:
262 case nir_intrinsic_ssbo_atomic_xor:
263 case nir_intrinsic_ssbo_atomic_exchange:
264 case nir_intrinsic_ssbo_atomic_comp_swap:
265 info->writes_memory = true;
266 break;
267 case nir_intrinsic_load_deref: {
268 nir_variable *var = intrinsic_get_var(intr);
269 nir_variable_mode mode = var->data.mode;
270 enum glsl_base_type base_type =
271 glsl_get_base_type(glsl_without_array(var->type));
272
273 if (mode == nir_var_shader_in) {
274 gather_intrinsic_load_deref_input_info(nir, intr, var, info);
275
276 switch (var->data.interpolation) {
277 case INTERP_MODE_NONE:
278 if (glsl_base_type_is_integer(base_type))
279 break;
280
281 /* fall-through */
282 case INTERP_MODE_SMOOTH:
283 if (var->data.sample)
284 info->uses_persp_sample = true;
285 else if (var->data.centroid)
286 info->uses_persp_centroid = true;
287 else
288 info->uses_persp_center = true;
289 break;
290
291 case INTERP_MODE_NOPERSPECTIVE:
292 if (var->data.sample)
293 info->uses_linear_sample = true;
294 else if (var->data.centroid)
295 info->uses_linear_centroid = true;
296 else
297 info->uses_linear_center = true;
298 break;
299 }
300 } else if (mode == nir_var_shader_out) {
301 gather_intrinsic_load_deref_output_info(nir, intr, var, info);
302 }
303 break;
304 }
305 case nir_intrinsic_interp_deref_at_centroid:
306 case nir_intrinsic_interp_deref_at_sample:
307 case nir_intrinsic_interp_deref_at_offset: {
308 enum glsl_interp_mode interp = intrinsic_get_var(intr)->data.interpolation;
309 switch (interp) {
310 case INTERP_MODE_SMOOTH:
311 case INTERP_MODE_NONE:
312 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
313 info->uses_persp_opcode_interp_centroid = true;
314 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
315 info->uses_persp_opcode_interp_sample = true;
316 else
317 info->uses_persp_opcode_interp_offset = true;
318 break;
319 case INTERP_MODE_NOPERSPECTIVE:
320 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
321 info->uses_linear_opcode_interp_centroid = true;
322 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
323 info->uses_linear_opcode_interp_sample = true;
324 else
325 info->uses_linear_opcode_interp_offset = true;
326 break;
327 case INTERP_MODE_FLAT:
328 break;
329 default:
330 unreachable("Unsupported interpoation type");
331 }
332 break;
333 }
334 default:
335 break;
336 }
337 }
338 }
339
340 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
341 struct tgsi_tessctrl_info *out)
342 {
343 memset(out, 0, sizeof(*out));
344
345 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
346 return;
347
348 out->tessfactors_are_def_in_all_invocs =
349 ac_are_tessfactors_def_in_all_invocs(nir);
350 }
351
352 void si_nir_scan_shader(const struct nir_shader *nir,
353 struct tgsi_shader_info *info)
354 {
355 nir_function *func;
356 unsigned i;
357
358 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
359 info->num_tokens = 2; /* indicate that the shader is non-empty */
360 info->num_instructions = 2;
361
362 info->properties[TGSI_PROPERTY_NEXT_SHADER] =
363 pipe_shader_type_from_mesa(nir->info.next_stage);
364
365 if (nir->info.stage == MESA_SHADER_VERTEX) {
366 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
367 nir->info.vs.window_space_position;
368 }
369
370 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
371 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
372 nir->info.tess.tcs_vertices_out;
373 }
374
375 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
376 if (nir->info.tess.primitive_mode == GL_ISOLINES)
377 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
378 else
379 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
380
381 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
382 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
383 PIPE_TESS_SPACING_FRACTIONAL_ODD);
384 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
385 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
386
387 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
388 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
389 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
390 }
391
392 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
393 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
394 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
395 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
396 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
397 }
398
399 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
400 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
401 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
402 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
403
404 if (nir->info.fs.pixel_center_integer) {
405 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
406 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
407 }
408
409 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
410 switch (nir->info.fs.depth_layout) {
411 case FRAG_DEPTH_LAYOUT_ANY:
412 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
413 break;
414 case FRAG_DEPTH_LAYOUT_GREATER:
415 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
416 break;
417 case FRAG_DEPTH_LAYOUT_LESS:
418 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
419 break;
420 case FRAG_DEPTH_LAYOUT_UNCHANGED:
421 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
422 break;
423 default:
424 unreachable("Unknow depth layout");
425 }
426 }
427 }
428
429 if (gl_shader_stage_is_compute(nir->info.stage)) {
430 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
431 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
432 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
433 }
434
435 i = 0;
436 uint64_t processed_inputs = 0;
437 unsigned num_inputs = 0;
438 nir_foreach_variable(variable, &nir->inputs) {
439 unsigned semantic_name, semantic_index;
440
441 const struct glsl_type *type = variable->type;
442 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
443 assert(glsl_type_is_array(type));
444 type = glsl_get_array_element(type);
445 }
446
447 unsigned attrib_count = glsl_count_attribute_slots(type,
448 nir->info.stage == MESA_SHADER_VERTEX);
449
450 i = variable->data.driver_location;
451
452 /* Vertex shader inputs don't have semantics. The state
453 * tracker has already mapped them to attributes via
454 * variable->data.driver_location.
455 */
456 if (nir->info.stage == MESA_SHADER_VERTEX) {
457 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)))
458 num_inputs++;
459
460 num_inputs++;
461 continue;
462 }
463
464 for (unsigned j = 0; j < attrib_count; j++, i++) {
465
466 if (processed_inputs & ((uint64_t)1 << i))
467 continue;
468
469 processed_inputs |= ((uint64_t)1 << i);
470 num_inputs++;
471
472 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
473 &semantic_name, &semantic_index);
474
475 info->input_semantic_name[i] = semantic_name;
476 info->input_semantic_index[i] = semantic_index;
477
478 if (semantic_name == TGSI_SEMANTIC_PRIMID)
479 info->uses_primid = true;
480
481 enum glsl_base_type base_type =
482 glsl_get_base_type(glsl_without_array(variable->type));
483
484 switch (variable->data.interpolation) {
485 case INTERP_MODE_NONE:
486 if (glsl_base_type_is_integer(base_type)) {
487 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
488 break;
489 }
490
491 if (semantic_name == TGSI_SEMANTIC_COLOR) {
492 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
493 break;
494 }
495 /* fall-through */
496
497 case INTERP_MODE_SMOOTH:
498 assert(!glsl_base_type_is_integer(base_type));
499
500 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
501 break;
502
503 case INTERP_MODE_NOPERSPECTIVE:
504 assert(!glsl_base_type_is_integer(base_type));
505
506 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
507 break;
508
509 case INTERP_MODE_FLAT:
510 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
511 break;
512 }
513 }
514 }
515
516 info->num_inputs = num_inputs;
517
518 i = 0;
519 uint64_t processed_outputs = 0;
520 unsigned num_outputs = 0;
521 nir_foreach_variable(variable, &nir->outputs) {
522 unsigned semantic_name, semantic_index;
523
524 i = variable->data.driver_location;
525
526 const struct glsl_type *type = variable->type;
527 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
528 assert(glsl_type_is_array(type));
529 type = glsl_get_array_element(type);
530 }
531
532 unsigned attrib_count = glsl_count_attribute_slots(type, false);
533 for (unsigned k = 0; k < attrib_count; k++, i++) {
534
535 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
536 tgsi_get_gl_frag_result_semantic(variable->data.location + k,
537 &semantic_name, &semantic_index);
538
539 /* Adjust for dual source blending */
540 if (variable->data.index > 0) {
541 semantic_index++;
542 }
543 } else {
544 tgsi_get_gl_varying_semantic(variable->data.location + k, true,
545 &semantic_name, &semantic_index);
546 }
547
548 unsigned num_components = 4;
549 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
550 if (vector_elements)
551 num_components = vector_elements;
552
553 unsigned component = variable->data.location_frac;
554 if (glsl_type_is_64bit(glsl_without_array(variable->type))) {
555 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)) && k % 2) {
556 num_components = (num_components * 2) - 4;
557 component = 0;
558 } else {
559 num_components = MIN2(num_components * 2, 4);
560 }
561 }
562
563 ubyte usagemask = 0;
564 for (unsigned j = component; j < num_components + component; j++) {
565 switch (j) {
566 case 0:
567 usagemask |= TGSI_WRITEMASK_X;
568 break;
569 case 1:
570 usagemask |= TGSI_WRITEMASK_Y;
571 break;
572 case 2:
573 usagemask |= TGSI_WRITEMASK_Z;
574 break;
575 case 3:
576 usagemask |= TGSI_WRITEMASK_W;
577 break;
578 default:
579 unreachable("error calculating component index");
580 }
581 }
582
583 unsigned gs_out_streams;
584 if (variable->data.stream & (1u << 31)) {
585 gs_out_streams = variable->data.stream & ~(1u << 31);
586 } else {
587 assert(variable->data.stream < 4);
588 gs_out_streams = 0;
589 for (unsigned j = 0; j < num_components; ++j)
590 gs_out_streams |= variable->data.stream << (2 * (component + j));
591 }
592
593 unsigned streamx = gs_out_streams & 3;
594 unsigned streamy = (gs_out_streams >> 2) & 3;
595 unsigned streamz = (gs_out_streams >> 4) & 3;
596 unsigned streamw = (gs_out_streams >> 6) & 3;
597
598 if (usagemask & TGSI_WRITEMASK_X) {
599 info->output_usagemask[i] |= TGSI_WRITEMASK_X;
600 info->output_streams[i] |= streamx;
601 info->num_stream_output_components[streamx]++;
602 }
603 if (usagemask & TGSI_WRITEMASK_Y) {
604 info->output_usagemask[i] |= TGSI_WRITEMASK_Y;
605 info->output_streams[i] |= streamy << 2;
606 info->num_stream_output_components[streamy]++;
607 }
608 if (usagemask & TGSI_WRITEMASK_Z) {
609 info->output_usagemask[i] |= TGSI_WRITEMASK_Z;
610 info->output_streams[i] |= streamz << 4;
611 info->num_stream_output_components[streamz]++;
612 }
613 if (usagemask & TGSI_WRITEMASK_W) {
614 info->output_usagemask[i] |= TGSI_WRITEMASK_W;
615 info->output_streams[i] |= streamw << 6;
616 info->num_stream_output_components[streamw]++;
617 }
618
619 /* make sure we only count this location once against
620 * the num_outputs counter.
621 */
622 if (processed_outputs & ((uint64_t)1 << i))
623 continue;
624
625 processed_outputs |= ((uint64_t)1 << i);
626 num_outputs++;
627
628 info->output_semantic_name[i] = semantic_name;
629 info->output_semantic_index[i] = semantic_index;
630
631 switch (semantic_name) {
632 case TGSI_SEMANTIC_PRIMID:
633 info->writes_primid = true;
634 break;
635 case TGSI_SEMANTIC_VIEWPORT_INDEX:
636 info->writes_viewport_index = true;
637 break;
638 case TGSI_SEMANTIC_LAYER:
639 info->writes_layer = true;
640 break;
641 case TGSI_SEMANTIC_PSIZE:
642 info->writes_psize = true;
643 break;
644 case TGSI_SEMANTIC_CLIPVERTEX:
645 info->writes_clipvertex = true;
646 break;
647 case TGSI_SEMANTIC_COLOR:
648 info->colors_written |= 1 << semantic_index;
649 break;
650 case TGSI_SEMANTIC_STENCIL:
651 info->writes_stencil = true;
652 break;
653 case TGSI_SEMANTIC_SAMPLEMASK:
654 info->writes_samplemask = true;
655 break;
656 case TGSI_SEMANTIC_EDGEFLAG:
657 info->writes_edgeflag = true;
658 break;
659 case TGSI_SEMANTIC_POSITION:
660 if (info->processor == PIPE_SHADER_FRAGMENT)
661 info->writes_z = true;
662 else
663 info->writes_position = true;
664 break;
665 }
666
667 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
668 switch (semantic_name) {
669 case TGSI_SEMANTIC_PATCH:
670 info->reads_perpatch_outputs = true;
671 break;
672 case TGSI_SEMANTIC_TESSINNER:
673 case TGSI_SEMANTIC_TESSOUTER:
674 info->reads_tessfactor_outputs = true;
675 break;
676 default:
677 info->reads_pervertex_outputs = true;
678 }
679 }
680 }
681
682 unsigned loc = variable->data.location;
683 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
684 loc == FRAG_RESULT_COLOR &&
685 nir->info.outputs_written & (1ull << loc)) {
686 assert(attrib_count == 1);
687 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
688 }
689 }
690
691 info->num_outputs = num_outputs;
692
693 struct set *ubo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
694 _mesa_key_pointer_equal);
695 struct set *ssbo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
696 _mesa_key_pointer_equal);
697
698 /* Intialise const_file_max[0] */
699 info->const_file_max[0] = -1;
700
701 /* The first 8 are reserved for atomic counters using ssbo */
702 unsigned ssbo_idx = 8;
703
704 unsigned ubo_idx = 1;
705 nir_foreach_variable(variable, &nir->uniforms) {
706 const struct glsl_type *type = variable->type;
707 enum glsl_base_type base_type =
708 glsl_get_base_type(glsl_without_array(type));
709 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
710 unsigned loc = variable->data.driver_location / 4;
711 int slot_count = glsl_count_attribute_slots(type, false);
712 int max_slot = MAX2(info->const_file_max[0], (int) loc) + slot_count;
713
714 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
715 * really use the mask (other than ubo_idx == 1 for regular
716 * uniforms) its really only used for getting the buffer count
717 * so we don't need to worry about the ordering.
718 */
719 if (variable->interface_type != NULL) {
720 if (variable->data.mode == nir_var_uniform ||
721 variable->data.mode == nir_var_mem_ubo ||
722 variable->data.mode == nir_var_mem_ssbo) {
723
724 struct set *buf_set = variable->data.mode == nir_var_mem_ssbo ?
725 ssbo_set : ubo_set;
726
727 unsigned block_count;
728 if (base_type != GLSL_TYPE_INTERFACE) {
729 struct set_entry *entry =
730 _mesa_set_search(buf_set, variable->interface_type);
731
732 /* Check if we have already processed
733 * a member from this ubo.
734 */
735 if (entry)
736 continue;
737
738 block_count = 1;
739 } else {
740 block_count = aoa_size;
741 }
742
743 if (variable->data.mode == nir_var_uniform ||
744 variable->data.mode == nir_var_mem_ubo) {
745 info->const_buffers_declared |= u_bit_consecutive(ubo_idx, block_count);
746 ubo_idx += block_count;
747 } else {
748 assert(variable->data.mode == nir_var_mem_ssbo);
749
750 info->shader_buffers_declared |= u_bit_consecutive(ssbo_idx, block_count);
751 ssbo_idx += block_count;
752 }
753
754 _mesa_set_add(buf_set, variable->interface_type);
755 }
756
757 continue;
758 }
759
760 /* We rely on the fact that nir_lower_samplers_as_deref has
761 * eliminated struct dereferences.
762 */
763 if (base_type == GLSL_TYPE_SAMPLER && !variable->data.bindless) {
764 info->samplers_declared |=
765 u_bit_consecutive(variable->data.binding, aoa_size);
766 } else if (base_type == GLSL_TYPE_IMAGE && !variable->data.bindless) {
767 info->images_declared |=
768 u_bit_consecutive(variable->data.binding, aoa_size);
769 } else if (base_type != GLSL_TYPE_ATOMIC_UINT) {
770 info->const_buffers_declared |= 1;
771 info->const_file_max[0] = max_slot;
772 }
773 }
774
775 _mesa_set_destroy(ubo_set, NULL);
776 _mesa_set_destroy(ssbo_set, NULL);
777
778 info->num_written_clipdistance = nir->info.clip_distance_array_size;
779 info->num_written_culldistance = nir->info.cull_distance_array_size;
780 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
781 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
782
783 if (info->processor == PIPE_SHADER_FRAGMENT)
784 info->uses_kill = nir->info.fs.uses_discard;
785
786 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
787 nir_foreach_block(block, func->impl) {
788 nir_foreach_instr(instr, block)
789 scan_instruction(nir, info, instr);
790 }
791 }
792
793 void
794 si_nir_opts(struct nir_shader *nir)
795 {
796 bool progress;
797 unsigned lower_flrp =
798 (nir->options->lower_flrp16 ? 16 : 0) |
799 (nir->options->lower_flrp32 ? 32 : 0) |
800 (nir->options->lower_flrp64 ? 64 : 0);
801
802 do {
803 progress = false;
804
805 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
806
807 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
808 NIR_PASS(progress, nir, nir_opt_dead_write_vars);
809
810 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL);
811 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
812
813 /* (Constant) copy propagation is needed for txf with offsets. */
814 NIR_PASS(progress, nir, nir_copy_prop);
815 NIR_PASS(progress, nir, nir_opt_remove_phis);
816 NIR_PASS(progress, nir, nir_opt_dce);
817 if (nir_opt_trivial_continues(nir)) {
818 progress = true;
819 NIR_PASS(progress, nir, nir_copy_prop);
820 NIR_PASS(progress, nir, nir_opt_dce);
821 }
822 NIR_PASS(progress, nir, nir_opt_if, true);
823 NIR_PASS(progress, nir, nir_opt_dead_cf);
824 NIR_PASS(progress, nir, nir_opt_cse);
825 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
826
827 /* Needed for algebraic lowering */
828 NIR_PASS(progress, nir, nir_opt_algebraic);
829 NIR_PASS(progress, nir, nir_opt_constant_folding);
830
831 if (lower_flrp != 0) {
832 bool lower_flrp_progress = false;
833
834 NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp,
835 lower_flrp,
836 false /* always_precise */,
837 nir->options->lower_ffma);
838 if (lower_flrp_progress) {
839 NIR_PASS(progress, nir,
840 nir_opt_constant_folding);
841 progress = true;
842 }
843
844 /* Nothing should rematerialize any flrps, so we only
845 * need to do this lowering once.
846 */
847 lower_flrp = 0;
848 }
849
850 NIR_PASS(progress, nir, nir_opt_undef);
851 NIR_PASS(progress, nir, nir_opt_conditional_discard);
852 if (nir->options->max_unroll_iterations) {
853 NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
854 }
855 } while (progress);
856 }
857
858 static int
859 type_size_vec4(const struct glsl_type *type, bool bindless)
860 {
861 return glsl_count_attribute_slots(type, false);
862 }
863
864 static void
865 si_nir_lower_color(nir_shader *nir)
866 {
867 nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
868
869 nir_builder b;
870 nir_builder_init(&b, entrypoint);
871
872 nir_foreach_block(block, entrypoint) {
873 nir_foreach_instr_safe(instr, block) {
874 if (instr->type != nir_instr_type_intrinsic)
875 continue;
876
877 nir_intrinsic_instr *intrin =
878 nir_instr_as_intrinsic(instr);
879
880 if (intrin->intrinsic != nir_intrinsic_load_deref)
881 continue;
882
883 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
884 if (deref->mode != nir_var_shader_in)
885 continue;
886
887 b.cursor = nir_before_instr(instr);
888 nir_variable *var = nir_deref_instr_get_variable(deref);
889 nir_ssa_def *def;
890
891 if (var->data.location == VARYING_SLOT_COL0) {
892 def = nir_load_color0(&b);
893 } else if (var->data.location == VARYING_SLOT_COL1) {
894 def = nir_load_color1(&b);
895 } else {
896 continue;
897 }
898
899 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(def));
900 nir_instr_remove(instr);
901 }
902 }
903 }
904
905 /**
906 * Perform "lowering" operations on the NIR that are run once when the shader
907 * selector is created.
908 */
909 void
910 si_lower_nir(struct si_shader_selector* sel, unsigned wave_size)
911 {
912 /* Adjust the driver location of inputs and outputs. The state tracker
913 * interprets them as slots, while the ac/nir backend interprets them
914 * as individual components.
915 */
916 if (sel->nir->info.stage != MESA_SHADER_FRAGMENT) {
917 nir_foreach_variable(variable, &sel->nir->inputs)
918 variable->data.driver_location *= 4;
919 } else {
920 NIR_PASS_V(sel->nir, nir_lower_io_to_temporaries,
921 nir_shader_get_entrypoint(sel->nir), false, true);
922
923 /* Since we're doing nir_lower_io_to_temporaries late, we need
924 * to lower all the copy_deref's introduced by
925 * lower_io_to_temporaries before calling nir_lower_io.
926 */
927 NIR_PASS_V(sel->nir, nir_split_var_copies);
928 NIR_PASS_V(sel->nir, nir_lower_var_copies);
929 NIR_PASS_V(sel->nir, nir_lower_global_vars_to_local);
930
931 si_nir_lower_color(sel->nir);
932 NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
933
934 /* This pass needs actual constants */
935 NIR_PASS_V(sel->nir, nir_opt_constant_folding);
936 NIR_PASS_V(sel->nir, nir_io_add_const_offset_to_base,
937 nir_var_shader_in);
938 }
939
940 nir_foreach_variable(variable, &sel->nir->outputs) {
941 variable->data.driver_location *= 4;
942
943 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
944 if (variable->data.location == FRAG_RESULT_DEPTH)
945 variable->data.driver_location += 2;
946 else if (variable->data.location == FRAG_RESULT_STENCIL)
947 variable->data.driver_location += 1;
948 }
949 }
950
951 /* Perform lowerings (and optimizations) of code.
952 *
953 * Performance considerations aside, we must:
954 * - lower certain ALU operations
955 * - ensure constant offsets for texture instructions are folded
956 * and copy-propagated
957 */
958
959 static const struct nir_lower_tex_options lower_tex_options = {
960 .lower_txp = ~0u,
961 };
962 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
963
964 const nir_lower_subgroups_options subgroups_options = {
965 .subgroup_size = wave_size,
966 .ballot_bit_size = wave_size,
967 .lower_to_scalar = true,
968 .lower_subgroup_masks = true,
969 .lower_vote_trivial = false,
970 .lower_vote_eq_to_ballot = true,
971 };
972 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
973
974 ac_lower_indirect_derefs(sel->nir, sel->screen->info.chip_class);
975
976 si_nir_opts(sel->nir);
977
978 NIR_PASS_V(sel->nir, nir_lower_bool_to_int32);
979
980 /* Strip the resulting shader so that the shader cache is more likely
981 * to hit from other similar shaders.
982 */
983 nir_strip(sel->nir);
984 }
985
986 static void declare_nir_input_vs(struct si_shader_context *ctx,
987 struct nir_variable *variable,
988 unsigned input_index,
989 LLVMValueRef out[4])
990 {
991 si_llvm_load_input_vs(ctx, input_index, out);
992 }
993
994 LLVMValueRef
995 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
996 enum glsl_interp_mode interp, unsigned location)
997 {
998 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
999 int interp_param_idx = -1;
1000
1001 switch (interp) {
1002 case INTERP_MODE_FLAT:
1003 return NULL;
1004 case INTERP_MODE_SMOOTH:
1005 case INTERP_MODE_NONE:
1006 if (location == INTERP_CENTER)
1007 interp_param_idx = SI_PARAM_PERSP_CENTER;
1008 else if (location == INTERP_CENTROID)
1009 interp_param_idx = SI_PARAM_PERSP_CENTROID;
1010 else if (location == INTERP_SAMPLE)
1011 interp_param_idx = SI_PARAM_PERSP_SAMPLE;
1012 break;
1013 case INTERP_MODE_NOPERSPECTIVE:
1014 if (location == INTERP_CENTER)
1015 interp_param_idx = SI_PARAM_LINEAR_CENTER;
1016 else if (location == INTERP_CENTROID)
1017 interp_param_idx = SI_PARAM_LINEAR_CENTROID;
1018 else if (location == INTERP_SAMPLE)
1019 interp_param_idx = SI_PARAM_LINEAR_SAMPLE;
1020 break;
1021 default:
1022 assert(!"Unhandled interpolation mode.");
1023 return NULL;
1024 }
1025
1026 return interp_param_idx != -1 ?
1027 LLVMGetParam(ctx->main_fn, interp_param_idx) : NULL;
1028 }
1029
1030 static LLVMValueRef
1031 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
1032 unsigned descriptor_set, unsigned base_index,
1033 unsigned constant_index, LLVMValueRef dynamic_index,
1034 enum ac_descriptor_type desc_type, bool image,
1035 bool write, bool bindless)
1036 {
1037 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1038 LLVMBuilderRef builder = ctx->ac.builder;
1039 unsigned const_index = base_index + constant_index;
1040
1041 assert(!descriptor_set);
1042 assert(!image || desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
1043
1044 if (bindless) {
1045 LLVMValueRef list =
1046 LLVMGetParam(ctx->main_fn, ctx->param_bindless_samplers_and_images);
1047
1048 /* dynamic_index is the bindless handle */
1049 if (image) {
1050 /* For simplicity, bindless image descriptors use fixed
1051 * 16-dword slots for now.
1052 */
1053 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1054 LLVMConstInt(ctx->i64, 2, 0), "");
1055
1056 return si_load_image_desc(ctx, list, dynamic_index, desc_type,
1057 write, true);
1058 }
1059
1060 /* Since bindless handle arithmetic can contain an unsigned integer
1061 * wraparound and si_load_sampler_desc assumes there isn't any,
1062 * use GEP without "inbounds" (inside ac_build_pointer_add)
1063 * to prevent incorrect code generation and hangs.
1064 */
1065 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1066 LLVMConstInt(ctx->i64, 2, 0), "");
1067 list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
1068 return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
1069 }
1070
1071 unsigned num_slots = image ? ctx->num_images : ctx->num_samplers;
1072 assert(const_index < num_slots);
1073
1074 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1075 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, const_index, false);
1076
1077 if (dynamic_index) {
1078 index = LLVMBuildAdd(builder, index, dynamic_index, "");
1079
1080 /* From the GL_ARB_shader_image_load_store extension spec:
1081 *
1082 * If a shader performs an image load, store, or atomic
1083 * operation using an image variable declared as an array,
1084 * and if the index used to select an individual element is
1085 * negative or greater than or equal to the size of the
1086 * array, the results of the operation are undefined but may
1087 * not lead to termination.
1088 */
1089 index = si_llvm_bound_index(ctx, index, num_slots);
1090 }
1091
1092 if (image) {
1093 index = LLVMBuildSub(ctx->ac.builder,
1094 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
1095 index, "");
1096 return si_load_image_desc(ctx, list, index, desc_type, write, false);
1097 }
1098
1099 index = LLVMBuildAdd(ctx->ac.builder, index,
1100 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1101 return si_load_sampler_desc(ctx, list, index, desc_type);
1102 }
1103
1104 static void bitcast_inputs(struct si_shader_context *ctx,
1105 LLVMValueRef data[4],
1106 unsigned input_idx)
1107 {
1108 for (unsigned chan = 0; chan < 4; chan++) {
1109 ctx->inputs[input_idx + chan] =
1110 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
1111 }
1112 }
1113
1114 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
1115 {
1116 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1117
1118 if (nir->info.stage == MESA_SHADER_VERTEX) {
1119 uint64_t processed_inputs = 0;
1120 nir_foreach_variable(variable, &nir->inputs) {
1121 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
1122 true);
1123 unsigned input_idx = variable->data.driver_location;
1124
1125 LLVMValueRef data[4];
1126 unsigned loc = variable->data.location;
1127
1128 for (unsigned i = 0; i < attrib_count; i++) {
1129 /* Packed components share the same location so skip
1130 * them if we have already processed the location.
1131 */
1132 if (processed_inputs & ((uint64_t)1 << (loc + i))) {
1133 input_idx += 4;
1134 continue;
1135 }
1136
1137 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1138 bitcast_inputs(ctx, data, input_idx);
1139 if (glsl_type_is_dual_slot(variable->type)) {
1140 input_idx += 4;
1141 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1142 bitcast_inputs(ctx, data, input_idx);
1143 }
1144
1145 processed_inputs |= ((uint64_t)1 << (loc + i));
1146 input_idx += 4;
1147 }
1148 }
1149 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1150 unsigned colors_read =
1151 ctx->shader->selector->info.colors_read;
1152 LLVMValueRef main_fn = ctx->main_fn;
1153
1154 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1155
1156 unsigned offset = SI_PARAM_POS_FIXED_PT + 1;
1157
1158 if (colors_read & 0x0f) {
1159 unsigned mask = colors_read & 0x0f;
1160 LLVMValueRef values[4];
1161 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1162 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1163 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1164 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1165 ctx->abi.color0 =
1166 ac_to_integer(&ctx->ac,
1167 ac_build_gather_values(&ctx->ac, values, 4));
1168 }
1169 if (colors_read & 0xf0) {
1170 unsigned mask = (colors_read & 0xf0) >> 4;
1171 LLVMValueRef values[4];
1172 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1173 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1174 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1175 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1176 ctx->abi.color1 =
1177 ac_to_integer(&ctx->ac,
1178 ac_build_gather_values(&ctx->ac, values, 4));
1179 }
1180 }
1181
1182 ctx->abi.inputs = &ctx->inputs[0];
1183 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
1184 ctx->abi.clamp_shadow_reference = true;
1185
1186 ctx->num_samplers = util_last_bit(info->samplers_declared);
1187 ctx->num_images = util_last_bit(info->images_declared);
1188
1189 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
1190 assert(gl_shader_stage_is_compute(nir->info.stage));
1191 si_declare_compute_memory(ctx);
1192 }
1193 ac_nir_translate(&ctx->ac, &ctx->abi, nir);
1194
1195 return true;
1196 }