src/gallium/drivers/radeonsi/si_shader_nir.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_shader.h"
  25 #include "si_shader_internal.h"
  26
  27 #include "ac_nir_to_llvm.h"
  28
  29 #include "tgsi/tgsi_from_mesa.h"
  30
  31 #include "compiler/nir/nir.h"
  32 #include "compiler/nir_types.h"
  33
  34
  35 static int
  36 type_size(const struct glsl_type *type)
  37 {
  38    return glsl_count_attribute_slots(type, false);
  39 }
  40
  41 static void scan_instruction(struct tgsi_shader_info *info,
  42                              nir_instr *instr)
  43 {
  44         if (instr->type == nir_instr_type_alu) {
  45                 nir_alu_instr *alu = nir_instr_as_alu(instr);
  46
  47                 switch (alu->op) {
  48                 case nir_op_fddx:
  49                 case nir_op_fddy:
  50                 case nir_op_fddx_fine:
  51                 case nir_op_fddy_fine:
  52                 case nir_op_fddx_coarse:
  53                 case nir_op_fddy_coarse:
  54                         info->uses_derivatives = true;
  55                         break;
  56                 default:
  57                         break;
  58                 }
  59         } else if (instr->type == nir_instr_type_tex) {
  60                 nir_tex_instr *tex = nir_instr_as_tex(instr);
  61
  62                 if (!tex->texture) {
  63                         info->samplers_declared |=
  64                                 u_bit_consecutive(tex->sampler_index, 1);
  65                 }
  66
  67                 switch (tex->op) {
  68                 case nir_texop_tex:
  69                 case nir_texop_txb:
  70                 case nir_texop_lod:
  71                         info->uses_derivatives = true;
  72                         break;
  73                 default:
  74                         break;
  75                 }
  76         } else if (instr->type == nir_instr_type_intrinsic) {
  77                 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
  78
  79                 switch (intr->intrinsic) {
  80                 case nir_intrinsic_load_front_face:
  81                         info->uses_frontface = 1;
  82                         break;
  83                 case nir_intrinsic_load_instance_id:
  84                         info->uses_instanceid = 1;
  85                         break;
  86                 case nir_intrinsic_load_invocation_id:
  87                         info->uses_invocationid = true;
  88                         break;
  89                 case nir_intrinsic_load_vertex_id:
  90                         info->uses_vertexid = 1;
  91                         break;
  92                 case nir_intrinsic_load_vertex_id_zero_base:
  93                         info->uses_vertexid_nobase = 1;
  94                         break;
  95                 case nir_intrinsic_load_base_vertex:
  96                         info->uses_basevertex = 1;
  97                         break;
  98                 case nir_intrinsic_load_primitive_id:
  99                         info->uses_primid = 1;
 100                         break;
 101                 case nir_intrinsic_load_sample_mask_in:
 102                         info->reads_samplemask = true;
 103                         break;
 104                 case nir_intrinsic_load_tess_level_inner:
 105                 case nir_intrinsic_load_tess_level_outer:
 106                         info->reads_tess_factors = true;
 107                         break;
 108                 case nir_intrinsic_image_store:
 109                 case nir_intrinsic_image_atomic_add:
 110                 case nir_intrinsic_image_atomic_min:
 111                 case nir_intrinsic_image_atomic_max:
 112                 case nir_intrinsic_image_atomic_and:
 113                 case nir_intrinsic_image_atomic_or:
 114                 case nir_intrinsic_image_atomic_xor:
 115                 case nir_intrinsic_image_atomic_exchange:
 116                 case nir_intrinsic_image_atomic_comp_swap:
 117                 case nir_intrinsic_store_ssbo:
 118                 case nir_intrinsic_ssbo_atomic_add:
 119                 case nir_intrinsic_ssbo_atomic_imin:
 120                 case nir_intrinsic_ssbo_atomic_umin:
 121                 case nir_intrinsic_ssbo_atomic_imax:
 122                 case nir_intrinsic_ssbo_atomic_umax:
 123                 case nir_intrinsic_ssbo_atomic_and:
 124                 case nir_intrinsic_ssbo_atomic_or:
 125                 case nir_intrinsic_ssbo_atomic_xor:
 126                 case nir_intrinsic_ssbo_atomic_exchange:
 127                 case nir_intrinsic_ssbo_atomic_comp_swap:
 128                         info->writes_memory = true;
 129                         break;
 130                 default:
 131                         break;
 132                 }
 133         }
 134 }
 135
 136 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
 137                            const struct tgsi_shader_info *info,
 138                            struct tgsi_tessctrl_info *out)
 139 {
 140         memset(out, 0, sizeof(*out));
 141
 142         if (nir->info.stage != MESA_SHADER_TESS_CTRL)
 143                 return;
 144
 145         /* Initial value = true. Here the pass will accumulate results from
 146          * multiple segments surrounded by barriers. If tess factors aren't
 147          * written at all, it's a shader bug and we don't care if this will be
 148          * true.
 149          */
 150         out->tessfactors_are_def_in_all_invocs = true;
 151
 152         /* TODO: Implement scanning of tess factors, see tgsi backend. */
 153 }
 154
 155 void si_nir_scan_shader(const struct nir_shader *nir,
 156                         struct tgsi_shader_info *info)
 157 {
 158         nir_function *func;
 159         unsigned i;
 160
 161         assert(nir->info.stage == MESA_SHADER_VERTEX ||
 162                nir->info.stage == MESA_SHADER_GEOMETRY ||
 163                nir->info.stage == MESA_SHADER_TESS_CTRL ||
 164                nir->info.stage == MESA_SHADER_TESS_EVAL ||
 165                nir->info.stage == MESA_SHADER_FRAGMENT);
 166
 167         info->processor = pipe_shader_type_from_mesa(nir->info.stage);
 168         info->num_tokens = 2; /* indicate that the shader is non-empty */
 169         info->num_instructions = 2;
 170
 171         if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
 172                 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
 173                         nir->info.tess.tcs_vertices_out;
 174         }
 175
 176         if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
 177                 if (nir->info.tess.primitive_mode == GL_ISOLINES)
 178                         info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
 179                 else
 180                         info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
 181
 182                 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
 183                 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
 184                               PIPE_TESS_SPACING_FRACTIONAL_ODD);
 185                 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
 186                               PIPE_TESS_SPACING_FRACTIONAL_EVEN);
 187
 188                 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
 189                 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
 190                 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
 191         }
 192
 193         if (nir->info.stage == MESA_SHADER_GEOMETRY) {
 194                 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
 195                 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
 196                 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
 197                 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
 198         }
 199
 200         i = 0;
 201         uint64_t processed_inputs = 0;
 202         unsigned num_inputs = 0;
 203         nir_foreach_variable(variable, &nir->inputs) {
 204                 unsigned semantic_name, semantic_index;
 205                 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
 206                                                                    nir->info.stage == MESA_SHADER_VERTEX);
 207
 208                 /* Vertex shader inputs don't have semantics. The state
 209                  * tracker has already mapped them to attributes via
 210                  * variable->data.driver_location.
 211                  */
 212                 if (nir->info.stage == MESA_SHADER_VERTEX)
 213                         continue;
 214
 215                 assert(nir->info.stage != MESA_SHADER_FRAGMENT ||
 216                        (attrib_count == 1 && "not implemented"));
 217
 218                 /* Fragment shader position is a system value. */
 219                 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
 220                     variable->data.location == VARYING_SLOT_POS) {
 221                         if (variable->data.pixel_center_integer)
 222                                 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
 223                                         TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
 224
 225                         num_inputs++;
 226                         continue;
 227                 }
 228
 229                 i = variable->data.driver_location;
 230                 if (processed_inputs & ((uint64_t)1 << i))
 231                         continue;
 232
 233                 processed_inputs |= ((uint64_t)1 << i);
 234                 num_inputs++;
 235
 236                 tgsi_get_gl_varying_semantic(variable->data.location, true,
 237                                              &semantic_name, &semantic_index);
 238
 239                 info->input_semantic_name[i] = semantic_name;
 240                 info->input_semantic_index[i] = semantic_index;
 241
 242                 if (semantic_name == TGSI_SEMANTIC_PRIMID)
 243                         info->uses_primid = true;
 244
 245                 if (variable->data.sample)
 246                         info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
 247                 else if (variable->data.centroid)
 248                         info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
 249                 else
 250                         info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
 251
 252                 enum glsl_base_type base_type =
 253                         glsl_get_base_type(glsl_without_array(variable->type));
 254
 255                 switch (variable->data.interpolation) {
 256                 case INTERP_MODE_NONE:
 257                         if (glsl_base_type_is_integer(base_type)) {
 258                                 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
 259                                 break;
 260                         }
 261
 262                         if (semantic_name == TGSI_SEMANTIC_COLOR) {
 263                                 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
 264                                 goto persp_locations;
 265                         }
 266                         /* fall-through */
 267                 case INTERP_MODE_SMOOTH:
 268                         assert(!glsl_base_type_is_integer(base_type));
 269
 270                         info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
 271
 272                 persp_locations:
 273                         if (variable->data.sample)
 274                                 info->uses_persp_sample = true;
 275                         else if (variable->data.centroid)
 276                                 info->uses_persp_centroid = true;
 277                         else
 278                                 info->uses_persp_center = true;
 279                         break;
 280
 281                 case INTERP_MODE_NOPERSPECTIVE:
 282                         assert(!glsl_base_type_is_integer(base_type));
 283
 284                         info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
 285
 286                         if (variable->data.sample)
 287                                 info->uses_linear_sample = true;
 288                         else if (variable->data.centroid)
 289                                 info->uses_linear_centroid = true;
 290                         else
 291                                 info->uses_linear_center = true;
 292                         break;
 293
 294                 case INTERP_MODE_FLAT:
 295                         info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
 296                         break;
 297                 }
 298
 299                 /* TODO make this more precise */
 300                 if (variable->data.location == VARYING_SLOT_COL0)
 301                         info->colors_read |= 0x0f;
 302                 else if (variable->data.location == VARYING_SLOT_COL1)
 303                         info->colors_read |= 0xf0;
 304         }
 305
 306         if (nir->info.stage != MESA_SHADER_VERTEX)
 307                 info->num_inputs = num_inputs;
 308         else
 309                 info->num_inputs = nir->num_inputs;
 310
 311         i = 0;
 312         uint64_t processed_outputs = 0;
 313         unsigned num_outputs = 0;
 314         nir_foreach_variable(variable, &nir->outputs) {
 315                 unsigned semantic_name, semantic_index;
 316
 317                 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 318                         tgsi_get_gl_frag_result_semantic(variable->data.location,
 319                                 &semantic_name, &semantic_index);
 320                 } else {
 321                         tgsi_get_gl_varying_semantic(variable->data.location, true,
 322                                                      &semantic_name, &semantic_index);
 323                 }
 324
 325                 i = variable->data.driver_location;
 326                 if (processed_outputs & ((uint64_t)1 << i))
 327                         continue;
 328
 329                 processed_outputs |= ((uint64_t)1 << i);
 330                 num_outputs++;
 331
 332                 info->output_semantic_name[i] = semantic_name;
 333                 info->output_semantic_index[i] = semantic_index;
 334                 info->output_usagemask[i] = TGSI_WRITEMASK_XYZW;
 335
 336                 unsigned num_components = 4;
 337                 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
 338                 if (vector_elements)
 339                         num_components = vector_elements;
 340
 341                 unsigned gs_out_streams;
 342                 if (variable->data.stream & (1u << 31)) {
 343                         gs_out_streams = variable->data.stream & ~(1u << 31);
 344                 } else {
 345                         assert(variable->data.stream < 4);
 346                         gs_out_streams = 0;
 347                         for (unsigned j = 0; j < num_components; ++j)
 348                                 gs_out_streams |= variable->data.stream << (2 * (variable->data.location_frac + j));
 349                 }
 350
 351                 unsigned streamx = gs_out_streams & 3;
 352                 unsigned streamy = (gs_out_streams >> 2) & 3;
 353                 unsigned streamz = (gs_out_streams >> 4) & 3;
 354                 unsigned streamw = (gs_out_streams >> 6) & 3;
 355
 356                 if (info->output_usagemask[i] & TGSI_WRITEMASK_X) {
 357                         info->output_streams[i] |= streamx;
 358                         info->num_stream_output_components[streamx]++;
 359                 }
 360                 if (info->output_usagemask[i] & TGSI_WRITEMASK_Y) {
 361                         info->output_streams[i] |= streamy << 2;
 362                         info->num_stream_output_components[streamy]++;
 363                 }
 364                 if (info->output_usagemask[i] & TGSI_WRITEMASK_Z) {
 365                         info->output_streams[i] |= streamz << 4;
 366                         info->num_stream_output_components[streamz]++;
 367                 }
 368                 if (info->output_usagemask[i] & TGSI_WRITEMASK_W) {
 369                         info->output_streams[i] |= streamw << 6;
 370                         info->num_stream_output_components[streamw]++;
 371                 }
 372
 373                 switch (semantic_name) {
 374                 case TGSI_SEMANTIC_PRIMID:
 375                         info->writes_primid = true;
 376                         break;
 377                 case TGSI_SEMANTIC_VIEWPORT_INDEX:
 378                         info->writes_viewport_index = true;
 379                         break;
 380                 case TGSI_SEMANTIC_LAYER:
 381                         info->writes_layer = true;
 382                         break;
 383                 case TGSI_SEMANTIC_PSIZE:
 384                         info->writes_psize = true;
 385                         break;
 386                 case TGSI_SEMANTIC_CLIPVERTEX:
 387                         info->writes_clipvertex = true;
 388                         break;
 389                 case TGSI_SEMANTIC_COLOR:
 390                         info->colors_written |= 1 << semantic_index;
 391                         break;
 392                 case TGSI_SEMANTIC_STENCIL:
 393                         info->writes_stencil = true;
 394                         break;
 395                 case TGSI_SEMANTIC_SAMPLEMASK:
 396                         info->writes_samplemask = true;
 397                         break;
 398                 case TGSI_SEMANTIC_EDGEFLAG:
 399                         info->writes_edgeflag = true;
 400                         break;
 401                 case TGSI_SEMANTIC_POSITION:
 402                         if (info->processor == PIPE_SHADER_FRAGMENT)
 403                                 info->writes_z = true;
 404                         else
 405                                 info->writes_position = true;
 406                         break;
 407                 }
 408
 409                 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
 410                         switch (semantic_name) {
 411                         case TGSI_SEMANTIC_PATCH:
 412                                 info->reads_perpatch_outputs = true;
 413                         break;
 414                         case TGSI_SEMANTIC_TESSINNER:
 415                         case TGSI_SEMANTIC_TESSOUTER:
 416                                 info->reads_tessfactor_outputs = true;
 417                         break;
 418                         default:
 419                                 info->reads_pervertex_outputs = true;
 420                         }
 421                 }
 422         }
 423
 424         info->num_outputs = num_outputs;
 425
 426         nir_foreach_variable(variable, &nir->uniforms) {
 427                 const struct glsl_type *type = variable->type;
 428                 enum glsl_base_type base_type =
 429                         glsl_get_base_type(glsl_without_array(type));
 430                 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
 431
 432                 /* We rely on the fact that nir_lower_samplers_as_deref has
 433                  * eliminated struct dereferences.
 434                  */
 435                 if (base_type == GLSL_TYPE_SAMPLER)
 436                         info->samplers_declared |=
 437                                 u_bit_consecutive(variable->data.binding, aoa_size);
 438                 else if (base_type == GLSL_TYPE_IMAGE)
 439                         info->images_declared |=
 440                                 u_bit_consecutive(variable->data.binding, aoa_size);
 441         }
 442
 443         info->num_written_clipdistance = nir->info.clip_distance_array_size;
 444         info->num_written_culldistance = nir->info.cull_distance_array_size;
 445         info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
 446         info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
 447
 448         if (info->processor == PIPE_SHADER_FRAGMENT)
 449                 info->uses_kill = nir->info.fs.uses_discard;
 450
 451         /* TODO make this more accurate */
 452         info->const_buffers_declared = u_bit_consecutive(0, SI_NUM_CONST_BUFFERS);
 453         info->shader_buffers_declared = u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
 454
 455         func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
 456         nir_foreach_block(block, func->impl) {
 457                 nir_foreach_instr(instr, block)
 458                         scan_instruction(info, instr);
 459         }
 460 }
 461
 462 /**
 463  * Perform "lowering" operations on the NIR that are run once when the shader
 464  * selector is created.
 465  */
 466 void
 467 si_lower_nir(struct si_shader_selector* sel)
 468 {
 469         /* Adjust the driver location of inputs and outputs. The state tracker
 470          * interprets them as slots, while the ac/nir backend interprets them
 471          * as individual components.
 472          */
 473         nir_foreach_variable(variable, &sel->nir->inputs)
 474                 variable->data.driver_location *= 4;
 475
 476         nir_foreach_variable(variable, &sel->nir->outputs) {
 477                 variable->data.driver_location *= 4;
 478
 479                 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
 480                         if (variable->data.location == FRAG_RESULT_DEPTH)
 481                                 variable->data.driver_location += 2;
 482                         else if (variable->data.location == FRAG_RESULT_STENCIL)
 483                                 variable->data.driver_location += 1;
 484                 }
 485         }
 486
 487         /* Perform lowerings (and optimizations) of code.
 488          *
 489          * Performance considerations aside, we must:
 490          * - lower certain ALU operations
 491          * - ensure constant offsets for texture instructions are folded
 492          *   and copy-propagated
 493          */
 494         NIR_PASS_V(sel->nir, nir_lower_io, nir_var_uniform, type_size,
 495                    (nir_lower_io_options)0);
 496         NIR_PASS_V(sel->nir, nir_lower_uniforms_to_ubo);
 497
 498         NIR_PASS_V(sel->nir, nir_lower_returns);
 499         NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
 500         NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
 501         NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
 502
 503         static const struct nir_lower_tex_options lower_tex_options = {
 504                 .lower_txp = ~0u,
 505         };
 506         NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
 507
 508         const nir_lower_subgroups_options subgroups_options = {
 509                 .subgroup_size = 64,
 510                 .ballot_bit_size = 32,
 511                 .lower_to_scalar = true,
 512                 .lower_subgroup_masks = true,
 513                 .lower_vote_trivial = false,
 514         };
 515         NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
 516
 517         bool progress;
 518         do {
 519                 progress = false;
 520
 521                 /* (Constant) copy propagation is needed for txf with offsets. */
 522                 NIR_PASS(progress, sel->nir, nir_copy_prop);
 523                 NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
 524                 NIR_PASS(progress, sel->nir, nir_opt_dce);
 525                 if (nir_opt_trivial_continues(sel->nir)) {
 526                         progress = true;
 527                         NIR_PASS(progress, sel->nir, nir_copy_prop);
 528                         NIR_PASS(progress, sel->nir, nir_opt_dce);
 529                 }
 530                 NIR_PASS(progress, sel->nir, nir_opt_if);
 531                 NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
 532                 NIR_PASS(progress, sel->nir, nir_opt_cse);
 533                 NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8);
 534
 535                 /* Needed for algebraic lowering */
 536                 NIR_PASS(progress, sel->nir, nir_opt_algebraic);
 537                 NIR_PASS(progress, sel->nir, nir_opt_constant_folding);
 538
 539                 NIR_PASS(progress, sel->nir, nir_opt_undef);
 540                 NIR_PASS(progress, sel->nir, nir_opt_conditional_discard);
 541                 if (sel->nir->options->max_unroll_iterations) {
 542                         NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
 543                 }
 544         } while (progress);
 545 }
 546
 547 static void declare_nir_input_vs(struct si_shader_context *ctx,
 548                                  struct nir_variable *variable,
 549                                  LLVMValueRef out[4])
 550 {
 551         si_llvm_load_input_vs(ctx, variable->data.driver_location / 4, out);
 552 }
 553
 554 static void declare_nir_input_fs(struct si_shader_context *ctx,
 555                                  struct nir_variable *variable,
 556                                  unsigned input_index,
 557                                  LLVMValueRef out[4])
 558 {
 559         unsigned slot = variable->data.location;
 560         if (slot == VARYING_SLOT_POS) {
 561                 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
 562                 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
 563                 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
 564                 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
 565                                 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
 566                 return;
 567         }
 568
 569         si_llvm_load_input_fs(ctx, input_index, out);
 570 }
 571
 572 LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
 573                                   unsigned location,
 574                                   unsigned driver_location,
 575                                   unsigned component,
 576                                   unsigned num_components,
 577                                   unsigned vertex_index,
 578                                   unsigned const_index,
 579                                   LLVMTypeRef type)
 580 {
 581         struct si_shader_context *ctx = si_shader_context_from_abi(abi);
 582
 583         LLVMValueRef value[4];
 584         for (unsigned i = component; i < num_components + component; i++) {
 585                 value[i] = si_llvm_load_input_gs(&ctx->abi, driver_location  / 4,
 586                                                  vertex_index, type, i);
 587         }
 588
 589         return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
 590 }
 591
 592 static LLVMValueRef
 593 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
 594                          unsigned descriptor_set, unsigned base_index,
 595                          unsigned constant_index, LLVMValueRef dynamic_index,
 596                          enum ac_descriptor_type desc_type, bool image,
 597                          bool write)
 598 {
 599         struct si_shader_context *ctx = si_shader_context_from_abi(abi);
 600         LLVMBuilderRef builder = ctx->ac.builder;
 601         LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
 602         LLVMValueRef index = dynamic_index;
 603
 604         assert(!descriptor_set);
 605
 606         if (!index)
 607                 index = ctx->ac.i32_0;
 608
 609         index = LLVMBuildAdd(builder, index,
 610                              LLVMConstInt(ctx->ac.i32, base_index + constant_index, false),
 611                              "");
 612
 613         if (image) {
 614                 assert(desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
 615                 assert(base_index + constant_index < ctx->num_images);
 616
 617                 if (dynamic_index)
 618                         index = si_llvm_bound_index(ctx, index, ctx->num_images);
 619
 620                 index = LLVMBuildSub(ctx->gallivm.builder,
 621                                      LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
 622                                      index, "");
 623
 624                 /* TODO: be smarter about when we use dcc_off */
 625                 return si_load_image_desc(ctx, list, index, desc_type, write);
 626         }
 627
 628         assert(base_index + constant_index < ctx->num_samplers);
 629
 630         if (dynamic_index)
 631                 index = si_llvm_bound_index(ctx, index, ctx->num_samplers);
 632
 633         index = LLVMBuildAdd(ctx->gallivm.builder, index,
 634                              LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
 635
 636         return si_load_sampler_desc(ctx, list, index, desc_type);
 637 }
 638
 639 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
 640 {
 641         struct tgsi_shader_info *info = &ctx->shader->selector->info;
 642
 643         if (nir->info.stage == MESA_SHADER_VERTEX ||
 644             nir->info.stage == MESA_SHADER_FRAGMENT) {
 645                 uint64_t processed_inputs = 0;
 646                 nir_foreach_variable(variable, &nir->inputs) {
 647                         unsigned attrib_count = glsl_count_attribute_slots(variable->type,
 648                                                                            nir->info.stage == MESA_SHADER_VERTEX);
 649                         unsigned input_idx = variable->data.driver_location;
 650
 651                         assert(attrib_count == 1);
 652
 653                         LLVMValueRef data[4];
 654                         unsigned loc = variable->data.location;
 655
 656                         /* Packed components share the same location so skip
 657                          * them if we have already processed the location.
 658                          */
 659                         if (processed_inputs & ((uint64_t)1 << loc))
 660                                 continue;
 661
 662                         if (nir->info.stage == MESA_SHADER_VERTEX)
 663                                 declare_nir_input_vs(ctx, variable, data);
 664                         else if (nir->info.stage == MESA_SHADER_FRAGMENT)
 665                                 declare_nir_input_fs(ctx, variable, input_idx / 4, data);
 666
 667                         for (unsigned chan = 0; chan < 4; chan++) {
 668                                 ctx->inputs[input_idx + chan] =
 669                                         LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
 670                         }
 671                         processed_inputs |= ((uint64_t)1 << loc);
 672                 }
 673         }
 674
 675         ctx->abi.inputs = &ctx->inputs[0];
 676         ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
 677         ctx->abi.clamp_shadow_reference = true;
 678
 679         ctx->num_samplers = util_last_bit(info->samplers_declared);
 680         ctx->num_images = util_last_bit(info->images_declared);
 681
 682         ac_nir_translate(&ctx->ac, &ctx->abi, nir, NULL);
 683
 684         return true;
 685 }