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radeonsi/nir: parse more information about bindless usage
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 #include "tgsi/tgsi_from_mesa.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34
35 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
36 {
37 for (unsigned i = 0; i < instr->num_srcs; i++) {
38 switch (instr->src[i].src_type) {
39 case nir_tex_src_texture_deref:
40 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
41 default:
42 break;
43 }
44 }
45
46 return NULL;
47 }
48
49 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
50 {
51 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
52 }
53
54 static void scan_instruction(struct tgsi_shader_info *info,
55 nir_instr *instr)
56 {
57 if (instr->type == nir_instr_type_alu) {
58 nir_alu_instr *alu = nir_instr_as_alu(instr);
59
60 switch (alu->op) {
61 case nir_op_fddx:
62 case nir_op_fddy:
63 case nir_op_fddx_fine:
64 case nir_op_fddy_fine:
65 case nir_op_fddx_coarse:
66 case nir_op_fddy_coarse:
67 info->uses_derivatives = true;
68 break;
69 default:
70 break;
71 }
72 } else if (instr->type == nir_instr_type_tex) {
73 nir_tex_instr *tex = nir_instr_as_tex(instr);
74 nir_variable *texture = tex_get_texture_var(tex);
75
76 if (!texture) {
77 info->samplers_declared |=
78 u_bit_consecutive(tex->sampler_index, 1);
79 } else {
80 if (texture->data.bindless)
81 info->uses_bindless_samplers = true;
82 }
83
84 switch (tex->op) {
85 case nir_texop_tex:
86 case nir_texop_txb:
87 case nir_texop_lod:
88 info->uses_derivatives = true;
89 break;
90 default:
91 break;
92 }
93 } else if (instr->type == nir_instr_type_intrinsic) {
94 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
95
96 switch (intr->intrinsic) {
97 case nir_intrinsic_load_front_face:
98 info->uses_frontface = 1;
99 break;
100 case nir_intrinsic_load_instance_id:
101 info->uses_instanceid = 1;
102 break;
103 case nir_intrinsic_load_invocation_id:
104 info->uses_invocationid = true;
105 break;
106 case nir_intrinsic_load_num_work_groups:
107 info->uses_grid_size = true;
108 break;
109 case nir_intrinsic_load_local_group_size:
110 /* The block size is translated to IMM with a fixed block size. */
111 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
112 info->uses_block_size = true;
113 break;
114 case nir_intrinsic_load_local_invocation_id:
115 case nir_intrinsic_load_work_group_id: {
116 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
117 while (mask) {
118 unsigned i = u_bit_scan(&mask);
119
120 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
121 info->uses_block_id[i] = true;
122 else
123 info->uses_thread_id[i] = true;
124 }
125 break;
126 }
127 case nir_intrinsic_load_vertex_id:
128 info->uses_vertexid = 1;
129 break;
130 case nir_intrinsic_load_vertex_id_zero_base:
131 info->uses_vertexid_nobase = 1;
132 break;
133 case nir_intrinsic_load_base_vertex:
134 info->uses_basevertex = 1;
135 break;
136 case nir_intrinsic_load_primitive_id:
137 info->uses_primid = 1;
138 break;
139 case nir_intrinsic_load_sample_mask_in:
140 info->reads_samplemask = true;
141 break;
142 case nir_intrinsic_load_tess_level_inner:
143 case nir_intrinsic_load_tess_level_outer:
144 info->reads_tess_factors = true;
145 break;
146 case nir_intrinsic_image_deref_load: {
147 nir_variable *var = intrinsic_get_var(intr);
148 if (var->data.bindless) {
149 info->uses_bindless_images = true;
150
151 if (glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_BUF)
152 info->uses_bindless_buffer_load = true;
153 else
154 info->uses_bindless_image_load = true;
155 }
156 break;
157 }
158 case nir_intrinsic_image_deref_size:
159 case nir_intrinsic_image_deref_samples: {
160 nir_variable *var = intrinsic_get_var(intr);
161 if (var->data.bindless)
162 info->uses_bindless_images = true;
163 break;
164 }
165 case nir_intrinsic_image_deref_store: {
166 nir_variable *var = intrinsic_get_var(intr);
167 if (var->data.bindless) {
168 info->uses_bindless_images = true;
169
170 if (glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_BUF)
171 info->uses_bindless_buffer_store = true;
172 else
173 info->uses_bindless_image_store = true;
174 }
175 info->writes_memory = true;
176 break;
177 }
178 case nir_intrinsic_image_deref_atomic_add:
179 case nir_intrinsic_image_deref_atomic_min:
180 case nir_intrinsic_image_deref_atomic_max:
181 case nir_intrinsic_image_deref_atomic_and:
182 case nir_intrinsic_image_deref_atomic_or:
183 case nir_intrinsic_image_deref_atomic_xor:
184 case nir_intrinsic_image_deref_atomic_exchange:
185 case nir_intrinsic_image_deref_atomic_comp_swap: {
186 nir_variable *var = intrinsic_get_var(intr);
187 if (var->data.bindless) {
188 info->uses_bindless_images = true;
189
190 if (glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_BUF)
191 info->uses_bindless_buffer_atomic = true;
192 else
193 info->uses_bindless_image_atomic = true;
194 }
195 info->writes_memory = true;
196 break;
197 }
198 case nir_intrinsic_store_ssbo:
199 case nir_intrinsic_ssbo_atomic_add:
200 case nir_intrinsic_ssbo_atomic_imin:
201 case nir_intrinsic_ssbo_atomic_umin:
202 case nir_intrinsic_ssbo_atomic_imax:
203 case nir_intrinsic_ssbo_atomic_umax:
204 case nir_intrinsic_ssbo_atomic_and:
205 case nir_intrinsic_ssbo_atomic_or:
206 case nir_intrinsic_ssbo_atomic_xor:
207 case nir_intrinsic_ssbo_atomic_exchange:
208 case nir_intrinsic_ssbo_atomic_comp_swap:
209 info->writes_memory = true;
210 break;
211 case nir_intrinsic_load_deref: {
212 nir_variable *var = intrinsic_get_var(intr);
213 nir_variable_mode mode = var->data.mode;
214 enum glsl_base_type base_type =
215 glsl_get_base_type(glsl_without_array(var->type));
216
217 if (mode == nir_var_shader_in) {
218 switch (var->data.interpolation) {
219 case INTERP_MODE_NONE:
220 if (glsl_base_type_is_integer(base_type))
221 break;
222
223 /* fall-through */
224 case INTERP_MODE_SMOOTH:
225 if (var->data.sample)
226 info->uses_persp_sample = true;
227 else if (var->data.centroid)
228 info->uses_persp_centroid = true;
229 else
230 info->uses_persp_center = true;
231 break;
232
233 case INTERP_MODE_NOPERSPECTIVE:
234 if (var->data.sample)
235 info->uses_linear_sample = true;
236 else if (var->data.centroid)
237 info->uses_linear_centroid = true;
238 else
239 info->uses_linear_center = true;
240 break;
241 }
242 }
243 break;
244 }
245 case nir_intrinsic_interp_deref_at_centroid:
246 case nir_intrinsic_interp_deref_at_sample:
247 case nir_intrinsic_interp_deref_at_offset: {
248 enum glsl_interp_mode interp = intrinsic_get_var(intr)->data.interpolation;
249 switch (interp) {
250 case INTERP_MODE_SMOOTH:
251 case INTERP_MODE_NONE:
252 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
253 info->uses_persp_opcode_interp_centroid = true;
254 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
255 info->uses_persp_opcode_interp_sample = true;
256 else
257 info->uses_persp_opcode_interp_offset = true;
258 break;
259 case INTERP_MODE_NOPERSPECTIVE:
260 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
261 info->uses_linear_opcode_interp_centroid = true;
262 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
263 info->uses_linear_opcode_interp_sample = true;
264 else
265 info->uses_linear_opcode_interp_offset = true;
266 break;
267 case INTERP_MODE_FLAT:
268 break;
269 default:
270 unreachable("Unsupported interpoation type");
271 }
272 break;
273 }
274 default:
275 break;
276 }
277 }
278 }
279
280 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
281 const struct tgsi_shader_info *info,
282 struct tgsi_tessctrl_info *out)
283 {
284 memset(out, 0, sizeof(*out));
285
286 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
287 return;
288
289 /* Initial value = true. Here the pass will accumulate results from
290 * multiple segments surrounded by barriers. If tess factors aren't
291 * written at all, it's a shader bug and we don't care if this will be
292 * true.
293 */
294 out->tessfactors_are_def_in_all_invocs = true;
295
296 /* TODO: Implement scanning of tess factors, see tgsi backend. */
297 }
298
299 void si_nir_scan_shader(const struct nir_shader *nir,
300 struct tgsi_shader_info *info)
301 {
302 nir_function *func;
303 unsigned i;
304
305 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
306 info->num_tokens = 2; /* indicate that the shader is non-empty */
307 info->num_instructions = 2;
308
309 info->properties[TGSI_PROPERTY_NEXT_SHADER] =
310 pipe_shader_type_from_mesa(nir->info.next_stage);
311
312 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
313 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
314 nir->info.tess.tcs_vertices_out;
315 }
316
317 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
318 if (nir->info.tess.primitive_mode == GL_ISOLINES)
319 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
320 else
321 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
322
323 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
324 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
325 PIPE_TESS_SPACING_FRACTIONAL_ODD);
326 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
327 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
328
329 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
330 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
331 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
332 }
333
334 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
335 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
336 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
337 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
338 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
339 }
340
341 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
342 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
343 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
344 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
345
346 if (nir->info.fs.pixel_center_integer) {
347 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
348 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
349 }
350
351 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
352 switch (nir->info.fs.depth_layout) {
353 case FRAG_DEPTH_LAYOUT_ANY:
354 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
355 break;
356 case FRAG_DEPTH_LAYOUT_GREATER:
357 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
358 break;
359 case FRAG_DEPTH_LAYOUT_LESS:
360 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
361 break;
362 case FRAG_DEPTH_LAYOUT_UNCHANGED:
363 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
364 break;
365 default:
366 unreachable("Unknow depth layout");
367 }
368 }
369 }
370
371 if (nir->info.stage == MESA_SHADER_COMPUTE) {
372 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
373 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
374 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
375 }
376
377 i = 0;
378 uint64_t processed_inputs = 0;
379 unsigned num_inputs = 0;
380 nir_foreach_variable(variable, &nir->inputs) {
381 unsigned semantic_name, semantic_index;
382
383 const struct glsl_type *type = variable->type;
384 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
385 assert(glsl_type_is_array(type));
386 type = glsl_get_array_element(type);
387 }
388
389 unsigned attrib_count = glsl_count_attribute_slots(type,
390 nir->info.stage == MESA_SHADER_VERTEX);
391
392 i = variable->data.driver_location;
393
394 /* Vertex shader inputs don't have semantics. The state
395 * tracker has already mapped them to attributes via
396 * variable->data.driver_location.
397 */
398 if (nir->info.stage == MESA_SHADER_VERTEX) {
399 /* TODO: gather the actual input useage and remove this. */
400 info->input_usage_mask[i] = TGSI_WRITEMASK_XYZW;
401
402 if (glsl_type_is_dual_slot(variable->type)) {
403 num_inputs += 2;
404
405 /* TODO: gather the actual input useage and remove this. */
406 info->input_usage_mask[i+1] = TGSI_WRITEMASK_XYZW;
407 } else
408 num_inputs++;
409 continue;
410 }
411
412 /* Fragment shader position is a system value. */
413 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
414 variable->data.location == VARYING_SLOT_POS) {
415 if (variable->data.pixel_center_integer)
416 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
417 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
418
419 num_inputs++;
420 continue;
421 }
422
423 for (unsigned j = 0; j < attrib_count; j++, i++) {
424
425 if (processed_inputs & ((uint64_t)1 << i))
426 continue;
427
428 processed_inputs |= ((uint64_t)1 << i);
429 num_inputs++;
430
431 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
432 &semantic_name, &semantic_index);
433
434 info->input_semantic_name[i] = semantic_name;
435 info->input_semantic_index[i] = semantic_index;
436
437 if (semantic_name == TGSI_SEMANTIC_PRIMID)
438 info->uses_primid = true;
439
440 if (variable->data.sample)
441 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
442 else if (variable->data.centroid)
443 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
444 else
445 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
446
447 enum glsl_base_type base_type =
448 glsl_get_base_type(glsl_without_array(variable->type));
449
450 switch (variable->data.interpolation) {
451 case INTERP_MODE_NONE:
452 if (glsl_base_type_is_integer(base_type)) {
453 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
454 break;
455 }
456
457 if (semantic_name == TGSI_SEMANTIC_COLOR) {
458 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
459 break;
460 }
461 /* fall-through */
462
463 case INTERP_MODE_SMOOTH:
464 assert(!glsl_base_type_is_integer(base_type));
465
466 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
467 break;
468
469 case INTERP_MODE_NOPERSPECTIVE:
470 assert(!glsl_base_type_is_integer(base_type));
471
472 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
473 break;
474
475 case INTERP_MODE_FLAT:
476 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
477 break;
478 }
479
480 /* TODO make this more precise */
481 if (variable->data.location == VARYING_SLOT_COL0)
482 info->colors_read |= 0x0f;
483 else if (variable->data.location == VARYING_SLOT_COL1)
484 info->colors_read |= 0xf0;
485 }
486 }
487
488 info->num_inputs = num_inputs;
489
490
491 i = 0;
492 uint64_t processed_outputs = 0;
493 unsigned num_outputs = 0;
494 nir_foreach_variable(variable, &nir->outputs) {
495 unsigned semantic_name, semantic_index;
496
497 i = variable->data.driver_location;
498
499 const struct glsl_type *type = variable->type;
500 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
501 assert(glsl_type_is_array(type));
502 type = glsl_get_array_element(type);
503 }
504
505 unsigned attrib_count = glsl_count_attribute_slots(type, false);
506 for (unsigned k = 0; k < attrib_count; k++, i++) {
507
508 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
509 tgsi_get_gl_frag_result_semantic(variable->data.location + k,
510 &semantic_name, &semantic_index);
511
512 /* Adjust for dual source blending */
513 if (variable->data.index > 0) {
514 semantic_index++;
515 }
516 } else {
517 tgsi_get_gl_varying_semantic(variable->data.location + k, true,
518 &semantic_name, &semantic_index);
519 }
520
521 unsigned num_components = 4;
522 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
523 if (vector_elements)
524 num_components = vector_elements;
525
526 unsigned component = variable->data.location_frac;
527 if (glsl_type_is_64bit(glsl_without_array(variable->type))) {
528 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)) && k % 2) {
529 num_components = (num_components * 2) - 4;
530 component = 0;
531 } else {
532 num_components = MIN2(num_components * 2, 4);
533 }
534 }
535
536 ubyte usagemask = 0;
537 for (unsigned j = component; j < num_components + component; j++) {
538 switch (j) {
539 case 0:
540 usagemask |= TGSI_WRITEMASK_X;
541 break;
542 case 1:
543 usagemask |= TGSI_WRITEMASK_Y;
544 break;
545 case 2:
546 usagemask |= TGSI_WRITEMASK_Z;
547 break;
548 case 3:
549 usagemask |= TGSI_WRITEMASK_W;
550 break;
551 default:
552 unreachable("error calculating component index");
553 }
554 }
555
556 unsigned gs_out_streams;
557 if (variable->data.stream & (1u << 31)) {
558 gs_out_streams = variable->data.stream & ~(1u << 31);
559 } else {
560 assert(variable->data.stream < 4);
561 gs_out_streams = 0;
562 for (unsigned j = 0; j < num_components; ++j)
563 gs_out_streams |= variable->data.stream << (2 * (component + j));
564 }
565
566 unsigned streamx = gs_out_streams & 3;
567 unsigned streamy = (gs_out_streams >> 2) & 3;
568 unsigned streamz = (gs_out_streams >> 4) & 3;
569 unsigned streamw = (gs_out_streams >> 6) & 3;
570
571 if (usagemask & TGSI_WRITEMASK_X) {
572 info->output_usagemask[i] |= TGSI_WRITEMASK_X;
573 info->output_streams[i] |= streamx;
574 info->num_stream_output_components[streamx]++;
575 }
576 if (usagemask & TGSI_WRITEMASK_Y) {
577 info->output_usagemask[i] |= TGSI_WRITEMASK_Y;
578 info->output_streams[i] |= streamy << 2;
579 info->num_stream_output_components[streamy]++;
580 }
581 if (usagemask & TGSI_WRITEMASK_Z) {
582 info->output_usagemask[i] |= TGSI_WRITEMASK_Z;
583 info->output_streams[i] |= streamz << 4;
584 info->num_stream_output_components[streamz]++;
585 }
586 if (usagemask & TGSI_WRITEMASK_W) {
587 info->output_usagemask[i] |= TGSI_WRITEMASK_W;
588 info->output_streams[i] |= streamw << 6;
589 info->num_stream_output_components[streamw]++;
590 }
591
592 /* make sure we only count this location once against
593 * the num_outputs counter.
594 */
595 if (processed_outputs & ((uint64_t)1 << i))
596 continue;
597
598 processed_outputs |= ((uint64_t)1 << i);
599 num_outputs++;
600
601 info->output_semantic_name[i] = semantic_name;
602 info->output_semantic_index[i] = semantic_index;
603
604 switch (semantic_name) {
605 case TGSI_SEMANTIC_PRIMID:
606 info->writes_primid = true;
607 break;
608 case TGSI_SEMANTIC_VIEWPORT_INDEX:
609 info->writes_viewport_index = true;
610 break;
611 case TGSI_SEMANTIC_LAYER:
612 info->writes_layer = true;
613 break;
614 case TGSI_SEMANTIC_PSIZE:
615 info->writes_psize = true;
616 break;
617 case TGSI_SEMANTIC_CLIPVERTEX:
618 info->writes_clipvertex = true;
619 break;
620 case TGSI_SEMANTIC_COLOR:
621 info->colors_written |= 1 << semantic_index;
622 break;
623 case TGSI_SEMANTIC_STENCIL:
624 info->writes_stencil = true;
625 break;
626 case TGSI_SEMANTIC_SAMPLEMASK:
627 info->writes_samplemask = true;
628 break;
629 case TGSI_SEMANTIC_EDGEFLAG:
630 info->writes_edgeflag = true;
631 break;
632 case TGSI_SEMANTIC_POSITION:
633 if (info->processor == PIPE_SHADER_FRAGMENT)
634 info->writes_z = true;
635 else
636 info->writes_position = true;
637 break;
638 }
639
640 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
641 switch (semantic_name) {
642 case TGSI_SEMANTIC_PATCH:
643 info->reads_perpatch_outputs = true;
644 break;
645 case TGSI_SEMANTIC_TESSINNER:
646 case TGSI_SEMANTIC_TESSOUTER:
647 info->reads_tessfactor_outputs = true;
648 break;
649 default:
650 info->reads_pervertex_outputs = true;
651 }
652 }
653 }
654
655 unsigned loc = variable->data.location;
656 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
657 loc == FRAG_RESULT_COLOR &&
658 nir->info.outputs_written & (1ull << loc)) {
659 assert(attrib_count == 1);
660 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
661 }
662 }
663
664 info->num_outputs = num_outputs;
665
666 struct set *ubo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
667 _mesa_key_pointer_equal);
668
669 /* Intialise const_file_max[0] */
670 info->const_file_max[0] = -1;
671
672 unsigned ubo_idx = 1;
673 nir_foreach_variable(variable, &nir->uniforms) {
674 const struct glsl_type *type = variable->type;
675 enum glsl_base_type base_type =
676 glsl_get_base_type(glsl_without_array(type));
677 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
678
679 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
680 * really use the mask (other than ubo_idx == 1 for regular
681 * uniforms) its really only used for getting the buffer count
682 * so we don't need to worry about the ordering.
683 */
684 if (variable->interface_type != NULL) {
685 if (variable->data.mode == nir_var_uniform) {
686
687 unsigned block_count;
688 if (base_type != GLSL_TYPE_INTERFACE) {
689 struct set_entry *entry =
690 _mesa_set_search(ubo_set, variable->interface_type);
691
692 /* Check if we have already processed
693 * a member from this ubo.
694 */
695 if (entry)
696 continue;
697
698 block_count = 1;
699 } else {
700 block_count = aoa_size;
701 }
702
703 info->const_buffers_declared |= u_bit_consecutive(ubo_idx, block_count);
704 ubo_idx += block_count;
705
706 _mesa_set_add(ubo_set, variable->interface_type);
707 }
708
709 if (variable->data.mode == nir_var_shader_storage) {
710 /* TODO: make this more accurate */
711 info->shader_buffers_declared =
712 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
713 }
714
715 continue;
716 }
717
718 /* We rely on the fact that nir_lower_samplers_as_deref has
719 * eliminated struct dereferences.
720 */
721 if (base_type == GLSL_TYPE_SAMPLER) {
722 if (variable->data.bindless) {
723 info->const_buffers_declared |= 1;
724 info->const_file_max[0] +=
725 glsl_count_attribute_slots(type, false);
726 } else {
727 info->samplers_declared |=
728 u_bit_consecutive(variable->data.binding, aoa_size);
729 }
730 } else if (base_type == GLSL_TYPE_IMAGE) {
731 if (variable->data.bindless) {
732 info->const_buffers_declared |= 1;
733 info->const_file_max[0] +=
734 glsl_count_attribute_slots(type, false);
735 } else {
736 info->images_declared |=
737 u_bit_consecutive(variable->data.binding, aoa_size);
738 }
739 } else if (base_type != GLSL_TYPE_ATOMIC_UINT) {
740 if (strncmp(variable->name, "state.", 6) == 0 ||
741 strncmp(variable->name, "gl_", 3) == 0) {
742 /* FIXME: figure out why piglit tests with builtin
743 * uniforms are failing without this.
744 */
745 info->const_buffers_declared =
746 u_bit_consecutive(0, SI_NUM_CONST_BUFFERS);
747 } else {
748 info->const_buffers_declared |= 1;
749 info->const_file_max[0] +=
750 glsl_count_attribute_slots(type, false);
751 }
752 }
753 }
754
755 _mesa_set_destroy(ubo_set, NULL);
756
757 info->num_written_clipdistance = nir->info.clip_distance_array_size;
758 info->num_written_culldistance = nir->info.cull_distance_array_size;
759 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
760 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
761
762 if (info->processor == PIPE_SHADER_FRAGMENT)
763 info->uses_kill = nir->info.fs.uses_discard;
764
765 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
766 nir_foreach_block(block, func->impl) {
767 nir_foreach_instr(instr, block)
768 scan_instruction(info, instr);
769 }
770 }
771
772 /**
773 * Perform "lowering" operations on the NIR that are run once when the shader
774 * selector is created.
775 */
776 void
777 si_lower_nir(struct si_shader_selector* sel)
778 {
779 /* Adjust the driver location of inputs and outputs. The state tracker
780 * interprets them as slots, while the ac/nir backend interprets them
781 * as individual components.
782 */
783 nir_foreach_variable(variable, &sel->nir->inputs)
784 variable->data.driver_location *= 4;
785
786 nir_foreach_variable(variable, &sel->nir->outputs) {
787 variable->data.driver_location *= 4;
788
789 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
790 if (variable->data.location == FRAG_RESULT_DEPTH)
791 variable->data.driver_location += 2;
792 else if (variable->data.location == FRAG_RESULT_STENCIL)
793 variable->data.driver_location += 1;
794 }
795 }
796
797 /* Perform lowerings (and optimizations) of code.
798 *
799 * Performance considerations aside, we must:
800 * - lower certain ALU operations
801 * - ensure constant offsets for texture instructions are folded
802 * and copy-propagated
803 */
804 NIR_PASS_V(sel->nir, nir_lower_returns);
805 NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
806 NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
807 NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
808
809 static const struct nir_lower_tex_options lower_tex_options = {
810 .lower_txp = ~0u,
811 };
812 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
813
814 const nir_lower_subgroups_options subgroups_options = {
815 .subgroup_size = 64,
816 .ballot_bit_size = 64,
817 .lower_to_scalar = true,
818 .lower_subgroup_masks = true,
819 .lower_vote_trivial = false,
820 .lower_vote_eq_to_ballot = true,
821 };
822 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
823
824 ac_lower_indirect_derefs(sel->nir, sel->screen->info.chip_class);
825
826 NIR_PASS_V(sel->nir, nir_lower_load_const_to_scalar);
827
828 bool progress;
829 do {
830 progress = false;
831
832 /* (Constant) copy propagation is needed for txf with offsets. */
833 NIR_PASS(progress, sel->nir, nir_copy_prop);
834 NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
835 NIR_PASS(progress, sel->nir, nir_opt_dce);
836 if (nir_opt_trivial_continues(sel->nir)) {
837 progress = true;
838 NIR_PASS(progress, sel->nir, nir_copy_prop);
839 NIR_PASS(progress, sel->nir, nir_opt_dce);
840 }
841 NIR_PASS(progress, sel->nir, nir_opt_if);
842 NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
843 NIR_PASS(progress, sel->nir, nir_opt_cse);
844 NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8);
845
846 /* Needed for algebraic lowering */
847 NIR_PASS(progress, sel->nir, nir_opt_algebraic);
848 NIR_PASS(progress, sel->nir, nir_opt_constant_folding);
849
850 NIR_PASS(progress, sel->nir, nir_opt_undef);
851 NIR_PASS(progress, sel->nir, nir_opt_conditional_discard);
852 if (sel->nir->options->max_unroll_iterations) {
853 NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
854 }
855 } while (progress);
856 }
857
858 static void declare_nir_input_vs(struct si_shader_context *ctx,
859 struct nir_variable *variable,
860 unsigned input_index,
861 LLVMValueRef out[4])
862 {
863 si_llvm_load_input_vs(ctx, input_index, out);
864 }
865
866 static void declare_nir_input_fs(struct si_shader_context *ctx,
867 struct nir_variable *variable,
868 unsigned input_index,
869 LLVMValueRef out[4])
870 {
871 unsigned slot = variable->data.location;
872 if (slot == VARYING_SLOT_POS) {
873 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
874 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
875 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
876 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
877 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
878 return;
879 }
880
881 si_llvm_load_input_fs(ctx, input_index, out);
882 }
883
884 LLVMValueRef
885 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
886 enum glsl_interp_mode interp, unsigned location)
887 {
888 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
889 int interp_param_idx = -1;
890
891 switch (interp) {
892 case INTERP_MODE_FLAT:
893 return NULL;
894 case INTERP_MODE_SMOOTH:
895 case INTERP_MODE_NONE:
896 if (location == INTERP_CENTER)
897 interp_param_idx = SI_PARAM_PERSP_CENTER;
898 else if (location == INTERP_CENTROID)
899 interp_param_idx = SI_PARAM_PERSP_CENTROID;
900 else if (location == INTERP_SAMPLE)
901 interp_param_idx = SI_PARAM_PERSP_SAMPLE;
902 break;
903 case INTERP_MODE_NOPERSPECTIVE:
904 if (location == INTERP_CENTER)
905 interp_param_idx = SI_PARAM_LINEAR_CENTER;
906 else if (location == INTERP_CENTROID)
907 interp_param_idx = SI_PARAM_LINEAR_CENTROID;
908 else if (location == INTERP_SAMPLE)
909 interp_param_idx = SI_PARAM_LINEAR_SAMPLE;
910 break;
911 default:
912 assert(!"Unhandled interpolation mode.");
913 return NULL;
914 }
915
916 return interp_param_idx != -1 ?
917 LLVMGetParam(ctx->main_fn, interp_param_idx) : NULL;
918 }
919
920 static LLVMValueRef
921 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
922 unsigned descriptor_set, unsigned base_index,
923 unsigned constant_index, LLVMValueRef dynamic_index,
924 enum ac_descriptor_type desc_type, bool image,
925 bool write, bool bindless)
926 {
927 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
928 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
929 LLVMBuilderRef builder = ctx->ac.builder;
930 unsigned const_index = base_index + constant_index;
931 bool dcc_off = write;
932
933 /* TODO: images_store and images_atomic are not set */
934 if (!dynamic_index && image &&
935 (info->images_store | info->images_atomic) & (1 << const_index))
936 dcc_off = true;
937
938 assert(!descriptor_set);
939 assert(!image || desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
940
941 if (bindless) {
942 LLVMValueRef list =
943 LLVMGetParam(ctx->main_fn, ctx->param_bindless_samplers_and_images);
944
945 /* dynamic_index is the bindless handle */
946 if (image) {
947 return si_load_image_desc(ctx, list, dynamic_index, desc_type,
948 dcc_off, true);
949 }
950
951 /* Since bindless handle arithmetic can contain an unsigned integer
952 * wraparound and si_load_sampler_desc assumes there isn't any,
953 * use GEP without "inbounds" (inside ac_build_pointer_add)
954 * to prevent incorrect code generation and hangs.
955 */
956 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
957 LLVMConstInt(ctx->i32, 2, 0), "");
958 list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
959 return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
960 }
961
962 unsigned num_slots = image ? ctx->num_images : ctx->num_samplers;
963 assert(const_index < num_slots);
964
965 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
966 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, const_index, false);
967
968 if (dynamic_index) {
969 index = LLVMBuildAdd(builder, index, dynamic_index, "");
970
971 /* From the GL_ARB_shader_image_load_store extension spec:
972 *
973 * If a shader performs an image load, store, or atomic
974 * operation using an image variable declared as an array,
975 * and if the index used to select an individual element is
976 * negative or greater than or equal to the size of the
977 * array, the results of the operation are undefined but may
978 * not lead to termination.
979 */
980 index = si_llvm_bound_index(ctx, index, num_slots);
981 }
982
983 if (image) {
984 index = LLVMBuildSub(ctx->ac.builder,
985 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
986 index, "");
987 return si_load_image_desc(ctx, list, index, desc_type, dcc_off, false);
988 }
989
990 index = LLVMBuildAdd(ctx->ac.builder, index,
991 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
992 return si_load_sampler_desc(ctx, list, index, desc_type);
993 }
994
995 static void bitcast_inputs(struct si_shader_context *ctx,
996 LLVMValueRef data[4],
997 unsigned input_idx)
998 {
999 for (unsigned chan = 0; chan < 4; chan++) {
1000 ctx->inputs[input_idx + chan] =
1001 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
1002 }
1003 }
1004
1005 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
1006 {
1007 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1008
1009 if (nir->info.stage == MESA_SHADER_VERTEX ||
1010 nir->info.stage == MESA_SHADER_FRAGMENT) {
1011 uint64_t processed_inputs = 0;
1012 nir_foreach_variable(variable, &nir->inputs) {
1013 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
1014 nir->info.stage == MESA_SHADER_VERTEX);
1015 unsigned input_idx = variable->data.driver_location;
1016
1017 LLVMValueRef data[4];
1018 unsigned loc = variable->data.location;
1019
1020 for (unsigned i = 0; i < attrib_count; i++) {
1021 /* Packed components share the same location so skip
1022 * them if we have already processed the location.
1023 */
1024 if (processed_inputs & ((uint64_t)1 << (loc + i))) {
1025 input_idx += 4;
1026 continue;
1027 }
1028
1029 if (nir->info.stage == MESA_SHADER_VERTEX) {
1030 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1031 bitcast_inputs(ctx, data, input_idx);
1032 if (glsl_type_is_dual_slot(variable->type)) {
1033 input_idx += 4;
1034 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1035 bitcast_inputs(ctx, data, input_idx);
1036 }
1037 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1038 declare_nir_input_fs(ctx, variable, input_idx / 4, data);
1039 bitcast_inputs(ctx, data, input_idx);
1040 }
1041
1042 processed_inputs |= ((uint64_t)1 << (loc + i));
1043 input_idx += 4;
1044 }
1045 }
1046 }
1047
1048 ctx->abi.inputs = &ctx->inputs[0];
1049 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
1050 ctx->abi.clamp_shadow_reference = true;
1051
1052 ctx->num_samplers = util_last_bit(info->samplers_declared);
1053 ctx->num_images = util_last_bit(info->images_declared);
1054
1055 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
1056 assert(nir->info.stage == MESA_SHADER_COMPUTE);
1057 si_declare_compute_memory(ctx);
1058 }
1059 ac_nir_translate(&ctx->ac, &ctx->abi, nir);
1060
1061 return true;
1062 }