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nir: Distinguish between normal uniforms and UBOs
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 #include "tgsi/tgsi_from_mesa.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34
35 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
36 {
37 for (unsigned i = 0; i < instr->num_srcs; i++) {
38 switch (instr->src[i].src_type) {
39 case nir_tex_src_texture_deref:
40 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
41 default:
42 break;
43 }
44 }
45
46 return NULL;
47 }
48
49 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
50 {
51 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
52 }
53
54 static void scan_instruction(struct tgsi_shader_info *info,
55 nir_instr *instr)
56 {
57 if (instr->type == nir_instr_type_alu) {
58 nir_alu_instr *alu = nir_instr_as_alu(instr);
59
60 switch (alu->op) {
61 case nir_op_fddx:
62 case nir_op_fddy:
63 case nir_op_fddx_fine:
64 case nir_op_fddy_fine:
65 case nir_op_fddx_coarse:
66 case nir_op_fddy_coarse:
67 info->uses_derivatives = true;
68 break;
69 default:
70 break;
71 }
72 } else if (instr->type == nir_instr_type_tex) {
73 nir_tex_instr *tex = nir_instr_as_tex(instr);
74 nir_variable *texture = tex_get_texture_var(tex);
75
76 if (!texture) {
77 info->samplers_declared |=
78 u_bit_consecutive(tex->sampler_index, 1);
79 } else {
80 if (texture->data.bindless)
81 info->uses_bindless_samplers = true;
82 }
83
84 switch (tex->op) {
85 case nir_texop_tex:
86 case nir_texop_txb:
87 case nir_texop_lod:
88 info->uses_derivatives = true;
89 break;
90 default:
91 break;
92 }
93 } else if (instr->type == nir_instr_type_intrinsic) {
94 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
95
96 switch (intr->intrinsic) {
97 case nir_intrinsic_load_front_face:
98 info->uses_frontface = 1;
99 break;
100 case nir_intrinsic_load_instance_id:
101 info->uses_instanceid = 1;
102 break;
103 case nir_intrinsic_load_invocation_id:
104 info->uses_invocationid = true;
105 break;
106 case nir_intrinsic_load_num_work_groups:
107 info->uses_grid_size = true;
108 break;
109 case nir_intrinsic_load_local_group_size:
110 /* The block size is translated to IMM with a fixed block size. */
111 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
112 info->uses_block_size = true;
113 break;
114 case nir_intrinsic_load_local_invocation_id:
115 case nir_intrinsic_load_work_group_id: {
116 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
117 while (mask) {
118 unsigned i = u_bit_scan(&mask);
119
120 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
121 info->uses_block_id[i] = true;
122 else
123 info->uses_thread_id[i] = true;
124 }
125 break;
126 }
127 case nir_intrinsic_load_vertex_id:
128 info->uses_vertexid = 1;
129 break;
130 case nir_intrinsic_load_vertex_id_zero_base:
131 info->uses_vertexid_nobase = 1;
132 break;
133 case nir_intrinsic_load_base_vertex:
134 info->uses_basevertex = 1;
135 break;
136 case nir_intrinsic_load_primitive_id:
137 info->uses_primid = 1;
138 break;
139 case nir_intrinsic_load_sample_mask_in:
140 info->reads_samplemask = true;
141 break;
142 case nir_intrinsic_load_tess_level_inner:
143 case nir_intrinsic_load_tess_level_outer:
144 info->reads_tess_factors = true;
145 break;
146 case nir_intrinsic_image_deref_load: {
147 nir_variable *var = intrinsic_get_var(intr);
148 if (var->data.bindless) {
149 info->uses_bindless_images = true;
150
151 if (glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_BUF)
152 info->uses_bindless_buffer_load = true;
153 else
154 info->uses_bindless_image_load = true;
155 }
156 break;
157 }
158 case nir_intrinsic_image_deref_size:
159 case nir_intrinsic_image_deref_samples: {
160 nir_variable *var = intrinsic_get_var(intr);
161 if (var->data.bindless)
162 info->uses_bindless_images = true;
163 break;
164 }
165 case nir_intrinsic_image_deref_store: {
166 nir_variable *var = intrinsic_get_var(intr);
167 if (var->data.bindless) {
168 info->uses_bindless_images = true;
169
170 if (glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_BUF)
171 info->uses_bindless_buffer_store = true;
172 else
173 info->uses_bindless_image_store = true;
174 }
175 info->writes_memory = true;
176 break;
177 }
178 case nir_intrinsic_image_deref_atomic_add:
179 case nir_intrinsic_image_deref_atomic_min:
180 case nir_intrinsic_image_deref_atomic_max:
181 case nir_intrinsic_image_deref_atomic_and:
182 case nir_intrinsic_image_deref_atomic_or:
183 case nir_intrinsic_image_deref_atomic_xor:
184 case nir_intrinsic_image_deref_atomic_exchange:
185 case nir_intrinsic_image_deref_atomic_comp_swap: {
186 nir_variable *var = intrinsic_get_var(intr);
187 if (var->data.bindless) {
188 info->uses_bindless_images = true;
189
190 if (glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_BUF)
191 info->uses_bindless_buffer_atomic = true;
192 else
193 info->uses_bindless_image_atomic = true;
194 }
195 info->writes_memory = true;
196 break;
197 }
198 case nir_intrinsic_store_ssbo:
199 case nir_intrinsic_ssbo_atomic_add:
200 case nir_intrinsic_ssbo_atomic_imin:
201 case nir_intrinsic_ssbo_atomic_umin:
202 case nir_intrinsic_ssbo_atomic_imax:
203 case nir_intrinsic_ssbo_atomic_umax:
204 case nir_intrinsic_ssbo_atomic_and:
205 case nir_intrinsic_ssbo_atomic_or:
206 case nir_intrinsic_ssbo_atomic_xor:
207 case nir_intrinsic_ssbo_atomic_exchange:
208 case nir_intrinsic_ssbo_atomic_comp_swap:
209 info->writes_memory = true;
210 break;
211 case nir_intrinsic_load_deref: {
212 nir_variable *var = intrinsic_get_var(intr);
213 nir_variable_mode mode = var->data.mode;
214 enum glsl_base_type base_type =
215 glsl_get_base_type(glsl_without_array(var->type));
216
217 if (mode == nir_var_shader_in) {
218 switch (var->data.interpolation) {
219 case INTERP_MODE_NONE:
220 if (glsl_base_type_is_integer(base_type))
221 break;
222
223 /* fall-through */
224 case INTERP_MODE_SMOOTH:
225 if (var->data.sample)
226 info->uses_persp_sample = true;
227 else if (var->data.centroid)
228 info->uses_persp_centroid = true;
229 else
230 info->uses_persp_center = true;
231 break;
232
233 case INTERP_MODE_NOPERSPECTIVE:
234 if (var->data.sample)
235 info->uses_linear_sample = true;
236 else if (var->data.centroid)
237 info->uses_linear_centroid = true;
238 else
239 info->uses_linear_center = true;
240 break;
241 }
242 }
243 break;
244 }
245 case nir_intrinsic_interp_deref_at_centroid:
246 case nir_intrinsic_interp_deref_at_sample:
247 case nir_intrinsic_interp_deref_at_offset: {
248 enum glsl_interp_mode interp = intrinsic_get_var(intr)->data.interpolation;
249 switch (interp) {
250 case INTERP_MODE_SMOOTH:
251 case INTERP_MODE_NONE:
252 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
253 info->uses_persp_opcode_interp_centroid = true;
254 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
255 info->uses_persp_opcode_interp_sample = true;
256 else
257 info->uses_persp_opcode_interp_offset = true;
258 break;
259 case INTERP_MODE_NOPERSPECTIVE:
260 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
261 info->uses_linear_opcode_interp_centroid = true;
262 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
263 info->uses_linear_opcode_interp_sample = true;
264 else
265 info->uses_linear_opcode_interp_offset = true;
266 break;
267 case INTERP_MODE_FLAT:
268 break;
269 default:
270 unreachable("Unsupported interpoation type");
271 }
272 break;
273 }
274 default:
275 break;
276 }
277 }
278 }
279
280 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
281 struct tgsi_tessctrl_info *out)
282 {
283 memset(out, 0, sizeof(*out));
284
285 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
286 return;
287
288 out->tessfactors_are_def_in_all_invocs =
289 ac_are_tessfactors_def_in_all_invocs(nir);
290 }
291
292 void si_nir_scan_shader(const struct nir_shader *nir,
293 struct tgsi_shader_info *info)
294 {
295 nir_function *func;
296 unsigned i;
297
298 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
299 info->num_tokens = 2; /* indicate that the shader is non-empty */
300 info->num_instructions = 2;
301
302 info->properties[TGSI_PROPERTY_NEXT_SHADER] =
303 pipe_shader_type_from_mesa(nir->info.next_stage);
304
305 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
306 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
307 nir->info.tess.tcs_vertices_out;
308 }
309
310 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
311 if (nir->info.tess.primitive_mode == GL_ISOLINES)
312 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
313 else
314 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
315
316 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
317 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
318 PIPE_TESS_SPACING_FRACTIONAL_ODD);
319 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
320 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
321
322 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
323 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
324 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
325 }
326
327 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
328 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
329 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
330 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
331 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
332 }
333
334 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
335 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
336 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
337 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
338
339 if (nir->info.fs.pixel_center_integer) {
340 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
341 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
342 }
343
344 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
345 switch (nir->info.fs.depth_layout) {
346 case FRAG_DEPTH_LAYOUT_ANY:
347 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
348 break;
349 case FRAG_DEPTH_LAYOUT_GREATER:
350 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
351 break;
352 case FRAG_DEPTH_LAYOUT_LESS:
353 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
354 break;
355 case FRAG_DEPTH_LAYOUT_UNCHANGED:
356 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
357 break;
358 default:
359 unreachable("Unknow depth layout");
360 }
361 }
362 }
363
364 if (nir->info.stage == MESA_SHADER_COMPUTE) {
365 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
366 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
367 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
368 }
369
370 i = 0;
371 uint64_t processed_inputs = 0;
372 unsigned num_inputs = 0;
373 nir_foreach_variable(variable, &nir->inputs) {
374 unsigned semantic_name, semantic_index;
375
376 const struct glsl_type *type = variable->type;
377 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
378 assert(glsl_type_is_array(type));
379 type = glsl_get_array_element(type);
380 }
381
382 unsigned attrib_count = glsl_count_attribute_slots(type,
383 nir->info.stage == MESA_SHADER_VERTEX);
384
385 i = variable->data.driver_location;
386
387 /* Vertex shader inputs don't have semantics. The state
388 * tracker has already mapped them to attributes via
389 * variable->data.driver_location.
390 */
391 if (nir->info.stage == MESA_SHADER_VERTEX) {
392 /* TODO: gather the actual input useage and remove this. */
393 info->input_usage_mask[i] = TGSI_WRITEMASK_XYZW;
394
395 if (glsl_type_is_dual_slot(variable->type)) {
396 num_inputs += 2;
397
398 /* TODO: gather the actual input useage and remove this. */
399 info->input_usage_mask[i+1] = TGSI_WRITEMASK_XYZW;
400 } else
401 num_inputs++;
402 continue;
403 }
404
405 /* Fragment shader position is a system value. */
406 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
407 variable->data.location == VARYING_SLOT_POS) {
408 if (variable->data.pixel_center_integer)
409 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
410 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
411
412 num_inputs++;
413 continue;
414 }
415
416 for (unsigned j = 0; j < attrib_count; j++, i++) {
417
418 if (processed_inputs & ((uint64_t)1 << i))
419 continue;
420
421 processed_inputs |= ((uint64_t)1 << i);
422 num_inputs++;
423
424 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
425 &semantic_name, &semantic_index);
426
427 info->input_semantic_name[i] = semantic_name;
428 info->input_semantic_index[i] = semantic_index;
429
430 if (semantic_name == TGSI_SEMANTIC_PRIMID)
431 info->uses_primid = true;
432
433 if (variable->data.sample)
434 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
435 else if (variable->data.centroid)
436 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
437 else
438 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
439
440 enum glsl_base_type base_type =
441 glsl_get_base_type(glsl_without_array(variable->type));
442
443 switch (variable->data.interpolation) {
444 case INTERP_MODE_NONE:
445 if (glsl_base_type_is_integer(base_type)) {
446 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
447 break;
448 }
449
450 if (semantic_name == TGSI_SEMANTIC_COLOR) {
451 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
452 break;
453 }
454 /* fall-through */
455
456 case INTERP_MODE_SMOOTH:
457 assert(!glsl_base_type_is_integer(base_type));
458
459 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
460 break;
461
462 case INTERP_MODE_NOPERSPECTIVE:
463 assert(!glsl_base_type_is_integer(base_type));
464
465 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
466 break;
467
468 case INTERP_MODE_FLAT:
469 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
470 break;
471 }
472
473 /* TODO make this more precise */
474 if (variable->data.location == VARYING_SLOT_COL0)
475 info->colors_read |= 0x0f;
476 else if (variable->data.location == VARYING_SLOT_COL1)
477 info->colors_read |= 0xf0;
478 }
479 }
480
481 info->num_inputs = num_inputs;
482
483
484 i = 0;
485 uint64_t processed_outputs = 0;
486 unsigned num_outputs = 0;
487 nir_foreach_variable(variable, &nir->outputs) {
488 unsigned semantic_name, semantic_index;
489
490 i = variable->data.driver_location;
491
492 const struct glsl_type *type = variable->type;
493 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
494 assert(glsl_type_is_array(type));
495 type = glsl_get_array_element(type);
496 }
497
498 unsigned attrib_count = glsl_count_attribute_slots(type, false);
499 for (unsigned k = 0; k < attrib_count; k++, i++) {
500
501 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
502 tgsi_get_gl_frag_result_semantic(variable->data.location + k,
503 &semantic_name, &semantic_index);
504
505 /* Adjust for dual source blending */
506 if (variable->data.index > 0) {
507 semantic_index++;
508 }
509 } else {
510 tgsi_get_gl_varying_semantic(variable->data.location + k, true,
511 &semantic_name, &semantic_index);
512 }
513
514 unsigned num_components = 4;
515 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
516 if (vector_elements)
517 num_components = vector_elements;
518
519 unsigned component = variable->data.location_frac;
520 if (glsl_type_is_64bit(glsl_without_array(variable->type))) {
521 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)) && k % 2) {
522 num_components = (num_components * 2) - 4;
523 component = 0;
524 } else {
525 num_components = MIN2(num_components * 2, 4);
526 }
527 }
528
529 ubyte usagemask = 0;
530 for (unsigned j = component; j < num_components + component; j++) {
531 switch (j) {
532 case 0:
533 usagemask |= TGSI_WRITEMASK_X;
534 break;
535 case 1:
536 usagemask |= TGSI_WRITEMASK_Y;
537 break;
538 case 2:
539 usagemask |= TGSI_WRITEMASK_Z;
540 break;
541 case 3:
542 usagemask |= TGSI_WRITEMASK_W;
543 break;
544 default:
545 unreachable("error calculating component index");
546 }
547 }
548
549 unsigned gs_out_streams;
550 if (variable->data.stream & (1u << 31)) {
551 gs_out_streams = variable->data.stream & ~(1u << 31);
552 } else {
553 assert(variable->data.stream < 4);
554 gs_out_streams = 0;
555 for (unsigned j = 0; j < num_components; ++j)
556 gs_out_streams |= variable->data.stream << (2 * (component + j));
557 }
558
559 unsigned streamx = gs_out_streams & 3;
560 unsigned streamy = (gs_out_streams >> 2) & 3;
561 unsigned streamz = (gs_out_streams >> 4) & 3;
562 unsigned streamw = (gs_out_streams >> 6) & 3;
563
564 if (usagemask & TGSI_WRITEMASK_X) {
565 info->output_usagemask[i] |= TGSI_WRITEMASK_X;
566 info->output_streams[i] |= streamx;
567 info->num_stream_output_components[streamx]++;
568 }
569 if (usagemask & TGSI_WRITEMASK_Y) {
570 info->output_usagemask[i] |= TGSI_WRITEMASK_Y;
571 info->output_streams[i] |= streamy << 2;
572 info->num_stream_output_components[streamy]++;
573 }
574 if (usagemask & TGSI_WRITEMASK_Z) {
575 info->output_usagemask[i] |= TGSI_WRITEMASK_Z;
576 info->output_streams[i] |= streamz << 4;
577 info->num_stream_output_components[streamz]++;
578 }
579 if (usagemask & TGSI_WRITEMASK_W) {
580 info->output_usagemask[i] |= TGSI_WRITEMASK_W;
581 info->output_streams[i] |= streamw << 6;
582 info->num_stream_output_components[streamw]++;
583 }
584
585 /* make sure we only count this location once against
586 * the num_outputs counter.
587 */
588 if (processed_outputs & ((uint64_t)1 << i))
589 continue;
590
591 processed_outputs |= ((uint64_t)1 << i);
592 num_outputs++;
593
594 info->output_semantic_name[i] = semantic_name;
595 info->output_semantic_index[i] = semantic_index;
596
597 switch (semantic_name) {
598 case TGSI_SEMANTIC_PRIMID:
599 info->writes_primid = true;
600 break;
601 case TGSI_SEMANTIC_VIEWPORT_INDEX:
602 info->writes_viewport_index = true;
603 break;
604 case TGSI_SEMANTIC_LAYER:
605 info->writes_layer = true;
606 break;
607 case TGSI_SEMANTIC_PSIZE:
608 info->writes_psize = true;
609 break;
610 case TGSI_SEMANTIC_CLIPVERTEX:
611 info->writes_clipvertex = true;
612 break;
613 case TGSI_SEMANTIC_COLOR:
614 info->colors_written |= 1 << semantic_index;
615 break;
616 case TGSI_SEMANTIC_STENCIL:
617 info->writes_stencil = true;
618 break;
619 case TGSI_SEMANTIC_SAMPLEMASK:
620 info->writes_samplemask = true;
621 break;
622 case TGSI_SEMANTIC_EDGEFLAG:
623 info->writes_edgeflag = true;
624 break;
625 case TGSI_SEMANTIC_POSITION:
626 if (info->processor == PIPE_SHADER_FRAGMENT)
627 info->writes_z = true;
628 else
629 info->writes_position = true;
630 break;
631 }
632
633 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
634 switch (semantic_name) {
635 case TGSI_SEMANTIC_PATCH:
636 info->reads_perpatch_outputs = true;
637 break;
638 case TGSI_SEMANTIC_TESSINNER:
639 case TGSI_SEMANTIC_TESSOUTER:
640 info->reads_tessfactor_outputs = true;
641 break;
642 default:
643 info->reads_pervertex_outputs = true;
644 }
645 }
646 }
647
648 unsigned loc = variable->data.location;
649 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
650 loc == FRAG_RESULT_COLOR &&
651 nir->info.outputs_written & (1ull << loc)) {
652 assert(attrib_count == 1);
653 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
654 }
655 }
656
657 info->num_outputs = num_outputs;
658
659 struct set *ubo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
660 _mesa_key_pointer_equal);
661
662 /* Intialise const_file_max[0] */
663 info->const_file_max[0] = -1;
664
665 unsigned ubo_idx = 1;
666 nir_foreach_variable(variable, &nir->uniforms) {
667 const struct glsl_type *type = variable->type;
668 enum glsl_base_type base_type =
669 glsl_get_base_type(glsl_without_array(type));
670 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
671
672 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
673 * really use the mask (other than ubo_idx == 1 for regular
674 * uniforms) its really only used for getting the buffer count
675 * so we don't need to worry about the ordering.
676 */
677 if (variable->interface_type != NULL) {
678 if (variable->data.mode == nir_var_uniform ||
679 variable->data.mode == nir_var_ubo) {
680
681 unsigned block_count;
682 if (base_type != GLSL_TYPE_INTERFACE) {
683 struct set_entry *entry =
684 _mesa_set_search(ubo_set, variable->interface_type);
685
686 /* Check if we have already processed
687 * a member from this ubo.
688 */
689 if (entry)
690 continue;
691
692 block_count = 1;
693 } else {
694 block_count = aoa_size;
695 }
696
697 info->const_buffers_declared |= u_bit_consecutive(ubo_idx, block_count);
698 ubo_idx += block_count;
699
700 _mesa_set_add(ubo_set, variable->interface_type);
701 }
702
703 if (variable->data.mode == nir_var_ssbo) {
704 /* TODO: make this more accurate */
705 info->shader_buffers_declared =
706 u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
707 }
708
709 continue;
710 }
711
712 /* We rely on the fact that nir_lower_samplers_as_deref has
713 * eliminated struct dereferences.
714 */
715 if (base_type == GLSL_TYPE_SAMPLER) {
716 if (variable->data.bindless) {
717 info->const_buffers_declared |= 1;
718 info->const_file_max[0] +=
719 glsl_count_attribute_slots(type, false);
720 } else {
721 info->samplers_declared |=
722 u_bit_consecutive(variable->data.binding, aoa_size);
723 }
724 } else if (base_type == GLSL_TYPE_IMAGE) {
725 if (variable->data.bindless) {
726 info->const_buffers_declared |= 1;
727 info->const_file_max[0] +=
728 glsl_count_attribute_slots(type, false);
729 } else {
730 info->images_declared |=
731 u_bit_consecutive(variable->data.binding, aoa_size);
732 }
733 } else if (base_type != GLSL_TYPE_ATOMIC_UINT) {
734 if (strncmp(variable->name, "state.", 6) == 0 ||
735 strncmp(variable->name, "gl_", 3) == 0) {
736 /* FIXME: figure out why piglit tests with builtin
737 * uniforms are failing without this.
738 */
739 info->const_buffers_declared =
740 u_bit_consecutive(0, SI_NUM_CONST_BUFFERS);
741 } else {
742 info->const_buffers_declared |= 1;
743 info->const_file_max[0] +=
744 glsl_count_attribute_slots(type, false);
745 }
746 }
747 }
748
749 _mesa_set_destroy(ubo_set, NULL);
750
751 info->num_written_clipdistance = nir->info.clip_distance_array_size;
752 info->num_written_culldistance = nir->info.cull_distance_array_size;
753 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
754 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
755
756 if (info->processor == PIPE_SHADER_FRAGMENT)
757 info->uses_kill = nir->info.fs.uses_discard;
758
759 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
760 nir_foreach_block(block, func->impl) {
761 nir_foreach_instr(instr, block)
762 scan_instruction(info, instr);
763 }
764 }
765
766 /**
767 * Perform "lowering" operations on the NIR that are run once when the shader
768 * selector is created.
769 */
770 void
771 si_lower_nir(struct si_shader_selector* sel)
772 {
773 /* Adjust the driver location of inputs and outputs. The state tracker
774 * interprets them as slots, while the ac/nir backend interprets them
775 * as individual components.
776 */
777 nir_foreach_variable(variable, &sel->nir->inputs)
778 variable->data.driver_location *= 4;
779
780 nir_foreach_variable(variable, &sel->nir->outputs) {
781 variable->data.driver_location *= 4;
782
783 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
784 if (variable->data.location == FRAG_RESULT_DEPTH)
785 variable->data.driver_location += 2;
786 else if (variable->data.location == FRAG_RESULT_STENCIL)
787 variable->data.driver_location += 1;
788 }
789 }
790
791 /* Perform lowerings (and optimizations) of code.
792 *
793 * Performance considerations aside, we must:
794 * - lower certain ALU operations
795 * - ensure constant offsets for texture instructions are folded
796 * and copy-propagated
797 */
798 NIR_PASS_V(sel->nir, nir_lower_returns);
799 NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
800 NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
801 NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
802
803 static const struct nir_lower_tex_options lower_tex_options = {
804 .lower_txp = ~0u,
805 };
806 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
807
808 const nir_lower_subgroups_options subgroups_options = {
809 .subgroup_size = 64,
810 .ballot_bit_size = 64,
811 .lower_to_scalar = true,
812 .lower_subgroup_masks = true,
813 .lower_vote_trivial = false,
814 .lower_vote_eq_to_ballot = true,
815 };
816 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
817
818 ac_lower_indirect_derefs(sel->nir, sel->screen->info.chip_class);
819
820 bool progress;
821 do {
822 progress = false;
823
824 /* (Constant) copy propagation is needed for txf with offsets. */
825 NIR_PASS(progress, sel->nir, nir_copy_prop);
826 NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
827 NIR_PASS(progress, sel->nir, nir_opt_dce);
828 if (nir_opt_trivial_continues(sel->nir)) {
829 progress = true;
830 NIR_PASS(progress, sel->nir, nir_copy_prop);
831 NIR_PASS(progress, sel->nir, nir_opt_dce);
832 }
833 NIR_PASS(progress, sel->nir, nir_opt_if);
834 NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
835 NIR_PASS(progress, sel->nir, nir_opt_cse);
836 NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8, true, true);
837
838 /* Needed for algebraic lowering */
839 NIR_PASS(progress, sel->nir, nir_opt_algebraic);
840 NIR_PASS(progress, sel->nir, nir_opt_constant_folding);
841
842 NIR_PASS(progress, sel->nir, nir_opt_undef);
843 NIR_PASS(progress, sel->nir, nir_opt_conditional_discard);
844 if (sel->nir->options->max_unroll_iterations) {
845 NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
846 }
847 } while (progress);
848
849 NIR_PASS_V(sel->nir, nir_lower_bool_to_int32);
850 }
851
852 static void declare_nir_input_vs(struct si_shader_context *ctx,
853 struct nir_variable *variable,
854 unsigned input_index,
855 LLVMValueRef out[4])
856 {
857 si_llvm_load_input_vs(ctx, input_index, out);
858 }
859
860 static void declare_nir_input_fs(struct si_shader_context *ctx,
861 struct nir_variable *variable,
862 unsigned input_index,
863 LLVMValueRef out[4])
864 {
865 unsigned slot = variable->data.location;
866 if (slot == VARYING_SLOT_POS) {
867 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
868 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
869 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
870 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
871 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
872 return;
873 }
874
875 si_llvm_load_input_fs(ctx, input_index, out);
876 }
877
878 LLVMValueRef
879 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
880 enum glsl_interp_mode interp, unsigned location)
881 {
882 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
883 int interp_param_idx = -1;
884
885 switch (interp) {
886 case INTERP_MODE_FLAT:
887 return NULL;
888 case INTERP_MODE_SMOOTH:
889 case INTERP_MODE_NONE:
890 if (location == INTERP_CENTER)
891 interp_param_idx = SI_PARAM_PERSP_CENTER;
892 else if (location == INTERP_CENTROID)
893 interp_param_idx = SI_PARAM_PERSP_CENTROID;
894 else if (location == INTERP_SAMPLE)
895 interp_param_idx = SI_PARAM_PERSP_SAMPLE;
896 break;
897 case INTERP_MODE_NOPERSPECTIVE:
898 if (location == INTERP_CENTER)
899 interp_param_idx = SI_PARAM_LINEAR_CENTER;
900 else if (location == INTERP_CENTROID)
901 interp_param_idx = SI_PARAM_LINEAR_CENTROID;
902 else if (location == INTERP_SAMPLE)
903 interp_param_idx = SI_PARAM_LINEAR_SAMPLE;
904 break;
905 default:
906 assert(!"Unhandled interpolation mode.");
907 return NULL;
908 }
909
910 return interp_param_idx != -1 ?
911 LLVMGetParam(ctx->main_fn, interp_param_idx) : NULL;
912 }
913
914 static LLVMValueRef
915 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
916 unsigned descriptor_set, unsigned base_index,
917 unsigned constant_index, LLVMValueRef dynamic_index,
918 enum ac_descriptor_type desc_type, bool image,
919 bool write, bool bindless)
920 {
921 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
922 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
923 LLVMBuilderRef builder = ctx->ac.builder;
924 unsigned const_index = base_index + constant_index;
925 bool dcc_off = write;
926
927 /* TODO: images_store and images_atomic are not set */
928 if (!dynamic_index && image &&
929 (info->images_store | info->images_atomic) & (1 << const_index))
930 dcc_off = true;
931
932 assert(!descriptor_set);
933 assert(!image || desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
934
935 if (bindless) {
936 LLVMValueRef list =
937 LLVMGetParam(ctx->main_fn, ctx->param_bindless_samplers_and_images);
938
939 /* dynamic_index is the bindless handle */
940 if (image) {
941 return si_load_image_desc(ctx, list, dynamic_index, desc_type,
942 dcc_off, true);
943 }
944
945 /* Since bindless handle arithmetic can contain an unsigned integer
946 * wraparound and si_load_sampler_desc assumes there isn't any,
947 * use GEP without "inbounds" (inside ac_build_pointer_add)
948 * to prevent incorrect code generation and hangs.
949 */
950 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
951 LLVMConstInt(ctx->i32, 2, 0), "");
952 list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
953 return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
954 }
955
956 unsigned num_slots = image ? ctx->num_images : ctx->num_samplers;
957 assert(const_index < num_slots);
958
959 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
960 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, const_index, false);
961
962 if (dynamic_index) {
963 index = LLVMBuildAdd(builder, index, dynamic_index, "");
964
965 /* From the GL_ARB_shader_image_load_store extension spec:
966 *
967 * If a shader performs an image load, store, or atomic
968 * operation using an image variable declared as an array,
969 * and if the index used to select an individual element is
970 * negative or greater than or equal to the size of the
971 * array, the results of the operation are undefined but may
972 * not lead to termination.
973 */
974 index = si_llvm_bound_index(ctx, index, num_slots);
975 }
976
977 if (image) {
978 index = LLVMBuildSub(ctx->ac.builder,
979 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
980 index, "");
981 return si_load_image_desc(ctx, list, index, desc_type, dcc_off, false);
982 }
983
984 index = LLVMBuildAdd(ctx->ac.builder, index,
985 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
986 return si_load_sampler_desc(ctx, list, index, desc_type);
987 }
988
989 static void bitcast_inputs(struct si_shader_context *ctx,
990 LLVMValueRef data[4],
991 unsigned input_idx)
992 {
993 for (unsigned chan = 0; chan < 4; chan++) {
994 ctx->inputs[input_idx + chan] =
995 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
996 }
997 }
998
999 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
1000 {
1001 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1002
1003 if (nir->info.stage == MESA_SHADER_VERTEX ||
1004 nir->info.stage == MESA_SHADER_FRAGMENT) {
1005 uint64_t processed_inputs = 0;
1006 nir_foreach_variable(variable, &nir->inputs) {
1007 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
1008 nir->info.stage == MESA_SHADER_VERTEX);
1009 unsigned input_idx = variable->data.driver_location;
1010
1011 LLVMValueRef data[4];
1012 unsigned loc = variable->data.location;
1013
1014 for (unsigned i = 0; i < attrib_count; i++) {
1015 /* Packed components share the same location so skip
1016 * them if we have already processed the location.
1017 */
1018 if (processed_inputs & ((uint64_t)1 << (loc + i))) {
1019 input_idx += 4;
1020 continue;
1021 }
1022
1023 if (nir->info.stage == MESA_SHADER_VERTEX) {
1024 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1025 bitcast_inputs(ctx, data, input_idx);
1026 if (glsl_type_is_dual_slot(variable->type)) {
1027 input_idx += 4;
1028 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1029 bitcast_inputs(ctx, data, input_idx);
1030 }
1031 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1032 declare_nir_input_fs(ctx, variable, input_idx / 4, data);
1033 bitcast_inputs(ctx, data, input_idx);
1034 }
1035
1036 processed_inputs |= ((uint64_t)1 << (loc + i));
1037 input_idx += 4;
1038 }
1039 }
1040 }
1041
1042 ctx->abi.inputs = &ctx->inputs[0];
1043 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
1044 ctx->abi.clamp_shadow_reference = true;
1045
1046 ctx->num_samplers = util_last_bit(info->samplers_declared);
1047 ctx->num_images = util_last_bit(info->images_declared);
1048
1049 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
1050 assert(nir->info.stage == MESA_SHADER_COMPUTE);
1051 si_declare_compute_memory(ctx);
1052 }
1053 ac_nir_translate(&ctx->ac, &ctx->abi, nir);
1054
1055 return true;
1056 }