radeonsi: copy some nir gs info
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_shader.h"
25 #include "si_shader_internal.h"
26
27 #include "ac_nir_to_llvm.h"
28
29 #include "tgsi/tgsi_from_mesa.h"
30
31 #include "compiler/nir/nir.h"
32 #include "compiler/nir_types.h"
33
34
35 static int
36 type_size(const struct glsl_type *type)
37 {
38 return glsl_count_attribute_slots(type, false);
39 }
40
41 static void scan_instruction(struct tgsi_shader_info *info,
42 nir_instr *instr)
43 {
44 if (instr->type == nir_instr_type_alu) {
45 nir_alu_instr *alu = nir_instr_as_alu(instr);
46
47 switch (alu->op) {
48 case nir_op_fddx:
49 case nir_op_fddy:
50 case nir_op_fddx_fine:
51 case nir_op_fddy_fine:
52 case nir_op_fddx_coarse:
53 case nir_op_fddy_coarse:
54 info->uses_derivatives = true;
55 break;
56 default:
57 break;
58 }
59 } else if (instr->type == nir_instr_type_tex) {
60 nir_tex_instr *tex = nir_instr_as_tex(instr);
61
62 if (!tex->texture) {
63 info->samplers_declared |=
64 u_bit_consecutive(tex->sampler_index, 1);
65 }
66
67 switch (tex->op) {
68 case nir_texop_tex:
69 case nir_texop_txb:
70 case nir_texop_lod:
71 info->uses_derivatives = true;
72 break;
73 default:
74 break;
75 }
76 } else if (instr->type == nir_instr_type_intrinsic) {
77 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
78
79 switch (intr->intrinsic) {
80 case nir_intrinsic_load_front_face:
81 info->uses_frontface = 1;
82 break;
83 case nir_intrinsic_load_instance_id:
84 info->uses_instanceid = 1;
85 break;
86 case nir_intrinsic_load_vertex_id:
87 info->uses_vertexid = 1;
88 break;
89 case nir_intrinsic_load_vertex_id_zero_base:
90 info->uses_vertexid_nobase = 1;
91 break;
92 case nir_intrinsic_load_base_vertex:
93 info->uses_basevertex = 1;
94 break;
95 case nir_intrinsic_load_primitive_id:
96 info->uses_primid = 1;
97 break;
98 case nir_intrinsic_image_store:
99 case nir_intrinsic_image_atomic_add:
100 case nir_intrinsic_image_atomic_min:
101 case nir_intrinsic_image_atomic_max:
102 case nir_intrinsic_image_atomic_and:
103 case nir_intrinsic_image_atomic_or:
104 case nir_intrinsic_image_atomic_xor:
105 case nir_intrinsic_image_atomic_exchange:
106 case nir_intrinsic_image_atomic_comp_swap:
107 case nir_intrinsic_store_ssbo:
108 case nir_intrinsic_ssbo_atomic_add:
109 case nir_intrinsic_ssbo_atomic_imin:
110 case nir_intrinsic_ssbo_atomic_umin:
111 case nir_intrinsic_ssbo_atomic_imax:
112 case nir_intrinsic_ssbo_atomic_umax:
113 case nir_intrinsic_ssbo_atomic_and:
114 case nir_intrinsic_ssbo_atomic_or:
115 case nir_intrinsic_ssbo_atomic_xor:
116 case nir_intrinsic_ssbo_atomic_exchange:
117 case nir_intrinsic_ssbo_atomic_comp_swap:
118 info->writes_memory = true;
119 break;
120 default:
121 break;
122 }
123 }
124 }
125
126 void si_nir_scan_shader(const struct nir_shader *nir,
127 struct tgsi_shader_info *info)
128 {
129 nir_function *func;
130 unsigned i;
131
132 assert(nir->info.stage == MESA_SHADER_VERTEX ||
133 nir->info.stage == MESA_SHADER_FRAGMENT);
134
135 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
136 info->num_tokens = 2; /* indicate that the shader is non-empty */
137 info->num_instructions = 2;
138
139 info->num_inputs = nir->num_inputs;
140 info->num_outputs = nir->num_outputs;
141
142 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
143 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
144 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
145 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
146 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
147 }
148
149 i = 0;
150 nir_foreach_variable(variable, &nir->inputs) {
151 unsigned semantic_name, semantic_index;
152 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
153 nir->info.stage == MESA_SHADER_VERTEX);
154
155 assert(attrib_count == 1 && "not implemented");
156
157 /* Vertex shader inputs don't have semantics. The state
158 * tracker has already mapped them to attributes via
159 * variable->data.driver_location.
160 */
161 if (nir->info.stage == MESA_SHADER_VERTEX)
162 continue;
163
164 /* Fragment shader position is a system value. */
165 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
166 variable->data.location == VARYING_SLOT_POS) {
167 if (variable->data.pixel_center_integer)
168 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
169 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
170 continue;
171 }
172
173 tgsi_get_gl_varying_semantic(variable->data.location, true,
174 &semantic_name, &semantic_index);
175
176 info->input_semantic_name[i] = semantic_name;
177 info->input_semantic_index[i] = semantic_index;
178
179 if (variable->data.sample)
180 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
181 else if (variable->data.centroid)
182 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
183 else
184 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
185
186 enum glsl_base_type base_type =
187 glsl_get_base_type(glsl_without_array(variable->type));
188
189 switch (variable->data.interpolation) {
190 case INTERP_MODE_NONE:
191 if (glsl_base_type_is_integer(base_type)) {
192 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
193 break;
194 }
195
196 if (semantic_name == TGSI_SEMANTIC_COLOR) {
197 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
198 goto persp_locations;
199 }
200 /* fall-through */
201 case INTERP_MODE_SMOOTH:
202 assert(!glsl_base_type_is_integer(base_type));
203
204 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
205
206 persp_locations:
207 if (variable->data.sample)
208 info->uses_persp_sample = true;
209 else if (variable->data.centroid)
210 info->uses_persp_centroid = true;
211 else
212 info->uses_persp_center = true;
213 break;
214
215 case INTERP_MODE_NOPERSPECTIVE:
216 assert(!glsl_base_type_is_integer(base_type));
217
218 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
219
220 if (variable->data.sample)
221 info->uses_linear_sample = true;
222 else if (variable->data.centroid)
223 info->uses_linear_centroid = true;
224 else
225 info->uses_linear_center = true;
226 break;
227
228 case INTERP_MODE_FLAT:
229 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
230 break;
231 }
232
233 /* TODO make this more precise */
234 if (variable->data.location == VARYING_SLOT_COL0)
235 info->colors_read |= 0x0f;
236 else if (variable->data.location == VARYING_SLOT_COL1)
237 info->colors_read |= 0xf0;
238
239 i++;
240 }
241
242 i = 0;
243 nir_foreach_variable(variable, &nir->outputs) {
244 unsigned semantic_name, semantic_index;
245
246 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
247 tgsi_get_gl_frag_result_semantic(variable->data.location,
248 &semantic_name, &semantic_index);
249 } else {
250 tgsi_get_gl_varying_semantic(variable->data.location, true,
251 &semantic_name, &semantic_index);
252 }
253
254 info->output_semantic_name[i] = semantic_name;
255 info->output_semantic_index[i] = semantic_index;
256 info->output_usagemask[i] = TGSI_WRITEMASK_XYZW;
257
258 unsigned num_components = 4;
259 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
260 if (vector_elements)
261 num_components = vector_elements;
262
263 unsigned gs_out_streams;
264 if (variable->data.stream & (1u << 31)) {
265 gs_out_streams = variable->data.stream & ~(1u << 31);
266 } else {
267 assert(variable->data.stream < 4);
268 gs_out_streams = 0;
269 for (unsigned j = 0; j < num_components; ++j)
270 gs_out_streams |= variable->data.stream << (2 * (variable->data.location_frac + j));
271 }
272
273 unsigned streamx = gs_out_streams & 3;
274 unsigned streamy = (gs_out_streams >> 2) & 3;
275 unsigned streamz = (gs_out_streams >> 4) & 3;
276 unsigned streamw = (gs_out_streams >> 6) & 3;
277
278 if (info->output_usagemask[i] & TGSI_WRITEMASK_X) {
279 info->output_streams[i] |= streamx;
280 info->num_stream_output_components[streamx]++;
281 }
282 if (info->output_usagemask[i] & TGSI_WRITEMASK_Y) {
283 info->output_streams[i] |= streamy << 2;
284 info->num_stream_output_components[streamy]++;
285 }
286 if (info->output_usagemask[i] & TGSI_WRITEMASK_Z) {
287 info->output_streams[i] |= streamz << 4;
288 info->num_stream_output_components[streamz]++;
289 }
290 if (info->output_usagemask[i] & TGSI_WRITEMASK_W) {
291 info->output_streams[i] |= streamw << 6;
292 info->num_stream_output_components[streamw]++;
293 }
294
295 switch (semantic_name) {
296 case TGSI_SEMANTIC_PRIMID:
297 info->writes_primid = true;
298 break;
299 case TGSI_SEMANTIC_VIEWPORT_INDEX:
300 info->writes_viewport_index = true;
301 break;
302 case TGSI_SEMANTIC_LAYER:
303 info->writes_layer = true;
304 break;
305 case TGSI_SEMANTIC_PSIZE:
306 info->writes_psize = true;
307 break;
308 case TGSI_SEMANTIC_CLIPVERTEX:
309 info->writes_clipvertex = true;
310 break;
311 case TGSI_SEMANTIC_COLOR:
312 info->colors_written |= 1 << semantic_index;
313 break;
314 case TGSI_SEMANTIC_STENCIL:
315 info->writes_stencil = true;
316 break;
317 case TGSI_SEMANTIC_SAMPLEMASK:
318 info->writes_samplemask = true;
319 break;
320 case TGSI_SEMANTIC_EDGEFLAG:
321 info->writes_edgeflag = true;
322 break;
323 case TGSI_SEMANTIC_POSITION:
324 if (info->processor == PIPE_SHADER_FRAGMENT)
325 info->writes_z = true;
326 else
327 info->writes_position = true;
328 break;
329 }
330
331 i++;
332 }
333
334 nir_foreach_variable(variable, &nir->uniforms) {
335 const struct glsl_type *type = variable->type;
336 enum glsl_base_type base_type =
337 glsl_get_base_type(glsl_without_array(type));
338 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
339
340 /* We rely on the fact that nir_lower_samplers_as_deref has
341 * eliminated struct dereferences.
342 */
343 if (base_type == GLSL_TYPE_SAMPLER)
344 info->samplers_declared |=
345 u_bit_consecutive(variable->data.binding, aoa_size);
346 else if (base_type == GLSL_TYPE_IMAGE)
347 info->images_declared |=
348 u_bit_consecutive(variable->data.binding, aoa_size);
349 }
350
351 info->num_written_clipdistance = nir->info.clip_distance_array_size;
352 info->num_written_culldistance = nir->info.cull_distance_array_size;
353 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
354 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
355
356 if (info->processor == PIPE_SHADER_FRAGMENT)
357 info->uses_kill = nir->info.fs.uses_discard;
358
359 /* TODO make this more accurate */
360 info->const_buffers_declared = u_bit_consecutive(0, SI_NUM_CONST_BUFFERS);
361 info->shader_buffers_declared = u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
362
363 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
364 nir_foreach_block(block, func->impl) {
365 nir_foreach_instr(instr, block)
366 scan_instruction(info, instr);
367 }
368 }
369
370 /**
371 * Perform "lowering" operations on the NIR that are run once when the shader
372 * selector is created.
373 */
374 void
375 si_lower_nir(struct si_shader_selector* sel)
376 {
377 /* Adjust the driver location of inputs and outputs. The state tracker
378 * interprets them as slots, while the ac/nir backend interprets them
379 * as individual components.
380 */
381 nir_foreach_variable(variable, &sel->nir->inputs)
382 variable->data.driver_location *= 4;
383
384 nir_foreach_variable(variable, &sel->nir->outputs) {
385 variable->data.driver_location *= 4;
386
387 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
388 if (variable->data.location == FRAG_RESULT_DEPTH)
389 variable->data.driver_location += 2;
390 else if (variable->data.location == FRAG_RESULT_STENCIL)
391 variable->data.driver_location += 1;
392 }
393 }
394
395 /* Perform lowerings (and optimizations) of code.
396 *
397 * Performance considerations aside, we must:
398 * - lower certain ALU operations
399 * - ensure constant offsets for texture instructions are folded
400 * and copy-propagated
401 */
402 NIR_PASS_V(sel->nir, nir_lower_io, nir_var_uniform, type_size,
403 (nir_lower_io_options)0);
404 NIR_PASS_V(sel->nir, nir_lower_uniforms_to_ubo);
405
406 NIR_PASS_V(sel->nir, nir_lower_returns);
407 NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
408 NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
409 NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
410
411 static const struct nir_lower_tex_options lower_tex_options = {
412 .lower_txp = ~0u,
413 };
414 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
415
416 bool progress;
417 do {
418 progress = false;
419
420 /* (Constant) copy propagation is needed for txf with offsets. */
421 NIR_PASS(progress, sel->nir, nir_copy_prop);
422 NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
423 NIR_PASS(progress, sel->nir, nir_opt_dce);
424 if (nir_opt_trivial_continues(sel->nir)) {
425 progress = true;
426 NIR_PASS(progress, sel->nir, nir_copy_prop);
427 NIR_PASS(progress, sel->nir, nir_opt_dce);
428 }
429 NIR_PASS(progress, sel->nir, nir_opt_if);
430 NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
431 NIR_PASS(progress, sel->nir, nir_opt_cse);
432 NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8);
433
434 /* Needed for algebraic lowering */
435 NIR_PASS(progress, sel->nir, nir_opt_algebraic);
436 NIR_PASS(progress, sel->nir, nir_opt_constant_folding);
437
438 NIR_PASS(progress, sel->nir, nir_opt_undef);
439 NIR_PASS(progress, sel->nir, nir_opt_conditional_discard);
440 if (sel->nir->options->max_unroll_iterations) {
441 NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
442 }
443 } while (progress);
444 }
445
446 static void declare_nir_input_vs(struct si_shader_context *ctx,
447 struct nir_variable *variable, unsigned rel,
448 LLVMValueRef out[4])
449 {
450 si_llvm_load_input_vs(ctx, variable->data.driver_location / 4 + rel, out);
451 }
452
453 static void declare_nir_input_fs(struct si_shader_context *ctx,
454 struct nir_variable *variable, unsigned rel,
455 unsigned *fs_attr_idx,
456 LLVMValueRef out[4])
457 {
458 unsigned slot = variable->data.location + rel;
459
460 assert(variable->data.location >= VARYING_SLOT_VAR0 || rel == 0);
461
462 if (slot == VARYING_SLOT_POS) {
463 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
464 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
465 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
466 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
467 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
468 return;
469 }
470
471 si_llvm_load_input_fs(ctx, *fs_attr_idx, out);
472 (*fs_attr_idx)++;
473 }
474
475 static LLVMValueRef
476 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
477 unsigned descriptor_set, unsigned base_index,
478 unsigned constant_index, LLVMValueRef dynamic_index,
479 enum ac_descriptor_type desc_type, bool image,
480 bool write)
481 {
482 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
483 LLVMBuilderRef builder = ctx->ac.builder;
484 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
485 LLVMValueRef index = dynamic_index;
486
487 assert(!descriptor_set);
488
489 if (!index)
490 index = ctx->ac.i32_0;
491
492 index = LLVMBuildAdd(builder, index,
493 LLVMConstInt(ctx->ac.i32, base_index + constant_index, false),
494 "");
495
496 if (image) {
497 assert(desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
498 assert(base_index + constant_index < ctx->num_images);
499
500 if (dynamic_index)
501 index = si_llvm_bound_index(ctx, index, ctx->num_images);
502
503 index = LLVMBuildSub(ctx->gallivm.builder,
504 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
505 index, "");
506
507 /* TODO: be smarter about when we use dcc_off */
508 return si_load_image_desc(ctx, list, index, desc_type, write);
509 }
510
511 assert(base_index + constant_index < ctx->num_samplers);
512
513 if (dynamic_index)
514 index = si_llvm_bound_index(ctx, index, ctx->num_samplers);
515
516 index = LLVMBuildAdd(ctx->gallivm.builder, index,
517 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
518
519 return si_load_sampler_desc(ctx, list, index, desc_type);
520 }
521
522 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
523 {
524 struct tgsi_shader_info *info = &ctx->shader->selector->info;
525
526 unsigned fs_attr_idx = 0;
527 nir_foreach_variable(variable, &nir->inputs) {
528 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
529 nir->info.stage == MESA_SHADER_VERTEX);
530 unsigned input_idx = variable->data.driver_location;
531
532 for (unsigned i = 0; i < attrib_count; ++i) {
533 LLVMValueRef data[4];
534
535 if (nir->info.stage == MESA_SHADER_VERTEX)
536 declare_nir_input_vs(ctx, variable, i, data);
537 else if (nir->info.stage == MESA_SHADER_FRAGMENT)
538 declare_nir_input_fs(ctx, variable, i, &fs_attr_idx, data);
539
540 for (unsigned chan = 0; chan < 4; chan++) {
541 ctx->inputs[input_idx + chan] =
542 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
543 }
544 }
545 }
546
547 ctx->abi.inputs = &ctx->inputs[0];
548 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
549 ctx->abi.clamp_shadow_reference = true;
550
551 ctx->num_samplers = util_last_bit(info->samplers_declared);
552 ctx->num_images = util_last_bit(info->images_declared);
553
554 ac_nir_translate(&ctx->ac, &ctx->abi, nir, NULL);
555
556 return true;
557 }