src/gallium/drivers/radeonsi/si_shader_nir.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include "si_shader.h"
  25 #include "si_shader_internal.h"
  26
  27 #include "ac_nir_to_llvm.h"
  28
  29 #include "tgsi/tgsi_from_mesa.h"
  30
  31 #include "compiler/nir/nir.h"
  32 #include "compiler/nir_types.h"
  33
  34
  35 static int
  36 type_size(const struct glsl_type *type)
  37 {
  38    return glsl_count_attribute_slots(type, false);
  39 }
  40
  41 static void scan_instruction(struct tgsi_shader_info *info,
  42                              nir_instr *instr)
  43 {
  44         if (instr->type == nir_instr_type_alu) {
  45                 nir_alu_instr *alu = nir_instr_as_alu(instr);
  46
  47                 switch (alu->op) {
  48                 case nir_op_fddx:
  49                 case nir_op_fddy:
  50                 case nir_op_fddx_fine:
  51                 case nir_op_fddy_fine:
  52                 case nir_op_fddx_coarse:
  53                 case nir_op_fddy_coarse:
  54                         info->uses_derivatives = true;
  55                         break;
  56                 default:
  57                         break;
  58                 }
  59         } else if (instr->type == nir_instr_type_tex) {
  60                 nir_tex_instr *tex = nir_instr_as_tex(instr);
  61
  62                 if (!tex->texture) {
  63                         info->samplers_declared |=
  64                                 u_bit_consecutive(tex->sampler_index, 1);
  65                 }
  66
  67                 switch (tex->op) {
  68                 case nir_texop_tex:
  69                 case nir_texop_txb:
  70                 case nir_texop_lod:
  71                         info->uses_derivatives = true;
  72                         break;
  73                 default:
  74                         break;
  75                 }
  76         } else if (instr->type == nir_instr_type_intrinsic) {
  77                 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
  78
  79                 switch (intr->intrinsic) {
  80                 case nir_intrinsic_load_front_face:
  81                         info->uses_frontface = 1;
  82                         break;
  83                 case nir_intrinsic_load_instance_id:
  84                         info->uses_instanceid = 1;
  85                         break;
  86                 case nir_intrinsic_load_invocation_id:
  87                         info->uses_invocationid = true;
  88                         break;
  89                 case nir_intrinsic_load_vertex_id:
  90                         info->uses_vertexid = 1;
  91                         break;
  92                 case nir_intrinsic_load_vertex_id_zero_base:
  93                         info->uses_vertexid_nobase = 1;
  94                         break;
  95                 case nir_intrinsic_load_base_vertex:
  96                         info->uses_basevertex = 1;
  97                         break;
  98                 case nir_intrinsic_load_primitive_id:
  99                         info->uses_primid = 1;
 100                         break;
 101                 case nir_intrinsic_load_tess_level_inner:
 102                 case nir_intrinsic_load_tess_level_outer:
 103                         info->reads_tess_factors = true;
 104                         break;
 105                 case nir_intrinsic_image_store:
 106                 case nir_intrinsic_image_atomic_add:
 107                 case nir_intrinsic_image_atomic_min:
 108                 case nir_intrinsic_image_atomic_max:
 109                 case nir_intrinsic_image_atomic_and:
 110                 case nir_intrinsic_image_atomic_or:
 111                 case nir_intrinsic_image_atomic_xor:
 112                 case nir_intrinsic_image_atomic_exchange:
 113                 case nir_intrinsic_image_atomic_comp_swap:
 114                 case nir_intrinsic_store_ssbo:
 115                 case nir_intrinsic_ssbo_atomic_add:
 116                 case nir_intrinsic_ssbo_atomic_imin:
 117                 case nir_intrinsic_ssbo_atomic_umin:
 118                 case nir_intrinsic_ssbo_atomic_imax:
 119                 case nir_intrinsic_ssbo_atomic_umax:
 120                 case nir_intrinsic_ssbo_atomic_and:
 121                 case nir_intrinsic_ssbo_atomic_or:
 122                 case nir_intrinsic_ssbo_atomic_xor:
 123                 case nir_intrinsic_ssbo_atomic_exchange:
 124                 case nir_intrinsic_ssbo_atomic_comp_swap:
 125                         info->writes_memory = true;
 126                         break;
 127                 default:
 128                         break;
 129                 }
 130         }
 131 }
 132
 133 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
 134                            const struct tgsi_shader_info *info,
 135                            struct tgsi_tessctrl_info *out)
 136 {
 137         memset(out, 0, sizeof(*out));
 138
 139         if (nir->info.stage != MESA_SHADER_TESS_CTRL)
 140                 return;
 141
 142         /* Initial value = true. Here the pass will accumulate results from
 143          * multiple segments surrounded by barriers. If tess factors aren't
 144          * written at all, it's a shader bug and we don't care if this will be
 145          * true.
 146          */
 147         out->tessfactors_are_def_in_all_invocs = true;
 148
 149         /* TODO: Implement scanning of tess factors, see tgsi backend. */
 150 }
 151
 152 void si_nir_scan_shader(const struct nir_shader *nir,
 153                         struct tgsi_shader_info *info)
 154 {
 155         nir_function *func;
 156         unsigned i;
 157
 158         assert(nir->info.stage == MESA_SHADER_VERTEX ||
 159                nir->info.stage == MESA_SHADER_GEOMETRY ||
 160                nir->info.stage == MESA_SHADER_TESS_CTRL ||
 161                nir->info.stage == MESA_SHADER_TESS_EVAL ||
 162                nir->info.stage == MESA_SHADER_FRAGMENT);
 163
 164         info->processor = pipe_shader_type_from_mesa(nir->info.stage);
 165         info->num_tokens = 2; /* indicate that the shader is non-empty */
 166         info->num_instructions = 2;
 167
 168         if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
 169                 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
 170                         nir->info.tess.tcs_vertices_out;
 171         }
 172
 173         if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
 174                 if (nir->info.tess.primitive_mode == GL_ISOLINES)
 175                         info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
 176                 else
 177                         info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
 178
 179                 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
 180                 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
 181                               PIPE_TESS_SPACING_FRACTIONAL_ODD);
 182                 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
 183                               PIPE_TESS_SPACING_FRACTIONAL_EVEN);
 184
 185                 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
 186                 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
 187                 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
 188         }
 189
 190         if (nir->info.stage == MESA_SHADER_GEOMETRY) {
 191                 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
 192                 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
 193                 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
 194                 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
 195         }
 196
 197         i = 0;
 198         uint64_t processed_inputs = 0;
 199         unsigned num_inputs = 0;
 200         nir_foreach_variable(variable, &nir->inputs) {
 201                 unsigned semantic_name, semantic_index;
 202                 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
 203                                                                    nir->info.stage == MESA_SHADER_VERTEX);
 204
 205                 /* Vertex shader inputs don't have semantics. The state
 206                  * tracker has already mapped them to attributes via
 207                  * variable->data.driver_location.
 208                  */
 209                 if (nir->info.stage == MESA_SHADER_VERTEX)
 210                         continue;
 211
 212                 assert(nir->info.stage != MESA_SHADER_FRAGMENT ||
 213                        (attrib_count == 1 && "not implemented"));
 214
 215                 /* Fragment shader position is a system value. */
 216                 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
 217                     variable->data.location == VARYING_SLOT_POS) {
 218                         if (variable->data.pixel_center_integer)
 219                                 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
 220                                         TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
 221
 222                         num_inputs++;
 223                         continue;
 224                 }
 225
 226                 i = variable->data.driver_location;
 227                 if (processed_inputs & ((uint64_t)1 << i))
 228                         continue;
 229
 230                 processed_inputs |= ((uint64_t)1 << i);
 231                 num_inputs++;
 232
 233                 tgsi_get_gl_varying_semantic(variable->data.location, true,
 234                                              &semantic_name, &semantic_index);
 235
 236                 info->input_semantic_name[i] = semantic_name;
 237                 info->input_semantic_index[i] = semantic_index;
 238
 239                 if (variable->data.sample)
 240                         info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
 241                 else if (variable->data.centroid)
 242                         info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
 243                 else
 244                         info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
 245
 246                 enum glsl_base_type base_type =
 247                         glsl_get_base_type(glsl_without_array(variable->type));
 248
 249                 switch (variable->data.interpolation) {
 250                 case INTERP_MODE_NONE:
 251                         if (glsl_base_type_is_integer(base_type)) {
 252                                 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
 253                                 break;
 254                         }
 255
 256                         if (semantic_name == TGSI_SEMANTIC_COLOR) {
 257                                 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
 258                                 goto persp_locations;
 259                         }
 260                         /* fall-through */
 261                 case INTERP_MODE_SMOOTH:
 262                         assert(!glsl_base_type_is_integer(base_type));
 263
 264                         info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
 265
 266                 persp_locations:
 267                         if (variable->data.sample)
 268                                 info->uses_persp_sample = true;
 269                         else if (variable->data.centroid)
 270                                 info->uses_persp_centroid = true;
 271                         else
 272                                 info->uses_persp_center = true;
 273                         break;
 274
 275                 case INTERP_MODE_NOPERSPECTIVE:
 276                         assert(!glsl_base_type_is_integer(base_type));
 277
 278                         info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
 279
 280                         if (variable->data.sample)
 281                                 info->uses_linear_sample = true;
 282                         else if (variable->data.centroid)
 283                                 info->uses_linear_centroid = true;
 284                         else
 285                                 info->uses_linear_center = true;
 286                         break;
 287
 288                 case INTERP_MODE_FLAT:
 289                         info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
 290                         break;
 291                 }
 292
 293                 /* TODO make this more precise */
 294                 if (variable->data.location == VARYING_SLOT_COL0)
 295                         info->colors_read |= 0x0f;
 296                 else if (variable->data.location == VARYING_SLOT_COL1)
 297                         info->colors_read |= 0xf0;
 298         }
 299
 300         if (nir->info.stage != MESA_SHADER_VERTEX)
 301                 info->num_inputs = num_inputs;
 302         else
 303                 info->num_inputs = nir->num_inputs;
 304
 305         i = 0;
 306         uint64_t processed_outputs = 0;
 307         unsigned num_outputs = 0;
 308         nir_foreach_variable(variable, &nir->outputs) {
 309                 unsigned semantic_name, semantic_index;
 310
 311                 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 312                         tgsi_get_gl_frag_result_semantic(variable->data.location,
 313                                 &semantic_name, &semantic_index);
 314                 } else {
 315                         tgsi_get_gl_varying_semantic(variable->data.location, true,
 316                                                      &semantic_name, &semantic_index);
 317                 }
 318
 319                 i = variable->data.driver_location;
 320                 if (processed_outputs & ((uint64_t)1 << i))
 321                         continue;
 322
 323                 processed_outputs |= ((uint64_t)1 << i);
 324                 num_outputs++;
 325
 326                 info->output_semantic_name[i] = semantic_name;
 327                 info->output_semantic_index[i] = semantic_index;
 328                 info->output_usagemask[i] = TGSI_WRITEMASK_XYZW;
 329
 330                 unsigned num_components = 4;
 331                 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
 332                 if (vector_elements)
 333                         num_components = vector_elements;
 334
 335                 unsigned gs_out_streams;
 336                 if (variable->data.stream & (1u << 31)) {
 337                         gs_out_streams = variable->data.stream & ~(1u << 31);
 338                 } else {
 339                         assert(variable->data.stream < 4);
 340                         gs_out_streams = 0;
 341                         for (unsigned j = 0; j < num_components; ++j)
 342                                 gs_out_streams |= variable->data.stream << (2 * (variable->data.location_frac + j));
 343                 }
 344
 345                 unsigned streamx = gs_out_streams & 3;
 346                 unsigned streamy = (gs_out_streams >> 2) & 3;
 347                 unsigned streamz = (gs_out_streams >> 4) & 3;
 348                 unsigned streamw = (gs_out_streams >> 6) & 3;
 349
 350                 if (info->output_usagemask[i] & TGSI_WRITEMASK_X) {
 351                         info->output_streams[i] |= streamx;
 352                         info->num_stream_output_components[streamx]++;
 353                 }
 354                 if (info->output_usagemask[i] & TGSI_WRITEMASK_Y) {
 355                         info->output_streams[i] |= streamy << 2;
 356                         info->num_stream_output_components[streamy]++;
 357                 }
 358                 if (info->output_usagemask[i] & TGSI_WRITEMASK_Z) {
 359                         info->output_streams[i] |= streamz << 4;
 360                         info->num_stream_output_components[streamz]++;
 361                 }
 362                 if (info->output_usagemask[i] & TGSI_WRITEMASK_W) {
 363                         info->output_streams[i] |= streamw << 6;
 364                         info->num_stream_output_components[streamw]++;
 365                 }
 366
 367                 switch (semantic_name) {
 368                 case TGSI_SEMANTIC_PRIMID:
 369                         info->writes_primid = true;
 370                         break;
 371                 case TGSI_SEMANTIC_VIEWPORT_INDEX:
 372                         info->writes_viewport_index = true;
 373                         break;
 374                 case TGSI_SEMANTIC_LAYER:
 375                         info->writes_layer = true;
 376                         break;
 377                 case TGSI_SEMANTIC_PSIZE:
 378                         info->writes_psize = true;
 379                         break;
 380                 case TGSI_SEMANTIC_CLIPVERTEX:
 381                         info->writes_clipvertex = true;
 382                         break;
 383                 case TGSI_SEMANTIC_COLOR:
 384                         info->colors_written |= 1 << semantic_index;
 385                         break;
 386                 case TGSI_SEMANTIC_STENCIL:
 387                         info->writes_stencil = true;
 388                         break;
 389                 case TGSI_SEMANTIC_SAMPLEMASK:
 390                         info->writes_samplemask = true;
 391                         break;
 392                 case TGSI_SEMANTIC_EDGEFLAG:
 393                         info->writes_edgeflag = true;
 394                         break;
 395                 case TGSI_SEMANTIC_POSITION:
 396                         if (info->processor == PIPE_SHADER_FRAGMENT)
 397                                 info->writes_z = true;
 398                         else
 399                                 info->writes_position = true;
 400                         break;
 401                 }
 402
 403                 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
 404                         switch (semantic_name) {
 405                         case TGSI_SEMANTIC_PATCH:
 406                                 info->reads_perpatch_outputs = true;
 407                         break;
 408                         case TGSI_SEMANTIC_TESSINNER:
 409                         case TGSI_SEMANTIC_TESSOUTER:
 410                                 info->reads_tessfactor_outputs = true;
 411                         break;
 412                         default:
 413                                 info->reads_pervertex_outputs = true;
 414                         }
 415                 }
 416         }
 417
 418         info->num_outputs = num_outputs;
 419
 420         nir_foreach_variable(variable, &nir->uniforms) {
 421                 const struct glsl_type *type = variable->type;
 422                 enum glsl_base_type base_type =
 423                         glsl_get_base_type(glsl_without_array(type));
 424                 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
 425
 426                 /* We rely on the fact that nir_lower_samplers_as_deref has
 427                  * eliminated struct dereferences.
 428                  */
 429                 if (base_type == GLSL_TYPE_SAMPLER)
 430                         info->samplers_declared |=
 431                                 u_bit_consecutive(variable->data.binding, aoa_size);
 432                 else if (base_type == GLSL_TYPE_IMAGE)
 433                         info->images_declared |=
 434                                 u_bit_consecutive(variable->data.binding, aoa_size);
 435         }
 436
 437         info->num_written_clipdistance = nir->info.clip_distance_array_size;
 438         info->num_written_culldistance = nir->info.cull_distance_array_size;
 439         info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
 440         info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
 441
 442         if (info->processor == PIPE_SHADER_FRAGMENT)
 443                 info->uses_kill = nir->info.fs.uses_discard;
 444
 445         /* TODO make this more accurate */
 446         info->const_buffers_declared = u_bit_consecutive(0, SI_NUM_CONST_BUFFERS);
 447         info->shader_buffers_declared = u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
 448
 449         func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
 450         nir_foreach_block(block, func->impl) {
 451                 nir_foreach_instr(instr, block)
 452                         scan_instruction(info, instr);
 453         }
 454 }
 455
 456 /**
 457  * Perform "lowering" operations on the NIR that are run once when the shader
 458  * selector is created.
 459  */
 460 void
 461 si_lower_nir(struct si_shader_selector* sel)
 462 {
 463         /* Adjust the driver location of inputs and outputs. The state tracker
 464          * interprets them as slots, while the ac/nir backend interprets them
 465          * as individual components.
 466          */
 467         nir_foreach_variable(variable, &sel->nir->inputs)
 468                 variable->data.driver_location *= 4;
 469
 470         nir_foreach_variable(variable, &sel->nir->outputs) {
 471                 variable->data.driver_location *= 4;
 472
 473                 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
 474                         if (variable->data.location == FRAG_RESULT_DEPTH)
 475                                 variable->data.driver_location += 2;
 476                         else if (variable->data.location == FRAG_RESULT_STENCIL)
 477                                 variable->data.driver_location += 1;
 478                 }
 479         }
 480
 481         /* Perform lowerings (and optimizations) of code.
 482          *
 483          * Performance considerations aside, we must:
 484          * - lower certain ALU operations
 485          * - ensure constant offsets for texture instructions are folded
 486          *   and copy-propagated
 487          */
 488         NIR_PASS_V(sel->nir, nir_lower_io, nir_var_uniform, type_size,
 489                    (nir_lower_io_options)0);
 490         NIR_PASS_V(sel->nir, nir_lower_uniforms_to_ubo);
 491
 492         NIR_PASS_V(sel->nir, nir_lower_returns);
 493         NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
 494         NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
 495         NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
 496
 497         static const struct nir_lower_tex_options lower_tex_options = {
 498                 .lower_txp = ~0u,
 499         };
 500         NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
 501
 502         bool progress;
 503         do {
 504                 progress = false;
 505
 506                 /* (Constant) copy propagation is needed for txf with offsets. */
 507                 NIR_PASS(progress, sel->nir, nir_copy_prop);
 508                 NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
 509                 NIR_PASS(progress, sel->nir, nir_opt_dce);
 510                 if (nir_opt_trivial_continues(sel->nir)) {
 511                         progress = true;
 512                         NIR_PASS(progress, sel->nir, nir_copy_prop);
 513                         NIR_PASS(progress, sel->nir, nir_opt_dce);
 514                 }
 515                 NIR_PASS(progress, sel->nir, nir_opt_if);
 516                 NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
 517                 NIR_PASS(progress, sel->nir, nir_opt_cse);
 518                 NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8);
 519
 520                 /* Needed for algebraic lowering */
 521                 NIR_PASS(progress, sel->nir, nir_opt_algebraic);
 522                 NIR_PASS(progress, sel->nir, nir_opt_constant_folding);
 523
 524                 NIR_PASS(progress, sel->nir, nir_opt_undef);
 525                 NIR_PASS(progress, sel->nir, nir_opt_conditional_discard);
 526                 if (sel->nir->options->max_unroll_iterations) {
 527                         NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
 528                 }
 529         } while (progress);
 530 }
 531
 532 static void declare_nir_input_vs(struct si_shader_context *ctx,
 533                                  struct nir_variable *variable,
 534                                  LLVMValueRef out[4])
 535 {
 536         si_llvm_load_input_vs(ctx, variable->data.driver_location / 4, out);
 537 }
 538
 539 static void declare_nir_input_fs(struct si_shader_context *ctx,
 540                                  struct nir_variable *variable,
 541                                  unsigned input_index,
 542                                  LLVMValueRef out[4])
 543 {
 544         unsigned slot = variable->data.location;
 545         if (slot == VARYING_SLOT_POS) {
 546                 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
 547                 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
 548                 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
 549                 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
 550                                 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
 551                 return;
 552         }
 553
 554         si_llvm_load_input_fs(ctx, input_index, out);
 555 }
 556
 557 LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
 558                                   unsigned location,
 559                                   unsigned driver_location,
 560                                   unsigned component,
 561                                   unsigned num_components,
 562                                   unsigned vertex_index,
 563                                   unsigned const_index,
 564                                   LLVMTypeRef type)
 565 {
 566         struct si_shader_context *ctx = si_shader_context_from_abi(abi);
 567
 568         LLVMValueRef value[4];
 569         for (unsigned i = component; i < num_components + component; i++) {
 570                 value[i] = si_llvm_load_input_gs(&ctx->abi, driver_location  / 4,
 571                                                  vertex_index, type, i);
 572         }
 573
 574         return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
 575 }
 576
 577 static LLVMValueRef
 578 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
 579                          unsigned descriptor_set, unsigned base_index,
 580                          unsigned constant_index, LLVMValueRef dynamic_index,
 581                          enum ac_descriptor_type desc_type, bool image,
 582                          bool write)
 583 {
 584         struct si_shader_context *ctx = si_shader_context_from_abi(abi);
 585         LLVMBuilderRef builder = ctx->ac.builder;
 586         LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
 587         LLVMValueRef index = dynamic_index;
 588
 589         assert(!descriptor_set);
 590
 591         if (!index)
 592                 index = ctx->ac.i32_0;
 593
 594         index = LLVMBuildAdd(builder, index,
 595                              LLVMConstInt(ctx->ac.i32, base_index + constant_index, false),
 596                              "");
 597
 598         if (image) {
 599                 assert(desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
 600                 assert(base_index + constant_index < ctx->num_images);
 601
 602                 if (dynamic_index)
 603                         index = si_llvm_bound_index(ctx, index, ctx->num_images);
 604
 605                 index = LLVMBuildSub(ctx->gallivm.builder,
 606                                      LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
 607                                      index, "");
 608
 609                 /* TODO: be smarter about when we use dcc_off */
 610                 return si_load_image_desc(ctx, list, index, desc_type, write);
 611         }
 612
 613         assert(base_index + constant_index < ctx->num_samplers);
 614
 615         if (dynamic_index)
 616                 index = si_llvm_bound_index(ctx, index, ctx->num_samplers);
 617
 618         index = LLVMBuildAdd(ctx->gallivm.builder, index,
 619                              LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
 620
 621         return si_load_sampler_desc(ctx, list, index, desc_type);
 622 }
 623
 624 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
 625 {
 626         struct tgsi_shader_info *info = &ctx->shader->selector->info;
 627
 628         if (nir->info.stage == MESA_SHADER_VERTEX ||
 629             nir->info.stage == MESA_SHADER_FRAGMENT) {
 630                 uint64_t processed_inputs = 0;
 631                 nir_foreach_variable(variable, &nir->inputs) {
 632                         unsigned attrib_count = glsl_count_attribute_slots(variable->type,
 633                                                                            nir->info.stage == MESA_SHADER_VERTEX);
 634                         unsigned input_idx = variable->data.driver_location;
 635
 636                         assert(attrib_count == 1);
 637
 638                         LLVMValueRef data[4];
 639                         unsigned loc = variable->data.location;
 640
 641                         /* Packed components share the same location so skip
 642                          * them if we have already processed the location.
 643                          */
 644                         if (processed_inputs & ((uint64_t)1 << loc))
 645                                 continue;
 646
 647                         if (nir->info.stage == MESA_SHADER_VERTEX)
 648                                 declare_nir_input_vs(ctx, variable, data);
 649                         else if (nir->info.stage == MESA_SHADER_FRAGMENT)
 650                                 declare_nir_input_fs(ctx, variable, input_idx / 4, data);
 651
 652                         for (unsigned chan = 0; chan < 4; chan++) {
 653                                 ctx->inputs[input_idx + chan] =
 654                                         LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
 655                         }
 656                         processed_inputs |= ((uint64_t)1 << loc);
 657                 }
 658         }
 659
 660         ctx->abi.inputs = &ctx->inputs[0];
 661         ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
 662         ctx->abi.clamp_shadow_reference = true;
 663
 664         ctx->num_samplers = util_last_bit(info->samplers_declared);
 665         ctx->num_images = util_last_bit(info->images_declared);
 666
 667         ac_nir_translate(&ctx->ac, &ctx->abi, nir, NULL);
 668
 669         return true;
 670 }