projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: make si_declare_compute_memory() more generic and call for nir
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_shader.h"
25 #include "si_shader_internal.h"
26
27 #include "ac_nir_to_llvm.h"
28
29 #include "tgsi/tgsi_from_mesa.h"
30
31 #include "compiler/nir/nir.h"
32 #include "compiler/nir_types.h"
33
34
35 static int
36 type_size(const struct glsl_type *type)
37 {
38 return glsl_count_attribute_slots(type, false);
39 }
40
41 static void scan_instruction(struct tgsi_shader_info *info,
42 nir_instr *instr)
43 {
44 if (instr->type == nir_instr_type_alu) {
45 nir_alu_instr *alu = nir_instr_as_alu(instr);
46
47 switch (alu->op) {
48 case nir_op_fddx:
49 case nir_op_fddy:
50 case nir_op_fddx_fine:
51 case nir_op_fddy_fine:
52 case nir_op_fddx_coarse:
53 case nir_op_fddy_coarse:
54 info->uses_derivatives = true;
55 break;
56 default:
57 break;
58 }
59 } else if (instr->type == nir_instr_type_tex) {
60 nir_tex_instr *tex = nir_instr_as_tex(instr);
61
62 if (!tex->texture) {
63 info->samplers_declared |=
64 u_bit_consecutive(tex->sampler_index, 1);
65 }
66
67 switch (tex->op) {
68 case nir_texop_tex:
69 case nir_texop_txb:
70 case nir_texop_lod:
71 info->uses_derivatives = true;
72 break;
73 default:
74 break;
75 }
76 } else if (instr->type == nir_instr_type_intrinsic) {
77 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
78
79 switch (intr->intrinsic) {
80 case nir_intrinsic_load_front_face:
81 info->uses_frontface = 1;
82 break;
83 case nir_intrinsic_load_instance_id:
84 info->uses_instanceid = 1;
85 break;
86 case nir_intrinsic_load_invocation_id:
87 info->uses_invocationid = true;
88 break;
89 case nir_intrinsic_load_num_work_groups:
90 info->uses_grid_size = true;
91 break;
92 case nir_intrinsic_load_local_group_size:
93 /* The block size is translated to IMM with a fixed block size. */
94 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
95 info->uses_block_size = true;
96 break;
97 case nir_intrinsic_load_local_invocation_id:
98 case nir_intrinsic_load_work_group_id: {
99 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
100 while (mask) {
101 unsigned i = u_bit_scan(&mask);
102
103 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
104 info->uses_block_id[i] = true;
105 else
106 info->uses_thread_id[i] = true;
107 }
108 break;
109 }
110 case nir_intrinsic_load_vertex_id:
111 info->uses_vertexid = 1;
112 break;
113 case nir_intrinsic_load_vertex_id_zero_base:
114 info->uses_vertexid_nobase = 1;
115 break;
116 case nir_intrinsic_load_base_vertex:
117 info->uses_basevertex = 1;
118 break;
119 case nir_intrinsic_load_primitive_id:
120 info->uses_primid = 1;
121 break;
122 case nir_intrinsic_load_sample_mask_in:
123 info->reads_samplemask = true;
124 break;
125 case nir_intrinsic_load_tess_level_inner:
126 case nir_intrinsic_load_tess_level_outer:
127 info->reads_tess_factors = true;
128 break;
129 case nir_intrinsic_image_store:
130 case nir_intrinsic_image_atomic_add:
131 case nir_intrinsic_image_atomic_min:
132 case nir_intrinsic_image_atomic_max:
133 case nir_intrinsic_image_atomic_and:
134 case nir_intrinsic_image_atomic_or:
135 case nir_intrinsic_image_atomic_xor:
136 case nir_intrinsic_image_atomic_exchange:
137 case nir_intrinsic_image_atomic_comp_swap:
138 case nir_intrinsic_store_ssbo:
139 case nir_intrinsic_ssbo_atomic_add:
140 case nir_intrinsic_ssbo_atomic_imin:
141 case nir_intrinsic_ssbo_atomic_umin:
142 case nir_intrinsic_ssbo_atomic_imax:
143 case nir_intrinsic_ssbo_atomic_umax:
144 case nir_intrinsic_ssbo_atomic_and:
145 case nir_intrinsic_ssbo_atomic_or:
146 case nir_intrinsic_ssbo_atomic_xor:
147 case nir_intrinsic_ssbo_atomic_exchange:
148 case nir_intrinsic_ssbo_atomic_comp_swap:
149 info->writes_memory = true;
150 break;
151 case nir_intrinsic_load_var: {
152 nir_variable *var = intr->variables[0]->var;
153 nir_variable_mode mode = var->data.mode;
154 enum glsl_base_type base_type =
155 glsl_get_base_type(glsl_without_array(var->type));
156
157 if (mode == nir_var_shader_in) {
158 switch (var->data.interpolation) {
159 case INTERP_MODE_NONE:
160 if (glsl_base_type_is_integer(base_type))
161 break;
162
163 /* fall-through */
164 case INTERP_MODE_SMOOTH:
165 if (var->data.sample)
166 info->uses_persp_sample = true;
167 else if (var->data.centroid)
168 info->uses_persp_centroid = true;
169 else
170 info->uses_persp_center = true;
171 break;
172
173 case INTERP_MODE_NOPERSPECTIVE:
174 if (var->data.sample)
175 info->uses_linear_sample = true;
176 else if (var->data.centroid)
177 info->uses_linear_centroid = true;
178 else
179 info->uses_linear_center = true;
180 break;
181 }
182 }
183 break;
184 }
185 case nir_intrinsic_interp_var_at_centroid:
186 case nir_intrinsic_interp_var_at_sample:
187 case nir_intrinsic_interp_var_at_offset: {
188 enum glsl_interp_mode interp =
189 intr->variables[0]->var->data.interpolation;
190 switch (interp) {
191 case INTERP_MODE_SMOOTH:
192 case INTERP_MODE_NONE:
193 if (intr->intrinsic == nir_intrinsic_interp_var_at_centroid)
194 info->uses_persp_opcode_interp_centroid = true;
195 else if (intr->intrinsic == nir_intrinsic_interp_var_at_sample)
196 info->uses_persp_opcode_interp_sample = true;
197 else
198 info->uses_persp_opcode_interp_offset = true;
199 break;
200 case INTERP_MODE_NOPERSPECTIVE:
201 if (intr->intrinsic == nir_intrinsic_interp_var_at_centroid)
202 info->uses_linear_opcode_interp_centroid = true;
203 else if (intr->intrinsic == nir_intrinsic_interp_var_at_sample)
204 info->uses_linear_opcode_interp_sample = true;
205 else
206 info->uses_linear_opcode_interp_offset = true;
207 break;
208 case INTERP_MODE_FLAT:
209 break;
210 default:
211 unreachable("Unsupported interpoation type");
212 }
213 break;
214 }
215 default:
216 break;
217 }
218 }
219 }
220
221 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
222 const struct tgsi_shader_info *info,
223 struct tgsi_tessctrl_info *out)
224 {
225 memset(out, 0, sizeof(*out));
226
227 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
228 return;
229
230 /* Initial value = true. Here the pass will accumulate results from
231 * multiple segments surrounded by barriers. If tess factors aren't
232 * written at all, it's a shader bug and we don't care if this will be
233 * true.
234 */
235 out->tessfactors_are_def_in_all_invocs = true;
236
237 /* TODO: Implement scanning of tess factors, see tgsi backend. */
238 }
239
240 void si_nir_scan_shader(const struct nir_shader *nir,
241 struct tgsi_shader_info *info)
242 {
243 nir_function *func;
244 unsigned i;
245
246 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
247 info->num_tokens = 2; /* indicate that the shader is non-empty */
248 info->num_instructions = 2;
249
250 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
251 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
252 nir->info.tess.tcs_vertices_out;
253 }
254
255 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
256 if (nir->info.tess.primitive_mode == GL_ISOLINES)
257 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
258 else
259 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
260
261 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
262 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
263 PIPE_TESS_SPACING_FRACTIONAL_ODD);
264 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
265 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
266
267 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
268 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
269 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
270 }
271
272 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
273 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
274 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
275 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
276 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
277 }
278
279 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
280 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] = nir->info.fs.early_fragment_tests;
281 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
282
283 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
284 switch (nir->info.fs.depth_layout) {
285 case FRAG_DEPTH_LAYOUT_ANY:
286 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
287 break;
288 case FRAG_DEPTH_LAYOUT_GREATER:
289 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
290 break;
291 case FRAG_DEPTH_LAYOUT_LESS:
292 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
293 break;
294 case FRAG_DEPTH_LAYOUT_UNCHANGED:
295 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
296 break;
297 default:
298 unreachable("Unknow depth layout");
299 }
300 }
301 }
302
303 if (nir->info.stage == MESA_SHADER_COMPUTE) {
304 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
305 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
306 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
307 }
308
309 i = 0;
310 uint64_t processed_inputs = 0;
311 unsigned num_inputs = 0;
312 nir_foreach_variable(variable, &nir->inputs) {
313 unsigned semantic_name, semantic_index;
314
315 const struct glsl_type *type = variable->type;
316 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
317 assert(glsl_type_is_array(type));
318 type = glsl_get_array_element(type);
319 }
320
321 unsigned attrib_count = glsl_count_attribute_slots(type,
322 nir->info.stage == MESA_SHADER_VERTEX);
323
324 i = variable->data.driver_location;
325
326 /* Vertex shader inputs don't have semantics. The state
327 * tracker has already mapped them to attributes via
328 * variable->data.driver_location.
329 */
330 if (nir->info.stage == MESA_SHADER_VERTEX) {
331 /* TODO: gather the actual input useage and remove this. */
332 info->input_usage_mask[i] = TGSI_WRITEMASK_XYZW;
333
334 if (glsl_type_is_dual_slot(variable->type)) {
335 num_inputs += 2;
336
337 /* TODO: gather the actual input useage and remove this. */
338 info->input_usage_mask[i+1] = TGSI_WRITEMASK_XYZW;
339 } else
340 num_inputs++;
341 continue;
342 }
343
344 /* Fragment shader position is a system value. */
345 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
346 variable->data.location == VARYING_SLOT_POS) {
347 if (variable->data.pixel_center_integer)
348 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
349 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
350
351 num_inputs++;
352 continue;
353 }
354
355 for (unsigned j = 0; j < attrib_count; j++, i++) {
356
357 if (processed_inputs & ((uint64_t)1 << i))
358 continue;
359
360 processed_inputs |= ((uint64_t)1 << i);
361 num_inputs++;
362
363 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
364 &semantic_name, &semantic_index);
365
366 info->input_semantic_name[i] = semantic_name;
367 info->input_semantic_index[i] = semantic_index;
368
369 if (semantic_name == TGSI_SEMANTIC_PRIMID)
370 info->uses_primid = true;
371
372 if (variable->data.sample)
373 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
374 else if (variable->data.centroid)
375 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
376 else
377 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
378
379 enum glsl_base_type base_type =
380 glsl_get_base_type(glsl_without_array(variable->type));
381
382 switch (variable->data.interpolation) {
383 case INTERP_MODE_NONE:
384 if (glsl_base_type_is_integer(base_type)) {
385 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
386 break;
387 }
388
389 if (semantic_name == TGSI_SEMANTIC_COLOR) {
390 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
391 break;
392 }
393 /* fall-through */
394
395 case INTERP_MODE_SMOOTH:
396 assert(!glsl_base_type_is_integer(base_type));
397
398 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
399 break;
400
401 case INTERP_MODE_NOPERSPECTIVE:
402 assert(!glsl_base_type_is_integer(base_type));
403
404 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
405 break;
406
407 case INTERP_MODE_FLAT:
408 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
409 break;
410 }
411
412 /* TODO make this more precise */
413 if (variable->data.location == VARYING_SLOT_COL0)
414 info->colors_read |= 0x0f;
415 else if (variable->data.location == VARYING_SLOT_COL1)
416 info->colors_read |= 0xf0;
417 }
418 }
419
420 info->num_inputs = num_inputs;
421
422
423 i = 0;
424 uint64_t processed_outputs = 0;
425 unsigned num_outputs = 0;
426 nir_foreach_variable(variable, &nir->outputs) {
427 unsigned semantic_name, semantic_index;
428
429 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
430 tgsi_get_gl_frag_result_semantic(variable->data.location,
431 &semantic_name, &semantic_index);
432
433 /* Adjust for dual source blending */
434 if (variable->data.index > 0) {
435 semantic_index++;
436 }
437 } else {
438 tgsi_get_gl_varying_semantic(variable->data.location, true,
439 &semantic_name, &semantic_index);
440 }
441
442 i = variable->data.driver_location;
443 if (processed_outputs & ((uint64_t)1 << i))
444 continue;
445
446 processed_outputs |= ((uint64_t)1 << i);
447 num_outputs++;
448
449 info->output_semantic_name[i] = semantic_name;
450 info->output_semantic_index[i] = semantic_index;
451 info->output_usagemask[i] = TGSI_WRITEMASK_XYZW;
452
453 unsigned num_components = 4;
454 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
455 if (vector_elements)
456 num_components = vector_elements;
457
458 unsigned gs_out_streams;
459 if (variable->data.stream & (1u << 31)) {
460 gs_out_streams = variable->data.stream & ~(1u << 31);
461 } else {
462 assert(variable->data.stream < 4);
463 gs_out_streams = 0;
464 for (unsigned j = 0; j < num_components; ++j)
465 gs_out_streams |= variable->data.stream << (2 * (variable->data.location_frac + j));
466 }
467
468 unsigned streamx = gs_out_streams & 3;
469 unsigned streamy = (gs_out_streams >> 2) & 3;
470 unsigned streamz = (gs_out_streams >> 4) & 3;
471 unsigned streamw = (gs_out_streams >> 6) & 3;
472
473 if (info->output_usagemask[i] & TGSI_WRITEMASK_X) {
474 info->output_streams[i] |= streamx;
475 info->num_stream_output_components[streamx]++;
476 }
477 if (info->output_usagemask[i] & TGSI_WRITEMASK_Y) {
478 info->output_streams[i] |= streamy << 2;
479 info->num_stream_output_components[streamy]++;
480 }
481 if (info->output_usagemask[i] & TGSI_WRITEMASK_Z) {
482 info->output_streams[i] |= streamz << 4;
483 info->num_stream_output_components[streamz]++;
484 }
485 if (info->output_usagemask[i] & TGSI_WRITEMASK_W) {
486 info->output_streams[i] |= streamw << 6;
487 info->num_stream_output_components[streamw]++;
488 }
489
490 switch (semantic_name) {
491 case TGSI_SEMANTIC_PRIMID:
492 info->writes_primid = true;
493 break;
494 case TGSI_SEMANTIC_VIEWPORT_INDEX:
495 info->writes_viewport_index = true;
496 break;
497 case TGSI_SEMANTIC_LAYER:
498 info->writes_layer = true;
499 break;
500 case TGSI_SEMANTIC_PSIZE:
501 info->writes_psize = true;
502 break;
503 case TGSI_SEMANTIC_CLIPVERTEX:
504 info->writes_clipvertex = true;
505 break;
506 case TGSI_SEMANTIC_COLOR:
507 info->colors_written |= 1 << semantic_index;
508 break;
509 case TGSI_SEMANTIC_STENCIL:
510 info->writes_stencil = true;
511 break;
512 case TGSI_SEMANTIC_SAMPLEMASK:
513 info->writes_samplemask = true;
514 break;
515 case TGSI_SEMANTIC_EDGEFLAG:
516 info->writes_edgeflag = true;
517 break;
518 case TGSI_SEMANTIC_POSITION:
519 if (info->processor == PIPE_SHADER_FRAGMENT)
520 info->writes_z = true;
521 else
522 info->writes_position = true;
523 break;
524 }
525
526 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
527 switch (semantic_name) {
528 case TGSI_SEMANTIC_PATCH:
529 info->reads_perpatch_outputs = true;
530 break;
531 case TGSI_SEMANTIC_TESSINNER:
532 case TGSI_SEMANTIC_TESSOUTER:
533 info->reads_tessfactor_outputs = true;
534 break;
535 default:
536 info->reads_pervertex_outputs = true;
537 }
538 }
539
540 unsigned loc = variable->data.location;
541 if (loc == FRAG_RESULT_COLOR &&
542 nir->info.outputs_written & (1ull << loc)) {
543 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
544 }
545 }
546
547 info->num_outputs = num_outputs;
548
549 nir_foreach_variable(variable, &nir->uniforms) {
550 const struct glsl_type *type = variable->type;
551 enum glsl_base_type base_type =
552 glsl_get_base_type(glsl_without_array(type));
553 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
554
555 /* We rely on the fact that nir_lower_samplers_as_deref has
556 * eliminated struct dereferences.
557 */
558 if (base_type == GLSL_TYPE_SAMPLER)
559 info->samplers_declared |=
560 u_bit_consecutive(variable->data.binding, aoa_size);
561 else if (base_type == GLSL_TYPE_IMAGE)
562 info->images_declared |=
563 u_bit_consecutive(variable->data.binding, aoa_size);
564 }
565
566 info->num_written_clipdistance = nir->info.clip_distance_array_size;
567 info->num_written_culldistance = nir->info.cull_distance_array_size;
568 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
569 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
570
571 if (info->processor == PIPE_SHADER_FRAGMENT)
572 info->uses_kill = nir->info.fs.uses_discard;
573
574 /* TODO make this more accurate */
575 info->const_buffers_declared = u_bit_consecutive(0, SI_NUM_CONST_BUFFERS);
576 info->shader_buffers_declared = u_bit_consecutive(0, SI_NUM_SHADER_BUFFERS);
577
578 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
579 nir_foreach_block(block, func->impl) {
580 nir_foreach_instr(instr, block)
581 scan_instruction(info, instr);
582 }
583 }
584
585 /**
586 * Perform "lowering" operations on the NIR that are run once when the shader
587 * selector is created.
588 */
589 void
590 si_lower_nir(struct si_shader_selector* sel)
591 {
592 /* Adjust the driver location of inputs and outputs. The state tracker
593 * interprets them as slots, while the ac/nir backend interprets them
594 * as individual components.
595 */
596 nir_foreach_variable(variable, &sel->nir->inputs)
597 variable->data.driver_location *= 4;
598
599 nir_foreach_variable(variable, &sel->nir->outputs) {
600 variable->data.driver_location *= 4;
601
602 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
603 if (variable->data.location == FRAG_RESULT_DEPTH)
604 variable->data.driver_location += 2;
605 else if (variable->data.location == FRAG_RESULT_STENCIL)
606 variable->data.driver_location += 1;
607 }
608 }
609
610 /* Perform lowerings (and optimizations) of code.
611 *
612 * Performance considerations aside, we must:
613 * - lower certain ALU operations
614 * - ensure constant offsets for texture instructions are folded
615 * and copy-propagated
616 */
617 NIR_PASS_V(sel->nir, nir_lower_io, nir_var_uniform, type_size,
618 (nir_lower_io_options)0);
619 NIR_PASS_V(sel->nir, nir_lower_uniforms_to_ubo);
620
621 NIR_PASS_V(sel->nir, nir_lower_returns);
622 NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
623 NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
624 NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
625
626 static const struct nir_lower_tex_options lower_tex_options = {
627 .lower_txp = ~0u,
628 };
629 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
630
631 const nir_lower_subgroups_options subgroups_options = {
632 .subgroup_size = 64,
633 .ballot_bit_size = 32,
634 .lower_to_scalar = true,
635 .lower_subgroup_masks = true,
636 .lower_vote_trivial = false,
637 };
638 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
639
640 bool progress;
641 do {
642 progress = false;
643
644 /* (Constant) copy propagation is needed for txf with offsets. */
645 NIR_PASS(progress, sel->nir, nir_copy_prop);
646 NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
647 NIR_PASS(progress, sel->nir, nir_opt_dce);
648 if (nir_opt_trivial_continues(sel->nir)) {
649 progress = true;
650 NIR_PASS(progress, sel->nir, nir_copy_prop);
651 NIR_PASS(progress, sel->nir, nir_opt_dce);
652 }
653 NIR_PASS(progress, sel->nir, nir_opt_if);
654 NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
655 NIR_PASS(progress, sel->nir, nir_opt_cse);
656 NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8);
657
658 /* Needed for algebraic lowering */
659 NIR_PASS(progress, sel->nir, nir_opt_algebraic);
660 NIR_PASS(progress, sel->nir, nir_opt_constant_folding);
661
662 NIR_PASS(progress, sel->nir, nir_opt_undef);
663 NIR_PASS(progress, sel->nir, nir_opt_conditional_discard);
664 if (sel->nir->options->max_unroll_iterations) {
665 NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
666 }
667 } while (progress);
668 }
669
670 static void declare_nir_input_vs(struct si_shader_context *ctx,
671 struct nir_variable *variable,
672 unsigned input_index,
673 LLVMValueRef out[4])
674 {
675 si_llvm_load_input_vs(ctx, input_index, out);
676 }
677
678 static void declare_nir_input_fs(struct si_shader_context *ctx,
679 struct nir_variable *variable,
680 unsigned input_index,
681 LLVMValueRef out[4])
682 {
683 unsigned slot = variable->data.location;
684 if (slot == VARYING_SLOT_POS) {
685 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
686 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
687 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
688 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
689 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
690 return;
691 }
692
693 si_llvm_load_input_fs(ctx, input_index, out);
694 }
695
696 LLVMValueRef si_nir_load_input_gs(struct ac_shader_abi *abi,
697 unsigned location,
698 unsigned driver_location,
699 unsigned component,
700 unsigned num_components,
701 unsigned vertex_index,
702 unsigned const_index,
703 LLVMTypeRef type)
704 {
705 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
706
707 LLVMValueRef value[4];
708 for (unsigned i = component; i < num_components + component; i++) {
709 value[i] = si_llvm_load_input_gs(&ctx->abi, driver_location / 4,
710 vertex_index, type, i);
711 }
712
713 return ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
714 }
715
716 LLVMValueRef
717 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
718 enum glsl_interp_mode interp, unsigned location)
719 {
720 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
721 int interp_param_idx = -1;
722
723 switch (interp) {
724 case INTERP_MODE_FLAT:
725 return NULL;
726 case INTERP_MODE_SMOOTH:
727 case INTERP_MODE_NONE:
728 if (location == INTERP_CENTER)
729 interp_param_idx = SI_PARAM_PERSP_CENTER;
730 else if (location == INTERP_CENTROID)
731 interp_param_idx = SI_PARAM_PERSP_CENTROID;
732 else if (location == INTERP_SAMPLE)
733 interp_param_idx = SI_PARAM_PERSP_SAMPLE;
734 break;
735 case INTERP_MODE_NOPERSPECTIVE:
736 if (location == INTERP_CENTER)
737 interp_param_idx = SI_PARAM_LINEAR_CENTER;
738 else if (location == INTERP_CENTROID)
739 interp_param_idx = SI_PARAM_LINEAR_CENTROID;
740 else if (location == INTERP_SAMPLE)
741 interp_param_idx = SI_PARAM_LINEAR_SAMPLE;
742 break;
743 default:
744 assert(!"Unhandled interpolation mode.");
745 return NULL;
746 }
747
748 return interp_param_idx != -1 ?
749 LLVMGetParam(ctx->main_fn, interp_param_idx) : NULL;
750 }
751
752 static LLVMValueRef
753 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
754 unsigned descriptor_set, unsigned base_index,
755 unsigned constant_index, LLVMValueRef dynamic_index,
756 enum ac_descriptor_type desc_type, bool image,
757 bool write)
758 {
759 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
760 LLVMBuilderRef builder = ctx->ac.builder;
761 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
762 LLVMValueRef index = dynamic_index;
763
764 assert(!descriptor_set);
765
766 if (!index)
767 index = ctx->ac.i32_0;
768
769 index = LLVMBuildAdd(builder, index,
770 LLVMConstInt(ctx->ac.i32, base_index + constant_index, false),
771 "");
772
773 if (image) {
774 assert(desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
775 assert(base_index + constant_index < ctx->num_images);
776
777 if (dynamic_index)
778 index = si_llvm_bound_index(ctx, index, ctx->num_images);
779
780 index = LLVMBuildSub(ctx->gallivm.builder,
781 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
782 index, "");
783
784 /* TODO: be smarter about when we use dcc_off */
785 return si_load_image_desc(ctx, list, index, desc_type, write);
786 }
787
788 assert(base_index + constant_index < ctx->num_samplers);
789
790 if (dynamic_index)
791 index = si_llvm_bound_index(ctx, index, ctx->num_samplers);
792
793 index = LLVMBuildAdd(ctx->gallivm.builder, index,
794 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
795
796 return si_load_sampler_desc(ctx, list, index, desc_type);
797 }
798
799 static void bitcast_inputs(struct si_shader_context *ctx,
800 LLVMValueRef data[4],
801 unsigned input_idx)
802 {
803 for (unsigned chan = 0; chan < 4; chan++) {
804 ctx->inputs[input_idx + chan] =
805 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
806 }
807 }
808
809 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
810 {
811 struct tgsi_shader_info *info = &ctx->shader->selector->info;
812
813 if (nir->info.stage == MESA_SHADER_VERTEX ||
814 nir->info.stage == MESA_SHADER_FRAGMENT) {
815 uint64_t processed_inputs = 0;
816 nir_foreach_variable(variable, &nir->inputs) {
817 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
818 nir->info.stage == MESA_SHADER_VERTEX);
819 unsigned input_idx = variable->data.driver_location;
820
821 LLVMValueRef data[4];
822 unsigned loc = variable->data.location;
823
824 for (unsigned i = 0; i < attrib_count; i++) {
825 /* Packed components share the same location so skip
826 * them if we have already processed the location.
827 */
828 if (processed_inputs & ((uint64_t)1 << loc)) {
829 input_idx += 4;
830 continue;
831 }
832
833 if (nir->info.stage == MESA_SHADER_VERTEX) {
834 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
835 bitcast_inputs(ctx, data, input_idx);
836 if (glsl_type_is_dual_slot(variable->type)) {
837 input_idx += 4;
838 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
839 bitcast_inputs(ctx, data, input_idx);
840 }
841 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
842 declare_nir_input_fs(ctx, variable, input_idx / 4, data);
843 bitcast_inputs(ctx, data, input_idx);
844 }
845
846 processed_inputs |= ((uint64_t)1 << loc);
847 loc++;
848 input_idx += 4;
849 }
850 }
851 }
852
853 ctx->abi.inputs = &ctx->inputs[0];
854 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
855 ctx->abi.clamp_shadow_reference = true;
856
857 ctx->num_samplers = util_last_bit(info->samplers_declared);
858 ctx->num_images = util_last_bit(info->images_declared);
859
860 if (ctx->shader->selector->local_size) {
861 assert(nir->info.stage == MESA_SHADER_COMPUTE);
862 si_declare_compute_memory(ctx);
863 }
864 ac_nir_translate(&ctx->ac, &ctx->abi, nir, NULL);
865
866 return true;
867 }