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radeonsi/nir: stop calling nir_lower_returns()
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 #include "tgsi/tgsi_from_mesa.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34
35 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
36 {
37 for (unsigned i = 0; i < instr->num_srcs; i++) {
38 switch (instr->src[i].src_type) {
39 case nir_tex_src_texture_deref:
40 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
41 default:
42 break;
43 }
44 }
45
46 return NULL;
47 }
48
49 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
50 {
51 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
52 }
53
54 static void gather_intrinsic_load_deref_info(const nir_shader *nir,
55 const nir_intrinsic_instr *instr,
56 nir_variable *var,
57 struct tgsi_shader_info *info)
58 {
59 assert(var && var->data.mode == nir_var_shader_in);
60
61 switch (nir->info.stage) {
62 case MESA_SHADER_VERTEX: {
63 unsigned i = var->data.driver_location;
64 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
65
66 for (unsigned j = 0; j < attrib_count; j++, i++) {
67 if (glsl_type_is_64bit(glsl_without_array(var->type))) {
68 /* TODO: set usage mask more accurately for doubles */
69 info->input_usage_mask[i] = TGSI_WRITEMASK_XYZW;
70 } else {
71 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
72 info->input_usage_mask[i] |= mask << var->data.location_frac;
73 }
74 }
75 break;
76 }
77 default: {
78 unsigned semantic_name, semantic_index;
79 tgsi_get_gl_varying_semantic(var->data.location, true,
80 &semantic_name, &semantic_index);
81
82 if (semantic_name == TGSI_SEMANTIC_COLOR) {
83 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
84 info->colors_read |= mask << (semantic_index * 4);
85 }
86 break;
87 }
88 }
89 }
90
91 static void scan_instruction(const struct nir_shader *nir,
92 struct tgsi_shader_info *info,
93 nir_instr *instr)
94 {
95 if (instr->type == nir_instr_type_alu) {
96 nir_alu_instr *alu = nir_instr_as_alu(instr);
97
98 switch (alu->op) {
99 case nir_op_fddx:
100 case nir_op_fddy:
101 case nir_op_fddx_fine:
102 case nir_op_fddy_fine:
103 case nir_op_fddx_coarse:
104 case nir_op_fddy_coarse:
105 info->uses_derivatives = true;
106 break;
107 default:
108 break;
109 }
110 } else if (instr->type == nir_instr_type_tex) {
111 nir_tex_instr *tex = nir_instr_as_tex(instr);
112 nir_variable *texture = tex_get_texture_var(tex);
113
114 if (!texture) {
115 info->samplers_declared |=
116 u_bit_consecutive(tex->sampler_index, 1);
117 } else {
118 if (texture->data.bindless)
119 info->uses_bindless_samplers = true;
120 }
121
122 switch (tex->op) {
123 case nir_texop_tex:
124 case nir_texop_txb:
125 case nir_texop_lod:
126 info->uses_derivatives = true;
127 break;
128 default:
129 break;
130 }
131 } else if (instr->type == nir_instr_type_intrinsic) {
132 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
133
134 switch (intr->intrinsic) {
135 case nir_intrinsic_load_front_face:
136 info->uses_frontface = 1;
137 break;
138 case nir_intrinsic_load_instance_id:
139 info->uses_instanceid = 1;
140 break;
141 case nir_intrinsic_load_invocation_id:
142 info->uses_invocationid = true;
143 break;
144 case nir_intrinsic_load_num_work_groups:
145 info->uses_grid_size = true;
146 break;
147 case nir_intrinsic_load_local_group_size:
148 /* The block size is translated to IMM with a fixed block size. */
149 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
150 info->uses_block_size = true;
151 break;
152 case nir_intrinsic_load_local_invocation_id:
153 case nir_intrinsic_load_work_group_id: {
154 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
155 while (mask) {
156 unsigned i = u_bit_scan(&mask);
157
158 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
159 info->uses_block_id[i] = true;
160 else
161 info->uses_thread_id[i] = true;
162 }
163 break;
164 }
165 case nir_intrinsic_load_vertex_id:
166 info->uses_vertexid = 1;
167 break;
168 case nir_intrinsic_load_vertex_id_zero_base:
169 info->uses_vertexid_nobase = 1;
170 break;
171 case nir_intrinsic_load_base_vertex:
172 info->uses_basevertex = 1;
173 break;
174 case nir_intrinsic_load_primitive_id:
175 info->uses_primid = 1;
176 break;
177 case nir_intrinsic_load_sample_mask_in:
178 info->reads_samplemask = true;
179 break;
180 case nir_intrinsic_load_tess_level_inner:
181 case nir_intrinsic_load_tess_level_outer:
182 info->reads_tess_factors = true;
183 break;
184 case nir_intrinsic_image_deref_load: {
185 nir_variable *var = intrinsic_get_var(intr);
186 if (var->data.bindless) {
187 info->uses_bindless_images = true;
188
189 if (glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_BUF)
190 info->uses_bindless_buffer_load = true;
191 else
192 info->uses_bindless_image_load = true;
193 }
194 break;
195 }
196 case nir_intrinsic_image_deref_size:
197 case nir_intrinsic_image_deref_samples: {
198 nir_variable *var = intrinsic_get_var(intr);
199 if (var->data.bindless)
200 info->uses_bindless_images = true;
201 break;
202 }
203 case nir_intrinsic_image_deref_store: {
204 const nir_deref_instr *image_deref = nir_instr_as_deref(intr->src[0].ssa->parent_instr);
205 nir_variable *var = intrinsic_get_var(intr);
206 if (var->data.bindless) {
207 info->uses_bindless_images = true;
208
209 if (glsl_get_sampler_dim(image_deref->type) == GLSL_SAMPLER_DIM_BUF)
210 info->uses_bindless_buffer_store = true;
211 else
212 info->uses_bindless_image_store = true;
213 }
214 info->writes_memory = true;
215 break;
216 }
217 case nir_intrinsic_image_deref_atomic_add:
218 case nir_intrinsic_image_deref_atomic_min:
219 case nir_intrinsic_image_deref_atomic_max:
220 case nir_intrinsic_image_deref_atomic_and:
221 case nir_intrinsic_image_deref_atomic_or:
222 case nir_intrinsic_image_deref_atomic_xor:
223 case nir_intrinsic_image_deref_atomic_exchange:
224 case nir_intrinsic_image_deref_atomic_comp_swap: {
225 nir_variable *var = intrinsic_get_var(intr);
226 if (var->data.bindless) {
227 info->uses_bindless_images = true;
228
229 if (glsl_get_sampler_dim(var->type) == GLSL_SAMPLER_DIM_BUF)
230 info->uses_bindless_buffer_atomic = true;
231 else
232 info->uses_bindless_image_atomic = true;
233 }
234 info->writes_memory = true;
235 break;
236 }
237 case nir_intrinsic_store_ssbo:
238 case nir_intrinsic_ssbo_atomic_add:
239 case nir_intrinsic_ssbo_atomic_imin:
240 case nir_intrinsic_ssbo_atomic_umin:
241 case nir_intrinsic_ssbo_atomic_imax:
242 case nir_intrinsic_ssbo_atomic_umax:
243 case nir_intrinsic_ssbo_atomic_and:
244 case nir_intrinsic_ssbo_atomic_or:
245 case nir_intrinsic_ssbo_atomic_xor:
246 case nir_intrinsic_ssbo_atomic_exchange:
247 case nir_intrinsic_ssbo_atomic_comp_swap:
248 info->writes_memory = true;
249 break;
250 case nir_intrinsic_load_deref: {
251 nir_variable *var = intrinsic_get_var(intr);
252 nir_variable_mode mode = var->data.mode;
253 enum glsl_base_type base_type =
254 glsl_get_base_type(glsl_without_array(var->type));
255
256 if (mode == nir_var_shader_in) {
257 gather_intrinsic_load_deref_info(nir, intr, var, info);
258
259 switch (var->data.interpolation) {
260 case INTERP_MODE_NONE:
261 if (glsl_base_type_is_integer(base_type))
262 break;
263
264 /* fall-through */
265 case INTERP_MODE_SMOOTH:
266 if (var->data.sample)
267 info->uses_persp_sample = true;
268 else if (var->data.centroid)
269 info->uses_persp_centroid = true;
270 else
271 info->uses_persp_center = true;
272 break;
273
274 case INTERP_MODE_NOPERSPECTIVE:
275 if (var->data.sample)
276 info->uses_linear_sample = true;
277 else if (var->data.centroid)
278 info->uses_linear_centroid = true;
279 else
280 info->uses_linear_center = true;
281 break;
282 }
283 }
284 break;
285 }
286 case nir_intrinsic_interp_deref_at_centroid:
287 case nir_intrinsic_interp_deref_at_sample:
288 case nir_intrinsic_interp_deref_at_offset: {
289 enum glsl_interp_mode interp = intrinsic_get_var(intr)->data.interpolation;
290 switch (interp) {
291 case INTERP_MODE_SMOOTH:
292 case INTERP_MODE_NONE:
293 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
294 info->uses_persp_opcode_interp_centroid = true;
295 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
296 info->uses_persp_opcode_interp_sample = true;
297 else
298 info->uses_persp_opcode_interp_offset = true;
299 break;
300 case INTERP_MODE_NOPERSPECTIVE:
301 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
302 info->uses_linear_opcode_interp_centroid = true;
303 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
304 info->uses_linear_opcode_interp_sample = true;
305 else
306 info->uses_linear_opcode_interp_offset = true;
307 break;
308 case INTERP_MODE_FLAT:
309 break;
310 default:
311 unreachable("Unsupported interpoation type");
312 }
313 break;
314 }
315 default:
316 break;
317 }
318 }
319 }
320
321 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
322 struct tgsi_tessctrl_info *out)
323 {
324 memset(out, 0, sizeof(*out));
325
326 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
327 return;
328
329 out->tessfactors_are_def_in_all_invocs =
330 ac_are_tessfactors_def_in_all_invocs(nir);
331 }
332
333 void si_nir_scan_shader(const struct nir_shader *nir,
334 struct tgsi_shader_info *info)
335 {
336 nir_function *func;
337 unsigned i;
338
339 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
340 info->num_tokens = 2; /* indicate that the shader is non-empty */
341 info->num_instructions = 2;
342
343 info->properties[TGSI_PROPERTY_NEXT_SHADER] =
344 pipe_shader_type_from_mesa(nir->info.next_stage);
345
346 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
347 nir->info.vs.window_space_position;
348
349 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
350 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
351 nir->info.tess.tcs_vertices_out;
352 }
353
354 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
355 if (nir->info.tess.primitive_mode == GL_ISOLINES)
356 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
357 else
358 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
359
360 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
361 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
362 PIPE_TESS_SPACING_FRACTIONAL_ODD);
363 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
364 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
365
366 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
367 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
368 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
369 }
370
371 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
372 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
373 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
374 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
375 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
376 }
377
378 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
379 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
380 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
381 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
382
383 if (nir->info.fs.pixel_center_integer) {
384 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
385 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
386 }
387
388 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
389 switch (nir->info.fs.depth_layout) {
390 case FRAG_DEPTH_LAYOUT_ANY:
391 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
392 break;
393 case FRAG_DEPTH_LAYOUT_GREATER:
394 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
395 break;
396 case FRAG_DEPTH_LAYOUT_LESS:
397 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
398 break;
399 case FRAG_DEPTH_LAYOUT_UNCHANGED:
400 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
401 break;
402 default:
403 unreachable("Unknow depth layout");
404 }
405 }
406 }
407
408 if (gl_shader_stage_is_compute(nir->info.stage)) {
409 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
410 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
411 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
412 }
413
414 i = 0;
415 uint64_t processed_inputs = 0;
416 unsigned num_inputs = 0;
417 nir_foreach_variable(variable, &nir->inputs) {
418 unsigned semantic_name, semantic_index;
419
420 const struct glsl_type *type = variable->type;
421 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
422 assert(glsl_type_is_array(type));
423 type = glsl_get_array_element(type);
424 }
425
426 unsigned attrib_count = glsl_count_attribute_slots(type,
427 nir->info.stage == MESA_SHADER_VERTEX);
428
429 i = variable->data.driver_location;
430
431 /* Vertex shader inputs don't have semantics. The state
432 * tracker has already mapped them to attributes via
433 * variable->data.driver_location.
434 */
435 if (nir->info.stage == MESA_SHADER_VERTEX) {
436 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)))
437 num_inputs++;
438
439 num_inputs++;
440 continue;
441 }
442
443 /* Fragment shader position is a system value. */
444 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
445 variable->data.location == VARYING_SLOT_POS) {
446 if (nir->info.fs.pixel_center_integer)
447 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
448 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
449
450 num_inputs++;
451 continue;
452 }
453
454 for (unsigned j = 0; j < attrib_count; j++, i++) {
455
456 if (processed_inputs & ((uint64_t)1 << i))
457 continue;
458
459 processed_inputs |= ((uint64_t)1 << i);
460 num_inputs++;
461
462 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
463 &semantic_name, &semantic_index);
464
465 info->input_semantic_name[i] = semantic_name;
466 info->input_semantic_index[i] = semantic_index;
467
468 if (semantic_name == TGSI_SEMANTIC_PRIMID)
469 info->uses_primid = true;
470
471 if (variable->data.sample)
472 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
473 else if (variable->data.centroid)
474 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
475 else
476 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
477
478 enum glsl_base_type base_type =
479 glsl_get_base_type(glsl_without_array(variable->type));
480
481 switch (variable->data.interpolation) {
482 case INTERP_MODE_NONE:
483 if (glsl_base_type_is_integer(base_type)) {
484 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
485 break;
486 }
487
488 if (semantic_name == TGSI_SEMANTIC_COLOR) {
489 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
490 break;
491 }
492 /* fall-through */
493
494 case INTERP_MODE_SMOOTH:
495 assert(!glsl_base_type_is_integer(base_type));
496
497 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
498 break;
499
500 case INTERP_MODE_NOPERSPECTIVE:
501 assert(!glsl_base_type_is_integer(base_type));
502
503 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
504 break;
505
506 case INTERP_MODE_FLAT:
507 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
508 break;
509 }
510 }
511 }
512
513 info->num_inputs = num_inputs;
514
515
516 i = 0;
517 uint64_t processed_outputs = 0;
518 unsigned num_outputs = 0;
519 nir_foreach_variable(variable, &nir->outputs) {
520 unsigned semantic_name, semantic_index;
521
522 i = variable->data.driver_location;
523
524 const struct glsl_type *type = variable->type;
525 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
526 assert(glsl_type_is_array(type));
527 type = glsl_get_array_element(type);
528 }
529
530 unsigned attrib_count = glsl_count_attribute_slots(type, false);
531 for (unsigned k = 0; k < attrib_count; k++, i++) {
532
533 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
534 tgsi_get_gl_frag_result_semantic(variable->data.location + k,
535 &semantic_name, &semantic_index);
536
537 /* Adjust for dual source blending */
538 if (variable->data.index > 0) {
539 semantic_index++;
540 }
541 } else {
542 tgsi_get_gl_varying_semantic(variable->data.location + k, true,
543 &semantic_name, &semantic_index);
544 }
545
546 unsigned num_components = 4;
547 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
548 if (vector_elements)
549 num_components = vector_elements;
550
551 unsigned component = variable->data.location_frac;
552 if (glsl_type_is_64bit(glsl_without_array(variable->type))) {
553 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)) && k % 2) {
554 num_components = (num_components * 2) - 4;
555 component = 0;
556 } else {
557 num_components = MIN2(num_components * 2, 4);
558 }
559 }
560
561 ubyte usagemask = 0;
562 for (unsigned j = component; j < num_components + component; j++) {
563 switch (j) {
564 case 0:
565 usagemask |= TGSI_WRITEMASK_X;
566 break;
567 case 1:
568 usagemask |= TGSI_WRITEMASK_Y;
569 break;
570 case 2:
571 usagemask |= TGSI_WRITEMASK_Z;
572 break;
573 case 3:
574 usagemask |= TGSI_WRITEMASK_W;
575 break;
576 default:
577 unreachable("error calculating component index");
578 }
579 }
580
581 unsigned gs_out_streams;
582 if (variable->data.stream & (1u << 31)) {
583 gs_out_streams = variable->data.stream & ~(1u << 31);
584 } else {
585 assert(variable->data.stream < 4);
586 gs_out_streams = 0;
587 for (unsigned j = 0; j < num_components; ++j)
588 gs_out_streams |= variable->data.stream << (2 * (component + j));
589 }
590
591 unsigned streamx = gs_out_streams & 3;
592 unsigned streamy = (gs_out_streams >> 2) & 3;
593 unsigned streamz = (gs_out_streams >> 4) & 3;
594 unsigned streamw = (gs_out_streams >> 6) & 3;
595
596 if (usagemask & TGSI_WRITEMASK_X) {
597 info->output_usagemask[i] |= TGSI_WRITEMASK_X;
598 info->output_streams[i] |= streamx;
599 info->num_stream_output_components[streamx]++;
600 }
601 if (usagemask & TGSI_WRITEMASK_Y) {
602 info->output_usagemask[i] |= TGSI_WRITEMASK_Y;
603 info->output_streams[i] |= streamy << 2;
604 info->num_stream_output_components[streamy]++;
605 }
606 if (usagemask & TGSI_WRITEMASK_Z) {
607 info->output_usagemask[i] |= TGSI_WRITEMASK_Z;
608 info->output_streams[i] |= streamz << 4;
609 info->num_stream_output_components[streamz]++;
610 }
611 if (usagemask & TGSI_WRITEMASK_W) {
612 info->output_usagemask[i] |= TGSI_WRITEMASK_W;
613 info->output_streams[i] |= streamw << 6;
614 info->num_stream_output_components[streamw]++;
615 }
616
617 /* make sure we only count this location once against
618 * the num_outputs counter.
619 */
620 if (processed_outputs & ((uint64_t)1 << i))
621 continue;
622
623 processed_outputs |= ((uint64_t)1 << i);
624 num_outputs++;
625
626 info->output_semantic_name[i] = semantic_name;
627 info->output_semantic_index[i] = semantic_index;
628
629 switch (semantic_name) {
630 case TGSI_SEMANTIC_PRIMID:
631 info->writes_primid = true;
632 break;
633 case TGSI_SEMANTIC_VIEWPORT_INDEX:
634 info->writes_viewport_index = true;
635 break;
636 case TGSI_SEMANTIC_LAYER:
637 info->writes_layer = true;
638 break;
639 case TGSI_SEMANTIC_PSIZE:
640 info->writes_psize = true;
641 break;
642 case TGSI_SEMANTIC_CLIPVERTEX:
643 info->writes_clipvertex = true;
644 break;
645 case TGSI_SEMANTIC_COLOR:
646 info->colors_written |= 1 << semantic_index;
647 break;
648 case TGSI_SEMANTIC_STENCIL:
649 info->writes_stencil = true;
650 break;
651 case TGSI_SEMANTIC_SAMPLEMASK:
652 info->writes_samplemask = true;
653 break;
654 case TGSI_SEMANTIC_EDGEFLAG:
655 info->writes_edgeflag = true;
656 break;
657 case TGSI_SEMANTIC_POSITION:
658 if (info->processor == PIPE_SHADER_FRAGMENT)
659 info->writes_z = true;
660 else
661 info->writes_position = true;
662 break;
663 }
664
665 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
666 switch (semantic_name) {
667 case TGSI_SEMANTIC_PATCH:
668 info->reads_perpatch_outputs = true;
669 break;
670 case TGSI_SEMANTIC_TESSINNER:
671 case TGSI_SEMANTIC_TESSOUTER:
672 info->reads_tessfactor_outputs = true;
673 break;
674 default:
675 info->reads_pervertex_outputs = true;
676 }
677 }
678 }
679
680 unsigned loc = variable->data.location;
681 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
682 loc == FRAG_RESULT_COLOR &&
683 nir->info.outputs_written & (1ull << loc)) {
684 assert(attrib_count == 1);
685 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
686 }
687 }
688
689 info->num_outputs = num_outputs;
690
691 struct set *ubo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
692 _mesa_key_pointer_equal);
693 struct set *ssbo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
694 _mesa_key_pointer_equal);
695
696 /* Intialise const_file_max[0] */
697 info->const_file_max[0] = -1;
698
699 /* The first 8 are reserved for atomic counters using ssbo */
700 unsigned ssbo_idx = 8;
701
702 unsigned ubo_idx = 1;
703 nir_foreach_variable(variable, &nir->uniforms) {
704 const struct glsl_type *type = variable->type;
705 enum glsl_base_type base_type =
706 glsl_get_base_type(glsl_without_array(type));
707 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
708 unsigned loc = variable->data.location;
709 int slot_count = glsl_count_attribute_slots(type, false);
710 int max_slot = MAX2(info->const_file_max[0], (int) loc) + slot_count;
711
712 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
713 * really use the mask (other than ubo_idx == 1 for regular
714 * uniforms) its really only used for getting the buffer count
715 * so we don't need to worry about the ordering.
716 */
717 if (variable->interface_type != NULL) {
718 if (variable->data.mode == nir_var_uniform ||
719 variable->data.mode == nir_var_mem_ubo ||
720 variable->data.mode == nir_var_mem_ssbo) {
721
722 struct set *buf_set = variable->data.mode == nir_var_mem_ssbo ?
723 ssbo_set : ubo_set;
724
725 unsigned block_count;
726 if (base_type != GLSL_TYPE_INTERFACE) {
727 struct set_entry *entry =
728 _mesa_set_search(buf_set, variable->interface_type);
729
730 /* Check if we have already processed
731 * a member from this ubo.
732 */
733 if (entry)
734 continue;
735
736 block_count = 1;
737 } else {
738 block_count = aoa_size;
739 }
740
741 if (variable->data.mode == nir_var_uniform ||
742 variable->data.mode == nir_var_mem_ubo) {
743 info->const_buffers_declared |= u_bit_consecutive(ubo_idx, block_count);
744 ubo_idx += block_count;
745 } else {
746 assert(variable->data.mode == nir_var_mem_ssbo);
747
748 info->shader_buffers_declared |= u_bit_consecutive(ssbo_idx, block_count);
749 ssbo_idx += block_count;
750 }
751
752 _mesa_set_add(buf_set, variable->interface_type);
753 }
754
755 continue;
756 }
757
758 /* We rely on the fact that nir_lower_samplers_as_deref has
759 * eliminated struct dereferences.
760 */
761 if (base_type == GLSL_TYPE_SAMPLER) {
762 if (variable->data.bindless) {
763 info->const_buffers_declared |= 1;
764 info->const_file_max[0] = max_slot;
765 } else {
766 info->samplers_declared |=
767 u_bit_consecutive(variable->data.binding, aoa_size);
768 }
769 } else if (base_type == GLSL_TYPE_IMAGE) {
770 if (variable->data.bindless) {
771 info->const_buffers_declared |= 1;
772 info->const_file_max[0] = max_slot;
773 } else {
774 info->images_declared |=
775 u_bit_consecutive(variable->data.binding, aoa_size);
776 }
777 } else if (base_type != GLSL_TYPE_ATOMIC_UINT) {
778 if (strncmp(variable->name, "state.", 6) == 0 ||
779 strncmp(variable->name, "gl_", 3) == 0) {
780 /* FIXME: figure out why piglit tests with builtin
781 * uniforms are failing without this.
782 */
783 info->const_buffers_declared =
784 u_bit_consecutive(0, SI_NUM_CONST_BUFFERS);
785 } else {
786 info->const_buffers_declared |= 1;
787 info->const_file_max[0] = max_slot;
788 }
789 }
790 }
791
792 _mesa_set_destroy(ubo_set, NULL);
793 _mesa_set_destroy(ssbo_set, NULL);
794
795 info->num_written_clipdistance = nir->info.clip_distance_array_size;
796 info->num_written_culldistance = nir->info.cull_distance_array_size;
797 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
798 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
799
800 if (info->processor == PIPE_SHADER_FRAGMENT)
801 info->uses_kill = nir->info.fs.uses_discard;
802
803 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
804 nir_foreach_block(block, func->impl) {
805 nir_foreach_instr(instr, block)
806 scan_instruction(nir, info, instr);
807 }
808 }
809
810 /**
811 * Perform "lowering" operations on the NIR that are run once when the shader
812 * selector is created.
813 */
814 void
815 si_lower_nir(struct si_shader_selector* sel)
816 {
817 /* Adjust the driver location of inputs and outputs. The state tracker
818 * interprets them as slots, while the ac/nir backend interprets them
819 * as individual components.
820 */
821 nir_foreach_variable(variable, &sel->nir->inputs)
822 variable->data.driver_location *= 4;
823
824 nir_foreach_variable(variable, &sel->nir->outputs) {
825 variable->data.driver_location *= 4;
826
827 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
828 if (variable->data.location == FRAG_RESULT_DEPTH)
829 variable->data.driver_location += 2;
830 else if (variable->data.location == FRAG_RESULT_STENCIL)
831 variable->data.driver_location += 1;
832 }
833 }
834
835 /* Perform lowerings (and optimizations) of code.
836 *
837 * Performance considerations aside, we must:
838 * - lower certain ALU operations
839 * - ensure constant offsets for texture instructions are folded
840 * and copy-propagated
841 */
842 NIR_PASS_V(sel->nir, nir_lower_vars_to_ssa);
843 NIR_PASS_V(sel->nir, nir_lower_alu_to_scalar);
844 NIR_PASS_V(sel->nir, nir_lower_phis_to_scalar);
845
846 static const struct nir_lower_tex_options lower_tex_options = {
847 .lower_txp = ~0u,
848 };
849 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
850
851 const nir_lower_subgroups_options subgroups_options = {
852 .subgroup_size = 64,
853 .ballot_bit_size = 64,
854 .lower_to_scalar = true,
855 .lower_subgroup_masks = true,
856 .lower_vote_trivial = false,
857 .lower_vote_eq_to_ballot = true,
858 };
859 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
860
861 ac_lower_indirect_derefs(sel->nir, sel->screen->info.chip_class);
862
863 bool progress;
864 do {
865 progress = false;
866
867 /* (Constant) copy propagation is needed for txf with offsets. */
868 NIR_PASS(progress, sel->nir, nir_copy_prop);
869 NIR_PASS(progress, sel->nir, nir_opt_remove_phis);
870 NIR_PASS(progress, sel->nir, nir_opt_dce);
871 if (nir_opt_trivial_continues(sel->nir)) {
872 progress = true;
873 NIR_PASS(progress, sel->nir, nir_copy_prop);
874 NIR_PASS(progress, sel->nir, nir_opt_dce);
875 }
876 NIR_PASS(progress, sel->nir, nir_opt_if);
877 NIR_PASS(progress, sel->nir, nir_opt_dead_cf);
878 NIR_PASS(progress, sel->nir, nir_opt_cse);
879 NIR_PASS(progress, sel->nir, nir_opt_peephole_select, 8, true, true);
880
881 /* Needed for algebraic lowering */
882 NIR_PASS(progress, sel->nir, nir_opt_algebraic);
883 NIR_PASS(progress, sel->nir, nir_opt_constant_folding);
884
885 NIR_PASS(progress, sel->nir, nir_opt_undef);
886 NIR_PASS(progress, sel->nir, nir_opt_conditional_discard);
887 if (sel->nir->options->max_unroll_iterations) {
888 NIR_PASS(progress, sel->nir, nir_opt_loop_unroll, 0);
889 }
890 } while (progress);
891
892 NIR_PASS_V(sel->nir, nir_lower_bool_to_int32);
893 }
894
895 static void declare_nir_input_vs(struct si_shader_context *ctx,
896 struct nir_variable *variable,
897 unsigned input_index,
898 LLVMValueRef out[4])
899 {
900 si_llvm_load_input_vs(ctx, input_index, out);
901 }
902
903 static void declare_nir_input_fs(struct si_shader_context *ctx,
904 struct nir_variable *variable,
905 unsigned input_index,
906 LLVMValueRef out[4])
907 {
908 unsigned slot = variable->data.location;
909 if (slot == VARYING_SLOT_POS) {
910 out[0] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_X_FLOAT);
911 out[1] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Y_FLOAT);
912 out[2] = LLVMGetParam(ctx->main_fn, SI_PARAM_POS_Z_FLOAT);
913 out[3] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1,
914 LLVMGetParam(ctx->main_fn, SI_PARAM_POS_W_FLOAT));
915 return;
916 }
917
918 si_llvm_load_input_fs(ctx, input_index, out);
919 }
920
921 LLVMValueRef
922 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
923 enum glsl_interp_mode interp, unsigned location)
924 {
925 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
926 int interp_param_idx = -1;
927
928 switch (interp) {
929 case INTERP_MODE_FLAT:
930 return NULL;
931 case INTERP_MODE_SMOOTH:
932 case INTERP_MODE_NONE:
933 if (location == INTERP_CENTER)
934 interp_param_idx = SI_PARAM_PERSP_CENTER;
935 else if (location == INTERP_CENTROID)
936 interp_param_idx = SI_PARAM_PERSP_CENTROID;
937 else if (location == INTERP_SAMPLE)
938 interp_param_idx = SI_PARAM_PERSP_SAMPLE;
939 break;
940 case INTERP_MODE_NOPERSPECTIVE:
941 if (location == INTERP_CENTER)
942 interp_param_idx = SI_PARAM_LINEAR_CENTER;
943 else if (location == INTERP_CENTROID)
944 interp_param_idx = SI_PARAM_LINEAR_CENTROID;
945 else if (location == INTERP_SAMPLE)
946 interp_param_idx = SI_PARAM_LINEAR_SAMPLE;
947 break;
948 default:
949 assert(!"Unhandled interpolation mode.");
950 return NULL;
951 }
952
953 return interp_param_idx != -1 ?
954 LLVMGetParam(ctx->main_fn, interp_param_idx) : NULL;
955 }
956
957 static LLVMValueRef
958 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
959 unsigned descriptor_set, unsigned base_index,
960 unsigned constant_index, LLVMValueRef dynamic_index,
961 enum ac_descriptor_type desc_type, bool image,
962 bool write, bool bindless)
963 {
964 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
965 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
966 LLVMBuilderRef builder = ctx->ac.builder;
967 unsigned const_index = base_index + constant_index;
968 bool dcc_off = write;
969
970 /* TODO: images_store and images_atomic are not set */
971 if (!dynamic_index && image &&
972 (info->images_store | info->images_atomic) & (1 << const_index))
973 dcc_off = true;
974
975 assert(!descriptor_set);
976 assert(!image || desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
977
978 if (bindless) {
979 LLVMValueRef list =
980 LLVMGetParam(ctx->main_fn, ctx->param_bindless_samplers_and_images);
981
982 /* dynamic_index is the bindless handle */
983 if (image) {
984 /* For simplicity, bindless image descriptors use fixed
985 * 16-dword slots for now.
986 */
987 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
988 LLVMConstInt(ctx->i32, 2, 0), "");
989
990 return si_load_image_desc(ctx, list, dynamic_index, desc_type,
991 dcc_off, true);
992 }
993
994 /* Since bindless handle arithmetic can contain an unsigned integer
995 * wraparound and si_load_sampler_desc assumes there isn't any,
996 * use GEP without "inbounds" (inside ac_build_pointer_add)
997 * to prevent incorrect code generation and hangs.
998 */
999 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1000 LLVMConstInt(ctx->i32, 2, 0), "");
1001 list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
1002 return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
1003 }
1004
1005 unsigned num_slots = image ? ctx->num_images : ctx->num_samplers;
1006 assert(const_index < num_slots);
1007
1008 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1009 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, const_index, false);
1010
1011 if (dynamic_index) {
1012 index = LLVMBuildAdd(builder, index, dynamic_index, "");
1013
1014 /* From the GL_ARB_shader_image_load_store extension spec:
1015 *
1016 * If a shader performs an image load, store, or atomic
1017 * operation using an image variable declared as an array,
1018 * and if the index used to select an individual element is
1019 * negative or greater than or equal to the size of the
1020 * array, the results of the operation are undefined but may
1021 * not lead to termination.
1022 */
1023 index = si_llvm_bound_index(ctx, index, num_slots);
1024 }
1025
1026 if (image) {
1027 index = LLVMBuildSub(ctx->ac.builder,
1028 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
1029 index, "");
1030 return si_load_image_desc(ctx, list, index, desc_type, dcc_off, false);
1031 }
1032
1033 index = LLVMBuildAdd(ctx->ac.builder, index,
1034 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1035 return si_load_sampler_desc(ctx, list, index, desc_type);
1036 }
1037
1038 static void bitcast_inputs(struct si_shader_context *ctx,
1039 LLVMValueRef data[4],
1040 unsigned input_idx)
1041 {
1042 for (unsigned chan = 0; chan < 4; chan++) {
1043 ctx->inputs[input_idx + chan] =
1044 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
1045 }
1046 }
1047
1048 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
1049 {
1050 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1051
1052 if (nir->info.stage == MESA_SHADER_VERTEX ||
1053 nir->info.stage == MESA_SHADER_FRAGMENT) {
1054 uint64_t processed_inputs = 0;
1055 nir_foreach_variable(variable, &nir->inputs) {
1056 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
1057 nir->info.stage == MESA_SHADER_VERTEX);
1058 unsigned input_idx = variable->data.driver_location;
1059
1060 LLVMValueRef data[4];
1061 unsigned loc = variable->data.location;
1062
1063 if (loc >= VARYING_SLOT_VAR0 && nir->info.stage == MESA_SHADER_FRAGMENT)
1064 ctx->abi.fs_input_attr_indices[loc - VARYING_SLOT_VAR0] = input_idx / 4;
1065
1066 for (unsigned i = 0; i < attrib_count; i++) {
1067 /* Packed components share the same location so skip
1068 * them if we have already processed the location.
1069 */
1070 if (processed_inputs & ((uint64_t)1 << (loc + i))) {
1071 input_idx += 4;
1072 continue;
1073 }
1074
1075 if (nir->info.stage == MESA_SHADER_VERTEX) {
1076 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1077 bitcast_inputs(ctx, data, input_idx);
1078 if (glsl_type_is_dual_slot(variable->type)) {
1079 input_idx += 4;
1080 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1081 bitcast_inputs(ctx, data, input_idx);
1082 }
1083 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1084 declare_nir_input_fs(ctx, variable, input_idx / 4, data);
1085 bitcast_inputs(ctx, data, input_idx);
1086 }
1087
1088 processed_inputs |= ((uint64_t)1 << (loc + i));
1089 input_idx += 4;
1090 }
1091 }
1092 }
1093
1094 ctx->abi.inputs = &ctx->inputs[0];
1095 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
1096 ctx->abi.clamp_shadow_reference = true;
1097
1098 ctx->num_samplers = util_last_bit(info->samplers_declared);
1099 ctx->num_images = util_last_bit(info->images_declared);
1100
1101 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
1102 assert(gl_shader_stage_is_compute(nir->info.stage));
1103 si_declare_compute_memory(ctx);
1104 }
1105 ac_nir_translate(&ctx->ac, &ctx->abi, nir);
1106
1107 return true;
1108 }