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radeonsi/nir: handle key.mono.u.ps.interpolate_at_sample_force_center
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_nir.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27
28 #include "ac_nir_to_llvm.h"
29
30 #include "tgsi/tgsi_from_mesa.h"
31
32 #include "compiler/nir/nir.h"
33 #include "compiler/nir_types.h"
34 #include "compiler/nir/nir_builder.h"
35
36 static nir_variable* tex_get_texture_var(nir_tex_instr *instr)
37 {
38 for (unsigned i = 0; i < instr->num_srcs; i++) {
39 switch (instr->src[i].src_type) {
40 case nir_tex_src_texture_deref:
41 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[i].src));
42 default:
43 break;
44 }
45 }
46
47 return NULL;
48 }
49
50 static nir_variable* intrinsic_get_var(nir_intrinsic_instr *instr)
51 {
52 return nir_deref_instr_get_variable(nir_src_as_deref(instr->src[0]));
53 }
54
55 static void gather_intrinsic_load_deref_input_info(const nir_shader *nir,
56 const nir_intrinsic_instr *instr,
57 nir_variable *var,
58 struct tgsi_shader_info *info)
59 {
60 assert(var && var->data.mode == nir_var_shader_in);
61
62 switch (nir->info.stage) {
63 case MESA_SHADER_VERTEX: {
64 unsigned i = var->data.driver_location;
65 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
66 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
67
68 for (unsigned j = 0; j < attrib_count; j++, i++) {
69 if (glsl_type_is_64bit(glsl_without_array(var->type))) {
70 unsigned dmask = mask;
71
72 if (glsl_type_is_dual_slot(glsl_without_array(var->type)) && j % 2)
73 dmask >>= 2;
74
75 dmask <<= var->data.location_frac / 2;
76
77 if (dmask & 0x1)
78 info->input_usage_mask[i] |= TGSI_WRITEMASK_XY;
79 if (dmask & 0x2)
80 info->input_usage_mask[i] |= TGSI_WRITEMASK_ZW;
81 } else {
82 info->input_usage_mask[i] |=
83 (mask << var->data.location_frac) & 0xf;
84 }
85 }
86 break;
87 }
88 case MESA_SHADER_FRAGMENT:
89 if (var->data.location == VARYING_SLOT_COL0 ||
90 var->data.location == VARYING_SLOT_COL1) {
91 unsigned index = var->data.location == VARYING_SLOT_COL1;
92 uint8_t mask = nir_ssa_def_components_read(&instr->dest.ssa);
93 info->colors_read |= mask << (index * 4);
94 }
95 break;
96 default:;
97 }
98 }
99
100 static void gather_intrinsic_load_deref_output_info(const nir_shader *nir,
101 const nir_intrinsic_instr *instr,
102 nir_variable *var,
103 struct tgsi_shader_info *info)
104 {
105 assert(var && var->data.mode == nir_var_shader_out);
106
107 switch (nir->info.stage) {
108 case MESA_SHADER_TESS_CTRL:
109 if (var->data.location == VARYING_SLOT_TESS_LEVEL_INNER ||
110 var->data.location == VARYING_SLOT_TESS_LEVEL_OUTER)
111 info->reads_tessfactor_outputs = true;
112 else if (var->data.patch)
113 info->reads_perpatch_outputs = true;
114 else
115 info->reads_pervertex_outputs = true;
116 break;
117
118 case MESA_SHADER_FRAGMENT:
119 if (var->data.fb_fetch_output)
120 info->uses_fbfetch = true;
121 break;
122 default:;
123 }
124 }
125
126 static void gather_intrinsic_store_deref_output_info(const nir_shader *nir,
127 const nir_intrinsic_instr *instr,
128 nir_variable *var,
129 struct tgsi_shader_info *info)
130 {
131 assert(var && var->data.mode == nir_var_shader_out);
132
133 switch (nir->info.stage) {
134 case MESA_SHADER_VERTEX: /* needed by LS, ES */
135 case MESA_SHADER_TESS_EVAL: /* needed by ES */
136 case MESA_SHADER_GEOMETRY: {
137 unsigned i = var->data.driver_location;
138 unsigned attrib_count = glsl_count_attribute_slots(var->type, false);
139 unsigned mask = nir_intrinsic_write_mask(instr);
140
141 assert(!var->data.compact);
142
143 for (unsigned j = 0; j < attrib_count; j++, i++) {
144 if (glsl_type_is_64bit(glsl_without_array(var->type))) {
145 unsigned dmask = mask;
146
147 if (glsl_type_is_dual_slot(glsl_without_array(var->type)) && j % 2)
148 dmask >>= 2;
149
150 dmask <<= var->data.location_frac / 2;
151
152 if (dmask & 0x1)
153 info->output_usagemask[i] |= TGSI_WRITEMASK_XY;
154 if (dmask & 0x2)
155 info->output_usagemask[i] |= TGSI_WRITEMASK_ZW;
156 } else {
157 info->output_usagemask[i] |=
158 (mask << var->data.location_frac) & 0xf;
159 }
160
161 }
162 break;
163 }
164 default:;
165 }
166 }
167
168 static void scan_instruction(const struct nir_shader *nir,
169 struct tgsi_shader_info *info,
170 nir_instr *instr)
171 {
172 if (instr->type == nir_instr_type_alu) {
173 nir_alu_instr *alu = nir_instr_as_alu(instr);
174
175 switch (alu->op) {
176 case nir_op_fddx:
177 case nir_op_fddy:
178 case nir_op_fddx_fine:
179 case nir_op_fddy_fine:
180 case nir_op_fddx_coarse:
181 case nir_op_fddy_coarse:
182 info->uses_derivatives = true;
183 break;
184 default:
185 break;
186 }
187 } else if (instr->type == nir_instr_type_tex) {
188 nir_tex_instr *tex = nir_instr_as_tex(instr);
189 nir_variable *texture = tex_get_texture_var(tex);
190
191 if (!texture) {
192 info->samplers_declared |=
193 u_bit_consecutive(tex->sampler_index, 1);
194 } else {
195 if (texture->data.bindless)
196 info->uses_bindless_samplers = true;
197 }
198
199 switch (tex->op) {
200 case nir_texop_tex:
201 case nir_texop_txb:
202 case nir_texop_lod:
203 info->uses_derivatives = true;
204 break;
205 default:
206 break;
207 }
208 } else if (instr->type == nir_instr_type_intrinsic) {
209 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
210
211 switch (intr->intrinsic) {
212 case nir_intrinsic_load_front_face:
213 info->uses_frontface = 1;
214 break;
215 case nir_intrinsic_load_instance_id:
216 info->uses_instanceid = 1;
217 break;
218 case nir_intrinsic_load_invocation_id:
219 info->uses_invocationid = true;
220 break;
221 case nir_intrinsic_load_num_work_groups:
222 info->uses_grid_size = true;
223 break;
224 case nir_intrinsic_load_local_group_size:
225 /* The block size is translated to IMM with a fixed block size. */
226 if (info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] == 0)
227 info->uses_block_size = true;
228 break;
229 case nir_intrinsic_load_local_invocation_id:
230 case nir_intrinsic_load_work_group_id: {
231 unsigned mask = nir_ssa_def_components_read(&intr->dest.ssa);
232 while (mask) {
233 unsigned i = u_bit_scan(&mask);
234
235 if (intr->intrinsic == nir_intrinsic_load_work_group_id)
236 info->uses_block_id[i] = true;
237 else
238 info->uses_thread_id[i] = true;
239 }
240 break;
241 }
242 case nir_intrinsic_load_vertex_id:
243 info->uses_vertexid = 1;
244 break;
245 case nir_intrinsic_load_vertex_id_zero_base:
246 info->uses_vertexid_nobase = 1;
247 break;
248 case nir_intrinsic_load_base_vertex:
249 info->uses_basevertex = 1;
250 break;
251 case nir_intrinsic_load_draw_id:
252 info->uses_drawid = 1;
253 break;
254 case nir_intrinsic_load_primitive_id:
255 info->uses_primid = 1;
256 break;
257 case nir_intrinsic_load_sample_mask_in:
258 info->reads_samplemask = true;
259 break;
260 case nir_intrinsic_load_tess_level_inner:
261 case nir_intrinsic_load_tess_level_outer:
262 info->reads_tess_factors = true;
263 break;
264 case nir_intrinsic_bindless_image_load:
265 info->uses_bindless_images = true;
266
267 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
268 info->uses_bindless_buffer_load = true;
269 else
270 info->uses_bindless_image_load = true;
271 break;
272 case nir_intrinsic_bindless_image_size:
273 case nir_intrinsic_bindless_image_samples:
274 info->uses_bindless_images = true;
275 break;
276 case nir_intrinsic_bindless_image_store:
277 info->uses_bindless_images = true;
278
279 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
280 info->uses_bindless_buffer_store = true;
281 else
282 info->uses_bindless_image_store = true;
283
284 info->writes_memory = true;
285 info->num_memory_instructions++; /* we only care about stores */
286 break;
287 case nir_intrinsic_image_deref_store:
288 info->writes_memory = true;
289 info->num_memory_instructions++; /* we only care about stores */
290 break;
291 case nir_intrinsic_bindless_image_atomic_add:
292 case nir_intrinsic_bindless_image_atomic_min:
293 case nir_intrinsic_bindless_image_atomic_max:
294 case nir_intrinsic_bindless_image_atomic_and:
295 case nir_intrinsic_bindless_image_atomic_or:
296 case nir_intrinsic_bindless_image_atomic_xor:
297 case nir_intrinsic_bindless_image_atomic_exchange:
298 case nir_intrinsic_bindless_image_atomic_comp_swap:
299 info->uses_bindless_images = true;
300
301 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF)
302 info->uses_bindless_buffer_atomic = true;
303 else
304 info->uses_bindless_image_atomic = true;
305
306 info->writes_memory = true;
307 info->num_memory_instructions++; /* we only care about stores */
308 break;
309 case nir_intrinsic_image_deref_atomic_add:
310 case nir_intrinsic_image_deref_atomic_min:
311 case nir_intrinsic_image_deref_atomic_max:
312 case nir_intrinsic_image_deref_atomic_and:
313 case nir_intrinsic_image_deref_atomic_or:
314 case nir_intrinsic_image_deref_atomic_xor:
315 case nir_intrinsic_image_deref_atomic_exchange:
316 case nir_intrinsic_image_deref_atomic_comp_swap:
317 info->writes_memory = true;
318 info->num_memory_instructions++; /* we only care about stores */
319 break;
320 case nir_intrinsic_store_ssbo:
321 case nir_intrinsic_ssbo_atomic_add:
322 case nir_intrinsic_ssbo_atomic_imin:
323 case nir_intrinsic_ssbo_atomic_umin:
324 case nir_intrinsic_ssbo_atomic_imax:
325 case nir_intrinsic_ssbo_atomic_umax:
326 case nir_intrinsic_ssbo_atomic_and:
327 case nir_intrinsic_ssbo_atomic_or:
328 case nir_intrinsic_ssbo_atomic_xor:
329 case nir_intrinsic_ssbo_atomic_exchange:
330 case nir_intrinsic_ssbo_atomic_comp_swap:
331 info->writes_memory = true;
332 info->num_memory_instructions++; /* we only care about stores */
333 break;
334 case nir_intrinsic_load_deref: {
335 nir_variable *var = intrinsic_get_var(intr);
336 nir_variable_mode mode = var->data.mode;
337 enum glsl_base_type base_type =
338 glsl_get_base_type(glsl_without_array(var->type));
339
340 if (mode == nir_var_shader_in) {
341 gather_intrinsic_load_deref_input_info(nir, intr, var, info);
342
343 switch (var->data.interpolation) {
344 case INTERP_MODE_NONE:
345 if (glsl_base_type_is_integer(base_type))
346 break;
347
348 /* fall-through */
349 case INTERP_MODE_SMOOTH:
350 if (var->data.sample)
351 info->uses_persp_sample = true;
352 else if (var->data.centroid)
353 info->uses_persp_centroid = true;
354 else
355 info->uses_persp_center = true;
356 break;
357
358 case INTERP_MODE_NOPERSPECTIVE:
359 if (var->data.sample)
360 info->uses_linear_sample = true;
361 else if (var->data.centroid)
362 info->uses_linear_centroid = true;
363 else
364 info->uses_linear_center = true;
365 break;
366 }
367 } else if (mode == nir_var_shader_out) {
368 gather_intrinsic_load_deref_output_info(nir, intr, var, info);
369 }
370 break;
371 }
372 case nir_intrinsic_store_deref: {
373 nir_variable *var = intrinsic_get_var(intr);
374
375 if (var->data.mode == nir_var_shader_out)
376 gather_intrinsic_store_deref_output_info(nir, intr, var, info);
377 break;
378 }
379 case nir_intrinsic_interp_deref_at_centroid:
380 case nir_intrinsic_interp_deref_at_sample:
381 case nir_intrinsic_interp_deref_at_offset: {
382 enum glsl_interp_mode interp = intrinsic_get_var(intr)->data.interpolation;
383 switch (interp) {
384 case INTERP_MODE_SMOOTH:
385 case INTERP_MODE_NONE:
386 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
387 info->uses_persp_opcode_interp_centroid = true;
388 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
389 info->uses_persp_opcode_interp_sample = true;
390 else
391 info->uses_persp_opcode_interp_offset = true;
392 break;
393 case INTERP_MODE_NOPERSPECTIVE:
394 if (intr->intrinsic == nir_intrinsic_interp_deref_at_centroid)
395 info->uses_linear_opcode_interp_centroid = true;
396 else if (intr->intrinsic == nir_intrinsic_interp_deref_at_sample)
397 info->uses_linear_opcode_interp_sample = true;
398 else
399 info->uses_linear_opcode_interp_offset = true;
400 break;
401 case INTERP_MODE_FLAT:
402 break;
403 default:
404 unreachable("Unsupported interpoation type");
405 }
406 break;
407 }
408 default:
409 break;
410 }
411 }
412 }
413
414 void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
415 struct tgsi_tessctrl_info *out)
416 {
417 memset(out, 0, sizeof(*out));
418
419 if (nir->info.stage != MESA_SHADER_TESS_CTRL)
420 return;
421
422 out->tessfactors_are_def_in_all_invocs =
423 ac_are_tessfactors_def_in_all_invocs(nir);
424 }
425
426 void si_nir_scan_shader(const struct nir_shader *nir,
427 struct tgsi_shader_info *info)
428 {
429 nir_function *func;
430 unsigned i;
431
432 info->processor = pipe_shader_type_from_mesa(nir->info.stage);
433 info->num_tokens = 2; /* indicate that the shader is non-empty */
434 info->num_instructions = 2;
435
436 info->properties[TGSI_PROPERTY_NEXT_SHADER] =
437 pipe_shader_type_from_mesa(nir->info.next_stage);
438
439 if (nir->info.stage == MESA_SHADER_VERTEX) {
440 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] =
441 nir->info.vs.window_space_position;
442 }
443
444 if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
445 info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
446 nir->info.tess.tcs_vertices_out;
447 }
448
449 if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
450 if (nir->info.tess.primitive_mode == GL_ISOLINES)
451 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = PIPE_PRIM_LINES;
452 else
453 info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = nir->info.tess.primitive_mode;
454
455 STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == PIPE_TESS_SPACING_EQUAL);
456 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
457 PIPE_TESS_SPACING_FRACTIONAL_ODD);
458 STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
459 PIPE_TESS_SPACING_FRACTIONAL_EVEN);
460
461 info->properties[TGSI_PROPERTY_TES_SPACING] = (nir->info.tess.spacing + 1) % 3;
462 info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = !nir->info.tess.ccw;
463 info->properties[TGSI_PROPERTY_TES_POINT_MODE] = nir->info.tess.point_mode;
464 }
465
466 if (nir->info.stage == MESA_SHADER_GEOMETRY) {
467 info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = nir->info.gs.input_primitive;
468 info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = nir->info.gs.output_primitive;
469 info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES] = nir->info.gs.vertices_out;
470 info->properties[TGSI_PROPERTY_GS_INVOCATIONS] = nir->info.gs.invocations;
471 }
472
473 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
474 info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] =
475 nir->info.fs.early_fragment_tests | nir->info.fs.post_depth_coverage;
476 info->properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE] = nir->info.fs.post_depth_coverage;
477
478 if (nir->info.fs.pixel_center_integer) {
479 info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] =
480 TGSI_FS_COORD_PIXEL_CENTER_INTEGER;
481 }
482
483 if (nir->info.fs.depth_layout != FRAG_DEPTH_LAYOUT_NONE) {
484 switch (nir->info.fs.depth_layout) {
485 case FRAG_DEPTH_LAYOUT_ANY:
486 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_ANY;
487 break;
488 case FRAG_DEPTH_LAYOUT_GREATER:
489 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_GREATER;
490 break;
491 case FRAG_DEPTH_LAYOUT_LESS:
492 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_LESS;
493 break;
494 case FRAG_DEPTH_LAYOUT_UNCHANGED:
495 info->properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT] = TGSI_FS_DEPTH_LAYOUT_UNCHANGED;
496 break;
497 default:
498 unreachable("Unknow depth layout");
499 }
500 }
501 }
502
503 if (gl_shader_stage_is_compute(nir->info.stage)) {
504 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH] = nir->info.cs.local_size[0];
505 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT] = nir->info.cs.local_size[1];
506 info->properties[TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH] = nir->info.cs.local_size[2];
507 }
508
509 i = 0;
510 uint64_t processed_inputs = 0;
511 unsigned num_inputs = 0;
512 nir_foreach_variable(variable, &nir->inputs) {
513 unsigned semantic_name, semantic_index;
514
515 const struct glsl_type *type = variable->type;
516 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
517 assert(glsl_type_is_array(type));
518 type = glsl_get_array_element(type);
519 }
520
521 unsigned attrib_count = glsl_count_attribute_slots(type,
522 nir->info.stage == MESA_SHADER_VERTEX);
523
524 i = variable->data.driver_location;
525
526 /* Vertex shader inputs don't have semantics. The state
527 * tracker has already mapped them to attributes via
528 * variable->data.driver_location.
529 */
530 if (nir->info.stage == MESA_SHADER_VERTEX) {
531 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)))
532 num_inputs++;
533
534 num_inputs++;
535 continue;
536 }
537
538 for (unsigned j = 0; j < attrib_count; j++, i++) {
539
540 if (processed_inputs & ((uint64_t)1 << i))
541 continue;
542
543 processed_inputs |= ((uint64_t)1 << i);
544 num_inputs++;
545
546 tgsi_get_gl_varying_semantic(variable->data.location + j, true,
547 &semantic_name, &semantic_index);
548
549 info->input_semantic_name[i] = semantic_name;
550 info->input_semantic_index[i] = semantic_index;
551
552 if (semantic_name == TGSI_SEMANTIC_PRIMID)
553 info->uses_primid = true;
554
555 if (semantic_name == TGSI_SEMANTIC_COLOR) {
556 /* We only need this for color inputs. */
557 if (variable->data.sample)
558 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_SAMPLE;
559 else if (variable->data.centroid)
560 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTROID;
561 else
562 info->input_interpolate_loc[i] = TGSI_INTERPOLATE_LOC_CENTER;
563 }
564
565 enum glsl_base_type base_type =
566 glsl_get_base_type(glsl_without_array(variable->type));
567
568 switch (variable->data.interpolation) {
569 case INTERP_MODE_NONE:
570 if (glsl_base_type_is_integer(base_type)) {
571 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
572 break;
573 }
574
575 if (semantic_name == TGSI_SEMANTIC_COLOR) {
576 info->input_interpolate[i] = TGSI_INTERPOLATE_COLOR;
577 break;
578 }
579 /* fall-through */
580
581 case INTERP_MODE_SMOOTH:
582 assert(!glsl_base_type_is_integer(base_type));
583
584 info->input_interpolate[i] = TGSI_INTERPOLATE_PERSPECTIVE;
585 break;
586
587 case INTERP_MODE_NOPERSPECTIVE:
588 assert(!glsl_base_type_is_integer(base_type));
589
590 info->input_interpolate[i] = TGSI_INTERPOLATE_LINEAR;
591 break;
592
593 case INTERP_MODE_FLAT:
594 info->input_interpolate[i] = TGSI_INTERPOLATE_CONSTANT;
595 break;
596 }
597 }
598 }
599
600 info->num_inputs = num_inputs;
601
602 i = 0;
603 uint64_t processed_outputs = 0;
604 unsigned num_outputs = 0;
605 nir_foreach_variable(variable, &nir->outputs) {
606 unsigned semantic_name, semantic_index;
607
608 i = variable->data.driver_location;
609
610 const struct glsl_type *type = variable->type;
611 if (nir_is_per_vertex_io(variable, nir->info.stage)) {
612 assert(glsl_type_is_array(type));
613 type = glsl_get_array_element(type);
614 }
615
616 unsigned attrib_count = glsl_count_attribute_slots(type, false);
617 for (unsigned k = 0; k < attrib_count; k++, i++) {
618
619 if (nir->info.stage == MESA_SHADER_FRAGMENT) {
620 tgsi_get_gl_frag_result_semantic(variable->data.location + k,
621 &semantic_name, &semantic_index);
622
623 /* Adjust for dual source blending */
624 if (variable->data.index > 0) {
625 semantic_index++;
626 }
627 } else {
628 tgsi_get_gl_varying_semantic(variable->data.location + k, true,
629 &semantic_name, &semantic_index);
630 }
631
632 unsigned num_components = 4;
633 unsigned vector_elements = glsl_get_vector_elements(glsl_without_array(variable->type));
634 if (vector_elements)
635 num_components = vector_elements;
636
637 unsigned component = variable->data.location_frac;
638 if (glsl_type_is_64bit(glsl_without_array(variable->type))) {
639 if (glsl_type_is_dual_slot(glsl_without_array(variable->type)) && k % 2) {
640 num_components = (num_components * 2) - 4;
641 component = 0;
642 } else {
643 num_components = MIN2(num_components * 2, 4);
644 }
645 }
646
647 ubyte usagemask = 0;
648 for (unsigned j = component; j < num_components + component; j++) {
649 switch (j) {
650 case 0:
651 usagemask |= TGSI_WRITEMASK_X;
652 break;
653 case 1:
654 usagemask |= TGSI_WRITEMASK_Y;
655 break;
656 case 2:
657 usagemask |= TGSI_WRITEMASK_Z;
658 break;
659 case 3:
660 usagemask |= TGSI_WRITEMASK_W;
661 break;
662 default:
663 unreachable("error calculating component index");
664 }
665 }
666
667 unsigned gs_out_streams;
668 if (variable->data.stream & (1u << 31)) {
669 gs_out_streams = variable->data.stream & ~(1u << 31);
670 } else {
671 assert(variable->data.stream < 4);
672 gs_out_streams = 0;
673 for (unsigned j = 0; j < num_components; ++j)
674 gs_out_streams |= variable->data.stream << (2 * (component + j));
675 }
676
677 unsigned streamx = gs_out_streams & 3;
678 unsigned streamy = (gs_out_streams >> 2) & 3;
679 unsigned streamz = (gs_out_streams >> 4) & 3;
680 unsigned streamw = (gs_out_streams >> 6) & 3;
681
682 if (usagemask & TGSI_WRITEMASK_X) {
683 info->output_streams[i] |= streamx;
684 info->num_stream_output_components[streamx]++;
685 }
686 if (usagemask & TGSI_WRITEMASK_Y) {
687 info->output_streams[i] |= streamy << 2;
688 info->num_stream_output_components[streamy]++;
689 }
690 if (usagemask & TGSI_WRITEMASK_Z) {
691 info->output_streams[i] |= streamz << 4;
692 info->num_stream_output_components[streamz]++;
693 }
694 if (usagemask & TGSI_WRITEMASK_W) {
695 info->output_streams[i] |= streamw << 6;
696 info->num_stream_output_components[streamw]++;
697 }
698
699 /* make sure we only count this location once against
700 * the num_outputs counter.
701 */
702 if (processed_outputs & ((uint64_t)1 << i))
703 continue;
704
705 processed_outputs |= ((uint64_t)1 << i);
706 num_outputs++;
707
708 info->output_semantic_name[i] = semantic_name;
709 info->output_semantic_index[i] = semantic_index;
710
711 switch (semantic_name) {
712 case TGSI_SEMANTIC_PRIMID:
713 info->writes_primid = true;
714 break;
715 case TGSI_SEMANTIC_VIEWPORT_INDEX:
716 info->writes_viewport_index = true;
717 break;
718 case TGSI_SEMANTIC_LAYER:
719 info->writes_layer = true;
720 break;
721 case TGSI_SEMANTIC_PSIZE:
722 info->writes_psize = true;
723 break;
724 case TGSI_SEMANTIC_CLIPVERTEX:
725 info->writes_clipvertex = true;
726 break;
727 case TGSI_SEMANTIC_COLOR:
728 info->colors_written |= 1 << semantic_index;
729 break;
730 case TGSI_SEMANTIC_STENCIL:
731 info->writes_stencil = true;
732 break;
733 case TGSI_SEMANTIC_SAMPLEMASK:
734 info->writes_samplemask = true;
735 break;
736 case TGSI_SEMANTIC_EDGEFLAG:
737 info->writes_edgeflag = true;
738 break;
739 case TGSI_SEMANTIC_POSITION:
740 if (info->processor == PIPE_SHADER_FRAGMENT)
741 info->writes_z = true;
742 else
743 info->writes_position = true;
744 break;
745 }
746 }
747
748 unsigned loc = variable->data.location;
749 if (nir->info.stage == MESA_SHADER_FRAGMENT &&
750 loc == FRAG_RESULT_COLOR &&
751 nir->info.outputs_written & (1ull << loc)) {
752 assert(attrib_count == 1);
753 info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
754 }
755 }
756
757 info->num_outputs = num_outputs;
758
759 struct set *ubo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
760 _mesa_key_pointer_equal);
761 struct set *ssbo_set = _mesa_set_create(NULL, _mesa_hash_pointer,
762 _mesa_key_pointer_equal);
763
764 /* Intialise const_file_max[0] */
765 info->const_file_max[0] = -1;
766
767 /* The first 8 are reserved for atomic counters using ssbo */
768 unsigned ssbo_idx = 8;
769
770 unsigned ubo_idx = 1;
771 nir_foreach_variable(variable, &nir->uniforms) {
772 const struct glsl_type *type = variable->type;
773 enum glsl_base_type base_type =
774 glsl_get_base_type(glsl_without_array(type));
775 unsigned aoa_size = MAX2(1, glsl_get_aoa_size(type));
776 unsigned loc = variable->data.driver_location / 4;
777 int slot_count = glsl_count_attribute_slots(type, false);
778 int max_slot = MAX2(info->const_file_max[0], (int) loc) + slot_count;
779
780 /* Gather buffers declared bitmasks. Note: radeonsi doesn't
781 * really use the mask (other than ubo_idx == 1 for regular
782 * uniforms) its really only used for getting the buffer count
783 * so we don't need to worry about the ordering.
784 */
785 if (variable->interface_type != NULL) {
786 if (variable->data.mode == nir_var_uniform ||
787 variable->data.mode == nir_var_mem_ubo ||
788 variable->data.mode == nir_var_mem_ssbo) {
789
790 struct set *buf_set = variable->data.mode == nir_var_mem_ssbo ?
791 ssbo_set : ubo_set;
792
793 unsigned block_count;
794 if (base_type != GLSL_TYPE_INTERFACE) {
795 struct set_entry *entry =
796 _mesa_set_search(buf_set, variable->interface_type);
797
798 /* Check if we have already processed
799 * a member from this ubo.
800 */
801 if (entry)
802 continue;
803
804 block_count = 1;
805 } else {
806 block_count = aoa_size;
807 }
808
809 if (variable->data.mode == nir_var_uniform ||
810 variable->data.mode == nir_var_mem_ubo) {
811 info->const_buffers_declared |= u_bit_consecutive(ubo_idx, block_count);
812 ubo_idx += block_count;
813 } else {
814 assert(variable->data.mode == nir_var_mem_ssbo);
815
816 info->shader_buffers_declared |= u_bit_consecutive(ssbo_idx, block_count);
817 ssbo_idx += block_count;
818 }
819
820 _mesa_set_add(buf_set, variable->interface_type);
821 }
822
823 continue;
824 }
825
826 /* We rely on the fact that nir_lower_samplers_as_deref has
827 * eliminated struct dereferences.
828 */
829 if (base_type == GLSL_TYPE_SAMPLER && !variable->data.bindless) {
830 info->samplers_declared |=
831 u_bit_consecutive(variable->data.binding, aoa_size);
832 } else if (base_type == GLSL_TYPE_IMAGE && !variable->data.bindless) {
833 info->images_declared |=
834 u_bit_consecutive(variable->data.binding, aoa_size);
835 } else if (base_type != GLSL_TYPE_ATOMIC_UINT) {
836 info->const_buffers_declared |= 1;
837 info->const_file_max[0] = max_slot;
838 }
839 }
840
841 _mesa_set_destroy(ubo_set, NULL);
842 _mesa_set_destroy(ssbo_set, NULL);
843
844 info->num_written_clipdistance = nir->info.clip_distance_array_size;
845 info->num_written_culldistance = nir->info.cull_distance_array_size;
846 info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance);
847 info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance);
848
849 if (info->processor == PIPE_SHADER_FRAGMENT)
850 info->uses_kill = nir->info.fs.uses_discard;
851
852 func = (struct nir_function *)exec_list_get_head_const(&nir->functions);
853 nir_foreach_block(block, func->impl) {
854 nir_foreach_instr(instr, block)
855 scan_instruction(nir, info, instr);
856 }
857 }
858
859 void
860 si_nir_opts(struct nir_shader *nir)
861 {
862 bool progress;
863 unsigned lower_flrp =
864 (nir->options->lower_flrp16 ? 16 : 0) |
865 (nir->options->lower_flrp32 ? 32 : 0) |
866 (nir->options->lower_flrp64 ? 64 : 0);
867
868 do {
869 progress = false;
870
871 NIR_PASS_V(nir, nir_lower_vars_to_ssa);
872
873 NIR_PASS(progress, nir, nir_opt_copy_prop_vars);
874 NIR_PASS(progress, nir, nir_opt_dead_write_vars);
875
876 NIR_PASS_V(nir, nir_lower_alu_to_scalar, NULL);
877 NIR_PASS_V(nir, nir_lower_phis_to_scalar);
878
879 /* (Constant) copy propagation is needed for txf with offsets. */
880 NIR_PASS(progress, nir, nir_copy_prop);
881 NIR_PASS(progress, nir, nir_opt_remove_phis);
882 NIR_PASS(progress, nir, nir_opt_dce);
883 if (nir_opt_trivial_continues(nir)) {
884 progress = true;
885 NIR_PASS(progress, nir, nir_copy_prop);
886 NIR_PASS(progress, nir, nir_opt_dce);
887 }
888 NIR_PASS(progress, nir, nir_opt_if, true);
889 NIR_PASS(progress, nir, nir_opt_dead_cf);
890 NIR_PASS(progress, nir, nir_opt_cse);
891 NIR_PASS(progress, nir, nir_opt_peephole_select, 8, true, true);
892
893 /* Needed for algebraic lowering */
894 NIR_PASS(progress, nir, nir_opt_algebraic);
895 NIR_PASS(progress, nir, nir_opt_constant_folding);
896
897 if (lower_flrp != 0) {
898 bool lower_flrp_progress = false;
899
900 NIR_PASS(lower_flrp_progress, nir, nir_lower_flrp,
901 lower_flrp,
902 false /* always_precise */,
903 nir->options->lower_ffma);
904 if (lower_flrp_progress) {
905 NIR_PASS(progress, nir,
906 nir_opt_constant_folding);
907 progress = true;
908 }
909
910 /* Nothing should rematerialize any flrps, so we only
911 * need to do this lowering once.
912 */
913 lower_flrp = 0;
914 }
915
916 NIR_PASS(progress, nir, nir_opt_undef);
917 NIR_PASS(progress, nir, nir_opt_conditional_discard);
918 if (nir->options->max_unroll_iterations) {
919 NIR_PASS(progress, nir, nir_opt_loop_unroll, 0);
920 }
921 } while (progress);
922 }
923
924 static int
925 type_size_vec4(const struct glsl_type *type, bool bindless)
926 {
927 return glsl_count_attribute_slots(type, false);
928 }
929
930 static void
931 si_nir_lower_color(nir_shader *nir)
932 {
933 nir_function_impl *entrypoint = nir_shader_get_entrypoint(nir);
934
935 nir_builder b;
936 nir_builder_init(&b, entrypoint);
937
938 nir_foreach_block(block, entrypoint) {
939 nir_foreach_instr_safe(instr, block) {
940 if (instr->type != nir_instr_type_intrinsic)
941 continue;
942
943 nir_intrinsic_instr *intrin =
944 nir_instr_as_intrinsic(instr);
945
946 if (intrin->intrinsic != nir_intrinsic_load_deref)
947 continue;
948
949 nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
950 if (deref->mode != nir_var_shader_in)
951 continue;
952
953 b.cursor = nir_before_instr(instr);
954 nir_variable *var = nir_deref_instr_get_variable(deref);
955 nir_ssa_def *def;
956
957 if (var->data.location == VARYING_SLOT_COL0) {
958 def = nir_load_color0(&b);
959 } else if (var->data.location == VARYING_SLOT_COL1) {
960 def = nir_load_color1(&b);
961 } else {
962 continue;
963 }
964
965 nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(def));
966 nir_instr_remove(instr);
967 }
968 }
969 }
970
971 /**
972 * Perform "lowering" operations on the NIR that are run once when the shader
973 * selector is created.
974 */
975 void
976 si_lower_nir(struct si_shader_selector* sel, unsigned wave_size)
977 {
978 /* Adjust the driver location of inputs and outputs. The state tracker
979 * interprets them as slots, while the ac/nir backend interprets them
980 * as individual components.
981 */
982 if (sel->nir->info.stage != MESA_SHADER_FRAGMENT) {
983 nir_foreach_variable(variable, &sel->nir->inputs)
984 variable->data.driver_location *= 4;
985 } else {
986 NIR_PASS_V(sel->nir, nir_lower_io_to_temporaries,
987 nir_shader_get_entrypoint(sel->nir), false, true);
988
989 /* Since we're doing nir_lower_io_to_temporaries late, we need
990 * to lower all the copy_deref's introduced by
991 * lower_io_to_temporaries before calling nir_lower_io.
992 */
993 NIR_PASS_V(sel->nir, nir_split_var_copies);
994 NIR_PASS_V(sel->nir, nir_lower_var_copies);
995 NIR_PASS_V(sel->nir, nir_lower_global_vars_to_local);
996
997 si_nir_lower_color(sel->nir);
998 NIR_PASS_V(sel->nir, nir_lower_io, nir_var_shader_in, type_size_vec4, 0);
999
1000 /* This pass needs actual constants */
1001 NIR_PASS_V(sel->nir, nir_opt_constant_folding);
1002 NIR_PASS_V(sel->nir, nir_io_add_const_offset_to_base,
1003 nir_var_shader_in);
1004 }
1005
1006 nir_foreach_variable(variable, &sel->nir->outputs) {
1007 variable->data.driver_location *= 4;
1008
1009 if (sel->nir->info.stage == MESA_SHADER_FRAGMENT) {
1010 if (variable->data.location == FRAG_RESULT_DEPTH)
1011 variable->data.driver_location += 2;
1012 else if (variable->data.location == FRAG_RESULT_STENCIL)
1013 variable->data.driver_location += 1;
1014 }
1015 }
1016
1017 /* Perform lowerings (and optimizations) of code.
1018 *
1019 * Performance considerations aside, we must:
1020 * - lower certain ALU operations
1021 * - ensure constant offsets for texture instructions are folded
1022 * and copy-propagated
1023 */
1024
1025 static const struct nir_lower_tex_options lower_tex_options = {
1026 .lower_txp = ~0u,
1027 };
1028 NIR_PASS_V(sel->nir, nir_lower_tex, &lower_tex_options);
1029
1030 const nir_lower_subgroups_options subgroups_options = {
1031 .subgroup_size = wave_size,
1032 .ballot_bit_size = wave_size,
1033 .lower_to_scalar = true,
1034 .lower_subgroup_masks = true,
1035 .lower_vote_trivial = false,
1036 .lower_vote_eq_to_ballot = true,
1037 };
1038 NIR_PASS_V(sel->nir, nir_lower_subgroups, &subgroups_options);
1039
1040 ac_lower_indirect_derefs(sel->nir, sel->screen->info.chip_class);
1041
1042 si_nir_opts(sel->nir);
1043
1044 NIR_PASS_V(sel->nir, nir_lower_bool_to_int32);
1045
1046 /* Strip the resulting shader so that the shader cache is more likely
1047 * to hit from other similar shaders.
1048 */
1049 nir_strip(sel->nir);
1050 }
1051
1052 static void declare_nir_input_vs(struct si_shader_context *ctx,
1053 struct nir_variable *variable,
1054 unsigned input_index,
1055 LLVMValueRef out[4])
1056 {
1057 si_llvm_load_input_vs(ctx, input_index, out);
1058 }
1059
1060 LLVMValueRef
1061 si_nir_lookup_interp_param(struct ac_shader_abi *abi,
1062 enum glsl_interp_mode interp, unsigned location)
1063 {
1064 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1065 int interp_param_idx = -1;
1066
1067 switch (interp) {
1068 case INTERP_MODE_FLAT:
1069 return NULL;
1070 case INTERP_MODE_SMOOTH:
1071 case INTERP_MODE_NONE:
1072 if (location == INTERP_CENTER)
1073 interp_param_idx = SI_PARAM_PERSP_CENTER;
1074 else if (location == INTERP_CENTROID)
1075 interp_param_idx = SI_PARAM_PERSP_CENTROID;
1076 else if (location == INTERP_SAMPLE)
1077 interp_param_idx = SI_PARAM_PERSP_SAMPLE;
1078 break;
1079 case INTERP_MODE_NOPERSPECTIVE:
1080 if (location == INTERP_CENTER)
1081 interp_param_idx = SI_PARAM_LINEAR_CENTER;
1082 else if (location == INTERP_CENTROID)
1083 interp_param_idx = SI_PARAM_LINEAR_CENTROID;
1084 else if (location == INTERP_SAMPLE)
1085 interp_param_idx = SI_PARAM_LINEAR_SAMPLE;
1086 break;
1087 default:
1088 assert(!"Unhandled interpolation mode.");
1089 return NULL;
1090 }
1091
1092 return interp_param_idx != -1 ?
1093 LLVMGetParam(ctx->main_fn, interp_param_idx) : NULL;
1094 }
1095
1096 static LLVMValueRef
1097 si_nir_load_sampler_desc(struct ac_shader_abi *abi,
1098 unsigned descriptor_set, unsigned base_index,
1099 unsigned constant_index, LLVMValueRef dynamic_index,
1100 enum ac_descriptor_type desc_type, bool image,
1101 bool write, bool bindless)
1102 {
1103 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1104 LLVMBuilderRef builder = ctx->ac.builder;
1105 unsigned const_index = base_index + constant_index;
1106
1107 assert(!descriptor_set);
1108 assert(!image || desc_type == AC_DESC_IMAGE || desc_type == AC_DESC_BUFFER);
1109
1110 if (bindless) {
1111 LLVMValueRef list =
1112 LLVMGetParam(ctx->main_fn, ctx->param_bindless_samplers_and_images);
1113
1114 /* dynamic_index is the bindless handle */
1115 if (image) {
1116 /* For simplicity, bindless image descriptors use fixed
1117 * 16-dword slots for now.
1118 */
1119 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1120 LLVMConstInt(ctx->i64, 2, 0), "");
1121
1122 return si_load_image_desc(ctx, list, dynamic_index, desc_type,
1123 write, true);
1124 }
1125
1126 /* Since bindless handle arithmetic can contain an unsigned integer
1127 * wraparound and si_load_sampler_desc assumes there isn't any,
1128 * use GEP without "inbounds" (inside ac_build_pointer_add)
1129 * to prevent incorrect code generation and hangs.
1130 */
1131 dynamic_index = LLVMBuildMul(ctx->ac.builder, dynamic_index,
1132 LLVMConstInt(ctx->i64, 2, 0), "");
1133 list = ac_build_pointer_add(&ctx->ac, list, dynamic_index);
1134 return si_load_sampler_desc(ctx, list, ctx->i32_0, desc_type);
1135 }
1136
1137 unsigned num_slots = image ? ctx->num_images : ctx->num_samplers;
1138 assert(const_index < num_slots);
1139
1140 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1141 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, const_index, false);
1142
1143 if (dynamic_index) {
1144 index = LLVMBuildAdd(builder, index, dynamic_index, "");
1145
1146 /* From the GL_ARB_shader_image_load_store extension spec:
1147 *
1148 * If a shader performs an image load, store, or atomic
1149 * operation using an image variable declared as an array,
1150 * and if the index used to select an individual element is
1151 * negative or greater than or equal to the size of the
1152 * array, the results of the operation are undefined but may
1153 * not lead to termination.
1154 */
1155 index = si_llvm_bound_index(ctx, index, num_slots);
1156 }
1157
1158 if (image) {
1159 index = LLVMBuildSub(ctx->ac.builder,
1160 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
1161 index, "");
1162 return si_load_image_desc(ctx, list, index, desc_type, write, false);
1163 }
1164
1165 index = LLVMBuildAdd(ctx->ac.builder, index,
1166 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1167 return si_load_sampler_desc(ctx, list, index, desc_type);
1168 }
1169
1170 static void bitcast_inputs(struct si_shader_context *ctx,
1171 LLVMValueRef data[4],
1172 unsigned input_idx)
1173 {
1174 for (unsigned chan = 0; chan < 4; chan++) {
1175 ctx->inputs[input_idx + chan] =
1176 LLVMBuildBitCast(ctx->ac.builder, data[chan], ctx->ac.i32, "");
1177 }
1178 }
1179
1180 bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
1181 {
1182 struct tgsi_shader_info *info = &ctx->shader->selector->info;
1183
1184 if (nir->info.stage == MESA_SHADER_VERTEX) {
1185 uint64_t processed_inputs = 0;
1186 nir_foreach_variable(variable, &nir->inputs) {
1187 unsigned attrib_count = glsl_count_attribute_slots(variable->type,
1188 true);
1189 unsigned input_idx = variable->data.driver_location;
1190
1191 LLVMValueRef data[4];
1192 unsigned loc = variable->data.location;
1193
1194 for (unsigned i = 0; i < attrib_count; i++) {
1195 /* Packed components share the same location so skip
1196 * them if we have already processed the location.
1197 */
1198 if (processed_inputs & ((uint64_t)1 << (loc + i))) {
1199 input_idx += 4;
1200 continue;
1201 }
1202
1203 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1204 bitcast_inputs(ctx, data, input_idx);
1205 if (glsl_type_is_dual_slot(variable->type)) {
1206 input_idx += 4;
1207 declare_nir_input_vs(ctx, variable, input_idx / 4, data);
1208 bitcast_inputs(ctx, data, input_idx);
1209 }
1210
1211 processed_inputs |= ((uint64_t)1 << (loc + i));
1212 input_idx += 4;
1213 }
1214 }
1215 } else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
1216 unsigned colors_read =
1217 ctx->shader->selector->info.colors_read;
1218 LLVMValueRef main_fn = ctx->main_fn;
1219
1220 LLVMValueRef undef = LLVMGetUndef(ctx->f32);
1221
1222 unsigned offset = SI_PARAM_POS_FIXED_PT + 1;
1223
1224 if (colors_read & 0x0f) {
1225 unsigned mask = colors_read & 0x0f;
1226 LLVMValueRef values[4];
1227 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1228 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1229 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1230 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1231 ctx->abi.color0 =
1232 ac_to_integer(&ctx->ac,
1233 ac_build_gather_values(&ctx->ac, values, 4));
1234 }
1235 if (colors_read & 0xf0) {
1236 unsigned mask = (colors_read & 0xf0) >> 4;
1237 LLVMValueRef values[4];
1238 values[0] = mask & 0x1 ? LLVMGetParam(main_fn, offset++) : undef;
1239 values[1] = mask & 0x2 ? LLVMGetParam(main_fn, offset++) : undef;
1240 values[2] = mask & 0x4 ? LLVMGetParam(main_fn, offset++) : undef;
1241 values[3] = mask & 0x8 ? LLVMGetParam(main_fn, offset++) : undef;
1242 ctx->abi.color1 =
1243 ac_to_integer(&ctx->ac,
1244 ac_build_gather_values(&ctx->ac, values, 4));
1245 }
1246
1247 ctx->abi.interp_at_sample_force_center =
1248 ctx->shader->key.mono.u.ps.interpolate_at_sample_force_center;
1249 }
1250
1251 ctx->abi.inputs = &ctx->inputs[0];
1252 ctx->abi.load_sampler_desc = si_nir_load_sampler_desc;
1253 ctx->abi.clamp_shadow_reference = true;
1254 ctx->abi.robust_buffer_access = true;
1255
1256 ctx->num_samplers = util_last_bit(info->samplers_declared);
1257 ctx->num_images = util_last_bit(info->images_declared);
1258
1259 if (ctx->shader->selector->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE]) {
1260 assert(gl_shader_stage_is_compute(nir->info.stage));
1261 si_declare_compute_memory(ctx);
1262 }
1263 ac_nir_translate(&ctx->ac, &ctx->abi, nir);
1264
1265 return true;
1266 }