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util: remove LIST_IS_EMPTY macro
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_tgsi_mem.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include <llvm/Config/llvm-config.h>
26
27 #include "si_shader_internal.h"
28 #include "si_pipe.h"
29 #include "sid.h"
30 #include "tgsi/tgsi_build.h"
31 #include "tgsi/tgsi_util.h"
32 #include "ac_llvm_util.h"
33
34 static void tex_fetch_ptrs(struct lp_build_tgsi_context *bld_base,
35 struct lp_build_emit_data *emit_data,
36 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
37 LLVMValueRef *fmask_ptr);
38
39 /**
40 * Given a v8i32 resource descriptor for a buffer, extract the size of the
41 * buffer in number of elements and return it as an i32.
42 */
43 static LLVMValueRef get_buffer_size(
44 struct lp_build_tgsi_context *bld_base,
45 LLVMValueRef descriptor)
46 {
47 struct si_shader_context *ctx = si_shader_context(bld_base);
48 LLVMBuilderRef builder = ctx->ac.builder;
49 LLVMValueRef size =
50 LLVMBuildExtractElement(builder, descriptor,
51 LLVMConstInt(ctx->i32, 2, 0), "");
52
53 if (ctx->screen->info.chip_class == GFX8) {
54 /* On GFX8, the descriptor contains the size in bytes,
55 * but TXQ must return the size in elements.
56 * The stride is always non-zero for resources using TXQ.
57 */
58 LLVMValueRef stride =
59 LLVMBuildExtractElement(builder, descriptor,
60 ctx->i32_1, "");
61 stride = LLVMBuildLShr(builder, stride,
62 LLVMConstInt(ctx->i32, 16, 0), "");
63 stride = LLVMBuildAnd(builder, stride,
64 LLVMConstInt(ctx->i32, 0x3FFF, 0), "");
65
66 size = LLVMBuildUDiv(builder, size, stride, "");
67 }
68
69 return size;
70 }
71
72 static LLVMValueRef
73 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
74 const struct tgsi_full_src_register *reg,
75 bool ubo)
76 {
77 LLVMValueRef index;
78
79 if (!reg->Register.Indirect) {
80 index = LLVMConstInt(ctx->i32, reg->Register.Index, false);
81 } else {
82 index = si_get_indirect_index(ctx, &reg->Indirect,
83 1, reg->Register.Index);
84 }
85
86 if (ubo)
87 return ctx->abi.load_ubo(&ctx->abi, index);
88 else
89 return ctx->abi.load_ssbo(&ctx->abi, index, false);
90 }
91
92 static enum ac_image_dim
93 ac_texture_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type target)
94 {
95 switch (target) {
96 case TGSI_TEXTURE_1D:
97 case TGSI_TEXTURE_SHADOW1D:
98 if (screen->info.chip_class == GFX9)
99 return ac_image_2d;
100 return ac_image_1d;
101 case TGSI_TEXTURE_2D:
102 case TGSI_TEXTURE_SHADOW2D:
103 case TGSI_TEXTURE_RECT:
104 case TGSI_TEXTURE_SHADOWRECT:
105 return ac_image_2d;
106 case TGSI_TEXTURE_3D:
107 return ac_image_3d;
108 case TGSI_TEXTURE_CUBE:
109 case TGSI_TEXTURE_SHADOWCUBE:
110 case TGSI_TEXTURE_CUBE_ARRAY:
111 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
112 return ac_image_cube;
113 case TGSI_TEXTURE_1D_ARRAY:
114 case TGSI_TEXTURE_SHADOW1D_ARRAY:
115 if (screen->info.chip_class == GFX9)
116 return ac_image_2darray;
117 return ac_image_1darray;
118 case TGSI_TEXTURE_2D_ARRAY:
119 case TGSI_TEXTURE_SHADOW2D_ARRAY:
120 return ac_image_2darray;
121 case TGSI_TEXTURE_2D_MSAA:
122 return ac_image_2dmsaa;
123 case TGSI_TEXTURE_2D_ARRAY_MSAA:
124 return ac_image_2darraymsaa;
125 default:
126 unreachable("unhandled texture type");
127 }
128 }
129
130 static enum ac_image_dim
131 ac_image_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type target)
132 {
133 enum ac_image_dim dim = ac_texture_dim_from_tgsi_target(screen, target);
134
135 /* Match the resource type set in the descriptor. */
136 if (dim == ac_image_cube ||
137 (screen->info.chip_class <= GFX8 && dim == ac_image_3d))
138 dim = ac_image_2darray;
139 else if (target == TGSI_TEXTURE_2D && screen->info.chip_class == GFX9) {
140 /* When a single layer of a 3D texture is bound, the shader
141 * will refer to a 2D target, but the descriptor has a 3D type.
142 * Since the HW ignores BASE_ARRAY in this case, we need to
143 * send 3 coordinates. This doesn't hurt when the underlying
144 * texture is non-3D.
145 */
146 dim = ac_image_3d;
147 }
148
149 return dim;
150 }
151
152 /**
153 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
154 *
155 * At least on Tonga, executing image stores on images with DCC enabled and
156 * non-trivial can eventually lead to lockups. This can occur when an
157 * application binds an image as read-only but then uses a shader that writes
158 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
159 * program termination) in this case, but it doesn't cost much to be a bit
160 * nicer: disabling DCC in the shader still leads to undefined results but
161 * avoids the lockup.
162 */
163 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
164 LLVMValueRef rsrc)
165 {
166 if (ctx->screen->info.chip_class <= GFX7) {
167 return rsrc;
168 } else {
169 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
170 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
171 LLVMValueRef tmp;
172
173 tmp = LLVMBuildExtractElement(ctx->ac.builder, rsrc, i32_6, "");
174 tmp = LLVMBuildAnd(ctx->ac.builder, tmp, i32_C, "");
175 return LLVMBuildInsertElement(ctx->ac.builder, rsrc, tmp, i32_6, "");
176 }
177 }
178
179 /* AC_DESC_FMASK is handled exactly like AC_DESC_IMAGE. The caller should
180 * adjust "index" to point to FMASK. */
181 LLVMValueRef si_load_image_desc(struct si_shader_context *ctx,
182 LLVMValueRef list, LLVMValueRef index,
183 enum ac_descriptor_type desc_type,
184 bool uses_store, bool bindless)
185 {
186 LLVMBuilderRef builder = ctx->ac.builder;
187 LLVMValueRef rsrc;
188
189 if (desc_type == AC_DESC_BUFFER) {
190 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 2, 0),
191 ctx->i32_1);
192 list = LLVMBuildPointerCast(builder, list,
193 ac_array_in_const32_addr_space(ctx->v4i32), "");
194 } else {
195 assert(desc_type == AC_DESC_IMAGE ||
196 desc_type == AC_DESC_FMASK);
197 }
198
199 if (bindless)
200 rsrc = ac_build_load_to_sgpr_uint_wraparound(&ctx->ac, list, index);
201 else
202 rsrc = ac_build_load_to_sgpr(&ctx->ac, list, index);
203
204 if (desc_type == AC_DESC_IMAGE && uses_store)
205 rsrc = force_dcc_off(ctx, rsrc);
206 return rsrc;
207 }
208
209 /**
210 * Load the resource descriptor for \p image.
211 */
212 static void
213 image_fetch_rsrc(
214 struct lp_build_tgsi_context *bld_base,
215 const struct tgsi_full_src_register *image,
216 bool fmask, bool is_store, unsigned target,
217 LLVMValueRef *rsrc)
218 {
219 struct si_shader_context *ctx = si_shader_context(bld_base);
220 bool bindless = image->Register.File != TGSI_FILE_IMAGE;
221 LLVMValueRef rsrc_ptr, index;
222
223 if (bindless) {
224 /* Bindless descriptors are accessible from a different pair of
225 * user SGPR indices.
226 */
227 rsrc_ptr = LLVMGetParam(ctx->main_fn,
228 ctx->param_bindless_samplers_and_images);
229 index = lp_build_emit_fetch_src(bld_base, image, TGSI_TYPE_UNSIGNED, 0);
230
231 /* Bindless image descriptors use 16-dword slots. */
232 index = LLVMBuildMul(ctx->ac.builder, index,
233 LLVMConstInt(ctx->i32, 2, 0), "");
234 /* FMASK is right after the image. */
235 if (fmask)
236 index = LLVMBuildAdd(ctx->ac.builder, index, ctx->i32_1, "");
237 } else {
238 rsrc_ptr = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
239
240 if (!image->Register.Indirect) {
241 index = LLVMConstInt(ctx->i32, image->Register.Index, 0);
242 } else {
243 /* From the GL_ARB_shader_image_load_store extension spec:
244 *
245 * If a shader performs an image load, store, or atomic
246 * operation using an image variable declared as an array,
247 * and if the index used to select an individual element is
248 * negative or greater than or equal to the size of the
249 * array, the results of the operation are undefined but may
250 * not lead to termination.
251 */
252 index = si_get_bounded_indirect_index(ctx, &image->Indirect,
253 image->Register.Index,
254 ctx->num_images);
255 }
256 /* FMASKs are separate from images. */
257 if (fmask) {
258 index = LLVMBuildAdd(ctx->ac.builder, index,
259 LLVMConstInt(ctx->i32, SI_NUM_IMAGES, 0), "");
260 }
261 index = LLVMBuildSub(ctx->ac.builder,
262 LLVMConstInt(ctx->i32, SI_NUM_IMAGE_SLOTS - 1, 0),
263 index, "");
264 }
265
266 *rsrc = si_load_image_desc(ctx, rsrc_ptr, index,
267 fmask ? AC_DESC_FMASK :
268 target == TGSI_TEXTURE_BUFFER ? AC_DESC_BUFFER : AC_DESC_IMAGE,
269 is_store, bindless);
270 }
271
272 static void image_fetch_coords(
273 struct lp_build_tgsi_context *bld_base,
274 const struct tgsi_full_instruction *inst,
275 unsigned src, LLVMValueRef desc,
276 LLVMValueRef *coords)
277 {
278 struct si_shader_context *ctx = si_shader_context(bld_base);
279 LLVMBuilderRef builder = ctx->ac.builder;
280 unsigned target = inst->Memory.Texture;
281 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
282 LLVMValueRef tmp;
283 int chan;
284
285 for (chan = 0; chan < num_coords; ++chan) {
286 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
287 tmp = ac_to_integer(&ctx->ac, tmp);
288 coords[chan] = tmp;
289 }
290
291 if (target == TGSI_TEXTURE_2D_MSAA ||
292 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
293 /* Need the sample index as well. */
294 tmp = lp_build_emit_fetch(bld_base, inst, src, TGSI_SWIZZLE_W);
295 coords[chan] = ac_to_integer(&ctx->ac, tmp);
296 }
297
298 if (ctx->screen->info.chip_class == GFX9) {
299 /* 1D textures are allocated and used as 2D on GFX9. */
300 if (target == TGSI_TEXTURE_1D) {
301 coords[1] = ctx->i32_0;
302 } else if (target == TGSI_TEXTURE_1D_ARRAY) {
303 coords[2] = coords[1];
304 coords[1] = ctx->i32_0;
305 } else if (target == TGSI_TEXTURE_2D) {
306 /* The hw can't bind a slice of a 3D image as a 2D
307 * image, because it ignores BASE_ARRAY if the target
308 * is 3D. The workaround is to read BASE_ARRAY and set
309 * it as the 3rd address operand for all 2D images.
310 */
311 LLVMValueRef first_layer, const5, mask;
312
313 const5 = LLVMConstInt(ctx->i32, 5, 0);
314 mask = LLVMConstInt(ctx->i32, S_008F24_BASE_ARRAY(~0), 0);
315 first_layer = LLVMBuildExtractElement(builder, desc, const5, "");
316 first_layer = LLVMBuildAnd(builder, first_layer, mask, "");
317
318 coords[2] = first_layer;
319 }
320 }
321 }
322
323 static unsigned get_cache_policy(struct si_shader_context *ctx,
324 const struct tgsi_full_instruction *inst,
325 bool atomic, bool may_store_unaligned,
326 bool writeonly_memory)
327 {
328 unsigned cache_policy = 0;
329
330 if (!atomic &&
331 /* GFX6 has a TC L1 bug causing corruption of 8bit/16bit stores.
332 * All store opcodes not aligned to a dword are affected.
333 * The only way to get unaligned stores in radeonsi is through
334 * shader images. */
335 ((may_store_unaligned && ctx->screen->info.chip_class == GFX6) ||
336 /* If this is write-only, don't keep data in L1 to prevent
337 * evicting L1 cache lines that may be needed by other
338 * instructions. */
339 writeonly_memory ||
340 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE))) {
341 cache_policy |= ac_glc;
342 }
343
344 if (inst->Memory.Qualifier & TGSI_MEMORY_STREAM_CACHE_POLICY)
345 cache_policy |= ac_slc;
346
347 return cache_policy;
348 }
349
350 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
351 const struct tgsi_full_instruction *inst,
352 LLVMTypeRef type, int arg)
353 {
354 LLVMBuilderRef builder = ctx->ac.builder;
355 LLVMValueRef offset, ptr;
356 int addr_space;
357
358 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
359 offset = ac_to_integer(&ctx->ac, offset);
360
361 ptr = ctx->ac.lds;
362 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
363 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
364 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
365
366 return ptr;
367 }
368
369 static void load_emit_memory(
370 struct si_shader_context *ctx,
371 struct lp_build_emit_data *emit_data)
372 {
373 const struct tgsi_full_instruction *inst = emit_data->inst;
374 unsigned writemask = inst->Dst[0].Register.WriteMask;
375 LLVMValueRef channels[4], ptr, derived_ptr, index;
376 int chan;
377
378 ptr = get_memory_ptr(ctx, inst, ctx->f32, 1);
379
380 for (chan = 0; chan < 4; ++chan) {
381 if (!(writemask & (1 << chan))) {
382 channels[chan] = LLVMGetUndef(ctx->f32);
383 continue;
384 }
385
386 index = LLVMConstInt(ctx->i32, chan, 0);
387 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
388 channels[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
389 }
390 emit_data->output[emit_data->chan] = ac_build_gather_values(&ctx->ac, channels, 4);
391 }
392
393 /**
394 * Return true if the memory accessed by a LOAD or STORE instruction is
395 * read-only or write-only, respectively.
396 *
397 * \param shader_buffers_reverse_access_mask
398 * For LOAD, set this to (store | atomic) slot usage in the shader.
399 * For STORE, set this to (load | atomic) slot usage in the shader.
400 * \param images_reverse_access_mask Same as above, but for images.
401 * \param bindless_buffer_reverse_access_mask Same as above, but for bindless image buffers.
402 * \param bindless_image_reverse_access_mask Same as above, but for bindless images.
403 */
404 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
405 const struct tgsi_shader_info *info,
406 unsigned shader_buffers_reverse_access_mask,
407 unsigned images_reverse_access_mask,
408 bool bindless_buffer_reverse_access_mask,
409 bool bindless_image_reverse_access_mask)
410 {
411 enum tgsi_file_type resource_file;
412 unsigned resource_index;
413 bool resource_indirect;
414
415 if (inst->Instruction.Opcode == TGSI_OPCODE_STORE) {
416 resource_file = inst->Dst[0].Register.File;
417 resource_index = inst->Dst[0].Register.Index;
418 resource_indirect = inst->Dst[0].Register.Indirect;
419 } else {
420 resource_file = inst->Src[0].Register.File;
421 resource_index = inst->Src[0].Register.Index;
422 resource_indirect = inst->Src[0].Register.Indirect;
423 }
424
425 assert(resource_file == TGSI_FILE_BUFFER ||
426 resource_file == TGSI_FILE_IMAGE ||
427 /* bindless image */
428 resource_file == TGSI_FILE_INPUT ||
429 resource_file == TGSI_FILE_OUTPUT ||
430 resource_file == TGSI_FILE_CONSTANT ||
431 resource_file == TGSI_FILE_TEMPORARY ||
432 resource_file == TGSI_FILE_IMMEDIATE);
433
434 assert(resource_file != TGSI_FILE_BUFFER ||
435 inst->Memory.Texture == TGSI_TEXTURE_BUFFER);
436
437 bool bindless = resource_file != TGSI_FILE_BUFFER &&
438 resource_file != TGSI_FILE_IMAGE;
439
440 /* RESTRICT means NOALIAS.
441 * If there are no writes, we can assume the accessed memory is read-only.
442 * If there are no reads, we can assume the accessed memory is write-only.
443 */
444 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT && !bindless) {
445 unsigned reverse_access_mask;
446
447 if (resource_file == TGSI_FILE_BUFFER) {
448 reverse_access_mask = shader_buffers_reverse_access_mask;
449 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
450 reverse_access_mask = info->images_buffers &
451 images_reverse_access_mask;
452 } else {
453 reverse_access_mask = ~info->images_buffers &
454 images_reverse_access_mask;
455 }
456
457 if (resource_indirect) {
458 if (!reverse_access_mask)
459 return true;
460 } else {
461 if (!(reverse_access_mask &
462 (1u << resource_index)))
463 return true;
464 }
465 }
466
467 /* If there are no buffer writes (for both shader buffers & image
468 * buffers), it implies that buffer memory is read-only.
469 * If there are no buffer reads (for both shader buffers & image
470 * buffers), it implies that buffer memory is write-only.
471 *
472 * Same for the case when there are no writes/reads for non-buffer
473 * images.
474 */
475 if (resource_file == TGSI_FILE_BUFFER ||
476 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
477 if (!shader_buffers_reverse_access_mask &&
478 !(info->images_buffers & images_reverse_access_mask) &&
479 !bindless_buffer_reverse_access_mask)
480 return true;
481 } else {
482 if (!(~info->images_buffers & images_reverse_access_mask) &&
483 !bindless_image_reverse_access_mask)
484 return true;
485 }
486 return false;
487 }
488
489 static void load_emit(
490 const struct lp_build_tgsi_action *action,
491 struct lp_build_tgsi_context *bld_base,
492 struct lp_build_emit_data *emit_data)
493 {
494 struct si_shader_context *ctx = si_shader_context(bld_base);
495 const struct tgsi_full_instruction * inst = emit_data->inst;
496 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
497 bool can_speculate = false;
498 LLVMValueRef vindex = ctx->i32_0;
499 LLVMValueRef voffset = ctx->i32_0;
500 struct ac_image_args args = {};
501
502 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
503 load_emit_memory(ctx, emit_data);
504 return;
505 }
506
507 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
508 inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
509 bool ubo = inst->Src[0].Register.File == TGSI_FILE_CONSTBUF;
510 args.resource = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], ubo);
511 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 1, 0));
512 } else {
513 unsigned target = inst->Memory.Texture;
514
515 image_fetch_rsrc(bld_base, &inst->Src[0], false, false, target, &args.resource);
516 image_fetch_coords(bld_base, inst, 1, args.resource, args.coords);
517
518 if ((inst->Memory.Texture == TGSI_TEXTURE_2D_MSAA ||
519 inst->Memory.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA) &&
520 !(ctx->screen->debug_flags & DBG(NO_FMASK))) {
521 LLVMValueRef fmask;
522
523 image_fetch_rsrc(bld_base, &inst->Src[0], true, false, target, &fmask);
524 ac_apply_fmask_to_sample(&ctx->ac, fmask, args.coords,
525 inst->Memory.Texture == TGSI_TEXTURE_2D_ARRAY_MSAA);
526 }
527 vindex = args.coords[0]; /* for buffers only */
528 }
529
530 if (inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
531 emit_data->output[emit_data->chan] =
532 ac_build_buffer_load(&ctx->ac, args.resource,
533 util_last_bit(inst->Dst[0].Register.WriteMask),
534 NULL, voffset, NULL, 0, 0, true, true);
535 return;
536 }
537
538 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
539 ac_build_waitcnt(&ctx->ac, AC_WAIT_VLOAD | AC_WAIT_VSTORE);
540
541 can_speculate = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
542 is_oneway_access_only(inst, info,
543 info->shader_buffers_store |
544 info->shader_buffers_atomic,
545 info->images_store |
546 info->images_atomic,
547 info->uses_bindless_buffer_store |
548 info->uses_bindless_buffer_atomic,
549 info->uses_bindless_image_store |
550 info->uses_bindless_image_atomic);
551 args.cache_policy = get_cache_policy(ctx, inst, false, false, false);
552
553 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
554 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
555 * select SMEM for SI.load.const with a non-constant offset, and
556 * constant offsets practically don't exist with shader buffers.
557 *
558 * Also, SI.load.const doesn't use inst_offset when it's lowered
559 * to VMEM, so we just end up with more VALU instructions in the end
560 * and no benefit.
561 *
562 * TODO: Remove this line once LLVM can select SMEM with a non-constant
563 * offset, and can derive inst_offset when VMEM is selected.
564 * After that, si_memory_barrier should invalidate sL1 for shader
565 * buffers.
566 */
567 emit_data->output[emit_data->chan] =
568 ac_build_buffer_load(&ctx->ac, args.resource,
569 util_last_bit(inst->Dst[0].Register.WriteMask),
570 NULL, voffset, NULL, 0,
571 args.cache_policy, can_speculate, false);
572 return;
573 }
574
575 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
576 unsigned num_channels = util_last_bit(inst->Dst[0].Register.WriteMask);
577 LLVMValueRef result =
578 ac_build_buffer_load_format(&ctx->ac,
579 args.resource,
580 vindex,
581 ctx->i32_0,
582 num_channels,
583 args.cache_policy,
584 can_speculate);
585 emit_data->output[emit_data->chan] =
586 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
587 } else {
588 args.opcode = ac_image_load;
589 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
590 args.attributes = ac_get_load_intr_attribs(can_speculate);
591 args.dmask = 0xf;
592
593 emit_data->output[emit_data->chan] =
594 ac_build_image_opcode(&ctx->ac, &args);
595 }
596 }
597
598 static void store_emit_buffer(struct si_shader_context *ctx,
599 LLVMValueRef resource,
600 unsigned writemask,
601 LLVMValueRef value,
602 LLVMValueRef voffset,
603 unsigned cache_policy,
604 bool writeonly_memory)
605 {
606 LLVMBuilderRef builder = ctx->ac.builder;
607 LLVMValueRef base_data = value;
608 LLVMValueRef base_offset = voffset;
609
610 while (writemask) {
611 int start, count;
612 LLVMValueRef data, voff;
613
614 u_bit_scan_consecutive_range(&writemask, &start, &count);
615
616 if (count == 3 && ac_has_vec3_support(ctx->ac.chip_class, false)) {
617 LLVMValueRef values[3] = {
618 LLVMBuildExtractElement(builder, base_data,
619 LLVMConstInt(ctx->i32, start, 0), ""),
620 LLVMBuildExtractElement(builder, base_data,
621 LLVMConstInt(ctx->i32, start + 1, 0), ""),
622 LLVMBuildExtractElement(builder, base_data,
623 LLVMConstInt(ctx->i32, start + 2, 0), ""),
624 };
625 data = ac_build_gather_values(&ctx->ac, values, 3);
626 } else if (count >= 3) {
627 data = base_data;
628 } else if (count == 2) {
629 LLVMValueRef values[2] = {
630 LLVMBuildExtractElement(builder, base_data,
631 LLVMConstInt(ctx->i32, start, 0), ""),
632 LLVMBuildExtractElement(builder, base_data,
633 LLVMConstInt(ctx->i32, start + 1, 0), ""),
634 };
635
636 data = ac_build_gather_values(&ctx->ac, values, 2);
637 } else {
638 assert(count == 1);
639 data = LLVMBuildExtractElement(
640 builder, base_data,
641 LLVMConstInt(ctx->i32, start, 0), "");
642 }
643
644 voff = base_offset;
645 if (start != 0) {
646 voff = LLVMBuildAdd(
647 builder, voff,
648 LLVMConstInt(ctx->i32, start * 4, 0), "");
649 }
650
651 ac_build_buffer_store_dword(&ctx->ac, resource, data, count,
652 voff, ctx->i32_0, 0, cache_policy,
653 false);
654 }
655 }
656
657 static void store_emit_memory(
658 struct si_shader_context *ctx,
659 struct lp_build_emit_data *emit_data)
660 {
661 const struct tgsi_full_instruction *inst = emit_data->inst;
662 LLVMBuilderRef builder = ctx->ac.builder;
663 unsigned writemask = inst->Dst[0].Register.WriteMask;
664 LLVMValueRef ptr, derived_ptr, data, index;
665 int chan;
666
667 ptr = get_memory_ptr(ctx, inst, ctx->f32, 0);
668
669 for (chan = 0; chan < 4; ++chan) {
670 if (!(writemask & (1 << chan))) {
671 continue;
672 }
673 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
674 index = LLVMConstInt(ctx->i32, chan, 0);
675 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
676 LLVMBuildStore(builder, data, derived_ptr);
677 }
678 }
679
680 static void store_emit(
681 const struct lp_build_tgsi_action *action,
682 struct lp_build_tgsi_context *bld_base,
683 struct lp_build_emit_data *emit_data)
684 {
685 struct si_shader_context *ctx = si_shader_context(bld_base);
686 const struct tgsi_full_instruction * inst = emit_data->inst;
687 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
688 struct tgsi_full_src_register resource_reg =
689 tgsi_full_src_register_from_dst(&inst->Dst[0]);
690 unsigned target = inst->Memory.Texture;
691
692 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
693 store_emit_memory(ctx, emit_data);
694 return;
695 }
696
697 bool writeonly_memory = is_oneway_access_only(inst, info,
698 info->shader_buffers_load |
699 info->shader_buffers_atomic,
700 info->images_load |
701 info->images_atomic,
702 info->uses_bindless_buffer_load |
703 info->uses_bindless_buffer_atomic,
704 info->uses_bindless_image_load |
705 info->uses_bindless_image_atomic);
706 LLVMValueRef chans[4];
707 LLVMValueRef vindex = ctx->i32_0;
708 LLVMValueRef voffset = ctx->i32_0;
709 struct ac_image_args args = {};
710
711 for (unsigned chan = 0; chan < 4; ++chan)
712 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
713
714 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
715 args.resource = shader_buffer_fetch_rsrc(ctx, &resource_reg, false);
716 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 0, 0));
717 } else {
718 image_fetch_rsrc(bld_base, &resource_reg, false, true, target, &args.resource);
719 image_fetch_coords(bld_base, inst, 0, args.resource, args.coords);
720 vindex = args.coords[0]; /* for buffers only */
721 }
722
723 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
724 ac_build_waitcnt(&ctx->ac, AC_WAIT_VLOAD | AC_WAIT_VSTORE);
725
726 bool is_image = inst->Dst[0].Register.File != TGSI_FILE_BUFFER;
727 args.cache_policy = get_cache_policy(ctx, inst,
728 false, /* atomic */
729 is_image, /* may_store_unaligned */
730 writeonly_memory);
731
732 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
733 store_emit_buffer(ctx, args.resource, inst->Dst[0].Register.WriteMask,
734 ac_build_gather_values(&ctx->ac, chans, 4),
735 voffset, args.cache_policy, writeonly_memory);
736 return;
737 }
738
739 if (target == TGSI_TEXTURE_BUFFER) {
740 unsigned num_channels = util_last_bit(inst->Dst[0].Register.WriteMask);
741
742 ac_build_buffer_store_format(&ctx->ac, args.resource,
743 ac_build_gather_values(&ctx->ac, chans, num_channels),
744 vindex, ctx->i32_0 /* voffset */,
745 num_channels,
746 args.cache_policy);
747 } else {
748 args.opcode = ac_image_store;
749 args.data[0] = ac_build_gather_values(&ctx->ac, chans, 4);
750 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
751 args.attributes = AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY;
752 args.dmask = 0xf;
753
754 emit_data->output[emit_data->chan] =
755 ac_build_image_opcode(&ctx->ac, &args);
756 }
757 }
758
759 static void atomic_emit_memory(struct si_shader_context *ctx,
760 struct lp_build_emit_data *emit_data) {
761 LLVMBuilderRef builder = ctx->ac.builder;
762 const struct tgsi_full_instruction * inst = emit_data->inst;
763 LLVMValueRef ptr, result, arg;
764 const char *sync_scope = LLVM_VERSION_MAJOR >= 9 ? "workgroup-one-as" : "workgroup";
765
766 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
767
768 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
769 arg = ac_to_integer(&ctx->ac, arg);
770
771 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
772 LLVMValueRef new_data;
773 new_data = lp_build_emit_fetch(&ctx->bld_base,
774 inst, 3, 0);
775
776 new_data = ac_to_integer(&ctx->ac, new_data);
777
778 result = ac_build_atomic_cmp_xchg(&ctx->ac, ptr, arg, new_data,
779 sync_scope);
780 result = LLVMBuildExtractValue(builder, result, 0, "");
781 } else {
782 LLVMAtomicRMWBinOp op;
783
784 switch(inst->Instruction.Opcode) {
785 case TGSI_OPCODE_ATOMUADD:
786 op = LLVMAtomicRMWBinOpAdd;
787 break;
788 case TGSI_OPCODE_ATOMXCHG:
789 op = LLVMAtomicRMWBinOpXchg;
790 break;
791 case TGSI_OPCODE_ATOMAND:
792 op = LLVMAtomicRMWBinOpAnd;
793 break;
794 case TGSI_OPCODE_ATOMOR:
795 op = LLVMAtomicRMWBinOpOr;
796 break;
797 case TGSI_OPCODE_ATOMXOR:
798 op = LLVMAtomicRMWBinOpXor;
799 break;
800 case TGSI_OPCODE_ATOMUMIN:
801 op = LLVMAtomicRMWBinOpUMin;
802 break;
803 case TGSI_OPCODE_ATOMUMAX:
804 op = LLVMAtomicRMWBinOpUMax;
805 break;
806 case TGSI_OPCODE_ATOMIMIN:
807 op = LLVMAtomicRMWBinOpMin;
808 break;
809 case TGSI_OPCODE_ATOMIMAX:
810 op = LLVMAtomicRMWBinOpMax;
811 break;
812 default:
813 unreachable("unknown atomic opcode");
814 }
815
816 result = ac_build_atomic_rmw(&ctx->ac, op, ptr, arg, sync_scope);
817 }
818 emit_data->output[emit_data->chan] =
819 LLVMBuildBitCast(builder, result, ctx->f32, "");
820 }
821
822 static void atomic_emit(
823 const struct lp_build_tgsi_action *action,
824 struct lp_build_tgsi_context *bld_base,
825 struct lp_build_emit_data *emit_data)
826 {
827 struct si_shader_context *ctx = si_shader_context(bld_base);
828 const struct tgsi_full_instruction * inst = emit_data->inst;
829 struct ac_image_args args = {};
830 unsigned num_data = 0;
831 LLVMValueRef vindex = ctx->i32_0;
832 LLVMValueRef voffset = ctx->i32_0;
833
834 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
835 atomic_emit_memory(ctx, emit_data);
836 return;
837 }
838
839 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
840 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
841 * of arguments, which is reversed relative to TGSI (and GLSL)
842 */
843 args.data[num_data++] =
844 ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 3, 0));
845 }
846
847 args.data[num_data++] =
848 ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 2, 0));
849
850 args.cache_policy = get_cache_policy(ctx, inst, true, false, false);
851
852 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
853 args.resource = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], false);
854 voffset = ac_to_integer(&ctx->ac, lp_build_emit_fetch(bld_base, inst, 1, 0));
855 } else {
856 image_fetch_rsrc(bld_base, &inst->Src[0], false, true,
857 inst->Memory.Texture, &args.resource);
858 image_fetch_coords(bld_base, inst, 1, args.resource, args.coords);
859 vindex = args.coords[0]; /* for buffers only */
860 }
861
862 if (inst->Src[0].Register.File != TGSI_FILE_BUFFER &&
863 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
864 LLVMValueRef buf_args[7];
865 unsigned num_args = 0;
866
867 buf_args[num_args++] = args.data[0];
868 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
869 buf_args[num_args++] = args.data[1];
870
871 buf_args[num_args++] = args.resource;
872 buf_args[num_args++] = vindex;
873 buf_args[num_args++] = voffset;
874 buf_args[num_args++] = ctx->i32_0; /* soffset */
875 buf_args[num_args++] = LLVMConstInt(ctx->i32, args.cache_policy & ac_slc, 0);
876
877 char intrinsic_name[64];
878 snprintf(intrinsic_name, sizeof(intrinsic_name),
879 "llvm.amdgcn.struct.buffer.atomic.%s", action->intr_name);
880 emit_data->output[emit_data->chan] =
881 ac_to_float(&ctx->ac,
882 ac_build_intrinsic(&ctx->ac, intrinsic_name,
883 ctx->i32, buf_args, num_args, 0));
884 return;
885 }
886
887 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
888 LLVMValueRef buf_args[7];
889 unsigned num_args = 0;
890
891 buf_args[num_args++] = args.data[0];
892 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
893 buf_args[num_args++] = args.data[1];
894
895 buf_args[num_args++] = args.resource;
896 buf_args[num_args++] = vindex;
897 buf_args[num_args++] = voffset;
898 buf_args[num_args++] = args.cache_policy & ac_slc ? ctx->i1true : ctx->i1false;
899
900 char intrinsic_name[40];
901 snprintf(intrinsic_name, sizeof(intrinsic_name),
902 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
903 emit_data->output[emit_data->chan] =
904 ac_to_float(&ctx->ac,
905 ac_build_intrinsic(&ctx->ac, intrinsic_name,
906 ctx->i32, buf_args, num_args, 0));
907 } else {
908 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
909 args.opcode = ac_image_atomic_cmpswap;
910 } else {
911 args.opcode = ac_image_atomic;
912 switch (inst->Instruction.Opcode) {
913 case TGSI_OPCODE_ATOMXCHG: args.atomic = ac_atomic_swap; break;
914 case TGSI_OPCODE_ATOMUADD: args.atomic = ac_atomic_add; break;
915 case TGSI_OPCODE_ATOMAND: args.atomic = ac_atomic_and; break;
916 case TGSI_OPCODE_ATOMOR: args.atomic = ac_atomic_or; break;
917 case TGSI_OPCODE_ATOMXOR: args.atomic = ac_atomic_xor; break;
918 case TGSI_OPCODE_ATOMUMIN: args.atomic = ac_atomic_umin; break;
919 case TGSI_OPCODE_ATOMUMAX: args.atomic = ac_atomic_umax; break;
920 case TGSI_OPCODE_ATOMIMIN: args.atomic = ac_atomic_smin; break;
921 case TGSI_OPCODE_ATOMIMAX: args.atomic = ac_atomic_smax; break;
922 case TGSI_OPCODE_ATOMINC_WRAP:
923 args.atomic = ac_atomic_inc_wrap;
924 break;
925 case TGSI_OPCODE_ATOMDEC_WRAP:
926 args.atomic = ac_atomic_dec_wrap;
927 break;
928 default: unreachable("unhandled image atomic");
929 }
930 }
931
932 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
933 emit_data->output[emit_data->chan] =
934 ac_to_float(&ctx->ac, ac_build_image_opcode(&ctx->ac, &args));
935 }
936 }
937
938 static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
939 unsigned target, LLVMValueRef out)
940 {
941 LLVMBuilderRef builder = ctx->ac.builder;
942
943 /* 1D textures are allocated and used as 2D on GFX9. */
944 if (ctx->screen->info.chip_class == GFX9 &&
945 (target == TGSI_TEXTURE_1D_ARRAY ||
946 target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
947 LLVMValueRef layers =
948 LLVMBuildExtractElement(builder, out,
949 LLVMConstInt(ctx->i32, 2, 0), "");
950 out = LLVMBuildInsertElement(builder, out, layers,
951 ctx->i32_1, "");
952 }
953
954 /* Divide the number of layers by 6 to get the number of cubes. */
955 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
956 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
957 LLVMValueRef imm2 = LLVMConstInt(ctx->i32, 2, 0);
958
959 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
960 z = LLVMBuildSDiv(builder, z, LLVMConstInt(ctx->i32, 6, 0), "");
961
962 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
963 }
964 return out;
965 }
966
967 static void resq_emit(
968 const struct lp_build_tgsi_action *action,
969 struct lp_build_tgsi_context *bld_base,
970 struct lp_build_emit_data *emit_data)
971 {
972 struct si_shader_context *ctx = si_shader_context(bld_base);
973 LLVMBuilderRef builder = ctx->ac.builder;
974 const struct tgsi_full_instruction *inst = emit_data->inst;
975 const struct tgsi_full_src_register *reg =
976 &inst->Src[inst->Instruction.Opcode == TGSI_OPCODE_TXQ ? 1 : 0];
977
978 if (reg->Register.File == TGSI_FILE_BUFFER) {
979 LLVMValueRef rsrc = shader_buffer_fetch_rsrc(ctx, reg, false);
980
981 emit_data->output[emit_data->chan] =
982 LLVMBuildExtractElement(builder, rsrc,
983 LLVMConstInt(ctx->i32, 2, 0), "");
984 return;
985 }
986
987 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
988 inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
989 LLVMValueRef rsrc;
990
991 tex_fetch_ptrs(bld_base, emit_data, &rsrc, NULL, NULL);
992 /* Read the size from the buffer descriptor directly. */
993 emit_data->output[emit_data->chan] =
994 get_buffer_size(bld_base, rsrc);
995 return;
996 }
997
998 if (inst->Instruction.Opcode == TGSI_OPCODE_RESQ &&
999 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
1000 LLVMValueRef rsrc;
1001
1002 image_fetch_rsrc(bld_base, reg, false, false, inst->Memory.Texture, &rsrc);
1003 emit_data->output[emit_data->chan] =
1004 get_buffer_size(bld_base, rsrc);
1005 return;
1006 }
1007
1008 unsigned target;
1009
1010 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
1011 target = inst->Texture.Texture;
1012 } else {
1013 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
1014 target = TGSI_TEXTURE_2D_ARRAY;
1015 else
1016 target = inst->Memory.Texture;
1017 }
1018
1019 struct ac_image_args args = {};
1020 args.opcode = ac_image_get_resinfo;
1021 args.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1022 args.dmask = 0xf;
1023 args.attributes = AC_FUNC_ATTR_READNONE;
1024
1025 if (inst->Instruction.Opcode == TGSI_OPCODE_TXQ) {
1026 tex_fetch_ptrs(bld_base, emit_data, &args.resource, NULL, NULL);
1027 args.lod = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1028 } else {
1029 image_fetch_rsrc(bld_base, reg, false, false, target, &args.resource);
1030 args.lod = ctx->i32_0;
1031 }
1032
1033 emit_data->output[emit_data->chan] =
1034 fix_resinfo(ctx, target, ac_build_image_opcode(&ctx->ac, &args));
1035
1036 if (inst->Instruction.Opcode == TGSI_OPCODE_RESQ &&
1037 (target == TGSI_TEXTURE_2D_MSAA ||
1038 target == TGSI_TEXTURE_2D_ARRAY_MSAA)) {
1039 LLVMValueRef samples =
1040 ac_build_image_get_sample_count(&ctx->ac, args.resource);
1041
1042 emit_data->output[emit_data->chan] =
1043 LLVMBuildInsertElement(ctx->ac.builder,
1044 emit_data->output[emit_data->chan],
1045 samples,
1046 LLVMConstInt(ctx->i32, 3, 0), "");
1047 }
1048 }
1049
1050 /**
1051 * Load an image view, fmask view. or sampler state descriptor.
1052 */
1053 LLVMValueRef si_load_sampler_desc(struct si_shader_context *ctx,
1054 LLVMValueRef list, LLVMValueRef index,
1055 enum ac_descriptor_type type)
1056 {
1057 LLVMBuilderRef builder = ctx->ac.builder;
1058
1059 switch (type) {
1060 case AC_DESC_IMAGE:
1061 /* The image is at [0:7]. */
1062 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1063 break;
1064 case AC_DESC_BUFFER:
1065 /* The buffer is in [4:7]. */
1066 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 4, 0),
1067 ctx->i32_1);
1068 list = LLVMBuildPointerCast(builder, list,
1069 ac_array_in_const32_addr_space(ctx->v4i32), "");
1070 break;
1071 case AC_DESC_FMASK:
1072 /* The FMASK is at [8:15]. */
1073 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 2, 0),
1074 ctx->i32_1);
1075 break;
1076 case AC_DESC_SAMPLER:
1077 /* The sampler state is at [12:15]. */
1078 index = ac_build_imad(&ctx->ac, index, LLVMConstInt(ctx->i32, 4, 0),
1079 LLVMConstInt(ctx->i32, 3, 0));
1080 list = LLVMBuildPointerCast(builder, list,
1081 ac_array_in_const32_addr_space(ctx->v4i32), "");
1082 break;
1083 case AC_DESC_PLANE_0:
1084 case AC_DESC_PLANE_1:
1085 case AC_DESC_PLANE_2:
1086 /* Only used for the multiplane image support for Vulkan. Should
1087 * never be reached in radeonsi.
1088 */
1089 unreachable("Plane descriptor requested in radeonsi.");
1090 }
1091
1092 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1093 }
1094
1095 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1096 *
1097 * GFX6-GFX7:
1098 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1099 * filtering manually. The driver sets img7 to a mask clearing
1100 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1101 * s_and_b32 samp0, samp0, img7
1102 *
1103 * GFX8:
1104 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1105 */
1106 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
1107 LLVMValueRef res, LLVMValueRef samp)
1108 {
1109 LLVMValueRef img7, samp0;
1110
1111 if (ctx->screen->info.chip_class >= GFX8)
1112 return samp;
1113
1114 img7 = LLVMBuildExtractElement(ctx->ac.builder, res,
1115 LLVMConstInt(ctx->i32, 7, 0), "");
1116 samp0 = LLVMBuildExtractElement(ctx->ac.builder, samp,
1117 ctx->i32_0, "");
1118 samp0 = LLVMBuildAnd(ctx->ac.builder, samp0, img7, "");
1119 return LLVMBuildInsertElement(ctx->ac.builder, samp, samp0,
1120 ctx->i32_0, "");
1121 }
1122
1123 static void tex_fetch_ptrs(struct lp_build_tgsi_context *bld_base,
1124 struct lp_build_emit_data *emit_data,
1125 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr,
1126 LLVMValueRef *fmask_ptr)
1127 {
1128 struct si_shader_context *ctx = si_shader_context(bld_base);
1129 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1130 const struct tgsi_full_instruction *inst = emit_data->inst;
1131 const struct tgsi_full_src_register *reg;
1132 unsigned target = inst->Texture.Texture;
1133 unsigned sampler_src;
1134 LLVMValueRef index;
1135
1136 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1137 reg = &emit_data->inst->Src[sampler_src];
1138
1139 if (reg->Register.Indirect) {
1140 index = si_get_bounded_indirect_index(ctx,
1141 &reg->Indirect,
1142 reg->Register.Index,
1143 ctx->num_samplers);
1144 index = LLVMBuildAdd(ctx->ac.builder, index,
1145 LLVMConstInt(ctx->i32, SI_NUM_IMAGE_SLOTS / 2, 0), "");
1146 } else {
1147 index = LLVMConstInt(ctx->i32,
1148 si_get_sampler_slot(reg->Register.Index), 0);
1149 }
1150
1151 if (reg->Register.File != TGSI_FILE_SAMPLER) {
1152 /* Bindless descriptors are accessible from a different pair of
1153 * user SGPR indices.
1154 */
1155 list = LLVMGetParam(ctx->main_fn,
1156 ctx->param_bindless_samplers_and_images);
1157 index = lp_build_emit_fetch_src(bld_base, reg,
1158 TGSI_TYPE_UNSIGNED, 0);
1159
1160 /* Since bindless handle arithmetic can contain an unsigned integer
1161 * wraparound and si_load_sampler_desc assumes there isn't any,
1162 * use GEP without "inbounds" (inside ac_build_pointer_add)
1163 * to prevent incorrect code generation and hangs.
1164 */
1165 index = LLVMBuildMul(ctx->ac.builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1166 list = ac_build_pointer_add(&ctx->ac, list, index);
1167 index = ctx->i32_0;
1168 }
1169
1170 if (target == TGSI_TEXTURE_BUFFER)
1171 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_BUFFER);
1172 else
1173 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_IMAGE);
1174
1175 if (samp_ptr)
1176 *samp_ptr = NULL;
1177 if (fmask_ptr)
1178 *fmask_ptr = NULL;
1179
1180 if (target == TGSI_TEXTURE_2D_MSAA ||
1181 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1182 if (fmask_ptr)
1183 *fmask_ptr = si_load_sampler_desc(ctx, list, index,
1184 AC_DESC_FMASK);
1185 } else if (target != TGSI_TEXTURE_BUFFER) {
1186 if (samp_ptr) {
1187 *samp_ptr = si_load_sampler_desc(ctx, list, index,
1188 AC_DESC_SAMPLER);
1189 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
1190 }
1191 }
1192 }
1193
1194 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1195 * incorrectly forces nearest filtering if the texture format is integer.
1196 * The only effect it has on Gather4, which always returns 4 texels for
1197 * bilinear filtering, is that the final coordinates are off by 0.5 of
1198 * the texel size.
1199 *
1200 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1201 * or (0.5 / size) from the normalized coordinates.
1202 *
1203 * However, cube textures with 8_8_8_8 data formats require a different
1204 * workaround of overriding the num format to USCALED/SSCALED. This would lose
1205 * precision in 32-bit data formats, so it needs to be applied dynamically at
1206 * runtime. In this case, return an i1 value that indicates whether the
1207 * descriptor was overridden (and hence a fixup of the sampler result is needed).
1208 */
1209 static LLVMValueRef
1210 si_lower_gather4_integer(struct si_shader_context *ctx,
1211 struct ac_image_args *args,
1212 unsigned target,
1213 enum tgsi_return_type return_type)
1214 {
1215 LLVMBuilderRef builder = ctx->ac.builder;
1216 LLVMValueRef wa_8888 = NULL;
1217 LLVMValueRef half_texel[2];
1218
1219 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1220 return_type == TGSI_RETURN_TYPE_UINT);
1221
1222 if (target == TGSI_TEXTURE_CUBE ||
1223 target == TGSI_TEXTURE_CUBE_ARRAY) {
1224 LLVMValueRef formats;
1225 LLVMValueRef data_format;
1226 LLVMValueRef wa_formats;
1227
1228 formats = LLVMBuildExtractElement(builder, args->resource, ctx->i32_1, "");
1229
1230 data_format = LLVMBuildLShr(builder, formats,
1231 LLVMConstInt(ctx->i32, 20, false), "");
1232 data_format = LLVMBuildAnd(builder, data_format,
1233 LLVMConstInt(ctx->i32, (1u << 6) - 1, false), "");
1234 wa_8888 = LLVMBuildICmp(
1235 builder, LLVMIntEQ, data_format,
1236 LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false),
1237 "");
1238
1239 uint32_t wa_num_format =
1240 return_type == TGSI_RETURN_TYPE_UINT ?
1241 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_USCALED) :
1242 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_SSCALED);
1243 wa_formats = LLVMBuildAnd(builder, formats,
1244 LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT, false),
1245 "");
1246 wa_formats = LLVMBuildOr(builder, wa_formats,
1247 LLVMConstInt(ctx->i32, wa_num_format, false), "");
1248
1249 formats = LLVMBuildSelect(builder, wa_8888, wa_formats, formats, "");
1250 args->resource = LLVMBuildInsertElement(
1251 builder, args->resource, formats, ctx->i32_1, "");
1252 }
1253
1254 if (target == TGSI_TEXTURE_RECT ||
1255 target == TGSI_TEXTURE_SHADOWRECT) {
1256 assert(!wa_8888);
1257 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
1258 } else {
1259 struct ac_image_args resinfo = {};
1260 struct lp_build_if_state if_ctx;
1261
1262 if (wa_8888) {
1263 /* Skip the texture size query entirely if we don't need it. */
1264 lp_build_if(&if_ctx, &ctx->gallivm, LLVMBuildNot(builder, wa_8888, ""));
1265 }
1266
1267 /* Query the texture size. */
1268 resinfo.opcode = ac_image_get_resinfo;
1269 resinfo.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1270 resinfo.resource = args->resource;
1271 resinfo.sampler = args->sampler;
1272 resinfo.lod = ctx->ac.i32_0;
1273 resinfo.dmask = 0xf;
1274 resinfo.attributes = AC_FUNC_ATTR_READNONE;
1275
1276 LLVMValueRef texsize =
1277 fix_resinfo(ctx, target,
1278 ac_build_image_opcode(&ctx->ac, &resinfo));
1279
1280 /* Compute -0.5 / size. */
1281 for (unsigned c = 0; c < 2; c++) {
1282 half_texel[c] =
1283 LLVMBuildExtractElement(builder, texsize,
1284 LLVMConstInt(ctx->i32, c, 0), "");
1285 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
1286 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, half_texel[c]);
1287 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
1288 LLVMConstReal(ctx->f32, -0.5), "");
1289 }
1290
1291 if (wa_8888) {
1292 lp_build_endif(&if_ctx);
1293
1294 LLVMBasicBlockRef bb[2] = { if_ctx.true_block, if_ctx.entry_block };
1295
1296 for (unsigned c = 0; c < 2; c++) {
1297 LLVMValueRef values[2] = { half_texel[c], ctx->ac.f32_0 };
1298 half_texel[c] = ac_build_phi(&ctx->ac, ctx->f32, 2,
1299 values, bb);
1300 }
1301 }
1302 }
1303
1304 for (unsigned c = 0; c < 2; c++) {
1305 LLVMValueRef tmp;
1306 tmp = ac_to_float(&ctx->ac, args->coords[c]);
1307 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
1308 args->coords[c] = ac_to_integer(&ctx->ac, tmp);
1309 }
1310
1311 return wa_8888;
1312 }
1313
1314 /* The second half of the cube texture 8_8_8_8 integer workaround: adjust the
1315 * result after the gather operation.
1316 */
1317 static LLVMValueRef
1318 si_fix_gather4_integer_result(struct si_shader_context *ctx,
1319 LLVMValueRef result,
1320 enum tgsi_return_type return_type,
1321 LLVMValueRef wa)
1322 {
1323 LLVMBuilderRef builder = ctx->ac.builder;
1324
1325 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1326 return_type == TGSI_RETURN_TYPE_UINT);
1327
1328 for (unsigned chan = 0; chan < 4; ++chan) {
1329 LLVMValueRef chanv = LLVMConstInt(ctx->i32, chan, false);
1330 LLVMValueRef value;
1331 LLVMValueRef wa_value;
1332
1333 value = LLVMBuildExtractElement(builder, result, chanv, "");
1334
1335 if (return_type == TGSI_RETURN_TYPE_UINT)
1336 wa_value = LLVMBuildFPToUI(builder, value, ctx->i32, "");
1337 else
1338 wa_value = LLVMBuildFPToSI(builder, value, ctx->i32, "");
1339 wa_value = ac_to_float(&ctx->ac, wa_value);
1340 value = LLVMBuildSelect(builder, wa, wa_value, value, "");
1341
1342 result = LLVMBuildInsertElement(builder, result, value, chanv, "");
1343 }
1344
1345 return result;
1346 }
1347
1348 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
1349 struct lp_build_tgsi_context *bld_base,
1350 struct lp_build_emit_data *emit_data)
1351 {
1352 struct si_shader_context *ctx = si_shader_context(bld_base);
1353 const struct tgsi_full_instruction *inst = emit_data->inst;
1354 unsigned opcode = inst->Instruction.Opcode;
1355 unsigned target = inst->Texture.Texture;
1356 struct ac_image_args args = {};
1357 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
1358 unsigned chan;
1359 bool has_offset = inst->Texture.NumOffsets > 0;
1360 LLVMValueRef fmask_ptr = NULL;
1361
1362 tex_fetch_ptrs(bld_base, emit_data, &args.resource, &args.sampler, &fmask_ptr);
1363
1364 if (target == TGSI_TEXTURE_BUFFER) {
1365 LLVMValueRef vindex = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1366 unsigned num_channels =
1367 util_last_bit(inst->Dst[0].Register.WriteMask);
1368 LLVMValueRef result =
1369 ac_build_buffer_load_format(&ctx->ac,
1370 args.resource,
1371 vindex,
1372 ctx->i32_0,
1373 num_channels, 0, true);
1374 emit_data->output[emit_data->chan] =
1375 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
1376 return;
1377 }
1378
1379 /* Fetch and project texture coordinates */
1380 args.coords[3] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_W);
1381 for (chan = 0; chan < 3; chan++) {
1382 args.coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
1383 if (opcode == TGSI_OPCODE_TXP)
1384 args.coords[chan] = ac_build_fdiv(&ctx->ac,
1385 args.coords[chan], args.coords[3]);
1386 }
1387
1388 if (opcode == TGSI_OPCODE_TXP)
1389 args.coords[3] = ctx->ac.f32_1;
1390
1391 /* Pack offsets. */
1392 if (has_offset &&
1393 opcode != TGSI_OPCODE_TXF &&
1394 opcode != TGSI_OPCODE_TXF_LZ) {
1395 /* The offsets are six-bit signed integers packed like this:
1396 * X=[5:0], Y=[13:8], and Z=[21:16].
1397 */
1398 LLVMValueRef offset[3], pack;
1399
1400 assert(inst->Texture.NumOffsets == 1);
1401
1402 for (chan = 0; chan < 3; chan++) {
1403 offset[chan] = lp_build_emit_fetch_texoffset(bld_base, inst, 0, chan);
1404 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
1405 LLVMConstInt(ctx->i32, 0x3f, 0), "");
1406 if (chan)
1407 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
1408 LLVMConstInt(ctx->i32, chan*8, 0), "");
1409 }
1410
1411 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
1412 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
1413 args.offset = pack;
1414 }
1415
1416 /* Pack LOD bias value */
1417 if (opcode == TGSI_OPCODE_TXB)
1418 args.bias = args.coords[3];
1419 if (opcode == TGSI_OPCODE_TXB2)
1420 args.bias = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1421
1422 /* Pack depth comparison value */
1423 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
1424 LLVMValueRef z;
1425
1426 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1427 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1428 } else {
1429 assert(ref_pos >= 0);
1430 z = args.coords[ref_pos];
1431 }
1432
1433 /* Section 8.23.1 (Depth Texture Comparison Mode) of the
1434 * OpenGL 4.5 spec says:
1435 *
1436 * "If the texture’s internal format indicates a fixed-point
1437 * depth texture, then D_t and D_ref are clamped to the
1438 * range [0, 1]; otherwise no clamping is performed."
1439 *
1440 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1441 * so the depth comparison value isn't clamped for Z16 and
1442 * Z24 anymore. Do it manually here for GFX8-9; GFX10 has
1443 * an explicitly clamped 32-bit float format.
1444 */
1445 if (ctx->screen->info.chip_class >= GFX8 &&
1446 ctx->screen->info.chip_class <= GFX9) {
1447 LLVMValueRef upgraded;
1448 LLVMValueRef clamped;
1449 upgraded = LLVMBuildExtractElement(ctx->ac.builder, args.sampler,
1450 LLVMConstInt(ctx->i32, 3, false), "");
1451 upgraded = LLVMBuildLShr(ctx->ac.builder, upgraded,
1452 LLVMConstInt(ctx->i32, 29, false), "");
1453 upgraded = LLVMBuildTrunc(ctx->ac.builder, upgraded, ctx->i1, "");
1454 clamped = ac_build_clamp(&ctx->ac, z);
1455 z = LLVMBuildSelect(ctx->ac.builder, upgraded, clamped, z, "");
1456 }
1457
1458 args.compare = z;
1459 }
1460
1461 /* Pack user derivatives */
1462 if (opcode == TGSI_OPCODE_TXD) {
1463 int param, num_src_deriv_channels, num_dst_deriv_channels;
1464
1465 switch (target) {
1466 case TGSI_TEXTURE_3D:
1467 num_src_deriv_channels = 3;
1468 num_dst_deriv_channels = 3;
1469 break;
1470 case TGSI_TEXTURE_2D:
1471 case TGSI_TEXTURE_SHADOW2D:
1472 case TGSI_TEXTURE_RECT:
1473 case TGSI_TEXTURE_SHADOWRECT:
1474 case TGSI_TEXTURE_2D_ARRAY:
1475 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1476 num_src_deriv_channels = 2;
1477 num_dst_deriv_channels = 2;
1478 break;
1479 case TGSI_TEXTURE_CUBE:
1480 case TGSI_TEXTURE_SHADOWCUBE:
1481 case TGSI_TEXTURE_CUBE_ARRAY:
1482 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1483 /* Cube derivatives will be converted to 2D. */
1484 num_src_deriv_channels = 3;
1485 num_dst_deriv_channels = 3;
1486 break;
1487 case TGSI_TEXTURE_1D:
1488 case TGSI_TEXTURE_SHADOW1D:
1489 case TGSI_TEXTURE_1D_ARRAY:
1490 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1491 num_src_deriv_channels = 1;
1492
1493 /* 1D textures are allocated and used as 2D on GFX9. */
1494 if (ctx->screen->info.chip_class == GFX9) {
1495 num_dst_deriv_channels = 2;
1496 } else {
1497 num_dst_deriv_channels = 1;
1498 }
1499 break;
1500 default:
1501 unreachable("invalid target");
1502 }
1503
1504 for (param = 0; param < 2; param++) {
1505 for (chan = 0; chan < num_src_deriv_channels; chan++)
1506 args.derivs[param * num_dst_deriv_channels + chan] =
1507 lp_build_emit_fetch(bld_base, inst, param+1, chan);
1508
1509 /* Fill in the rest with zeros. */
1510 for (chan = num_src_deriv_channels;
1511 chan < num_dst_deriv_channels; chan++)
1512 args.derivs[param * num_dst_deriv_channels + chan] =
1513 ctx->ac.f32_0;
1514 }
1515 }
1516
1517 if (target == TGSI_TEXTURE_CUBE ||
1518 target == TGSI_TEXTURE_CUBE_ARRAY ||
1519 target == TGSI_TEXTURE_SHADOWCUBE ||
1520 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1521 ac_prepare_cube_coords(&ctx->ac,
1522 opcode == TGSI_OPCODE_TXD,
1523 target == TGSI_TEXTURE_CUBE_ARRAY ||
1524 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
1525 opcode == TGSI_OPCODE_LODQ,
1526 args.coords, args.derivs);
1527 } else if (tgsi_is_array_sampler(target) &&
1528 opcode != TGSI_OPCODE_TXF &&
1529 opcode != TGSI_OPCODE_TXF_LZ &&
1530 ctx->screen->info.chip_class <= GFX8) {
1531 unsigned array_coord = target == TGSI_TEXTURE_1D_ARRAY ? 1 : 2;
1532 args.coords[array_coord] = ac_build_round(&ctx->ac, args.coords[array_coord]);
1533 }
1534
1535 /* 1D textures are allocated and used as 2D on GFX9. */
1536 if (ctx->screen->info.chip_class == GFX9) {
1537 LLVMValueRef filler;
1538
1539 /* Use 0.5, so that we don't sample the border color. */
1540 if (opcode == TGSI_OPCODE_TXF ||
1541 opcode == TGSI_OPCODE_TXF_LZ)
1542 filler = ctx->i32_0;
1543 else
1544 filler = LLVMConstReal(ctx->f32, 0.5);
1545
1546 if (target == TGSI_TEXTURE_1D ||
1547 target == TGSI_TEXTURE_SHADOW1D) {
1548 args.coords[1] = filler;
1549 } else if (target == TGSI_TEXTURE_1D_ARRAY ||
1550 target == TGSI_TEXTURE_SHADOW1D_ARRAY) {
1551 args.coords[2] = args.coords[1];
1552 args.coords[1] = filler;
1553 }
1554 }
1555
1556 /* Pack LOD or sample index */
1557 if (opcode == TGSI_OPCODE_TXL)
1558 args.lod = args.coords[3];
1559 else if (opcode == TGSI_OPCODE_TXL2)
1560 args.lod = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1561 else if (opcode == TGSI_OPCODE_TXF) {
1562 if (target == TGSI_TEXTURE_2D_MSAA) {
1563 /* No LOD, but move sample index into the right place. */
1564 args.coords[2] = args.coords[3];
1565 } else if (target != TGSI_TEXTURE_2D_ARRAY_MSAA) {
1566 args.lod = args.coords[3];
1567 }
1568 }
1569
1570 if ((target == TGSI_TEXTURE_2D_MSAA ||
1571 target == TGSI_TEXTURE_2D_ARRAY_MSAA) &&
1572 !(ctx->screen->debug_flags & DBG(NO_FMASK))) {
1573 ac_apply_fmask_to_sample(&ctx->ac, fmask_ptr, args.coords,
1574 target == TGSI_TEXTURE_2D_ARRAY_MSAA);
1575 }
1576
1577 if (opcode == TGSI_OPCODE_TXF ||
1578 opcode == TGSI_OPCODE_TXF_LZ) {
1579 /* add tex offsets */
1580 if (inst->Texture.NumOffsets) {
1581 const struct tgsi_texture_offset *off = inst->TexOffsets;
1582
1583 assert(inst->Texture.NumOffsets == 1);
1584
1585 switch (target) {
1586 case TGSI_TEXTURE_3D:
1587 args.coords[2] =
1588 LLVMBuildAdd(ctx->ac.builder, args.coords[2],
1589 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ], "");
1590 /* fall through */
1591 case TGSI_TEXTURE_2D:
1592 case TGSI_TEXTURE_SHADOW2D:
1593 case TGSI_TEXTURE_RECT:
1594 case TGSI_TEXTURE_SHADOWRECT:
1595 case TGSI_TEXTURE_2D_ARRAY:
1596 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1597 args.coords[1] =
1598 LLVMBuildAdd(ctx->ac.builder, args.coords[1],
1599 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY], "");
1600 /* fall through */
1601 case TGSI_TEXTURE_1D:
1602 case TGSI_TEXTURE_SHADOW1D:
1603 case TGSI_TEXTURE_1D_ARRAY:
1604 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1605 args.coords[0] =
1606 LLVMBuildAdd(ctx->ac.builder, args.coords[0],
1607 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX], "");
1608 break;
1609 /* texture offsets do not apply to other texture targets */
1610 }
1611 }
1612 }
1613
1614 if (opcode == TGSI_OPCODE_TG4) {
1615 unsigned gather_comp = 0;
1616
1617 /* DMASK was repurposed for GATHER4. 4 components are always
1618 * returned and DMASK works like a swizzle - it selects
1619 * the component to fetch. The only valid DMASK values are
1620 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1621 * (red,red,red,red) etc.) The ISA document doesn't mention
1622 * this.
1623 */
1624
1625 /* Get the component index from src1.x for Gather4. */
1626 if (!tgsi_is_shadow_target(target)) {
1627 LLVMValueRef comp_imm;
1628 struct tgsi_src_register src1 = inst->Src[1].Register;
1629
1630 assert(src1.File == TGSI_FILE_IMMEDIATE);
1631
1632 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
1633 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1634 gather_comp = CLAMP(gather_comp, 0, 3);
1635 }
1636
1637 args.dmask = 1 << gather_comp;
1638 } else {
1639 args.dmask = 0xf;
1640 }
1641
1642 args.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1643 args.unorm = target == TGSI_TEXTURE_RECT ||
1644 target == TGSI_TEXTURE_SHADOWRECT;
1645 args.opcode = ac_image_sample;
1646
1647 switch (opcode) {
1648 case TGSI_OPCODE_TXF:
1649 case TGSI_OPCODE_TXF_LZ:
1650 args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
1651 target == TGSI_TEXTURE_2D_MSAA ||
1652 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
1653 ac_image_load : ac_image_load_mip;
1654 break;
1655 case TGSI_OPCODE_LODQ:
1656 args.opcode = ac_image_get_lod;
1657 break;
1658 case TGSI_OPCODE_TEX:
1659 case TGSI_OPCODE_TEX2:
1660 case TGSI_OPCODE_TXP:
1661 if (ctx->type != PIPE_SHADER_FRAGMENT)
1662 args.level_zero = true;
1663 break;
1664 case TGSI_OPCODE_TEX_LZ:
1665 args.level_zero = true;
1666 break;
1667 case TGSI_OPCODE_TXB:
1668 case TGSI_OPCODE_TXB2:
1669 assert(ctx->type == PIPE_SHADER_FRAGMENT);
1670 break;
1671 case TGSI_OPCODE_TXL:
1672 case TGSI_OPCODE_TXL2:
1673 break;
1674 case TGSI_OPCODE_TXD:
1675 break;
1676 case TGSI_OPCODE_TG4:
1677 args.opcode = ac_image_gather4;
1678 args.level_zero = true;
1679 break;
1680 default:
1681 assert(0);
1682 return;
1683 }
1684
1685 /* The hardware needs special lowering for Gather4 with integer formats. */
1686 LLVMValueRef gather4_int_result_workaround = NULL;
1687
1688 if (ctx->screen->info.chip_class <= GFX8 &&
1689 opcode == TGSI_OPCODE_TG4) {
1690 assert(inst->Texture.ReturnType != TGSI_RETURN_TYPE_UNKNOWN);
1691
1692 if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
1693 inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT) {
1694 gather4_int_result_workaround =
1695 si_lower_gather4_integer(ctx, &args, target,
1696 inst->Texture.ReturnType);
1697 }
1698 }
1699
1700 args.attributes = AC_FUNC_ATTR_READNONE;
1701 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
1702
1703 if (gather4_int_result_workaround) {
1704 result = si_fix_gather4_integer_result(ctx, result,
1705 inst->Texture.ReturnType,
1706 gather4_int_result_workaround);
1707 }
1708
1709 emit_data->output[emit_data->chan] = result;
1710 }
1711
1712 static void si_llvm_emit_txqs(
1713 const struct lp_build_tgsi_action *action,
1714 struct lp_build_tgsi_context *bld_base,
1715 struct lp_build_emit_data *emit_data)
1716 {
1717 struct si_shader_context *ctx = si_shader_context(bld_base);
1718 LLVMValueRef rsrc;
1719
1720 tex_fetch_ptrs(bld_base, emit_data, &rsrc, NULL, NULL);
1721
1722 rsrc = LLVMBuildBitCast(ctx->ac.builder, rsrc, ctx->v8i32, "");
1723 emit_data->output[emit_data->chan] =
1724 ac_build_image_get_sample_count(&ctx->ac, rsrc);
1725 }
1726
1727 static LLVMValueRef si_llvm_emit_fbfetch(struct si_shader_context *ctx)
1728 {
1729 struct ac_image_args args = {};
1730 LLVMValueRef ptr, image, fmask;
1731
1732 /* Ignore src0, because KHR_blend_func_extended disallows multiple render
1733 * targets.
1734 */
1735
1736 /* Load the image descriptor. */
1737 STATIC_ASSERT(SI_PS_IMAGE_COLORBUF0 % 2 == 0);
1738 ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1739 ptr = LLVMBuildPointerCast(ctx->ac.builder, ptr,
1740 ac_array_in_const32_addr_space(ctx->v8i32), "");
1741 image = ac_build_load_to_sgpr(&ctx->ac, ptr,
1742 LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0 / 2, 0));
1743
1744 unsigned chan = 0;
1745
1746 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_POS_FIXED_PT, 0, 16);
1747
1748 if (!ctx->shader->key.mono.u.ps.fbfetch_is_1D)
1749 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_POS_FIXED_PT, 16, 16);
1750
1751 /* Get the current render target layer index. */
1752 if (ctx->shader->key.mono.u.ps.fbfetch_layered)
1753 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_ANCILLARY, 16, 11);
1754
1755 if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
1756 args.coords[chan++] = si_get_sample_id(ctx);
1757
1758 if (ctx->shader->key.mono.u.ps.fbfetch_msaa &&
1759 !(ctx->screen->debug_flags & DBG(NO_FMASK))) {
1760 fmask = ac_build_load_to_sgpr(&ctx->ac, ptr,
1761 LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0_FMASK / 2, 0));
1762
1763 ac_apply_fmask_to_sample(&ctx->ac, fmask, args.coords,
1764 ctx->shader->key.mono.u.ps.fbfetch_layered);
1765 }
1766
1767 args.opcode = ac_image_load;
1768 args.resource = image;
1769 args.dmask = 0xf;
1770 args.attributes = AC_FUNC_ATTR_READNONE;
1771
1772 if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
1773 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1774 ac_image_2darraymsaa : ac_image_2dmsaa;
1775 else if (ctx->shader->key.mono.u.ps.fbfetch_is_1D)
1776 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1777 ac_image_1darray : ac_image_1d;
1778 else
1779 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1780 ac_image_2darray : ac_image_2d;
1781
1782 return ac_build_image_opcode(&ctx->ac, &args);
1783 }
1784
1785 static void si_tgsi_emit_fbfetch(const struct lp_build_tgsi_action *action,
1786 struct lp_build_tgsi_context *bld_base,
1787 struct lp_build_emit_data *emit_data)
1788 {
1789 struct si_shader_context *ctx = si_shader_context(bld_base);
1790
1791 emit_data->output[emit_data->chan] = si_llvm_emit_fbfetch(ctx);
1792 }
1793
1794 LLVMValueRef si_nir_emit_fbfetch(struct ac_shader_abi *abi)
1795 {
1796 struct si_shader_context *ctx = si_shader_context_from_abi(abi);
1797
1798 return si_llvm_emit_fbfetch(ctx);
1799 }
1800
1801 /**
1802 * Setup actions for TGSI memory opcode, including texture opcodes.
1803 */
1804 void si_shader_context_init_mem(struct si_shader_context *ctx)
1805 {
1806 struct lp_build_tgsi_context *bld_base = &ctx->bld_base;
1807
1808 bld_base->op_actions[TGSI_OPCODE_TEX].emit = build_tex_intrinsic;
1809 bld_base->op_actions[TGSI_OPCODE_TEX_LZ].emit = build_tex_intrinsic;
1810 bld_base->op_actions[TGSI_OPCODE_TEX2].emit = build_tex_intrinsic;
1811 bld_base->op_actions[TGSI_OPCODE_TXB].emit = build_tex_intrinsic;
1812 bld_base->op_actions[TGSI_OPCODE_TXB2].emit = build_tex_intrinsic;
1813 bld_base->op_actions[TGSI_OPCODE_TXD].emit = build_tex_intrinsic;
1814 bld_base->op_actions[TGSI_OPCODE_TXF].emit = build_tex_intrinsic;
1815 bld_base->op_actions[TGSI_OPCODE_TXF_LZ].emit = build_tex_intrinsic;
1816 bld_base->op_actions[TGSI_OPCODE_TXL].emit = build_tex_intrinsic;
1817 bld_base->op_actions[TGSI_OPCODE_TXL2].emit = build_tex_intrinsic;
1818 bld_base->op_actions[TGSI_OPCODE_TXP].emit = build_tex_intrinsic;
1819 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = resq_emit;
1820 bld_base->op_actions[TGSI_OPCODE_TG4].emit = build_tex_intrinsic;
1821 bld_base->op_actions[TGSI_OPCODE_LODQ].emit = build_tex_intrinsic;
1822 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
1823
1824 bld_base->op_actions[TGSI_OPCODE_FBFETCH].emit = si_tgsi_emit_fbfetch;
1825
1826 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
1827 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
1828 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
1829
1830 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].emit = atomic_emit;
1831 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
1832 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].emit = atomic_emit;
1833 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
1834 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].emit = atomic_emit;
1835 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
1836 bld_base->op_actions[TGSI_OPCODE_ATOMAND].emit = atomic_emit;
1837 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
1838 bld_base->op_actions[TGSI_OPCODE_ATOMOR].emit = atomic_emit;
1839 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
1840 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].emit = atomic_emit;
1841 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
1842 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].emit = atomic_emit;
1843 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
1844 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].emit = atomic_emit;
1845 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
1846 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].emit = atomic_emit;
1847 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
1848 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].emit = atomic_emit;
1849 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
1850 bld_base->op_actions[TGSI_OPCODE_ATOMINC_WRAP].emit = atomic_emit;
1851 bld_base->op_actions[TGSI_OPCODE_ATOMINC_WRAP].intr_name = "inc";
1852 bld_base->op_actions[TGSI_OPCODE_ATOMDEC_WRAP].emit = atomic_emit;
1853 bld_base->op_actions[TGSI_OPCODE_ATOMDEC_WRAP].intr_name = "dec";
1854 }