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radeonsi: use get_resinfo directly in lower_gather4_integer
[mesa.git] / src / gallium / drivers / radeonsi / si_shader_tgsi_mem.c
1 /*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_shader_internal.h"
26 #include "si_pipe.h"
27 #include "sid.h"
28 #include "tgsi/tgsi_build.h"
29 #include "tgsi/tgsi_util.h"
30 #include "ac_llvm_util.h"
31
32 /**
33 * Given a v8i32 resource descriptor for a buffer, extract the size of the
34 * buffer in number of elements and return it as an i32.
35 */
36 static LLVMValueRef get_buffer_size(
37 struct lp_build_tgsi_context *bld_base,
38 LLVMValueRef descriptor)
39 {
40 struct si_shader_context *ctx = si_shader_context(bld_base);
41 LLVMBuilderRef builder = ctx->ac.builder;
42 LLVMValueRef size =
43 LLVMBuildExtractElement(builder, descriptor,
44 LLVMConstInt(ctx->i32, 2, 0), "");
45
46 if (ctx->screen->info.chip_class == VI) {
47 /* On VI, the descriptor contains the size in bytes,
48 * but TXQ must return the size in elements.
49 * The stride is always non-zero for resources using TXQ.
50 */
51 LLVMValueRef stride =
52 LLVMBuildExtractElement(builder, descriptor,
53 ctx->i32_1, "");
54 stride = LLVMBuildLShr(builder, stride,
55 LLVMConstInt(ctx->i32, 16, 0), "");
56 stride = LLVMBuildAnd(builder, stride,
57 LLVMConstInt(ctx->i32, 0x3FFF, 0), "");
58
59 size = LLVMBuildUDiv(builder, size, stride, "");
60 }
61
62 return size;
63 }
64
65 static LLVMValueRef
66 shader_buffer_fetch_rsrc(struct si_shader_context *ctx,
67 const struct tgsi_full_src_register *reg,
68 bool ubo)
69 {
70 LLVMValueRef index;
71
72 if (!reg->Register.Indirect) {
73 index = LLVMConstInt(ctx->i32, reg->Register.Index, false);
74 } else {
75 index = si_get_indirect_index(ctx, &reg->Indirect,
76 1, reg->Register.Index);
77 }
78
79 if (ubo)
80 return ctx->abi.load_ubo(&ctx->abi, index);
81 else
82 return ctx->abi.load_ssbo(&ctx->abi, index, false);
83 }
84
85 static enum ac_image_dim
86 ac_texture_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type target)
87 {
88 switch (target) {
89 case TGSI_TEXTURE_1D:
90 case TGSI_TEXTURE_SHADOW1D:
91 if (screen->info.chip_class >= GFX9)
92 return ac_image_2d;
93 return ac_image_1d;
94 case TGSI_TEXTURE_2D:
95 case TGSI_TEXTURE_SHADOW2D:
96 case TGSI_TEXTURE_RECT:
97 case TGSI_TEXTURE_SHADOWRECT:
98 return ac_image_2d;
99 case TGSI_TEXTURE_3D:
100 return ac_image_3d;
101 case TGSI_TEXTURE_CUBE:
102 case TGSI_TEXTURE_SHADOWCUBE:
103 case TGSI_TEXTURE_CUBE_ARRAY:
104 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
105 return ac_image_cube;
106 case TGSI_TEXTURE_1D_ARRAY:
107 case TGSI_TEXTURE_SHADOW1D_ARRAY:
108 if (screen->info.chip_class >= GFX9)
109 return ac_image_2darray;
110 return ac_image_1darray;
111 case TGSI_TEXTURE_2D_ARRAY:
112 case TGSI_TEXTURE_SHADOW2D_ARRAY:
113 return ac_image_2darray;
114 case TGSI_TEXTURE_2D_MSAA:
115 return ac_image_2dmsaa;
116 case TGSI_TEXTURE_2D_ARRAY_MSAA:
117 return ac_image_2darraymsaa;
118 default:
119 unreachable("unhandled texture type");
120 }
121 }
122
123 static enum ac_image_dim
124 ac_image_dim_from_tgsi_target(struct si_screen *screen, enum tgsi_texture_type target)
125 {
126 enum ac_image_dim dim = ac_texture_dim_from_tgsi_target(screen, target);
127
128 /* Match the resource type set in the descriptor. */
129 if (dim == ac_image_cube ||
130 (screen->info.chip_class <= VI && dim == ac_image_3d))
131 dim = ac_image_2darray;
132 else if (target == TGSI_TEXTURE_2D && screen->info.chip_class >= GFX9) {
133 /* When a single layer of a 3D texture is bound, the shader
134 * will refer to a 2D target, but the descriptor has a 3D type.
135 * Since the HW ignores BASE_ARRAY in this case, we need to
136 * send 3 coordinates. This doesn't hurt when the underlying
137 * texture is non-3D.
138 */
139 dim = ac_image_3d;
140 }
141
142 return dim;
143 }
144
145 /**
146 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
147 *
148 * At least on Tonga, executing image stores on images with DCC enabled and
149 * non-trivial can eventually lead to lockups. This can occur when an
150 * application binds an image as read-only but then uses a shader that writes
151 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
152 * program termination) in this case, but it doesn't cost much to be a bit
153 * nicer: disabling DCC in the shader still leads to undefined results but
154 * avoids the lockup.
155 */
156 static LLVMValueRef force_dcc_off(struct si_shader_context *ctx,
157 LLVMValueRef rsrc)
158 {
159 if (ctx->screen->info.chip_class <= CIK) {
160 return rsrc;
161 } else {
162 LLVMValueRef i32_6 = LLVMConstInt(ctx->i32, 6, 0);
163 LLVMValueRef i32_C = LLVMConstInt(ctx->i32, C_008F28_COMPRESSION_EN, 0);
164 LLVMValueRef tmp;
165
166 tmp = LLVMBuildExtractElement(ctx->ac.builder, rsrc, i32_6, "");
167 tmp = LLVMBuildAnd(ctx->ac.builder, tmp, i32_C, "");
168 return LLVMBuildInsertElement(ctx->ac.builder, rsrc, tmp, i32_6, "");
169 }
170 }
171
172 LLVMValueRef si_load_image_desc(struct si_shader_context *ctx,
173 LLVMValueRef list, LLVMValueRef index,
174 enum ac_descriptor_type desc_type, bool dcc_off)
175 {
176 LLVMBuilderRef builder = ctx->ac.builder;
177 LLVMValueRef rsrc;
178
179 if (desc_type == AC_DESC_BUFFER) {
180 index = LLVMBuildMul(builder, index,
181 LLVMConstInt(ctx->i32, 2, 0), "");
182 index = LLVMBuildAdd(builder, index,
183 ctx->i32_1, "");
184 list = LLVMBuildPointerCast(builder, list,
185 ac_array_in_const32_addr_space(ctx->v4i32), "");
186 } else {
187 assert(desc_type == AC_DESC_IMAGE);
188 }
189
190 rsrc = ac_build_load_to_sgpr(&ctx->ac, list, index);
191 if (desc_type == AC_DESC_IMAGE && dcc_off)
192 rsrc = force_dcc_off(ctx, rsrc);
193 return rsrc;
194 }
195
196 /**
197 * Load the resource descriptor for \p image.
198 */
199 static void
200 image_fetch_rsrc(
201 struct lp_build_tgsi_context *bld_base,
202 const struct tgsi_full_src_register *image,
203 bool is_store, unsigned target,
204 LLVMValueRef *rsrc)
205 {
206 struct si_shader_context *ctx = si_shader_context(bld_base);
207 LLVMValueRef rsrc_ptr = LLVMGetParam(ctx->main_fn,
208 ctx->param_samplers_and_images);
209 LLVMValueRef index;
210 bool dcc_off = is_store;
211
212 if (!image->Register.Indirect) {
213 const struct tgsi_shader_info *info = bld_base->info;
214 unsigned images_writemask = info->images_store |
215 info->images_atomic;
216
217 index = LLVMConstInt(ctx->i32,
218 si_get_image_slot(image->Register.Index), 0);
219
220 if (images_writemask & (1 << image->Register.Index))
221 dcc_off = true;
222 } else {
223 /* From the GL_ARB_shader_image_load_store extension spec:
224 *
225 * If a shader performs an image load, store, or atomic
226 * operation using an image variable declared as an array,
227 * and if the index used to select an individual element is
228 * negative or greater than or equal to the size of the
229 * array, the results of the operation are undefined but may
230 * not lead to termination.
231 */
232 index = si_get_bounded_indirect_index(ctx, &image->Indirect,
233 image->Register.Index,
234 ctx->num_images);
235 index = LLVMBuildSub(ctx->ac.builder,
236 LLVMConstInt(ctx->i32, SI_NUM_IMAGES - 1, 0),
237 index, "");
238 }
239
240 if (image->Register.File != TGSI_FILE_IMAGE) {
241 /* Bindless descriptors are accessible from a different pair of
242 * user SGPR indices.
243 */
244 rsrc_ptr = LLVMGetParam(ctx->main_fn,
245 ctx->param_bindless_samplers_and_images);
246 index = lp_build_emit_fetch_src(bld_base, image,
247 TGSI_TYPE_UNSIGNED, 0);
248
249 /* For simplicity, bindless image descriptors use fixed
250 * 16-dword slots for now.
251 */
252 index = LLVMBuildMul(ctx->ac.builder, index,
253 LLVMConstInt(ctx->i32, 2, 0), "");
254 }
255
256 *rsrc = si_load_image_desc(ctx, rsrc_ptr, index,
257 target == TGSI_TEXTURE_BUFFER ? AC_DESC_BUFFER : AC_DESC_IMAGE,
258 dcc_off);
259 }
260
261 static void image_fetch_coords(
262 struct lp_build_tgsi_context *bld_base,
263 const struct tgsi_full_instruction *inst,
264 unsigned src, LLVMValueRef desc,
265 LLVMValueRef *coords)
266 {
267 struct si_shader_context *ctx = si_shader_context(bld_base);
268 LLVMBuilderRef builder = ctx->ac.builder;
269 unsigned target = inst->Memory.Texture;
270 unsigned num_coords = tgsi_util_get_texture_coord_dim(target);
271 LLVMValueRef tmp;
272 int chan;
273
274 if (target == TGSI_TEXTURE_2D_MSAA ||
275 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
276 /* Need the sample index as well. */
277 num_coords++;
278 }
279
280 for (chan = 0; chan < num_coords; ++chan) {
281 tmp = lp_build_emit_fetch(bld_base, inst, src, chan);
282 tmp = ac_to_integer(&ctx->ac, tmp);
283 coords[chan] = tmp;
284 }
285
286 if (ctx->screen->info.chip_class >= GFX9) {
287 /* 1D textures are allocated and used as 2D on GFX9. */
288 if (target == TGSI_TEXTURE_1D) {
289 coords[1] = ctx->i32_0;
290 } else if (target == TGSI_TEXTURE_1D_ARRAY) {
291 coords[2] = coords[1];
292 coords[1] = ctx->i32_0;
293 } else if (target == TGSI_TEXTURE_2D) {
294 /* The hw can't bind a slice of a 3D image as a 2D
295 * image, because it ignores BASE_ARRAY if the target
296 * is 3D. The workaround is to read BASE_ARRAY and set
297 * it as the 3rd address operand for all 2D images.
298 */
299 LLVMValueRef first_layer, const5, mask;
300
301 const5 = LLVMConstInt(ctx->i32, 5, 0);
302 mask = LLVMConstInt(ctx->i32, S_008F24_BASE_ARRAY(~0), 0);
303 first_layer = LLVMBuildExtractElement(builder, desc, const5, "");
304 first_layer = LLVMBuildAnd(builder, first_layer, mask, "");
305
306 coords[2] = first_layer;
307 }
308 }
309 }
310
311 /**
312 * Append the resource and indexing arguments for buffer intrinsics.
313 *
314 * \param rsrc the v4i32 buffer resource
315 * \param index index into the buffer (stride-based)
316 * \param offset byte offset into the buffer
317 */
318 static void buffer_append_args(
319 struct si_shader_context *ctx,
320 struct lp_build_emit_data *emit_data,
321 LLVMValueRef rsrc,
322 LLVMValueRef index,
323 LLVMValueRef offset,
324 bool atomic,
325 bool force_glc)
326 {
327 const struct tgsi_full_instruction *inst = emit_data->inst;
328 LLVMValueRef i1false = LLVMConstInt(ctx->i1, 0, 0);
329 LLVMValueRef i1true = LLVMConstInt(ctx->i1, 1, 0);
330
331 emit_data->args[emit_data->arg_count++] = rsrc;
332 emit_data->args[emit_data->arg_count++] = index; /* vindex */
333 emit_data->args[emit_data->arg_count++] = offset; /* voffset */
334 if (!atomic) {
335 emit_data->args[emit_data->arg_count++] =
336 force_glc ||
337 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE) ?
338 i1true : i1false; /* glc */
339 }
340 emit_data->args[emit_data->arg_count++] = i1false; /* slc */
341 }
342
343 static void load_fetch_args(
344 struct lp_build_tgsi_context * bld_base,
345 struct lp_build_emit_data * emit_data)
346 {
347 struct si_shader_context *ctx = si_shader_context(bld_base);
348 const struct tgsi_full_instruction * inst = emit_data->inst;
349 unsigned target = inst->Memory.Texture;
350 LLVMValueRef rsrc;
351
352 emit_data->dst_type = ctx->v4f32;
353
354 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
355 inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
356 LLVMValueRef offset;
357 LLVMValueRef tmp;
358
359 bool ubo = inst->Src[0].Register.File == TGSI_FILE_CONSTBUF;
360 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], ubo);
361
362 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
363 offset = ac_to_integer(&ctx->ac, tmp);
364
365 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
366 offset, false, false);
367 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
368 tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
369 image_fetch_rsrc(bld_base, &inst->Src[0], false, target, &rsrc);
370 image_fetch_coords(bld_base, inst, 1, rsrc, &emit_data->args[1]);
371
372 if (target == TGSI_TEXTURE_BUFFER) {
373 buffer_append_args(ctx, emit_data, rsrc, emit_data->args[1],
374 ctx->i32_0, false, false);
375 } else {
376 emit_data->args[0] = rsrc;
377 }
378 }
379 }
380
381 static void load_emit_buffer(struct si_shader_context *ctx,
382 struct lp_build_emit_data *emit_data,
383 bool can_speculate, bool allow_smem)
384 {
385 const struct tgsi_full_instruction *inst = emit_data->inst;
386 uint writemask = inst->Dst[0].Register.WriteMask;
387 uint count = util_last_bit(writemask);
388 LLVMValueRef *args = emit_data->args;
389
390 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
391 * select SMEM for SI.load.const with a non-constant offset, and
392 * constant offsets practically don't exist with shader buffers.
393 *
394 * Also, SI.load.const doesn't use inst_offset when it's lowered
395 * to VMEM, so we just end up with more VALU instructions in the end
396 * and no benefit.
397 *
398 * TODO: Remove this line once LLVM can select SMEM with a non-constant
399 * offset, and can derive inst_offset when VMEM is selected.
400 * After that, si_memory_barrier should invalidate sL1 for shader
401 * buffers.
402 */
403
404 assert(LLVMConstIntGetZExtValue(args[1]) == 0); /* vindex */
405 emit_data->output[emit_data->chan] =
406 ac_build_buffer_load(&ctx->ac, args[0], count, NULL,
407 args[2], NULL, 0,
408 LLVMConstIntGetZExtValue(args[3]),
409 LLVMConstIntGetZExtValue(args[4]),
410 can_speculate, allow_smem);
411 }
412
413 static LLVMValueRef get_memory_ptr(struct si_shader_context *ctx,
414 const struct tgsi_full_instruction *inst,
415 LLVMTypeRef type, int arg)
416 {
417 LLVMBuilderRef builder = ctx->ac.builder;
418 LLVMValueRef offset, ptr;
419 int addr_space;
420
421 offset = lp_build_emit_fetch(&ctx->bld_base, inst, arg, 0);
422 offset = ac_to_integer(&ctx->ac, offset);
423
424 ptr = ctx->ac.lds;
425 ptr = LLVMBuildGEP(builder, ptr, &offset, 1, "");
426 addr_space = LLVMGetPointerAddressSpace(LLVMTypeOf(ptr));
427 ptr = LLVMBuildBitCast(builder, ptr, LLVMPointerType(type, addr_space), "");
428
429 return ptr;
430 }
431
432 static void load_emit_memory(
433 struct si_shader_context *ctx,
434 struct lp_build_emit_data *emit_data)
435 {
436 const struct tgsi_full_instruction *inst = emit_data->inst;
437 unsigned writemask = inst->Dst[0].Register.WriteMask;
438 LLVMValueRef channels[4], ptr, derived_ptr, index;
439 int chan;
440
441 ptr = get_memory_ptr(ctx, inst, ctx->f32, 1);
442
443 for (chan = 0; chan < 4; ++chan) {
444 if (!(writemask & (1 << chan))) {
445 channels[chan] = LLVMGetUndef(ctx->f32);
446 continue;
447 }
448
449 index = LLVMConstInt(ctx->i32, chan, 0);
450 derived_ptr = LLVMBuildGEP(ctx->ac.builder, ptr, &index, 1, "");
451 channels[chan] = LLVMBuildLoad(ctx->ac.builder, derived_ptr, "");
452 }
453 emit_data->output[emit_data->chan] = ac_build_gather_values(&ctx->ac, channels, 4);
454 }
455
456 /**
457 * Return true if the memory accessed by a LOAD or STORE instruction is
458 * read-only or write-only, respectively.
459 *
460 * \param shader_buffers_reverse_access_mask
461 * For LOAD, set this to (store | atomic) slot usage in the shader.
462 * For STORE, set this to (load | atomic) slot usage in the shader.
463 * \param images_reverse_access_mask Same as above, but for images.
464 */
465 static bool is_oneway_access_only(const struct tgsi_full_instruction *inst,
466 const struct tgsi_shader_info *info,
467 unsigned shader_buffers_reverse_access_mask,
468 unsigned images_reverse_access_mask)
469 {
470 /* RESTRICT means NOALIAS.
471 * If there are no writes, we can assume the accessed memory is read-only.
472 * If there are no reads, we can assume the accessed memory is write-only.
473 */
474 if (inst->Memory.Qualifier & TGSI_MEMORY_RESTRICT) {
475 unsigned reverse_access_mask;
476
477 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
478 reverse_access_mask = shader_buffers_reverse_access_mask;
479 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
480 reverse_access_mask = info->images_buffers &
481 images_reverse_access_mask;
482 } else {
483 reverse_access_mask = ~info->images_buffers &
484 images_reverse_access_mask;
485 }
486
487 if (inst->Src[0].Register.Indirect) {
488 if (!reverse_access_mask)
489 return true;
490 } else {
491 if (!(reverse_access_mask &
492 (1u << inst->Src[0].Register.Index)))
493 return true;
494 }
495 }
496
497 /* If there are no buffer writes (for both shader buffers & image
498 * buffers), it implies that buffer memory is read-only.
499 * If there are no buffer reads (for both shader buffers & image
500 * buffers), it implies that buffer memory is write-only.
501 *
502 * Same for the case when there are no writes/reads for non-buffer
503 * images.
504 */
505 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
506 (inst->Memory.Texture == TGSI_TEXTURE_BUFFER &&
507 (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
508 tgsi_is_bindless_image_file(inst->Src[0].Register.File)))) {
509 if (!shader_buffers_reverse_access_mask &&
510 !(info->images_buffers & images_reverse_access_mask))
511 return true;
512 } else {
513 if (!(~info->images_buffers & images_reverse_access_mask))
514 return true;
515 }
516 return false;
517 }
518
519 static void load_emit(
520 const struct lp_build_tgsi_action *action,
521 struct lp_build_tgsi_context *bld_base,
522 struct lp_build_emit_data *emit_data)
523 {
524 struct si_shader_context *ctx = si_shader_context(bld_base);
525 const struct tgsi_full_instruction * inst = emit_data->inst;
526 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
527 bool can_speculate = false;
528
529 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
530 load_emit_memory(ctx, emit_data);
531 return;
532 }
533
534 if (inst->Src[0].Register.File == TGSI_FILE_CONSTBUF) {
535 load_emit_buffer(ctx, emit_data, true, true);
536 return;
537 }
538
539 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
540 ac_build_waitcnt(&ctx->ac, VM_CNT);
541
542 can_speculate = !(inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE) &&
543 is_oneway_access_only(inst, info,
544 info->shader_buffers_store |
545 info->shader_buffers_atomic,
546 info->images_store |
547 info->images_atomic);
548
549 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
550 load_emit_buffer(ctx, emit_data, can_speculate, false);
551 return;
552 }
553
554 if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
555 unsigned num_channels = util_last_bit(inst->Dst[0].Register.WriteMask);
556 LLVMValueRef result =
557 ac_build_buffer_load_format(&ctx->ac,
558 emit_data->args[0],
559 emit_data->args[1],
560 emit_data->args[2],
561 num_channels,
562 LLVMConstIntGetZExtValue(emit_data->args[3]),
563 can_speculate);
564 emit_data->output[emit_data->chan] =
565 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
566 } else {
567 struct ac_image_args args = {};
568 args.opcode = ac_image_load;
569 args.resource = emit_data->args[0];
570 memcpy(args.coords, &emit_data->args[1], sizeof(args.coords));
571 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
572 if (inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE))
573 args.cache_policy = ac_glc;
574 args.attributes = ac_get_load_intr_attribs(can_speculate);
575 args.dmask = 0xf;
576
577 emit_data->output[emit_data->chan] =
578 ac_build_image_opcode(&ctx->ac, &args);
579 }
580 }
581
582 static void store_fetch_args(
583 struct lp_build_tgsi_context * bld_base,
584 struct lp_build_emit_data * emit_data)
585 {
586 struct si_shader_context *ctx = si_shader_context(bld_base);
587 const struct tgsi_full_instruction * inst = emit_data->inst;
588 struct tgsi_full_src_register memory;
589 LLVMValueRef chans[4];
590 LLVMValueRef data;
591 LLVMValueRef rsrc;
592 unsigned chan;
593
594 emit_data->dst_type = ctx->voidt;
595
596 for (chan = 0; chan < 4; ++chan) {
597 chans[chan] = lp_build_emit_fetch(bld_base, inst, 1, chan);
598 }
599 data = ac_build_gather_values(&ctx->ac, chans, 4);
600
601 emit_data->args[emit_data->arg_count++] = data;
602
603 memory = tgsi_full_src_register_from_dst(&inst->Dst[0]);
604
605 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
606 LLVMValueRef offset;
607 LLVMValueRef tmp;
608
609 rsrc = shader_buffer_fetch_rsrc(ctx, &memory, false);
610
611 tmp = lp_build_emit_fetch(bld_base, inst, 0, 0);
612 offset = ac_to_integer(&ctx->ac, tmp);
613
614 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
615 offset, false, false);
616 } else if (inst->Dst[0].Register.File == TGSI_FILE_IMAGE ||
617 tgsi_is_bindless_image_file(inst->Dst[0].Register.File)) {
618 unsigned target = inst->Memory.Texture;
619
620 /* 8bit/16bit TC L1 write corruption bug on SI.
621 * All store opcodes not aligned to a dword are affected.
622 *
623 * The only way to get unaligned stores in radeonsi is through
624 * shader images.
625 */
626 bool force_glc = ctx->screen->info.chip_class == SI;
627
628 image_fetch_rsrc(bld_base, &memory, true, target, &rsrc);
629 image_fetch_coords(bld_base, inst, 0, rsrc, &emit_data->args[2]);
630
631 if (target == TGSI_TEXTURE_BUFFER) {
632 buffer_append_args(ctx, emit_data, rsrc, emit_data->args[2],
633 ctx->i32_0, false, force_glc);
634 } else {
635 emit_data->args[1] = rsrc;
636 }
637 }
638 }
639
640 static void store_emit_buffer(
641 struct si_shader_context *ctx,
642 struct lp_build_emit_data *emit_data,
643 bool writeonly_memory)
644 {
645 const struct tgsi_full_instruction *inst = emit_data->inst;
646 LLVMBuilderRef builder = ctx->ac.builder;
647 LLVMValueRef base_data = emit_data->args[0];
648 LLVMValueRef base_offset = emit_data->args[3];
649 unsigned writemask = inst->Dst[0].Register.WriteMask;
650
651 /* If this is write-only, don't keep data in L1 to prevent
652 * evicting L1 cache lines that may be needed by other
653 * instructions.
654 */
655 if (writeonly_memory)
656 emit_data->args[4] = LLVMConstInt(ctx->i1, 1, 0); /* GLC = 1 */
657
658 while (writemask) {
659 int start, count;
660 const char *intrinsic_name;
661 LLVMValueRef data;
662 LLVMValueRef offset;
663 LLVMValueRef tmp;
664
665 u_bit_scan_consecutive_range(&writemask, &start, &count);
666
667 /* Due to an LLVM limitation, split 3-element writes
668 * into a 2-element and a 1-element write. */
669 if (count == 3) {
670 writemask |= 1 << (start + 2);
671 count = 2;
672 }
673
674 if (count == 4) {
675 data = base_data;
676 intrinsic_name = "llvm.amdgcn.buffer.store.v4f32";
677 } else if (count == 2) {
678 LLVMTypeRef v2f32 = LLVMVectorType(ctx->f32, 2);
679
680 tmp = LLVMBuildExtractElement(
681 builder, base_data,
682 LLVMConstInt(ctx->i32, start, 0), "");
683 data = LLVMBuildInsertElement(
684 builder, LLVMGetUndef(v2f32), tmp,
685 ctx->i32_0, "");
686
687 tmp = LLVMBuildExtractElement(
688 builder, base_data,
689 LLVMConstInt(ctx->i32, start + 1, 0), "");
690 data = LLVMBuildInsertElement(
691 builder, data, tmp, ctx->i32_1, "");
692
693 intrinsic_name = "llvm.amdgcn.buffer.store.v2f32";
694 } else {
695 assert(count == 1);
696 data = LLVMBuildExtractElement(
697 builder, base_data,
698 LLVMConstInt(ctx->i32, start, 0), "");
699 intrinsic_name = "llvm.amdgcn.buffer.store.f32";
700 }
701
702 offset = base_offset;
703 if (start != 0) {
704 offset = LLVMBuildAdd(
705 builder, offset,
706 LLVMConstInt(ctx->i32, start * 4, 0), "");
707 }
708
709 emit_data->args[0] = data;
710 emit_data->args[3] = offset;
711
712 ac_build_intrinsic(
713 &ctx->ac, intrinsic_name, emit_data->dst_type,
714 emit_data->args, emit_data->arg_count,
715 ac_get_store_intr_attribs(writeonly_memory));
716 }
717 }
718
719 static void store_emit_memory(
720 struct si_shader_context *ctx,
721 struct lp_build_emit_data *emit_data)
722 {
723 const struct tgsi_full_instruction *inst = emit_data->inst;
724 LLVMBuilderRef builder = ctx->ac.builder;
725 unsigned writemask = inst->Dst[0].Register.WriteMask;
726 LLVMValueRef ptr, derived_ptr, data, index;
727 int chan;
728
729 ptr = get_memory_ptr(ctx, inst, ctx->f32, 0);
730
731 for (chan = 0; chan < 4; ++chan) {
732 if (!(writemask & (1 << chan))) {
733 continue;
734 }
735 data = lp_build_emit_fetch(&ctx->bld_base, inst, 1, chan);
736 index = LLVMConstInt(ctx->i32, chan, 0);
737 derived_ptr = LLVMBuildGEP(builder, ptr, &index, 1, "");
738 LLVMBuildStore(builder, data, derived_ptr);
739 }
740 }
741
742 static void store_emit(
743 const struct lp_build_tgsi_action *action,
744 struct lp_build_tgsi_context *bld_base,
745 struct lp_build_emit_data *emit_data)
746 {
747 struct si_shader_context *ctx = si_shader_context(bld_base);
748 const struct tgsi_full_instruction * inst = emit_data->inst;
749 const struct tgsi_shader_info *info = &ctx->shader->selector->info;
750 unsigned target = inst->Memory.Texture;
751 bool writeonly_memory = false;
752
753 if (inst->Dst[0].Register.File == TGSI_FILE_MEMORY) {
754 store_emit_memory(ctx, emit_data);
755 return;
756 }
757
758 if (inst->Memory.Qualifier & TGSI_MEMORY_VOLATILE)
759 ac_build_waitcnt(&ctx->ac, VM_CNT);
760
761 writeonly_memory = is_oneway_access_only(inst, info,
762 info->shader_buffers_load |
763 info->shader_buffers_atomic,
764 info->images_load |
765 info->images_atomic);
766
767 if (inst->Dst[0].Register.File == TGSI_FILE_BUFFER) {
768 store_emit_buffer(ctx, emit_data, writeonly_memory);
769 return;
770 }
771
772 if (target == TGSI_TEXTURE_BUFFER) {
773 /* If this is write-only, don't keep data in L1 to prevent
774 * evicting L1 cache lines that may be needed by other
775 * instructions.
776 */
777 if (writeonly_memory)
778 emit_data->args[4] = LLVMConstInt(ctx->i1, 1, 0); /* GLC = 1 */
779
780 emit_data->output[emit_data->chan] = ac_build_intrinsic(
781 &ctx->ac, "llvm.amdgcn.buffer.store.format.v4f32",
782 emit_data->dst_type, emit_data->args,
783 emit_data->arg_count,
784 ac_get_store_intr_attribs(writeonly_memory));
785 } else {
786 struct ac_image_args args = {};
787 args.opcode = ac_image_store;
788 args.data[0] = emit_data->args[0];
789 args.resource = emit_data->args[1];
790 memcpy(args.coords, &emit_data->args[2], sizeof(args.coords));
791 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
792 args.attributes = ac_get_store_intr_attribs(writeonly_memory);
793 args.dmask = 0xf;
794
795 /* Workaround for 8bit/16bit TC L1 write corruption bug on SI.
796 * All store opcodes not aligned to a dword are affected.
797 */
798 if (ctx->screen->info.chip_class == SI ||
799 /* If this is write-only, don't keep data in L1 to prevent
800 * evicting L1 cache lines that may be needed by other
801 * instructions. */
802 writeonly_memory ||
803 inst->Memory.Qualifier & (TGSI_MEMORY_COHERENT | TGSI_MEMORY_VOLATILE))
804 args.cache_policy = ac_glc;
805
806 emit_data->output[emit_data->chan] =
807 ac_build_image_opcode(&ctx->ac, &args);
808 }
809 }
810
811 static void atomic_fetch_args(
812 struct lp_build_tgsi_context * bld_base,
813 struct lp_build_emit_data * emit_data)
814 {
815 struct si_shader_context *ctx = si_shader_context(bld_base);
816 const struct tgsi_full_instruction * inst = emit_data->inst;
817 LLVMValueRef data1, data2;
818 LLVMValueRef rsrc;
819 LLVMValueRef tmp;
820
821 emit_data->dst_type = ctx->f32;
822
823 tmp = lp_build_emit_fetch(bld_base, inst, 2, 0);
824 data1 = ac_to_integer(&ctx->ac, tmp);
825
826 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
827 tmp = lp_build_emit_fetch(bld_base, inst, 3, 0);
828 data2 = ac_to_integer(&ctx->ac, tmp);
829 }
830
831 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
832 * of arguments, which is reversed relative to TGSI (and GLSL)
833 */
834 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS)
835 emit_data->args[emit_data->arg_count++] = data2;
836 emit_data->args[emit_data->arg_count++] = data1;
837
838 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
839 LLVMValueRef offset;
840
841 rsrc = shader_buffer_fetch_rsrc(ctx, &inst->Src[0], false);
842
843 tmp = lp_build_emit_fetch(bld_base, inst, 1, 0);
844 offset = ac_to_integer(&ctx->ac, tmp);
845
846 buffer_append_args(ctx, emit_data, rsrc, ctx->i32_0,
847 offset, true, false);
848 } else if (inst->Src[0].Register.File == TGSI_FILE_IMAGE ||
849 tgsi_is_bindless_image_file(inst->Src[0].Register.File)) {
850 unsigned target = inst->Memory.Texture;
851
852 image_fetch_rsrc(bld_base, &inst->Src[0], true, target, &rsrc);
853 image_fetch_coords(bld_base, inst, 1, rsrc,
854 &emit_data->args[emit_data->arg_count + 1]);
855
856 if (target == TGSI_TEXTURE_BUFFER) {
857 buffer_append_args(ctx, emit_data, rsrc,
858 emit_data->args[emit_data->arg_count + 1],
859 ctx->i32_0, true, false);
860 } else {
861 emit_data->args[emit_data->arg_count] = rsrc;
862 }
863 }
864 }
865
866 static void atomic_emit_memory(struct si_shader_context *ctx,
867 struct lp_build_emit_data *emit_data) {
868 LLVMBuilderRef builder = ctx->ac.builder;
869 const struct tgsi_full_instruction * inst = emit_data->inst;
870 LLVMValueRef ptr, result, arg;
871
872 ptr = get_memory_ptr(ctx, inst, ctx->i32, 1);
873
874 arg = lp_build_emit_fetch(&ctx->bld_base, inst, 2, 0);
875 arg = ac_to_integer(&ctx->ac, arg);
876
877 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
878 LLVMValueRef new_data;
879 new_data = lp_build_emit_fetch(&ctx->bld_base,
880 inst, 3, 0);
881
882 new_data = ac_to_integer(&ctx->ac, new_data);
883
884 result = LLVMBuildAtomicCmpXchg(builder, ptr, arg, new_data,
885 LLVMAtomicOrderingSequentiallyConsistent,
886 LLVMAtomicOrderingSequentiallyConsistent,
887 false);
888
889 result = LLVMBuildExtractValue(builder, result, 0, "");
890 } else {
891 LLVMAtomicRMWBinOp op;
892
893 switch(inst->Instruction.Opcode) {
894 case TGSI_OPCODE_ATOMUADD:
895 op = LLVMAtomicRMWBinOpAdd;
896 break;
897 case TGSI_OPCODE_ATOMXCHG:
898 op = LLVMAtomicRMWBinOpXchg;
899 break;
900 case TGSI_OPCODE_ATOMAND:
901 op = LLVMAtomicRMWBinOpAnd;
902 break;
903 case TGSI_OPCODE_ATOMOR:
904 op = LLVMAtomicRMWBinOpOr;
905 break;
906 case TGSI_OPCODE_ATOMXOR:
907 op = LLVMAtomicRMWBinOpXor;
908 break;
909 case TGSI_OPCODE_ATOMUMIN:
910 op = LLVMAtomicRMWBinOpUMin;
911 break;
912 case TGSI_OPCODE_ATOMUMAX:
913 op = LLVMAtomicRMWBinOpUMax;
914 break;
915 case TGSI_OPCODE_ATOMIMIN:
916 op = LLVMAtomicRMWBinOpMin;
917 break;
918 case TGSI_OPCODE_ATOMIMAX:
919 op = LLVMAtomicRMWBinOpMax;
920 break;
921 default:
922 unreachable("unknown atomic opcode");
923 }
924
925 result = LLVMBuildAtomicRMW(builder, op, ptr, arg,
926 LLVMAtomicOrderingSequentiallyConsistent,
927 false);
928 }
929 emit_data->output[emit_data->chan] = LLVMBuildBitCast(builder, result, emit_data->dst_type, "");
930 }
931
932 static void atomic_emit(
933 const struct lp_build_tgsi_action *action,
934 struct lp_build_tgsi_context *bld_base,
935 struct lp_build_emit_data *emit_data)
936 {
937 struct si_shader_context *ctx = si_shader_context(bld_base);
938 const struct tgsi_full_instruction * inst = emit_data->inst;
939 LLVMValueRef tmp;
940
941 if (inst->Src[0].Register.File == TGSI_FILE_MEMORY) {
942 atomic_emit_memory(ctx, emit_data);
943 return;
944 }
945
946 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER ||
947 inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
948 char intrinsic_name[40];
949 snprintf(intrinsic_name, sizeof(intrinsic_name),
950 "llvm.amdgcn.buffer.atomic.%s", action->intr_name);
951 tmp = ac_build_intrinsic(
952 &ctx->ac, intrinsic_name, ctx->i32,
953 emit_data->args, emit_data->arg_count, 0);
954 emit_data->output[emit_data->chan] = ac_to_float(&ctx->ac, tmp);
955 } else {
956 unsigned num_data = inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS ? 2 : 1;
957 struct ac_image_args args = {};
958
959 if (inst->Instruction.Opcode == TGSI_OPCODE_ATOMCAS) {
960 args.opcode = ac_image_atomic_cmpswap;
961 } else {
962 args.opcode = ac_image_atomic;
963 switch (inst->Instruction.Opcode) {
964 case TGSI_OPCODE_ATOMXCHG: args.atomic = ac_atomic_swap; break;
965 case TGSI_OPCODE_ATOMUADD: args.atomic = ac_atomic_add; break;
966 case TGSI_OPCODE_ATOMAND: args.atomic = ac_atomic_and; break;
967 case TGSI_OPCODE_ATOMOR: args.atomic = ac_atomic_or; break;
968 case TGSI_OPCODE_ATOMXOR: args.atomic = ac_atomic_xor; break;
969 case TGSI_OPCODE_ATOMUMIN: args.atomic = ac_atomic_umin; break;
970 case TGSI_OPCODE_ATOMUMAX: args.atomic = ac_atomic_umax; break;
971 case TGSI_OPCODE_ATOMIMIN: args.atomic = ac_atomic_smin; break;
972 case TGSI_OPCODE_ATOMIMAX: args.atomic = ac_atomic_smax; break;
973 default: unreachable("unhandled image atomic");
974 }
975 }
976
977 for (unsigned i = 0; i < num_data; ++i)
978 args.data[i] = emit_data->args[i];
979
980 args.resource = emit_data->args[num_data];
981 memcpy(args.coords, &emit_data->args[num_data + 1], sizeof(args.coords));
982 args.dim = ac_image_dim_from_tgsi_target(ctx->screen, inst->Memory.Texture);
983
984 emit_data->output[emit_data->chan] =
985 ac_to_float(&ctx->ac, ac_build_image_opcode(&ctx->ac, &args));
986 }
987 }
988
989 static void set_tex_fetch_args(struct si_shader_context *ctx,
990 struct lp_build_emit_data *emit_data,
991 struct ac_image_args *args,
992 unsigned target)
993 {
994 args->dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
995 args->unorm = target == TGSI_TEXTURE_RECT ||
996 target == TGSI_TEXTURE_SHADOWRECT;
997
998 /* Ugly, but we seem to have no other choice right now. */
999 STATIC_ASSERT(sizeof(*args) <= sizeof(emit_data->args));
1000 memcpy(emit_data->args, args, sizeof(*args));
1001 }
1002
1003 static LLVMValueRef fix_resinfo(struct si_shader_context *ctx,
1004 unsigned target, LLVMValueRef out)
1005 {
1006 LLVMBuilderRef builder = ctx->ac.builder;
1007
1008 /* 1D textures are allocated and used as 2D on GFX9. */
1009 if (ctx->screen->info.chip_class >= GFX9 &&
1010 (target == TGSI_TEXTURE_1D_ARRAY ||
1011 target == TGSI_TEXTURE_SHADOW1D_ARRAY)) {
1012 LLVMValueRef layers =
1013 LLVMBuildExtractElement(builder, out,
1014 LLVMConstInt(ctx->i32, 2, 0), "");
1015 out = LLVMBuildInsertElement(builder, out, layers,
1016 ctx->i32_1, "");
1017 }
1018
1019 /* Divide the number of layers by 6 to get the number of cubes. */
1020 if (target == TGSI_TEXTURE_CUBE_ARRAY ||
1021 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1022 LLVMValueRef imm2 = LLVMConstInt(ctx->i32, 2, 0);
1023
1024 LLVMValueRef z = LLVMBuildExtractElement(builder, out, imm2, "");
1025 z = LLVMBuildSDiv(builder, z, LLVMConstInt(ctx->i32, 6, 0), "");
1026
1027 out = LLVMBuildInsertElement(builder, out, z, imm2, "");
1028 }
1029 return out;
1030 }
1031
1032 static void resq_fetch_args(
1033 struct lp_build_tgsi_context * bld_base,
1034 struct lp_build_emit_data * emit_data)
1035 {
1036 struct si_shader_context *ctx = si_shader_context(bld_base);
1037 const struct tgsi_full_instruction *inst = emit_data->inst;
1038 const struct tgsi_full_src_register *reg = &inst->Src[0];
1039
1040 emit_data->dst_type = ctx->v4i32;
1041
1042 if (reg->Register.File == TGSI_FILE_BUFFER) {
1043 emit_data->args[0] = shader_buffer_fetch_rsrc(ctx, reg, false);
1044 emit_data->arg_count = 1;
1045 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
1046 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
1047 &emit_data->args[0]);
1048 emit_data->arg_count = 1;
1049 } else {
1050 struct ac_image_args args = {};
1051 unsigned image_target;
1052
1053 if (inst->Memory.Texture == TGSI_TEXTURE_3D)
1054 image_target = TGSI_TEXTURE_2D_ARRAY;
1055 else
1056 image_target = inst->Memory.Texture;
1057
1058 image_fetch_rsrc(bld_base, reg, false, inst->Memory.Texture,
1059 &args.resource);
1060 args.lod = ctx->i32_0;
1061 args.dmask = 0xf;
1062 set_tex_fetch_args(ctx, emit_data, &args, image_target);
1063 }
1064 }
1065
1066 static void resq_emit(
1067 const struct lp_build_tgsi_action *action,
1068 struct lp_build_tgsi_context *bld_base,
1069 struct lp_build_emit_data *emit_data)
1070 {
1071 struct si_shader_context *ctx = si_shader_context(bld_base);
1072 LLVMBuilderRef builder = ctx->ac.builder;
1073 const struct tgsi_full_instruction *inst = emit_data->inst;
1074 LLVMValueRef out;
1075
1076 if (inst->Src[0].Register.File == TGSI_FILE_BUFFER) {
1077 out = LLVMBuildExtractElement(builder, emit_data->args[0],
1078 LLVMConstInt(ctx->i32, 2, 0), "");
1079 } else if (inst->Memory.Texture == TGSI_TEXTURE_BUFFER) {
1080 out = get_buffer_size(bld_base, emit_data->args[0]);
1081 } else {
1082 struct ac_image_args args;
1083
1084 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
1085 args.opcode = ac_image_get_resinfo;
1086 out = ac_build_image_opcode(&ctx->ac, &args);
1087
1088 out = fix_resinfo(ctx, inst->Memory.Texture, out);
1089 }
1090
1091 emit_data->output[emit_data->chan] = out;
1092 }
1093
1094 /**
1095 * Load an image view, fmask view. or sampler state descriptor.
1096 */
1097 LLVMValueRef si_load_sampler_desc(struct si_shader_context *ctx,
1098 LLVMValueRef list, LLVMValueRef index,
1099 enum ac_descriptor_type type)
1100 {
1101 LLVMBuilderRef builder = ctx->ac.builder;
1102
1103 switch (type) {
1104 case AC_DESC_IMAGE:
1105 /* The image is at [0:7]. */
1106 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1107 break;
1108 case AC_DESC_BUFFER:
1109 /* The buffer is in [4:7]. */
1110 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
1111 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
1112 list = LLVMBuildPointerCast(builder, list,
1113 ac_array_in_const32_addr_space(ctx->v4i32), "");
1114 break;
1115 case AC_DESC_FMASK:
1116 /* The FMASK is at [8:15]. */
1117 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 2, 0), "");
1118 index = LLVMBuildAdd(builder, index, ctx->i32_1, "");
1119 break;
1120 case AC_DESC_SAMPLER:
1121 /* The sampler state is at [12:15]. */
1122 index = LLVMBuildMul(builder, index, LLVMConstInt(ctx->i32, 4, 0), "");
1123 index = LLVMBuildAdd(builder, index, LLVMConstInt(ctx->i32, 3, 0), "");
1124 list = LLVMBuildPointerCast(builder, list,
1125 ac_array_in_const32_addr_space(ctx->v4i32), "");
1126 break;
1127 }
1128
1129 return ac_build_load_to_sgpr(&ctx->ac, list, index);
1130 }
1131
1132 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1133 *
1134 * SI-CI:
1135 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1136 * filtering manually. The driver sets img7 to a mask clearing
1137 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1138 * s_and_b32 samp0, samp0, img7
1139 *
1140 * VI:
1141 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1142 */
1143 static LLVMValueRef sici_fix_sampler_aniso(struct si_shader_context *ctx,
1144 LLVMValueRef res, LLVMValueRef samp)
1145 {
1146 LLVMValueRef img7, samp0;
1147
1148 if (ctx->screen->info.chip_class >= VI)
1149 return samp;
1150
1151 img7 = LLVMBuildExtractElement(ctx->ac.builder, res,
1152 LLVMConstInt(ctx->i32, 7, 0), "");
1153 samp0 = LLVMBuildExtractElement(ctx->ac.builder, samp,
1154 ctx->i32_0, "");
1155 samp0 = LLVMBuildAnd(ctx->ac.builder, samp0, img7, "");
1156 return LLVMBuildInsertElement(ctx->ac.builder, samp, samp0,
1157 ctx->i32_0, "");
1158 }
1159
1160 static void tex_fetch_ptrs(
1161 struct lp_build_tgsi_context *bld_base,
1162 struct lp_build_emit_data *emit_data,
1163 LLVMValueRef *res_ptr, LLVMValueRef *samp_ptr, LLVMValueRef *fmask_ptr)
1164 {
1165 struct si_shader_context *ctx = si_shader_context(bld_base);
1166 LLVMValueRef list = LLVMGetParam(ctx->main_fn, ctx->param_samplers_and_images);
1167 const struct tgsi_full_instruction *inst = emit_data->inst;
1168 const struct tgsi_full_src_register *reg;
1169 unsigned target = inst->Texture.Texture;
1170 unsigned sampler_src;
1171 LLVMValueRef index;
1172
1173 sampler_src = emit_data->inst->Instruction.NumSrcRegs - 1;
1174 reg = &emit_data->inst->Src[sampler_src];
1175
1176 if (reg->Register.Indirect) {
1177 index = si_get_bounded_indirect_index(ctx,
1178 &reg->Indirect,
1179 reg->Register.Index,
1180 ctx->num_samplers);
1181 index = LLVMBuildAdd(ctx->ac.builder, index,
1182 LLVMConstInt(ctx->i32, SI_NUM_IMAGES / 2, 0), "");
1183 } else {
1184 index = LLVMConstInt(ctx->i32,
1185 si_get_sampler_slot(reg->Register.Index), 0);
1186 }
1187
1188 if (reg->Register.File != TGSI_FILE_SAMPLER) {
1189 /* Bindless descriptors are accessible from a different pair of
1190 * user SGPR indices.
1191 */
1192 list = LLVMGetParam(ctx->main_fn,
1193 ctx->param_bindless_samplers_and_images);
1194 index = lp_build_emit_fetch_src(bld_base, reg,
1195 TGSI_TYPE_UNSIGNED, 0);
1196 }
1197
1198 if (target == TGSI_TEXTURE_BUFFER)
1199 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_BUFFER);
1200 else
1201 *res_ptr = si_load_sampler_desc(ctx, list, index, AC_DESC_IMAGE);
1202
1203 if (samp_ptr)
1204 *samp_ptr = NULL;
1205 if (fmask_ptr)
1206 *fmask_ptr = NULL;
1207
1208 if (target == TGSI_TEXTURE_2D_MSAA ||
1209 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1210 if (fmask_ptr)
1211 *fmask_ptr = si_load_sampler_desc(ctx, list, index,
1212 AC_DESC_FMASK);
1213 } else if (target != TGSI_TEXTURE_BUFFER) {
1214 if (samp_ptr) {
1215 *samp_ptr = si_load_sampler_desc(ctx, list, index,
1216 AC_DESC_SAMPLER);
1217 *samp_ptr = sici_fix_sampler_aniso(ctx, *res_ptr, *samp_ptr);
1218 }
1219 }
1220 }
1221
1222 static void txq_fetch_args(
1223 struct lp_build_tgsi_context *bld_base,
1224 struct lp_build_emit_data *emit_data)
1225 {
1226 struct si_shader_context *ctx = si_shader_context(bld_base);
1227 const struct tgsi_full_instruction *inst = emit_data->inst;
1228 unsigned target = inst->Texture.Texture;
1229 struct ac_image_args args = {};
1230
1231 tex_fetch_ptrs(bld_base, emit_data, &args.resource, NULL, NULL);
1232
1233 if (target == TGSI_TEXTURE_BUFFER) {
1234 /* Read the size from the buffer descriptor directly. */
1235 emit_data->args[0] = get_buffer_size(bld_base, args.resource);
1236 return;
1237 }
1238
1239 /* Textures - set the mip level. */
1240 args.lod = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1241 args.dmask = 0xf;
1242
1243 set_tex_fetch_args(ctx, emit_data, &args, target);
1244 }
1245
1246 static void txq_emit(const struct lp_build_tgsi_action *action,
1247 struct lp_build_tgsi_context *bld_base,
1248 struct lp_build_emit_data *emit_data)
1249 {
1250 struct si_shader_context *ctx = si_shader_context(bld_base);
1251 struct ac_image_args args;
1252 unsigned target = emit_data->inst->Texture.Texture;
1253
1254 if (target == TGSI_TEXTURE_BUFFER) {
1255 /* Just return the buffer size. */
1256 emit_data->output[emit_data->chan] = emit_data->args[0];
1257 return;
1258 }
1259
1260 memcpy(&args, emit_data->args, sizeof(args)); /* ugly */
1261
1262 args.opcode = ac_image_get_resinfo;
1263 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
1264
1265 emit_data->output[emit_data->chan] = fix_resinfo(ctx, target, result);
1266 }
1267
1268 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1269 * incorrectly forces nearest filtering if the texture format is integer.
1270 * The only effect it has on Gather4, which always returns 4 texels for
1271 * bilinear filtering, is that the final coordinates are off by 0.5 of
1272 * the texel size.
1273 *
1274 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1275 * or (0.5 / size) from the normalized coordinates.
1276 *
1277 * However, cube textures with 8_8_8_8 data formats require a different
1278 * workaround of overriding the num format to USCALED/SSCALED. This would lose
1279 * precision in 32-bit data formats, so it needs to be applied dynamically at
1280 * runtime. In this case, return an i1 value that indicates whether the
1281 * descriptor was overridden (and hence a fixup of the sampler result is needed).
1282 */
1283 static LLVMValueRef
1284 si_lower_gather4_integer(struct si_shader_context *ctx,
1285 struct ac_image_args *args,
1286 unsigned target,
1287 enum tgsi_return_type return_type)
1288 {
1289 LLVMBuilderRef builder = ctx->ac.builder;
1290 LLVMValueRef wa_8888 = NULL;
1291 LLVMValueRef half_texel[2];
1292
1293 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1294 return_type == TGSI_RETURN_TYPE_UINT);
1295
1296 if (target == TGSI_TEXTURE_CUBE ||
1297 target == TGSI_TEXTURE_CUBE_ARRAY) {
1298 LLVMValueRef formats;
1299 LLVMValueRef data_format;
1300 LLVMValueRef wa_formats;
1301
1302 formats = LLVMBuildExtractElement(builder, args->resource, ctx->i32_1, "");
1303
1304 data_format = LLVMBuildLShr(builder, formats,
1305 LLVMConstInt(ctx->i32, 20, false), "");
1306 data_format = LLVMBuildAnd(builder, data_format,
1307 LLVMConstInt(ctx->i32, (1u << 6) - 1, false), "");
1308 wa_8888 = LLVMBuildICmp(
1309 builder, LLVMIntEQ, data_format,
1310 LLVMConstInt(ctx->i32, V_008F14_IMG_DATA_FORMAT_8_8_8_8, false),
1311 "");
1312
1313 uint32_t wa_num_format =
1314 return_type == TGSI_RETURN_TYPE_UINT ?
1315 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_USCALED) :
1316 S_008F14_NUM_FORMAT_GFX6(V_008F14_IMG_NUM_FORMAT_SSCALED);
1317 wa_formats = LLVMBuildAnd(builder, formats,
1318 LLVMConstInt(ctx->i32, C_008F14_NUM_FORMAT_GFX6, false),
1319 "");
1320 wa_formats = LLVMBuildOr(builder, wa_formats,
1321 LLVMConstInt(ctx->i32, wa_num_format, false), "");
1322
1323 formats = LLVMBuildSelect(builder, wa_8888, wa_formats, formats, "");
1324 args->resource = LLVMBuildInsertElement(
1325 builder, args->resource, formats, ctx->i32_1, "");
1326 }
1327
1328 if (target == TGSI_TEXTURE_RECT ||
1329 target == TGSI_TEXTURE_SHADOWRECT) {
1330 assert(!wa_8888);
1331 half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
1332 } else {
1333 struct ac_image_args resinfo = {};
1334 struct lp_build_if_state if_ctx;
1335
1336 if (wa_8888) {
1337 /* Skip the texture size query entirely if we don't need it. */
1338 lp_build_if(&if_ctx, &ctx->gallivm, LLVMBuildNot(builder, wa_8888, ""));
1339 }
1340
1341 /* Query the texture size. */
1342 resinfo.opcode = ac_image_get_resinfo;
1343 resinfo.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1344 resinfo.resource = args->resource;
1345 resinfo.sampler = args->sampler;
1346 resinfo.lod = ctx->ac.i32_0;
1347 resinfo.dmask = 0xf;
1348
1349 LLVMValueRef texsize =
1350 fix_resinfo(ctx, target,
1351 ac_build_image_opcode(&ctx->ac, &resinfo));
1352
1353 /* Compute -0.5 / size. */
1354 for (unsigned c = 0; c < 2; c++) {
1355 half_texel[c] =
1356 LLVMBuildExtractElement(builder, texsize,
1357 LLVMConstInt(ctx->i32, c, 0), "");
1358 half_texel[c] = LLVMBuildUIToFP(builder, half_texel[c], ctx->f32, "");
1359 half_texel[c] = ac_build_fdiv(&ctx->ac, ctx->ac.f32_1, half_texel[c]);
1360 half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
1361 LLVMConstReal(ctx->f32, -0.5), "");
1362 }
1363
1364 if (wa_8888) {
1365 lp_build_endif(&if_ctx);
1366
1367 LLVMBasicBlockRef bb[2] = { if_ctx.true_block, if_ctx.entry_block };
1368
1369 for (unsigned c = 0; c < 2; c++) {
1370 LLVMValueRef values[2] = { half_texel[c], ctx->ac.f32_0 };
1371 half_texel[c] = ac_build_phi(&ctx->ac, ctx->f32, 2,
1372 values, bb);
1373 }
1374 }
1375 }
1376
1377 for (unsigned c = 0; c < 2; c++) {
1378 LLVMValueRef tmp;
1379 tmp = ac_to_float(&ctx->ac, args->coords[c]);
1380 tmp = LLVMBuildFAdd(builder, tmp, half_texel[c], "");
1381 args->coords[c] = ac_to_integer(&ctx->ac, tmp);
1382 }
1383
1384 return wa_8888;
1385 }
1386
1387 /* The second half of the cube texture 8_8_8_8 integer workaround: adjust the
1388 * result after the gather operation.
1389 */
1390 static LLVMValueRef
1391 si_fix_gather4_integer_result(struct si_shader_context *ctx,
1392 LLVMValueRef result,
1393 enum tgsi_return_type return_type,
1394 LLVMValueRef wa)
1395 {
1396 LLVMBuilderRef builder = ctx->ac.builder;
1397
1398 assert(return_type == TGSI_RETURN_TYPE_SINT ||
1399 return_type == TGSI_RETURN_TYPE_UINT);
1400
1401 for (unsigned chan = 0; chan < 4; ++chan) {
1402 LLVMValueRef chanv = LLVMConstInt(ctx->i32, chan, false);
1403 LLVMValueRef value;
1404 LLVMValueRef wa_value;
1405
1406 value = LLVMBuildExtractElement(builder, result, chanv, "");
1407
1408 if (return_type == TGSI_RETURN_TYPE_UINT)
1409 wa_value = LLVMBuildFPToUI(builder, value, ctx->i32, "");
1410 else
1411 wa_value = LLVMBuildFPToSI(builder, value, ctx->i32, "");
1412 wa_value = ac_to_float(&ctx->ac, wa_value);
1413 value = LLVMBuildSelect(builder, wa, wa_value, value, "");
1414
1415 result = LLVMBuildInsertElement(builder, result, value, chanv, "");
1416 }
1417
1418 return result;
1419 }
1420
1421 static void build_tex_intrinsic(const struct lp_build_tgsi_action *action,
1422 struct lp_build_tgsi_context *bld_base,
1423 struct lp_build_emit_data *emit_data)
1424 {
1425 struct si_shader_context *ctx = si_shader_context(bld_base);
1426 const struct tgsi_full_instruction *inst = emit_data->inst;
1427 unsigned opcode = inst->Instruction.Opcode;
1428 unsigned target = inst->Texture.Texture;
1429 struct ac_image_args args = {};
1430 int ref_pos = tgsi_util_get_shadow_ref_src_index(target);
1431 unsigned chan;
1432 bool has_offset = inst->Texture.NumOffsets > 0;
1433 LLVMValueRef fmask_ptr = NULL;
1434
1435 tex_fetch_ptrs(bld_base, emit_data, &args.resource, &args.sampler, &fmask_ptr);
1436
1437 if (target == TGSI_TEXTURE_BUFFER) {
1438 LLVMValueRef vindex = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_X);
1439 unsigned num_channels =
1440 util_last_bit(inst->Dst[0].Register.WriteMask);
1441 LLVMValueRef result =
1442 ac_build_buffer_load_format(&ctx->ac,
1443 args.resource,
1444 vindex,
1445 ctx->i32_0,
1446 num_channels, false, true);
1447 emit_data->output[emit_data->chan] =
1448 ac_build_expand_to_vec4(&ctx->ac, result, num_channels);
1449 return;
1450 }
1451
1452 /* Fetch and project texture coordinates */
1453 args.coords[3] = lp_build_emit_fetch(bld_base, inst, 0, TGSI_CHAN_W);
1454 for (chan = 0; chan < 3; chan++) {
1455 args.coords[chan] = lp_build_emit_fetch(bld_base, inst, 0, chan);
1456 if (opcode == TGSI_OPCODE_TXP)
1457 args.coords[chan] = ac_build_fdiv(&ctx->ac,
1458 args.coords[chan], args.coords[3]);
1459 }
1460
1461 if (opcode == TGSI_OPCODE_TXP)
1462 args.coords[3] = ctx->ac.f32_1;
1463
1464 /* Pack offsets. */
1465 if (has_offset &&
1466 opcode != TGSI_OPCODE_TXF &&
1467 opcode != TGSI_OPCODE_TXF_LZ) {
1468 /* The offsets are six-bit signed integers packed like this:
1469 * X=[5:0], Y=[13:8], and Z=[21:16].
1470 */
1471 LLVMValueRef offset[3], pack;
1472
1473 assert(inst->Texture.NumOffsets == 1);
1474
1475 for (chan = 0; chan < 3; chan++) {
1476 offset[chan] = lp_build_emit_fetch_texoffset(bld_base, inst, 0, chan);
1477 offset[chan] = LLVMBuildAnd(ctx->ac.builder, offset[chan],
1478 LLVMConstInt(ctx->i32, 0x3f, 0), "");
1479 if (chan)
1480 offset[chan] = LLVMBuildShl(ctx->ac.builder, offset[chan],
1481 LLVMConstInt(ctx->i32, chan*8, 0), "");
1482 }
1483
1484 pack = LLVMBuildOr(ctx->ac.builder, offset[0], offset[1], "");
1485 pack = LLVMBuildOr(ctx->ac.builder, pack, offset[2], "");
1486 args.offset = pack;
1487 }
1488
1489 /* Pack LOD bias value */
1490 if (opcode == TGSI_OPCODE_TXB)
1491 args.bias = args.coords[3];
1492 if (opcode == TGSI_OPCODE_TXB2)
1493 args.bias = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1494
1495 /* Pack depth comparison value */
1496 if (tgsi_is_shadow_target(target) && opcode != TGSI_OPCODE_LODQ) {
1497 LLVMValueRef z;
1498
1499 if (target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1500 z = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1501 } else {
1502 assert(ref_pos >= 0);
1503 z = args.coords[ref_pos];
1504 }
1505
1506 /* Section 8.23.1 (Depth Texture Comparison Mode) of the
1507 * OpenGL 4.5 spec says:
1508 *
1509 * "If the texture’s internal format indicates a fixed-point
1510 * depth texture, then D_t and D_ref are clamped to the
1511 * range [0, 1]; otherwise no clamping is performed."
1512 *
1513 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1514 * so the depth comparison value isn't clamped for Z16 and
1515 * Z24 anymore. Do it manually here.
1516 */
1517 if (ctx->screen->info.chip_class >= VI) {
1518 LLVMValueRef upgraded;
1519 LLVMValueRef clamped;
1520 upgraded = LLVMBuildExtractElement(ctx->ac.builder, args.sampler,
1521 LLVMConstInt(ctx->i32, 3, false), "");
1522 upgraded = LLVMBuildLShr(ctx->ac.builder, upgraded,
1523 LLVMConstInt(ctx->i32, 29, false), "");
1524 upgraded = LLVMBuildTrunc(ctx->ac.builder, upgraded, ctx->i1, "");
1525 clamped = ac_build_clamp(&ctx->ac, z);
1526 z = LLVMBuildSelect(ctx->ac.builder, upgraded, clamped, z, "");
1527 }
1528
1529 args.compare = z;
1530 }
1531
1532 /* Pack user derivatives */
1533 if (opcode == TGSI_OPCODE_TXD) {
1534 int param, num_src_deriv_channels, num_dst_deriv_channels;
1535
1536 switch (target) {
1537 case TGSI_TEXTURE_3D:
1538 num_src_deriv_channels = 3;
1539 num_dst_deriv_channels = 3;
1540 break;
1541 case TGSI_TEXTURE_2D:
1542 case TGSI_TEXTURE_SHADOW2D:
1543 case TGSI_TEXTURE_RECT:
1544 case TGSI_TEXTURE_SHADOWRECT:
1545 case TGSI_TEXTURE_2D_ARRAY:
1546 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1547 num_src_deriv_channels = 2;
1548 num_dst_deriv_channels = 2;
1549 break;
1550 case TGSI_TEXTURE_CUBE:
1551 case TGSI_TEXTURE_SHADOWCUBE:
1552 case TGSI_TEXTURE_CUBE_ARRAY:
1553 case TGSI_TEXTURE_SHADOWCUBE_ARRAY:
1554 /* Cube derivatives will be converted to 2D. */
1555 num_src_deriv_channels = 3;
1556 num_dst_deriv_channels = 3;
1557 break;
1558 case TGSI_TEXTURE_1D:
1559 case TGSI_TEXTURE_SHADOW1D:
1560 case TGSI_TEXTURE_1D_ARRAY:
1561 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1562 num_src_deriv_channels = 1;
1563
1564 /* 1D textures are allocated and used as 2D on GFX9. */
1565 if (ctx->screen->info.chip_class >= GFX9) {
1566 num_dst_deriv_channels = 2;
1567 } else {
1568 num_dst_deriv_channels = 1;
1569 }
1570 break;
1571 default:
1572 unreachable("invalid target");
1573 }
1574
1575 for (param = 0; param < 2; param++) {
1576 for (chan = 0; chan < num_src_deriv_channels; chan++)
1577 args.derivs[param * num_dst_deriv_channels + chan] =
1578 lp_build_emit_fetch(bld_base, inst, param+1, chan);
1579
1580 /* Fill in the rest with zeros. */
1581 for (chan = num_src_deriv_channels;
1582 chan < num_dst_deriv_channels; chan++)
1583 args.derivs[param * num_dst_deriv_channels + chan] =
1584 ctx->ac.f32_0;
1585 }
1586 }
1587
1588 if (target == TGSI_TEXTURE_CUBE ||
1589 target == TGSI_TEXTURE_CUBE_ARRAY ||
1590 target == TGSI_TEXTURE_SHADOWCUBE ||
1591 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY) {
1592 ac_prepare_cube_coords(&ctx->ac,
1593 opcode == TGSI_OPCODE_TXD,
1594 target == TGSI_TEXTURE_CUBE_ARRAY ||
1595 target == TGSI_TEXTURE_SHADOWCUBE_ARRAY,
1596 opcode == TGSI_OPCODE_LODQ,
1597 args.coords, args.derivs);
1598 } else if (tgsi_is_array_sampler(target) &&
1599 opcode != TGSI_OPCODE_TXF &&
1600 opcode != TGSI_OPCODE_TXF_LZ &&
1601 ctx->screen->info.chip_class <= VI) {
1602 unsigned array_coord = target == TGSI_TEXTURE_1D_ARRAY ? 1 : 2;
1603 args.coords[array_coord] =
1604 ac_build_intrinsic(&ctx->ac, "llvm.rint.f32", ctx->f32,
1605 &args.coords[array_coord], 1, 0);
1606 }
1607
1608 /* 1D textures are allocated and used as 2D on GFX9. */
1609 if (ctx->screen->info.chip_class >= GFX9) {
1610 LLVMValueRef filler;
1611
1612 /* Use 0.5, so that we don't sample the border color. */
1613 if (opcode == TGSI_OPCODE_TXF ||
1614 opcode == TGSI_OPCODE_TXF_LZ)
1615 filler = ctx->i32_0;
1616 else
1617 filler = LLVMConstReal(ctx->f32, 0.5);
1618
1619 if (target == TGSI_TEXTURE_1D ||
1620 target == TGSI_TEXTURE_SHADOW1D) {
1621 args.coords[1] = filler;
1622 } else if (target == TGSI_TEXTURE_1D_ARRAY ||
1623 target == TGSI_TEXTURE_SHADOW1D_ARRAY) {
1624 args.coords[2] = args.coords[1];
1625 args.coords[1] = filler;
1626 }
1627 }
1628
1629 /* Pack LOD or sample index */
1630 if (opcode == TGSI_OPCODE_TXL)
1631 args.lod = args.coords[3];
1632 else if (opcode == TGSI_OPCODE_TXL2)
1633 args.lod = lp_build_emit_fetch(bld_base, inst, 1, TGSI_CHAN_X);
1634 else if (opcode == TGSI_OPCODE_TXF) {
1635 if (target == TGSI_TEXTURE_2D_MSAA) {
1636 /* No LOD, but move sample index into the right place. */
1637 args.coords[2] = args.coords[3];
1638 } else if (target != TGSI_TEXTURE_2D_ARRAY_MSAA) {
1639 args.lod = args.coords[3];
1640 }
1641 }
1642
1643 if (target == TGSI_TEXTURE_2D_MSAA ||
1644 target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
1645 ac_apply_fmask_to_sample(&ctx->ac, fmask_ptr, args.coords,
1646 target == TGSI_TEXTURE_2D_ARRAY_MSAA);
1647 }
1648
1649 if (opcode == TGSI_OPCODE_TXF ||
1650 opcode == TGSI_OPCODE_TXF_LZ) {
1651 /* add tex offsets */
1652 if (inst->Texture.NumOffsets) {
1653 const struct tgsi_texture_offset *off = inst->TexOffsets;
1654
1655 assert(inst->Texture.NumOffsets == 1);
1656
1657 switch (target) {
1658 case TGSI_TEXTURE_3D:
1659 args.coords[2] =
1660 LLVMBuildAdd(ctx->ac.builder, args.coords[2],
1661 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleZ], "");
1662 /* fall through */
1663 case TGSI_TEXTURE_2D:
1664 case TGSI_TEXTURE_SHADOW2D:
1665 case TGSI_TEXTURE_RECT:
1666 case TGSI_TEXTURE_SHADOWRECT:
1667 case TGSI_TEXTURE_2D_ARRAY:
1668 case TGSI_TEXTURE_SHADOW2D_ARRAY:
1669 args.coords[1] =
1670 LLVMBuildAdd(ctx->ac.builder, args.coords[1],
1671 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleY], "");
1672 /* fall through */
1673 case TGSI_TEXTURE_1D:
1674 case TGSI_TEXTURE_SHADOW1D:
1675 case TGSI_TEXTURE_1D_ARRAY:
1676 case TGSI_TEXTURE_SHADOW1D_ARRAY:
1677 args.coords[0] =
1678 LLVMBuildAdd(ctx->ac.builder, args.coords[0],
1679 ctx->imms[off->Index * TGSI_NUM_CHANNELS + off->SwizzleX], "");
1680 break;
1681 /* texture offsets do not apply to other texture targets */
1682 }
1683 }
1684 }
1685
1686 if (opcode == TGSI_OPCODE_TG4) {
1687 unsigned gather_comp = 0;
1688
1689 /* DMASK was repurposed for GATHER4. 4 components are always
1690 * returned and DMASK works like a swizzle - it selects
1691 * the component to fetch. The only valid DMASK values are
1692 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1693 * (red,red,red,red) etc.) The ISA document doesn't mention
1694 * this.
1695 */
1696
1697 /* Get the component index from src1.x for Gather4. */
1698 if (!tgsi_is_shadow_target(target)) {
1699 LLVMValueRef comp_imm;
1700 struct tgsi_src_register src1 = inst->Src[1].Register;
1701
1702 assert(src1.File == TGSI_FILE_IMMEDIATE);
1703
1704 comp_imm = ctx->imms[src1.Index * TGSI_NUM_CHANNELS + src1.SwizzleX];
1705 gather_comp = LLVMConstIntGetZExtValue(comp_imm);
1706 gather_comp = CLAMP(gather_comp, 0, 3);
1707 }
1708
1709 args.dmask = 1 << gather_comp;
1710 } else {
1711 args.dmask = 0xf;
1712 }
1713
1714 args.dim = ac_texture_dim_from_tgsi_target(ctx->screen, target);
1715 args.unorm = target == TGSI_TEXTURE_RECT ||
1716 target == TGSI_TEXTURE_SHADOWRECT;
1717 args.opcode = ac_image_sample;
1718
1719 switch (opcode) {
1720 case TGSI_OPCODE_TXF:
1721 case TGSI_OPCODE_TXF_LZ:
1722 args.opcode = opcode == TGSI_OPCODE_TXF_LZ ||
1723 target == TGSI_TEXTURE_2D_MSAA ||
1724 target == TGSI_TEXTURE_2D_ARRAY_MSAA ?
1725 ac_image_load : ac_image_load_mip;
1726 break;
1727 case TGSI_OPCODE_LODQ:
1728 args.opcode = ac_image_get_lod;
1729 break;
1730 case TGSI_OPCODE_TEX:
1731 case TGSI_OPCODE_TEX2:
1732 case TGSI_OPCODE_TXP:
1733 if (ctx->type != PIPE_SHADER_FRAGMENT)
1734 args.level_zero = true;
1735 break;
1736 case TGSI_OPCODE_TEX_LZ:
1737 args.level_zero = true;
1738 break;
1739 case TGSI_OPCODE_TXB:
1740 case TGSI_OPCODE_TXB2:
1741 assert(ctx->type == PIPE_SHADER_FRAGMENT);
1742 break;
1743 case TGSI_OPCODE_TXL:
1744 case TGSI_OPCODE_TXL2:
1745 break;
1746 case TGSI_OPCODE_TXD:
1747 break;
1748 case TGSI_OPCODE_TG4:
1749 args.opcode = ac_image_gather4;
1750 args.level_zero = true;
1751 break;
1752 default:
1753 assert(0);
1754 return;
1755 }
1756
1757 /* The hardware needs special lowering for Gather4 with integer formats. */
1758 LLVMValueRef gather4_int_result_workaround = NULL;
1759
1760 if (ctx->screen->info.chip_class <= VI &&
1761 opcode == TGSI_OPCODE_TG4) {
1762 assert(inst->Texture.ReturnType != TGSI_RETURN_TYPE_UNKNOWN);
1763
1764 if (inst->Texture.ReturnType == TGSI_RETURN_TYPE_SINT ||
1765 inst->Texture.ReturnType == TGSI_RETURN_TYPE_UINT) {
1766 gather4_int_result_workaround =
1767 si_lower_gather4_integer(ctx, &args, target,
1768 inst->Texture.ReturnType);
1769 }
1770 }
1771
1772 args.attributes = AC_FUNC_ATTR_READNONE;
1773 LLVMValueRef result = ac_build_image_opcode(&ctx->ac, &args);
1774
1775 if (gather4_int_result_workaround) {
1776 result = si_fix_gather4_integer_result(ctx, result,
1777 inst->Texture.ReturnType,
1778 gather4_int_result_workaround);
1779 }
1780
1781 emit_data->output[emit_data->chan] = result;
1782 }
1783
1784 static void si_llvm_emit_txqs(
1785 const struct lp_build_tgsi_action *action,
1786 struct lp_build_tgsi_context *bld_base,
1787 struct lp_build_emit_data *emit_data)
1788 {
1789 struct si_shader_context *ctx = si_shader_context(bld_base);
1790 LLVMValueRef res, samples;
1791 LLVMValueRef res_ptr, samp_ptr, fmask_ptr = NULL;
1792
1793 tex_fetch_ptrs(bld_base, emit_data, &res_ptr, &samp_ptr, &fmask_ptr);
1794
1795 /* Read the samples from the descriptor directly. */
1796 res = LLVMBuildBitCast(ctx->ac.builder, res_ptr, ctx->v8i32, "");
1797 samples = LLVMBuildExtractElement(ctx->ac.builder, res,
1798 LLVMConstInt(ctx->i32, 3, 0), "");
1799 samples = LLVMBuildLShr(ctx->ac.builder, samples,
1800 LLVMConstInt(ctx->i32, 16, 0), "");
1801 samples = LLVMBuildAnd(ctx->ac.builder, samples,
1802 LLVMConstInt(ctx->i32, 0xf, 0), "");
1803 samples = LLVMBuildShl(ctx->ac.builder, ctx->i32_1,
1804 samples, "");
1805
1806 emit_data->output[emit_data->chan] = samples;
1807 }
1808
1809 static void si_llvm_emit_fbfetch(const struct lp_build_tgsi_action *action,
1810 struct lp_build_tgsi_context *bld_base,
1811 struct lp_build_emit_data *emit_data)
1812 {
1813 struct si_shader_context *ctx = si_shader_context(bld_base);
1814 struct ac_image_args args = {};
1815 LLVMValueRef ptr, image, fmask;
1816
1817 /* Ignore src0, because KHR_blend_func_extended disallows multiple render
1818 * targets.
1819 */
1820
1821 /* Load the image descriptor. */
1822 STATIC_ASSERT(SI_PS_IMAGE_COLORBUF0 % 2 == 0);
1823 ptr = LLVMGetParam(ctx->main_fn, ctx->param_rw_buffers);
1824 ptr = LLVMBuildPointerCast(ctx->ac.builder, ptr,
1825 ac_array_in_const32_addr_space(ctx->v8i32), "");
1826 image = ac_build_load_to_sgpr(&ctx->ac, ptr,
1827 LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0 / 2, 0));
1828
1829 unsigned chan = 0;
1830
1831 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_POS_FIXED_PT, 0, 16);
1832
1833 if (!ctx->shader->key.mono.u.ps.fbfetch_is_1D)
1834 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_POS_FIXED_PT, 16, 16);
1835
1836 /* Get the current render target layer index. */
1837 if (ctx->shader->key.mono.u.ps.fbfetch_layered)
1838 args.coords[chan++] = si_unpack_param(ctx, SI_PARAM_ANCILLARY, 16, 11);
1839
1840 if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
1841 args.coords[chan++] = si_get_sample_id(ctx);
1842
1843 if (ctx->shader->key.mono.u.ps.fbfetch_msaa) {
1844 fmask = ac_build_load_to_sgpr(&ctx->ac, ptr,
1845 LLVMConstInt(ctx->i32, SI_PS_IMAGE_COLORBUF0_FMASK / 2, 0));
1846
1847 ac_apply_fmask_to_sample(&ctx->ac, fmask, args.coords,
1848 ctx->shader->key.mono.u.ps.fbfetch_layered);
1849 }
1850
1851 args.opcode = ac_image_load;
1852 args.resource = image;
1853 args.dmask = 0xf;
1854 if (ctx->shader->key.mono.u.ps.fbfetch_msaa)
1855 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1856 ac_image_2darraymsaa : ac_image_2dmsaa;
1857 else if (ctx->shader->key.mono.u.ps.fbfetch_is_1D)
1858 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1859 ac_image_1darray : ac_image_1d;
1860 else
1861 args.dim = ctx->shader->key.mono.u.ps.fbfetch_layered ?
1862 ac_image_2darray : ac_image_2d;
1863
1864 emit_data->output[emit_data->chan] =
1865 ac_build_image_opcode(&ctx->ac, &args);
1866 }
1867
1868 /**
1869 * Setup actions for TGSI memory opcode, including texture opcodes.
1870 */
1871 void si_shader_context_init_mem(struct si_shader_context *ctx)
1872 {
1873 struct lp_build_tgsi_context *bld_base;
1874 struct lp_build_tgsi_action tmpl = {};
1875
1876 bld_base = &ctx->bld_base;
1877
1878 bld_base->op_actions[TGSI_OPCODE_TEX].emit = build_tex_intrinsic;
1879 bld_base->op_actions[TGSI_OPCODE_TEX_LZ].emit = build_tex_intrinsic;
1880 bld_base->op_actions[TGSI_OPCODE_TEX2].emit = build_tex_intrinsic;
1881 bld_base->op_actions[TGSI_OPCODE_TXB].emit = build_tex_intrinsic;
1882 bld_base->op_actions[TGSI_OPCODE_TXB2].emit = build_tex_intrinsic;
1883 bld_base->op_actions[TGSI_OPCODE_TXD].emit = build_tex_intrinsic;
1884 bld_base->op_actions[TGSI_OPCODE_TXF].emit = build_tex_intrinsic;
1885 bld_base->op_actions[TGSI_OPCODE_TXF_LZ].emit = build_tex_intrinsic;
1886 bld_base->op_actions[TGSI_OPCODE_TXL].emit = build_tex_intrinsic;
1887 bld_base->op_actions[TGSI_OPCODE_TXL2].emit = build_tex_intrinsic;
1888 bld_base->op_actions[TGSI_OPCODE_TXP].emit = build_tex_intrinsic;
1889 bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = txq_fetch_args;
1890 bld_base->op_actions[TGSI_OPCODE_TXQ].emit = txq_emit;
1891 bld_base->op_actions[TGSI_OPCODE_TG4].emit = build_tex_intrinsic;
1892 bld_base->op_actions[TGSI_OPCODE_LODQ].emit = build_tex_intrinsic;
1893 bld_base->op_actions[TGSI_OPCODE_TXQS].emit = si_llvm_emit_txqs;
1894
1895 bld_base->op_actions[TGSI_OPCODE_FBFETCH].emit = si_llvm_emit_fbfetch;
1896
1897 bld_base->op_actions[TGSI_OPCODE_LOAD].fetch_args = load_fetch_args;
1898 bld_base->op_actions[TGSI_OPCODE_LOAD].emit = load_emit;
1899 bld_base->op_actions[TGSI_OPCODE_STORE].fetch_args = store_fetch_args;
1900 bld_base->op_actions[TGSI_OPCODE_STORE].emit = store_emit;
1901 bld_base->op_actions[TGSI_OPCODE_RESQ].fetch_args = resq_fetch_args;
1902 bld_base->op_actions[TGSI_OPCODE_RESQ].emit = resq_emit;
1903
1904 tmpl.fetch_args = atomic_fetch_args;
1905 tmpl.emit = atomic_emit;
1906 bld_base->op_actions[TGSI_OPCODE_ATOMUADD] = tmpl;
1907 bld_base->op_actions[TGSI_OPCODE_ATOMUADD].intr_name = "add";
1908 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG] = tmpl;
1909 bld_base->op_actions[TGSI_OPCODE_ATOMXCHG].intr_name = "swap";
1910 bld_base->op_actions[TGSI_OPCODE_ATOMCAS] = tmpl;
1911 bld_base->op_actions[TGSI_OPCODE_ATOMCAS].intr_name = "cmpswap";
1912 bld_base->op_actions[TGSI_OPCODE_ATOMAND] = tmpl;
1913 bld_base->op_actions[TGSI_OPCODE_ATOMAND].intr_name = "and";
1914 bld_base->op_actions[TGSI_OPCODE_ATOMOR] = tmpl;
1915 bld_base->op_actions[TGSI_OPCODE_ATOMOR].intr_name = "or";
1916 bld_base->op_actions[TGSI_OPCODE_ATOMXOR] = tmpl;
1917 bld_base->op_actions[TGSI_OPCODE_ATOMXOR].intr_name = "xor";
1918 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN] = tmpl;
1919 bld_base->op_actions[TGSI_OPCODE_ATOMUMIN].intr_name = "umin";
1920 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX] = tmpl;
1921 bld_base->op_actions[TGSI_OPCODE_ATOMUMAX].intr_name = "umax";
1922 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN] = tmpl;
1923 bld_base->op_actions[TGSI_OPCODE_ATOMIMIN].intr_name = "smin";
1924 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX] = tmpl;
1925 bld_base->op_actions[TGSI_OPCODE_ATOMIMAX].intr_name = "smax";
1926 }