2 * Copyright 2017 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_shader_internal.h"
28 #include "tgsi/tgsi_build.h"
29 #include "tgsi/tgsi_util.h"
30 #include "ac_llvm_util.h"
32 static void tex_fetch_ptrs(struct lp_build_tgsi_context
*bld_base
,
33 struct lp_build_emit_data
*emit_data
,
34 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
35 LLVMValueRef
*fmask_ptr
);
38 * Given a v8i32 resource descriptor for a buffer, extract the size of the
39 * buffer in number of elements and return it as an i32.
41 static LLVMValueRef
get_buffer_size(
42 struct lp_build_tgsi_context
*bld_base
,
43 LLVMValueRef descriptor
)
45 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
46 LLVMBuilderRef builder
= ctx
->ac
.builder
;
48 LLVMBuildExtractElement(builder
, descriptor
,
49 LLVMConstInt(ctx
->i32
, 2, 0), "");
51 if (ctx
->screen
->info
.chip_class
== GFX8
) {
52 /* On GFX8, the descriptor contains the size in bytes,
53 * but TXQ must return the size in elements.
54 * The stride is always non-zero for resources using TXQ.
57 LLVMBuildExtractElement(builder
, descriptor
,
59 stride
= LLVMBuildLShr(builder
, stride
,
60 LLVMConstInt(ctx
->i32
, 16, 0), "");
61 stride
= LLVMBuildAnd(builder
, stride
,
62 LLVMConstInt(ctx
->i32
, 0x3FFF, 0), "");
64 size
= LLVMBuildUDiv(builder
, size
, stride
, "");
71 shader_buffer_fetch_rsrc(struct si_shader_context
*ctx
,
72 const struct tgsi_full_src_register
*reg
,
77 if (!reg
->Register
.Indirect
) {
78 index
= LLVMConstInt(ctx
->i32
, reg
->Register
.Index
, false);
80 index
= si_get_indirect_index(ctx
, ®
->Indirect
,
81 1, reg
->Register
.Index
);
85 return ctx
->abi
.load_ubo(&ctx
->abi
, index
);
87 return ctx
->abi
.load_ssbo(&ctx
->abi
, index
, false);
90 static enum ac_image_dim
91 ac_texture_dim_from_tgsi_target(struct si_screen
*screen
, enum tgsi_texture_type target
)
95 case TGSI_TEXTURE_SHADOW1D
:
96 if (screen
->info
.chip_class
== GFX9
)
100 case TGSI_TEXTURE_SHADOW2D
:
101 case TGSI_TEXTURE_RECT
:
102 case TGSI_TEXTURE_SHADOWRECT
:
104 case TGSI_TEXTURE_3D
:
106 case TGSI_TEXTURE_CUBE
:
107 case TGSI_TEXTURE_SHADOWCUBE
:
108 case TGSI_TEXTURE_CUBE_ARRAY
:
109 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
110 return ac_image_cube
;
111 case TGSI_TEXTURE_1D_ARRAY
:
112 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
113 if (screen
->info
.chip_class
== GFX9
)
114 return ac_image_2darray
;
115 return ac_image_1darray
;
116 case TGSI_TEXTURE_2D_ARRAY
:
117 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
118 return ac_image_2darray
;
119 case TGSI_TEXTURE_2D_MSAA
:
120 return ac_image_2dmsaa
;
121 case TGSI_TEXTURE_2D_ARRAY_MSAA
:
122 return ac_image_2darraymsaa
;
124 unreachable("unhandled texture type");
128 static enum ac_image_dim
129 ac_image_dim_from_tgsi_target(struct si_screen
*screen
, enum tgsi_texture_type target
)
131 enum ac_image_dim dim
= ac_texture_dim_from_tgsi_target(screen
, target
);
133 /* Match the resource type set in the descriptor. */
134 if (dim
== ac_image_cube
||
135 (screen
->info
.chip_class
<= GFX8
&& dim
== ac_image_3d
))
136 dim
= ac_image_2darray
;
137 else if (target
== TGSI_TEXTURE_2D
&& screen
->info
.chip_class
== GFX9
) {
138 /* When a single layer of a 3D texture is bound, the shader
139 * will refer to a 2D target, but the descriptor has a 3D type.
140 * Since the HW ignores BASE_ARRAY in this case, we need to
141 * send 3 coordinates. This doesn't hurt when the underlying
151 * Given a 256-bit resource descriptor, force the DCC enable bit to off.
153 * At least on Tonga, executing image stores on images with DCC enabled and
154 * non-trivial can eventually lead to lockups. This can occur when an
155 * application binds an image as read-only but then uses a shader that writes
156 * to it. The OpenGL spec allows almost arbitrarily bad behavior (including
157 * program termination) in this case, but it doesn't cost much to be a bit
158 * nicer: disabling DCC in the shader still leads to undefined results but
161 static LLVMValueRef
force_dcc_off(struct si_shader_context
*ctx
,
164 if (ctx
->screen
->info
.chip_class
<= GFX7
) {
167 LLVMValueRef i32_6
= LLVMConstInt(ctx
->i32
, 6, 0);
168 LLVMValueRef i32_C
= LLVMConstInt(ctx
->i32
, C_008F28_COMPRESSION_EN
, 0);
171 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, rsrc
, i32_6
, "");
172 tmp
= LLVMBuildAnd(ctx
->ac
.builder
, tmp
, i32_C
, "");
173 return LLVMBuildInsertElement(ctx
->ac
.builder
, rsrc
, tmp
, i32_6
, "");
177 LLVMValueRef
si_load_image_desc(struct si_shader_context
*ctx
,
178 LLVMValueRef list
, LLVMValueRef index
,
179 enum ac_descriptor_type desc_type
,
180 bool uses_store
, bool bindless
)
182 LLVMBuilderRef builder
= ctx
->ac
.builder
;
185 if (desc_type
== AC_DESC_BUFFER
) {
186 index
= ac_build_imad(&ctx
->ac
, index
, LLVMConstInt(ctx
->i32
, 2, 0),
188 list
= LLVMBuildPointerCast(builder
, list
,
189 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
191 assert(desc_type
== AC_DESC_IMAGE
);
195 rsrc
= ac_build_load_to_sgpr_uint_wraparound(&ctx
->ac
, list
, index
);
197 rsrc
= ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
199 if (desc_type
== AC_DESC_IMAGE
&& uses_store
)
200 rsrc
= force_dcc_off(ctx
, rsrc
);
205 * Load the resource descriptor for \p image.
209 struct lp_build_tgsi_context
*bld_base
,
210 const struct tgsi_full_src_register
*image
,
211 bool is_store
, unsigned target
,
214 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
215 LLVMValueRef rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
216 ctx
->param_samplers_and_images
);
219 if (!image
->Register
.Indirect
) {
220 index
= LLVMConstInt(ctx
->i32
,
221 si_get_image_slot(image
->Register
.Index
), 0);
223 /* From the GL_ARB_shader_image_load_store extension spec:
225 * If a shader performs an image load, store, or atomic
226 * operation using an image variable declared as an array,
227 * and if the index used to select an individual element is
228 * negative or greater than or equal to the size of the
229 * array, the results of the operation are undefined but may
230 * not lead to termination.
232 index
= si_get_bounded_indirect_index(ctx
, &image
->Indirect
,
233 image
->Register
.Index
,
235 index
= LLVMBuildSub(ctx
->ac
.builder
,
236 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
- 1, 0),
240 bool bindless
= false;
242 if (image
->Register
.File
!= TGSI_FILE_IMAGE
) {
243 /* Bindless descriptors are accessible from a different pair of
246 rsrc_ptr
= LLVMGetParam(ctx
->main_fn
,
247 ctx
->param_bindless_samplers_and_images
);
248 index
= lp_build_emit_fetch_src(bld_base
, image
,
249 TGSI_TYPE_UNSIGNED
, 0);
251 /* For simplicity, bindless image descriptors use fixed
252 * 16-dword slots for now.
254 index
= LLVMBuildMul(ctx
->ac
.builder
, index
,
255 LLVMConstInt(ctx
->i32
, 2, 0), "");
259 *rsrc
= si_load_image_desc(ctx
, rsrc_ptr
, index
,
260 target
== TGSI_TEXTURE_BUFFER
? AC_DESC_BUFFER
: AC_DESC_IMAGE
,
264 static void image_fetch_coords(
265 struct lp_build_tgsi_context
*bld_base
,
266 const struct tgsi_full_instruction
*inst
,
267 unsigned src
, LLVMValueRef desc
,
268 LLVMValueRef
*coords
)
270 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
271 LLVMBuilderRef builder
= ctx
->ac
.builder
;
272 unsigned target
= inst
->Memory
.Texture
;
273 unsigned num_coords
= tgsi_util_get_texture_coord_dim(target
);
277 if (target
== TGSI_TEXTURE_2D_MSAA
||
278 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
279 /* Need the sample index as well. */
283 for (chan
= 0; chan
< num_coords
; ++chan
) {
284 tmp
= lp_build_emit_fetch(bld_base
, inst
, src
, chan
);
285 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
289 if (ctx
->screen
->info
.chip_class
== GFX9
) {
290 /* 1D textures are allocated and used as 2D on GFX9. */
291 if (target
== TGSI_TEXTURE_1D
) {
292 coords
[1] = ctx
->i32_0
;
293 } else if (target
== TGSI_TEXTURE_1D_ARRAY
) {
294 coords
[2] = coords
[1];
295 coords
[1] = ctx
->i32_0
;
296 } else if (target
== TGSI_TEXTURE_2D
) {
297 /* The hw can't bind a slice of a 3D image as a 2D
298 * image, because it ignores BASE_ARRAY if the target
299 * is 3D. The workaround is to read BASE_ARRAY and set
300 * it as the 3rd address operand for all 2D images.
302 LLVMValueRef first_layer
, const5
, mask
;
304 const5
= LLVMConstInt(ctx
->i32
, 5, 0);
305 mask
= LLVMConstInt(ctx
->i32
, S_008F24_BASE_ARRAY(~0), 0);
306 first_layer
= LLVMBuildExtractElement(builder
, desc
, const5
, "");
307 first_layer
= LLVMBuildAnd(builder
, first_layer
, mask
, "");
309 coords
[2] = first_layer
;
314 static unsigned get_cache_policy(struct si_shader_context
*ctx
,
315 const struct tgsi_full_instruction
*inst
,
316 bool atomic
, bool may_store_unaligned
,
317 bool writeonly_memory
)
319 unsigned cache_policy
= 0;
322 /* GFX6 has a TC L1 bug causing corruption of 8bit/16bit stores.
323 * All store opcodes not aligned to a dword are affected.
324 * The only way to get unaligned stores in radeonsi is through
326 ((may_store_unaligned
&& ctx
->screen
->info
.chip_class
== GFX6
) ||
327 /* If this is write-only, don't keep data in L1 to prevent
328 * evicting L1 cache lines that may be needed by other
331 inst
->Memory
.Qualifier
& (TGSI_MEMORY_COHERENT
| TGSI_MEMORY_VOLATILE
))) {
332 cache_policy
|= ac_glc
;
335 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_STREAM_CACHE_POLICY
)
336 cache_policy
|= ac_slc
;
341 static LLVMValueRef
get_memory_ptr(struct si_shader_context
*ctx
,
342 const struct tgsi_full_instruction
*inst
,
343 LLVMTypeRef type
, int arg
)
345 LLVMBuilderRef builder
= ctx
->ac
.builder
;
346 LLVMValueRef offset
, ptr
;
349 offset
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, arg
, 0);
350 offset
= ac_to_integer(&ctx
->ac
, offset
);
353 ptr
= LLVMBuildGEP(builder
, ptr
, &offset
, 1, "");
354 addr_space
= LLVMGetPointerAddressSpace(LLVMTypeOf(ptr
));
355 ptr
= LLVMBuildBitCast(builder
, ptr
, LLVMPointerType(type
, addr_space
), "");
360 static void load_emit_memory(
361 struct si_shader_context
*ctx
,
362 struct lp_build_emit_data
*emit_data
)
364 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
365 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
366 LLVMValueRef channels
[4], ptr
, derived_ptr
, index
;
369 ptr
= get_memory_ptr(ctx
, inst
, ctx
->f32
, 1);
371 for (chan
= 0; chan
< 4; ++chan
) {
372 if (!(writemask
& (1 << chan
))) {
373 channels
[chan
] = LLVMGetUndef(ctx
->f32
);
377 index
= LLVMConstInt(ctx
->i32
, chan
, 0);
378 derived_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ptr
, &index
, 1, "");
379 channels
[chan
] = LLVMBuildLoad(ctx
->ac
.builder
, derived_ptr
, "");
381 emit_data
->output
[emit_data
->chan
] = ac_build_gather_values(&ctx
->ac
, channels
, 4);
385 * Return true if the memory accessed by a LOAD or STORE instruction is
386 * read-only or write-only, respectively.
388 * \param shader_buffers_reverse_access_mask
389 * For LOAD, set this to (store | atomic) slot usage in the shader.
390 * For STORE, set this to (load | atomic) slot usage in the shader.
391 * \param images_reverse_access_mask Same as above, but for images.
392 * \param bindless_buffer_reverse_access_mask Same as above, but for bindless image buffers.
393 * \param bindless_image_reverse_access_mask Same as above, but for bindless images.
395 static bool is_oneway_access_only(const struct tgsi_full_instruction
*inst
,
396 const struct tgsi_shader_info
*info
,
397 unsigned shader_buffers_reverse_access_mask
,
398 unsigned images_reverse_access_mask
,
399 bool bindless_buffer_reverse_access_mask
,
400 bool bindless_image_reverse_access_mask
)
402 enum tgsi_file_type resource_file
;
403 unsigned resource_index
;
404 bool resource_indirect
;
406 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_STORE
) {
407 resource_file
= inst
->Dst
[0].Register
.File
;
408 resource_index
= inst
->Dst
[0].Register
.Index
;
409 resource_indirect
= inst
->Dst
[0].Register
.Indirect
;
411 resource_file
= inst
->Src
[0].Register
.File
;
412 resource_index
= inst
->Src
[0].Register
.Index
;
413 resource_indirect
= inst
->Src
[0].Register
.Indirect
;
416 assert(resource_file
== TGSI_FILE_BUFFER
||
417 resource_file
== TGSI_FILE_IMAGE
||
419 resource_file
== TGSI_FILE_INPUT
||
420 resource_file
== TGSI_FILE_OUTPUT
||
421 resource_file
== TGSI_FILE_CONSTANT
||
422 resource_file
== TGSI_FILE_TEMPORARY
||
423 resource_file
== TGSI_FILE_IMMEDIATE
);
425 assert(resource_file
!= TGSI_FILE_BUFFER
||
426 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
);
428 bool bindless
= resource_file
!= TGSI_FILE_BUFFER
&&
429 resource_file
!= TGSI_FILE_IMAGE
;
431 /* RESTRICT means NOALIAS.
432 * If there are no writes, we can assume the accessed memory is read-only.
433 * If there are no reads, we can assume the accessed memory is write-only.
435 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_RESTRICT
&& !bindless
) {
436 unsigned reverse_access_mask
;
438 if (resource_file
== TGSI_FILE_BUFFER
) {
439 reverse_access_mask
= shader_buffers_reverse_access_mask
;
440 } else if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
441 reverse_access_mask
= info
->images_buffers
&
442 images_reverse_access_mask
;
444 reverse_access_mask
= ~info
->images_buffers
&
445 images_reverse_access_mask
;
448 if (resource_indirect
) {
449 if (!reverse_access_mask
)
452 if (!(reverse_access_mask
&
453 (1u << resource_index
)))
458 /* If there are no buffer writes (for both shader buffers & image
459 * buffers), it implies that buffer memory is read-only.
460 * If there are no buffer reads (for both shader buffers & image
461 * buffers), it implies that buffer memory is write-only.
463 * Same for the case when there are no writes/reads for non-buffer
466 if (resource_file
== TGSI_FILE_BUFFER
||
467 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
468 if (!shader_buffers_reverse_access_mask
&&
469 !(info
->images_buffers
& images_reverse_access_mask
) &&
470 !bindless_buffer_reverse_access_mask
)
473 if (!(~info
->images_buffers
& images_reverse_access_mask
) &&
474 !bindless_image_reverse_access_mask
)
480 static void load_emit(
481 const struct lp_build_tgsi_action
*action
,
482 struct lp_build_tgsi_context
*bld_base
,
483 struct lp_build_emit_data
*emit_data
)
485 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
486 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
487 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
488 bool can_speculate
= false;
489 LLVMValueRef vindex
= ctx
->i32_0
;
490 LLVMValueRef voffset
= ctx
->i32_0
;
491 struct ac_image_args args
= {};
493 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
494 load_emit_memory(ctx
, emit_data
);
498 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
499 inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
) {
500 bool ubo
= inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
;
501 args
.resource
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0], ubo
);
502 voffset
= ac_to_integer(&ctx
->ac
, lp_build_emit_fetch(bld_base
, inst
, 1, 0));
504 unsigned target
= inst
->Memory
.Texture
;
506 image_fetch_rsrc(bld_base
, &inst
->Src
[0], false, target
, &args
.resource
);
507 image_fetch_coords(bld_base
, inst
, 1, args
.resource
, args
.coords
);
508 vindex
= args
.coords
[0]; /* for buffers only */
511 if (inst
->Src
[0].Register
.File
== TGSI_FILE_CONSTBUF
) {
512 emit_data
->output
[emit_data
->chan
] =
513 ac_build_buffer_load(&ctx
->ac
, args
.resource
,
514 util_last_bit(inst
->Dst
[0].Register
.WriteMask
),
515 NULL
, voffset
, NULL
, 0, 0, true, true);
519 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
520 ac_build_waitcnt(&ctx
->ac
, AC_WAIT_VLOAD
| AC_WAIT_VSTORE
);
522 can_speculate
= !(inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
) &&
523 is_oneway_access_only(inst
, info
,
524 info
->shader_buffers_store
|
525 info
->shader_buffers_atomic
,
528 info
->uses_bindless_buffer_store
|
529 info
->uses_bindless_buffer_atomic
,
530 info
->uses_bindless_image_store
|
531 info
->uses_bindless_image_atomic
);
532 args
.cache_policy
= get_cache_policy(ctx
, inst
, false, false, false);
534 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
535 /* Don't use SMEM for shader buffer loads, because LLVM doesn't
536 * select SMEM for SI.load.const with a non-constant offset, and
537 * constant offsets practically don't exist with shader buffers.
539 * Also, SI.load.const doesn't use inst_offset when it's lowered
540 * to VMEM, so we just end up with more VALU instructions in the end
543 * TODO: Remove this line once LLVM can select SMEM with a non-constant
544 * offset, and can derive inst_offset when VMEM is selected.
545 * After that, si_memory_barrier should invalidate sL1 for shader
548 emit_data
->output
[emit_data
->chan
] =
549 ac_build_buffer_load(&ctx
->ac
, args
.resource
,
550 util_last_bit(inst
->Dst
[0].Register
.WriteMask
),
551 NULL
, voffset
, NULL
, 0,
552 args
.cache_policy
, can_speculate
, false);
556 if (inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
557 unsigned num_channels
= util_last_bit(inst
->Dst
[0].Register
.WriteMask
);
558 LLVMValueRef result
=
559 ac_build_buffer_load_format(&ctx
->ac
,
566 emit_data
->output
[emit_data
->chan
] =
567 ac_build_expand_to_vec4(&ctx
->ac
, result
, num_channels
);
569 args
.opcode
= ac_image_load
;
570 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
571 args
.attributes
= ac_get_load_intr_attribs(can_speculate
);
574 emit_data
->output
[emit_data
->chan
] =
575 ac_build_image_opcode(&ctx
->ac
, &args
);
579 static void store_emit_buffer(struct si_shader_context
*ctx
,
580 LLVMValueRef resource
,
583 LLVMValueRef voffset
,
584 unsigned cache_policy
,
585 bool writeonly_memory
)
587 LLVMBuilderRef builder
= ctx
->ac
.builder
;
588 LLVMValueRef base_data
= value
;
589 LLVMValueRef base_offset
= voffset
;
593 LLVMValueRef data
, voff
;
595 u_bit_scan_consecutive_range(&writemask
, &start
, &count
);
597 if (count
== 3 && ac_has_vec3_support(ctx
->ac
.chip_class
, false)) {
598 LLVMValueRef values
[3] = {
599 LLVMBuildExtractElement(builder
, base_data
,
600 LLVMConstInt(ctx
->i32
, start
, 0), ""),
601 LLVMBuildExtractElement(builder
, base_data
,
602 LLVMConstInt(ctx
->i32
, start
+ 1, 0), ""),
603 LLVMBuildExtractElement(builder
, base_data
,
604 LLVMConstInt(ctx
->i32
, start
+ 2, 0), ""),
606 data
= ac_build_gather_values(&ctx
->ac
, values
, 3);
607 } else if (count
>= 3) {
609 } else if (count
== 2) {
610 LLVMValueRef values
[2] = {
611 LLVMBuildExtractElement(builder
, base_data
,
612 LLVMConstInt(ctx
->i32
, start
, 0), ""),
613 LLVMBuildExtractElement(builder
, base_data
,
614 LLVMConstInt(ctx
->i32
, start
+ 1, 0), ""),
617 data
= ac_build_gather_values(&ctx
->ac
, values
, 2);
620 data
= LLVMBuildExtractElement(
622 LLVMConstInt(ctx
->i32
, start
, 0), "");
629 LLVMConstInt(ctx
->i32
, start
* 4, 0), "");
632 ac_build_buffer_store_dword(&ctx
->ac
, resource
, data
, count
,
633 voff
, ctx
->i32_0
, 0, cache_policy
,
638 static void store_emit_memory(
639 struct si_shader_context
*ctx
,
640 struct lp_build_emit_data
*emit_data
)
642 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
643 LLVMBuilderRef builder
= ctx
->ac
.builder
;
644 unsigned writemask
= inst
->Dst
[0].Register
.WriteMask
;
645 LLVMValueRef ptr
, derived_ptr
, data
, index
;
648 ptr
= get_memory_ptr(ctx
, inst
, ctx
->f32
, 0);
650 for (chan
= 0; chan
< 4; ++chan
) {
651 if (!(writemask
& (1 << chan
))) {
654 data
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, 1, chan
);
655 index
= LLVMConstInt(ctx
->i32
, chan
, 0);
656 derived_ptr
= LLVMBuildGEP(builder
, ptr
, &index
, 1, "");
657 LLVMBuildStore(builder
, data
, derived_ptr
);
661 static void store_emit(
662 const struct lp_build_tgsi_action
*action
,
663 struct lp_build_tgsi_context
*bld_base
,
664 struct lp_build_emit_data
*emit_data
)
666 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
667 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
668 const struct tgsi_shader_info
*info
= &ctx
->shader
->selector
->info
;
669 struct tgsi_full_src_register resource_reg
=
670 tgsi_full_src_register_from_dst(&inst
->Dst
[0]);
671 unsigned target
= inst
->Memory
.Texture
;
673 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_MEMORY
) {
674 store_emit_memory(ctx
, emit_data
);
678 bool writeonly_memory
= is_oneway_access_only(inst
, info
,
679 info
->shader_buffers_load
|
680 info
->shader_buffers_atomic
,
683 info
->uses_bindless_buffer_load
|
684 info
->uses_bindless_buffer_atomic
,
685 info
->uses_bindless_image_load
|
686 info
->uses_bindless_image_atomic
);
687 LLVMValueRef chans
[4];
688 LLVMValueRef vindex
= ctx
->i32_0
;
689 LLVMValueRef voffset
= ctx
->i32_0
;
690 struct ac_image_args args
= {};
692 for (unsigned chan
= 0; chan
< 4; ++chan
)
693 chans
[chan
] = lp_build_emit_fetch(bld_base
, inst
, 1, chan
);
695 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
696 args
.resource
= shader_buffer_fetch_rsrc(ctx
, &resource_reg
, false);
697 voffset
= ac_to_integer(&ctx
->ac
, lp_build_emit_fetch(bld_base
, inst
, 0, 0));
699 image_fetch_rsrc(bld_base
, &resource_reg
, true, target
, &args
.resource
);
700 image_fetch_coords(bld_base
, inst
, 0, args
.resource
, args
.coords
);
701 vindex
= args
.coords
[0]; /* for buffers only */
704 if (inst
->Memory
.Qualifier
& TGSI_MEMORY_VOLATILE
)
705 ac_build_waitcnt(&ctx
->ac
, AC_WAIT_VLOAD
| AC_WAIT_VSTORE
);
707 bool is_image
= inst
->Dst
[0].Register
.File
!= TGSI_FILE_BUFFER
;
708 args
.cache_policy
= get_cache_policy(ctx
, inst
,
710 is_image
, /* may_store_unaligned */
713 if (inst
->Dst
[0].Register
.File
== TGSI_FILE_BUFFER
) {
714 store_emit_buffer(ctx
, args
.resource
, inst
->Dst
[0].Register
.WriteMask
,
715 ac_build_gather_values(&ctx
->ac
, chans
, 4),
716 voffset
, args
.cache_policy
, writeonly_memory
);
720 if (target
== TGSI_TEXTURE_BUFFER
) {
721 unsigned num_channels
= util_last_bit(inst
->Dst
[0].Register
.WriteMask
);
723 ac_build_buffer_store_format(&ctx
->ac
, args
.resource
,
724 ac_build_gather_values(&ctx
->ac
, chans
, num_channels
),
725 vindex
, ctx
->i32_0
/* voffset */,
729 args
.opcode
= ac_image_store
;
730 args
.data
[0] = ac_build_gather_values(&ctx
->ac
, chans
, 4);
731 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
732 args
.attributes
= AC_FUNC_ATTR_INACCESSIBLE_MEM_ONLY
;
735 emit_data
->output
[emit_data
->chan
] =
736 ac_build_image_opcode(&ctx
->ac
, &args
);
740 static void atomic_emit_memory(struct si_shader_context
*ctx
,
741 struct lp_build_emit_data
*emit_data
) {
742 LLVMBuilderRef builder
= ctx
->ac
.builder
;
743 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
744 LLVMValueRef ptr
, result
, arg
;
745 const char *sync_scope
= HAVE_LLVM
>= 0x0900 ? "workgroup-one-as" : "workgroup";
747 ptr
= get_memory_ptr(ctx
, inst
, ctx
->i32
, 1);
749 arg
= lp_build_emit_fetch(&ctx
->bld_base
, inst
, 2, 0);
750 arg
= ac_to_integer(&ctx
->ac
, arg
);
752 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
753 LLVMValueRef new_data
;
754 new_data
= lp_build_emit_fetch(&ctx
->bld_base
,
757 new_data
= ac_to_integer(&ctx
->ac
, new_data
);
759 result
= ac_build_atomic_cmp_xchg(&ctx
->ac
, ptr
, arg
, new_data
,
761 result
= LLVMBuildExtractValue(builder
, result
, 0, "");
763 LLVMAtomicRMWBinOp op
;
765 switch(inst
->Instruction
.Opcode
) {
766 case TGSI_OPCODE_ATOMUADD
:
767 op
= LLVMAtomicRMWBinOpAdd
;
769 case TGSI_OPCODE_ATOMXCHG
:
770 op
= LLVMAtomicRMWBinOpXchg
;
772 case TGSI_OPCODE_ATOMAND
:
773 op
= LLVMAtomicRMWBinOpAnd
;
775 case TGSI_OPCODE_ATOMOR
:
776 op
= LLVMAtomicRMWBinOpOr
;
778 case TGSI_OPCODE_ATOMXOR
:
779 op
= LLVMAtomicRMWBinOpXor
;
781 case TGSI_OPCODE_ATOMUMIN
:
782 op
= LLVMAtomicRMWBinOpUMin
;
784 case TGSI_OPCODE_ATOMUMAX
:
785 op
= LLVMAtomicRMWBinOpUMax
;
787 case TGSI_OPCODE_ATOMIMIN
:
788 op
= LLVMAtomicRMWBinOpMin
;
790 case TGSI_OPCODE_ATOMIMAX
:
791 op
= LLVMAtomicRMWBinOpMax
;
794 unreachable("unknown atomic opcode");
797 result
= ac_build_atomic_rmw(&ctx
->ac
, op
, ptr
, arg
, sync_scope
);
799 emit_data
->output
[emit_data
->chan
] =
800 LLVMBuildBitCast(builder
, result
, ctx
->f32
, "");
803 static void atomic_emit(
804 const struct lp_build_tgsi_action
*action
,
805 struct lp_build_tgsi_context
*bld_base
,
806 struct lp_build_emit_data
*emit_data
)
808 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
809 const struct tgsi_full_instruction
* inst
= emit_data
->inst
;
810 struct ac_image_args args
= {};
811 unsigned num_data
= 0;
812 LLVMValueRef vindex
= ctx
->i32_0
;
813 LLVMValueRef voffset
= ctx
->i32_0
;
815 if (inst
->Src
[0].Register
.File
== TGSI_FILE_MEMORY
) {
816 atomic_emit_memory(ctx
, emit_data
);
820 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
821 /* llvm.amdgcn.image/buffer.atomic.cmpswap reflect the hardware order
822 * of arguments, which is reversed relative to TGSI (and GLSL)
824 args
.data
[num_data
++] =
825 ac_to_integer(&ctx
->ac
, lp_build_emit_fetch(bld_base
, inst
, 3, 0));
828 args
.data
[num_data
++] =
829 ac_to_integer(&ctx
->ac
, lp_build_emit_fetch(bld_base
, inst
, 2, 0));
830 args
.cache_policy
= get_cache_policy(ctx
, inst
, true, false, false);
832 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
) {
833 args
.resource
= shader_buffer_fetch_rsrc(ctx
, &inst
->Src
[0], false);
834 voffset
= ac_to_integer(&ctx
->ac
, lp_build_emit_fetch(bld_base
, inst
, 1, 0));
836 image_fetch_rsrc(bld_base
, &inst
->Src
[0], true,
837 inst
->Memory
.Texture
, &args
.resource
);
838 image_fetch_coords(bld_base
, inst
, 1, args
.resource
, args
.coords
);
839 vindex
= args
.coords
[0]; /* for buffers only */
842 if (HAVE_LLVM
>= 0x0800 &&
843 inst
->Src
[0].Register
.File
!= TGSI_FILE_BUFFER
&&
844 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
845 LLVMValueRef buf_args
[7];
846 unsigned num_args
= 0;
848 buf_args
[num_args
++] = args
.data
[0];
849 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
850 buf_args
[num_args
++] = args
.data
[1];
852 buf_args
[num_args
++] = args
.resource
;
853 buf_args
[num_args
++] = vindex
;
854 buf_args
[num_args
++] = voffset
;
855 buf_args
[num_args
++] = ctx
->i32_0
; /* soffset */
856 buf_args
[num_args
++] = LLVMConstInt(ctx
->i32
, args
.cache_policy
& ac_slc
, 0);
858 char intrinsic_name
[64];
859 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
860 "llvm.amdgcn.struct.buffer.atomic.%s", action
->intr_name
);
861 emit_data
->output
[emit_data
->chan
] =
862 ac_to_float(&ctx
->ac
,
863 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
,
864 ctx
->i32
, buf_args
, num_args
, 0));
868 if (inst
->Src
[0].Register
.File
== TGSI_FILE_BUFFER
||
869 (HAVE_LLVM
< 0x0800 &&
870 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
)) {
871 LLVMValueRef buf_args
[7];
872 unsigned num_args
= 0;
874 buf_args
[num_args
++] = args
.data
[0];
875 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
)
876 buf_args
[num_args
++] = args
.data
[1];
878 buf_args
[num_args
++] = args
.resource
;
879 buf_args
[num_args
++] = vindex
;
880 buf_args
[num_args
++] = voffset
;
881 buf_args
[num_args
++] = args
.cache_policy
& ac_slc
? ctx
->i1true
: ctx
->i1false
;
883 char intrinsic_name
[40];
884 snprintf(intrinsic_name
, sizeof(intrinsic_name
),
885 "llvm.amdgcn.buffer.atomic.%s", action
->intr_name
);
886 emit_data
->output
[emit_data
->chan
] =
887 ac_to_float(&ctx
->ac
,
888 ac_build_intrinsic(&ctx
->ac
, intrinsic_name
,
889 ctx
->i32
, buf_args
, num_args
, 0));
891 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_ATOMCAS
) {
892 args
.opcode
= ac_image_atomic_cmpswap
;
894 args
.opcode
= ac_image_atomic
;
895 switch (inst
->Instruction
.Opcode
) {
896 case TGSI_OPCODE_ATOMXCHG
: args
.atomic
= ac_atomic_swap
; break;
897 case TGSI_OPCODE_ATOMUADD
: args
.atomic
= ac_atomic_add
; break;
898 case TGSI_OPCODE_ATOMAND
: args
.atomic
= ac_atomic_and
; break;
899 case TGSI_OPCODE_ATOMOR
: args
.atomic
= ac_atomic_or
; break;
900 case TGSI_OPCODE_ATOMXOR
: args
.atomic
= ac_atomic_xor
; break;
901 case TGSI_OPCODE_ATOMUMIN
: args
.atomic
= ac_atomic_umin
; break;
902 case TGSI_OPCODE_ATOMUMAX
: args
.atomic
= ac_atomic_umax
; break;
903 case TGSI_OPCODE_ATOMIMIN
: args
.atomic
= ac_atomic_smin
; break;
904 case TGSI_OPCODE_ATOMIMAX
: args
.atomic
= ac_atomic_smax
; break;
905 default: unreachable("unhandled image atomic");
909 args
.dim
= ac_image_dim_from_tgsi_target(ctx
->screen
, inst
->Memory
.Texture
);
910 emit_data
->output
[emit_data
->chan
] =
911 ac_to_float(&ctx
->ac
, ac_build_image_opcode(&ctx
->ac
, &args
));
915 static LLVMValueRef
fix_resinfo(struct si_shader_context
*ctx
,
916 unsigned target
, LLVMValueRef out
)
918 LLVMBuilderRef builder
= ctx
->ac
.builder
;
920 /* 1D textures are allocated and used as 2D on GFX9. */
921 if (ctx
->screen
->info
.chip_class
== GFX9
&&
922 (target
== TGSI_TEXTURE_1D_ARRAY
||
923 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
)) {
924 LLVMValueRef layers
=
925 LLVMBuildExtractElement(builder
, out
,
926 LLVMConstInt(ctx
->i32
, 2, 0), "");
927 out
= LLVMBuildInsertElement(builder
, out
, layers
,
931 /* Divide the number of layers by 6 to get the number of cubes. */
932 if (target
== TGSI_TEXTURE_CUBE_ARRAY
||
933 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
934 LLVMValueRef imm2
= LLVMConstInt(ctx
->i32
, 2, 0);
936 LLVMValueRef z
= LLVMBuildExtractElement(builder
, out
, imm2
, "");
937 z
= LLVMBuildSDiv(builder
, z
, LLVMConstInt(ctx
->i32
, 6, 0), "");
939 out
= LLVMBuildInsertElement(builder
, out
, z
, imm2
, "");
944 static void resq_emit(
945 const struct lp_build_tgsi_action
*action
,
946 struct lp_build_tgsi_context
*bld_base
,
947 struct lp_build_emit_data
*emit_data
)
949 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
950 LLVMBuilderRef builder
= ctx
->ac
.builder
;
951 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
952 const struct tgsi_full_src_register
*reg
=
953 &inst
->Src
[inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
? 1 : 0];
955 if (reg
->Register
.File
== TGSI_FILE_BUFFER
) {
956 LLVMValueRef rsrc
= shader_buffer_fetch_rsrc(ctx
, reg
, false);
958 emit_data
->output
[emit_data
->chan
] =
959 LLVMBuildExtractElement(builder
, rsrc
,
960 LLVMConstInt(ctx
->i32
, 2, 0), "");
964 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
&&
965 inst
->Texture
.Texture
== TGSI_TEXTURE_BUFFER
) {
968 tex_fetch_ptrs(bld_base
, emit_data
, &rsrc
, NULL
, NULL
);
969 /* Read the size from the buffer descriptor directly. */
970 emit_data
->output
[emit_data
->chan
] =
971 get_buffer_size(bld_base
, rsrc
);
975 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_RESQ
&&
976 inst
->Memory
.Texture
== TGSI_TEXTURE_BUFFER
) {
979 image_fetch_rsrc(bld_base
, reg
, false, inst
->Memory
.Texture
, &rsrc
);
980 emit_data
->output
[emit_data
->chan
] =
981 get_buffer_size(bld_base
, rsrc
);
987 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
) {
988 target
= inst
->Texture
.Texture
;
990 if (inst
->Memory
.Texture
== TGSI_TEXTURE_3D
)
991 target
= TGSI_TEXTURE_2D_ARRAY
;
993 target
= inst
->Memory
.Texture
;
996 struct ac_image_args args
= {};
997 args
.opcode
= ac_image_get_resinfo
;
998 args
.dim
= ac_texture_dim_from_tgsi_target(ctx
->screen
, target
);
1000 args
.attributes
= AC_FUNC_ATTR_READNONE
;
1002 if (inst
->Instruction
.Opcode
== TGSI_OPCODE_TXQ
) {
1003 tex_fetch_ptrs(bld_base
, emit_data
, &args
.resource
, NULL
, NULL
);
1004 args
.lod
= lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
1006 image_fetch_rsrc(bld_base
, reg
, false, target
, &args
.resource
);
1007 args
.lod
= ctx
->i32_0
;
1010 emit_data
->output
[emit_data
->chan
] =
1011 fix_resinfo(ctx
, target
, ac_build_image_opcode(&ctx
->ac
, &args
));
1015 * Load an image view, fmask view. or sampler state descriptor.
1017 LLVMValueRef
si_load_sampler_desc(struct si_shader_context
*ctx
,
1018 LLVMValueRef list
, LLVMValueRef index
,
1019 enum ac_descriptor_type type
)
1021 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1025 /* The image is at [0:7]. */
1026 index
= LLVMBuildMul(builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
1028 case AC_DESC_BUFFER
:
1029 /* The buffer is in [4:7]. */
1030 index
= ac_build_imad(&ctx
->ac
, index
, LLVMConstInt(ctx
->i32
, 4, 0),
1032 list
= LLVMBuildPointerCast(builder
, list
,
1033 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
1036 /* The FMASK is at [8:15]. */
1037 index
= ac_build_imad(&ctx
->ac
, index
, LLVMConstInt(ctx
->i32
, 2, 0),
1040 case AC_DESC_SAMPLER
:
1041 /* The sampler state is at [12:15]. */
1042 index
= ac_build_imad(&ctx
->ac
, index
, LLVMConstInt(ctx
->i32
, 4, 0),
1043 LLVMConstInt(ctx
->i32
, 3, 0));
1044 list
= LLVMBuildPointerCast(builder
, list
,
1045 ac_array_in_const32_addr_space(ctx
->v4i32
), "");
1047 case AC_DESC_PLANE_0
:
1048 case AC_DESC_PLANE_1
:
1049 case AC_DESC_PLANE_2
:
1050 /* Only used for the multiplane image support for Vulkan. Should
1051 * never be reached in radeonsi.
1053 unreachable("Plane descriptor requested in radeonsi.");
1056 return ac_build_load_to_sgpr(&ctx
->ac
, list
, index
);
1059 /* Disable anisotropic filtering if BASE_LEVEL == LAST_LEVEL.
1062 * If BASE_LEVEL == LAST_LEVEL, the shader must disable anisotropic
1063 * filtering manually. The driver sets img7 to a mask clearing
1064 * MAX_ANISO_RATIO if BASE_LEVEL == LAST_LEVEL. The shader must do:
1065 * s_and_b32 samp0, samp0, img7
1068 * The ANISO_OVERRIDE sampler field enables this fix in TA.
1070 static LLVMValueRef
sici_fix_sampler_aniso(struct si_shader_context
*ctx
,
1071 LLVMValueRef res
, LLVMValueRef samp
)
1073 LLVMValueRef img7
, samp0
;
1075 if (ctx
->screen
->info
.chip_class
>= GFX8
)
1078 img7
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
1079 LLVMConstInt(ctx
->i32
, 7, 0), "");
1080 samp0
= LLVMBuildExtractElement(ctx
->ac
.builder
, samp
,
1082 samp0
= LLVMBuildAnd(ctx
->ac
.builder
, samp0
, img7
, "");
1083 return LLVMBuildInsertElement(ctx
->ac
.builder
, samp
, samp0
,
1087 static void tex_fetch_ptrs(struct lp_build_tgsi_context
*bld_base
,
1088 struct lp_build_emit_data
*emit_data
,
1089 LLVMValueRef
*res_ptr
, LLVMValueRef
*samp_ptr
,
1090 LLVMValueRef
*fmask_ptr
)
1092 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1093 LLVMValueRef list
= LLVMGetParam(ctx
->main_fn
, ctx
->param_samplers_and_images
);
1094 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1095 const struct tgsi_full_src_register
*reg
;
1096 unsigned target
= inst
->Texture
.Texture
;
1097 unsigned sampler_src
;
1100 sampler_src
= emit_data
->inst
->Instruction
.NumSrcRegs
- 1;
1101 reg
= &emit_data
->inst
->Src
[sampler_src
];
1103 if (reg
->Register
.Indirect
) {
1104 index
= si_get_bounded_indirect_index(ctx
,
1106 reg
->Register
.Index
,
1108 index
= LLVMBuildAdd(ctx
->ac
.builder
, index
,
1109 LLVMConstInt(ctx
->i32
, SI_NUM_IMAGES
/ 2, 0), "");
1111 index
= LLVMConstInt(ctx
->i32
,
1112 si_get_sampler_slot(reg
->Register
.Index
), 0);
1115 if (reg
->Register
.File
!= TGSI_FILE_SAMPLER
) {
1116 /* Bindless descriptors are accessible from a different pair of
1117 * user SGPR indices.
1119 list
= LLVMGetParam(ctx
->main_fn
,
1120 ctx
->param_bindless_samplers_and_images
);
1121 index
= lp_build_emit_fetch_src(bld_base
, reg
,
1122 TGSI_TYPE_UNSIGNED
, 0);
1124 /* Since bindless handle arithmetic can contain an unsigned integer
1125 * wraparound and si_load_sampler_desc assumes there isn't any,
1126 * use GEP without "inbounds" (inside ac_build_pointer_add)
1127 * to prevent incorrect code generation and hangs.
1129 index
= LLVMBuildMul(ctx
->ac
.builder
, index
, LLVMConstInt(ctx
->i32
, 2, 0), "");
1130 list
= ac_build_pointer_add(&ctx
->ac
, list
, index
);
1134 if (target
== TGSI_TEXTURE_BUFFER
)
1135 *res_ptr
= si_load_sampler_desc(ctx
, list
, index
, AC_DESC_BUFFER
);
1137 *res_ptr
= si_load_sampler_desc(ctx
, list
, index
, AC_DESC_IMAGE
);
1144 if (target
== TGSI_TEXTURE_2D_MSAA
||
1145 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1147 *fmask_ptr
= si_load_sampler_desc(ctx
, list
, index
,
1149 } else if (target
!= TGSI_TEXTURE_BUFFER
) {
1151 *samp_ptr
= si_load_sampler_desc(ctx
, list
, index
,
1153 *samp_ptr
= sici_fix_sampler_aniso(ctx
, *res_ptr
, *samp_ptr
);
1158 /* Gather4 should follow the same rules as bilinear filtering, but the hardware
1159 * incorrectly forces nearest filtering if the texture format is integer.
1160 * The only effect it has on Gather4, which always returns 4 texels for
1161 * bilinear filtering, is that the final coordinates are off by 0.5 of
1164 * The workaround is to subtract 0.5 from the unnormalized coordinates,
1165 * or (0.5 / size) from the normalized coordinates.
1167 * However, cube textures with 8_8_8_8 data formats require a different
1168 * workaround of overriding the num format to USCALED/SSCALED. This would lose
1169 * precision in 32-bit data formats, so it needs to be applied dynamically at
1170 * runtime. In this case, return an i1 value that indicates whether the
1171 * descriptor was overridden (and hence a fixup of the sampler result is needed).
1174 si_lower_gather4_integer(struct si_shader_context
*ctx
,
1175 struct ac_image_args
*args
,
1177 enum tgsi_return_type return_type
)
1179 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1180 LLVMValueRef wa_8888
= NULL
;
1181 LLVMValueRef half_texel
[2];
1183 assert(return_type
== TGSI_RETURN_TYPE_SINT
||
1184 return_type
== TGSI_RETURN_TYPE_UINT
);
1186 if (target
== TGSI_TEXTURE_CUBE
||
1187 target
== TGSI_TEXTURE_CUBE_ARRAY
) {
1188 LLVMValueRef formats
;
1189 LLVMValueRef data_format
;
1190 LLVMValueRef wa_formats
;
1192 formats
= LLVMBuildExtractElement(builder
, args
->resource
, ctx
->i32_1
, "");
1194 data_format
= LLVMBuildLShr(builder
, formats
,
1195 LLVMConstInt(ctx
->i32
, 20, false), "");
1196 data_format
= LLVMBuildAnd(builder
, data_format
,
1197 LLVMConstInt(ctx
->i32
, (1u << 6) - 1, false), "");
1198 wa_8888
= LLVMBuildICmp(
1199 builder
, LLVMIntEQ
, data_format
,
1200 LLVMConstInt(ctx
->i32
, V_008F14_IMG_DATA_FORMAT_8_8_8_8
, false),
1203 uint32_t wa_num_format
=
1204 return_type
== TGSI_RETURN_TYPE_UINT
?
1205 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_USCALED
) :
1206 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_SSCALED
);
1207 wa_formats
= LLVMBuildAnd(builder
, formats
,
1208 LLVMConstInt(ctx
->i32
, C_008F14_NUM_FORMAT
, false),
1210 wa_formats
= LLVMBuildOr(builder
, wa_formats
,
1211 LLVMConstInt(ctx
->i32
, wa_num_format
, false), "");
1213 formats
= LLVMBuildSelect(builder
, wa_8888
, wa_formats
, formats
, "");
1214 args
->resource
= LLVMBuildInsertElement(
1215 builder
, args
->resource
, formats
, ctx
->i32_1
, "");
1218 if (target
== TGSI_TEXTURE_RECT
||
1219 target
== TGSI_TEXTURE_SHADOWRECT
) {
1221 half_texel
[0] = half_texel
[1] = LLVMConstReal(ctx
->f32
, -0.5);
1223 struct ac_image_args resinfo
= {};
1224 struct lp_build_if_state if_ctx
;
1227 /* Skip the texture size query entirely if we don't need it. */
1228 lp_build_if(&if_ctx
, &ctx
->gallivm
, LLVMBuildNot(builder
, wa_8888
, ""));
1231 /* Query the texture size. */
1232 resinfo
.opcode
= ac_image_get_resinfo
;
1233 resinfo
.dim
= ac_texture_dim_from_tgsi_target(ctx
->screen
, target
);
1234 resinfo
.resource
= args
->resource
;
1235 resinfo
.sampler
= args
->sampler
;
1236 resinfo
.lod
= ctx
->ac
.i32_0
;
1237 resinfo
.dmask
= 0xf;
1238 resinfo
.attributes
= AC_FUNC_ATTR_READNONE
;
1240 LLVMValueRef texsize
=
1241 fix_resinfo(ctx
, target
,
1242 ac_build_image_opcode(&ctx
->ac
, &resinfo
));
1244 /* Compute -0.5 / size. */
1245 for (unsigned c
= 0; c
< 2; c
++) {
1247 LLVMBuildExtractElement(builder
, texsize
,
1248 LLVMConstInt(ctx
->i32
, c
, 0), "");
1249 half_texel
[c
] = LLVMBuildUIToFP(builder
, half_texel
[c
], ctx
->f32
, "");
1250 half_texel
[c
] = ac_build_fdiv(&ctx
->ac
, ctx
->ac
.f32_1
, half_texel
[c
]);
1251 half_texel
[c
] = LLVMBuildFMul(builder
, half_texel
[c
],
1252 LLVMConstReal(ctx
->f32
, -0.5), "");
1256 lp_build_endif(&if_ctx
);
1258 LLVMBasicBlockRef bb
[2] = { if_ctx
.true_block
, if_ctx
.entry_block
};
1260 for (unsigned c
= 0; c
< 2; c
++) {
1261 LLVMValueRef values
[2] = { half_texel
[c
], ctx
->ac
.f32_0
};
1262 half_texel
[c
] = ac_build_phi(&ctx
->ac
, ctx
->f32
, 2,
1268 for (unsigned c
= 0; c
< 2; c
++) {
1270 tmp
= ac_to_float(&ctx
->ac
, args
->coords
[c
]);
1271 tmp
= LLVMBuildFAdd(builder
, tmp
, half_texel
[c
], "");
1272 args
->coords
[c
] = ac_to_integer(&ctx
->ac
, tmp
);
1278 /* The second half of the cube texture 8_8_8_8 integer workaround: adjust the
1279 * result after the gather operation.
1282 si_fix_gather4_integer_result(struct si_shader_context
*ctx
,
1283 LLVMValueRef result
,
1284 enum tgsi_return_type return_type
,
1287 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1289 assert(return_type
== TGSI_RETURN_TYPE_SINT
||
1290 return_type
== TGSI_RETURN_TYPE_UINT
);
1292 for (unsigned chan
= 0; chan
< 4; ++chan
) {
1293 LLVMValueRef chanv
= LLVMConstInt(ctx
->i32
, chan
, false);
1295 LLVMValueRef wa_value
;
1297 value
= LLVMBuildExtractElement(builder
, result
, chanv
, "");
1299 if (return_type
== TGSI_RETURN_TYPE_UINT
)
1300 wa_value
= LLVMBuildFPToUI(builder
, value
, ctx
->i32
, "");
1302 wa_value
= LLVMBuildFPToSI(builder
, value
, ctx
->i32
, "");
1303 wa_value
= ac_to_float(&ctx
->ac
, wa_value
);
1304 value
= LLVMBuildSelect(builder
, wa
, wa_value
, value
, "");
1306 result
= LLVMBuildInsertElement(builder
, result
, value
, chanv
, "");
1312 static void build_tex_intrinsic(const struct lp_build_tgsi_action
*action
,
1313 struct lp_build_tgsi_context
*bld_base
,
1314 struct lp_build_emit_data
*emit_data
)
1316 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1317 const struct tgsi_full_instruction
*inst
= emit_data
->inst
;
1318 unsigned opcode
= inst
->Instruction
.Opcode
;
1319 unsigned target
= inst
->Texture
.Texture
;
1320 struct ac_image_args args
= {};
1321 int ref_pos
= tgsi_util_get_shadow_ref_src_index(target
);
1323 bool has_offset
= inst
->Texture
.NumOffsets
> 0;
1324 LLVMValueRef fmask_ptr
= NULL
;
1326 tex_fetch_ptrs(bld_base
, emit_data
, &args
.resource
, &args
.sampler
, &fmask_ptr
);
1328 if (target
== TGSI_TEXTURE_BUFFER
) {
1329 LLVMValueRef vindex
= lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_X
);
1330 unsigned num_channels
=
1331 util_last_bit(inst
->Dst
[0].Register
.WriteMask
);
1332 LLVMValueRef result
=
1333 ac_build_buffer_load_format(&ctx
->ac
,
1337 num_channels
, 0, true);
1338 emit_data
->output
[emit_data
->chan
] =
1339 ac_build_expand_to_vec4(&ctx
->ac
, result
, num_channels
);
1343 /* Fetch and project texture coordinates */
1344 args
.coords
[3] = lp_build_emit_fetch(bld_base
, inst
, 0, TGSI_CHAN_W
);
1345 for (chan
= 0; chan
< 3; chan
++) {
1346 args
.coords
[chan
] = lp_build_emit_fetch(bld_base
, inst
, 0, chan
);
1347 if (opcode
== TGSI_OPCODE_TXP
)
1348 args
.coords
[chan
] = ac_build_fdiv(&ctx
->ac
,
1349 args
.coords
[chan
], args
.coords
[3]);
1352 if (opcode
== TGSI_OPCODE_TXP
)
1353 args
.coords
[3] = ctx
->ac
.f32_1
;
1357 opcode
!= TGSI_OPCODE_TXF
&&
1358 opcode
!= TGSI_OPCODE_TXF_LZ
) {
1359 /* The offsets are six-bit signed integers packed like this:
1360 * X=[5:0], Y=[13:8], and Z=[21:16].
1362 LLVMValueRef offset
[3], pack
;
1364 assert(inst
->Texture
.NumOffsets
== 1);
1366 for (chan
= 0; chan
< 3; chan
++) {
1367 offset
[chan
] = lp_build_emit_fetch_texoffset(bld_base
, inst
, 0, chan
);
1368 offset
[chan
] = LLVMBuildAnd(ctx
->ac
.builder
, offset
[chan
],
1369 LLVMConstInt(ctx
->i32
, 0x3f, 0), "");
1371 offset
[chan
] = LLVMBuildShl(ctx
->ac
.builder
, offset
[chan
],
1372 LLVMConstInt(ctx
->i32
, chan
*8, 0), "");
1375 pack
= LLVMBuildOr(ctx
->ac
.builder
, offset
[0], offset
[1], "");
1376 pack
= LLVMBuildOr(ctx
->ac
.builder
, pack
, offset
[2], "");
1380 /* Pack LOD bias value */
1381 if (opcode
== TGSI_OPCODE_TXB
)
1382 args
.bias
= args
.coords
[3];
1383 if (opcode
== TGSI_OPCODE_TXB2
)
1384 args
.bias
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1386 /* Pack depth comparison value */
1387 if (tgsi_is_shadow_target(target
) && opcode
!= TGSI_OPCODE_LODQ
) {
1390 if (target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1391 z
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1393 assert(ref_pos
>= 0);
1394 z
= args
.coords
[ref_pos
];
1397 /* Section 8.23.1 (Depth Texture Comparison Mode) of the
1398 * OpenGL 4.5 spec says:
1400 * "If the texture’s internal format indicates a fixed-point
1401 * depth texture, then D_t and D_ref are clamped to the
1402 * range [0, 1]; otherwise no clamping is performed."
1404 * TC-compatible HTILE promotes Z16 and Z24 to Z32_FLOAT,
1405 * so the depth comparison value isn't clamped for Z16 and
1406 * Z24 anymore. Do it manually here for GFX8-9; GFX10 has
1407 * an explicitly clamped 32-bit float format.
1409 if (ctx
->screen
->info
.chip_class
>= GFX8
&&
1410 ctx
->screen
->info
.chip_class
<= GFX9
) {
1411 LLVMValueRef upgraded
;
1412 LLVMValueRef clamped
;
1413 upgraded
= LLVMBuildExtractElement(ctx
->ac
.builder
, args
.sampler
,
1414 LLVMConstInt(ctx
->i32
, 3, false), "");
1415 upgraded
= LLVMBuildLShr(ctx
->ac
.builder
, upgraded
,
1416 LLVMConstInt(ctx
->i32
, 29, false), "");
1417 upgraded
= LLVMBuildTrunc(ctx
->ac
.builder
, upgraded
, ctx
->i1
, "");
1418 clamped
= ac_build_clamp(&ctx
->ac
, z
);
1419 z
= LLVMBuildSelect(ctx
->ac
.builder
, upgraded
, clamped
, z
, "");
1425 /* Pack user derivatives */
1426 if (opcode
== TGSI_OPCODE_TXD
) {
1427 int param
, num_src_deriv_channels
, num_dst_deriv_channels
;
1430 case TGSI_TEXTURE_3D
:
1431 num_src_deriv_channels
= 3;
1432 num_dst_deriv_channels
= 3;
1434 case TGSI_TEXTURE_2D
:
1435 case TGSI_TEXTURE_SHADOW2D
:
1436 case TGSI_TEXTURE_RECT
:
1437 case TGSI_TEXTURE_SHADOWRECT
:
1438 case TGSI_TEXTURE_2D_ARRAY
:
1439 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1440 num_src_deriv_channels
= 2;
1441 num_dst_deriv_channels
= 2;
1443 case TGSI_TEXTURE_CUBE
:
1444 case TGSI_TEXTURE_SHADOWCUBE
:
1445 case TGSI_TEXTURE_CUBE_ARRAY
:
1446 case TGSI_TEXTURE_SHADOWCUBE_ARRAY
:
1447 /* Cube derivatives will be converted to 2D. */
1448 num_src_deriv_channels
= 3;
1449 num_dst_deriv_channels
= 3;
1451 case TGSI_TEXTURE_1D
:
1452 case TGSI_TEXTURE_SHADOW1D
:
1453 case TGSI_TEXTURE_1D_ARRAY
:
1454 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1455 num_src_deriv_channels
= 1;
1457 /* 1D textures are allocated and used as 2D on GFX9. */
1458 if (ctx
->screen
->info
.chip_class
== GFX9
) {
1459 num_dst_deriv_channels
= 2;
1461 num_dst_deriv_channels
= 1;
1465 unreachable("invalid target");
1468 for (param
= 0; param
< 2; param
++) {
1469 for (chan
= 0; chan
< num_src_deriv_channels
; chan
++)
1470 args
.derivs
[param
* num_dst_deriv_channels
+ chan
] =
1471 lp_build_emit_fetch(bld_base
, inst
, param
+1, chan
);
1473 /* Fill in the rest with zeros. */
1474 for (chan
= num_src_deriv_channels
;
1475 chan
< num_dst_deriv_channels
; chan
++)
1476 args
.derivs
[param
* num_dst_deriv_channels
+ chan
] =
1481 if (target
== TGSI_TEXTURE_CUBE
||
1482 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1483 target
== TGSI_TEXTURE_SHADOWCUBE
||
1484 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
) {
1485 ac_prepare_cube_coords(&ctx
->ac
,
1486 opcode
== TGSI_OPCODE_TXD
,
1487 target
== TGSI_TEXTURE_CUBE_ARRAY
||
1488 target
== TGSI_TEXTURE_SHADOWCUBE_ARRAY
,
1489 opcode
== TGSI_OPCODE_LODQ
,
1490 args
.coords
, args
.derivs
);
1491 } else if (tgsi_is_array_sampler(target
) &&
1492 opcode
!= TGSI_OPCODE_TXF
&&
1493 opcode
!= TGSI_OPCODE_TXF_LZ
&&
1494 ctx
->screen
->info
.chip_class
<= GFX8
) {
1495 unsigned array_coord
= target
== TGSI_TEXTURE_1D_ARRAY
? 1 : 2;
1496 args
.coords
[array_coord
] = ac_build_round(&ctx
->ac
, args
.coords
[array_coord
]);
1499 /* 1D textures are allocated and used as 2D on GFX9. */
1500 if (ctx
->screen
->info
.chip_class
== GFX9
) {
1501 LLVMValueRef filler
;
1503 /* Use 0.5, so that we don't sample the border color. */
1504 if (opcode
== TGSI_OPCODE_TXF
||
1505 opcode
== TGSI_OPCODE_TXF_LZ
)
1506 filler
= ctx
->i32_0
;
1508 filler
= LLVMConstReal(ctx
->f32
, 0.5);
1510 if (target
== TGSI_TEXTURE_1D
||
1511 target
== TGSI_TEXTURE_SHADOW1D
) {
1512 args
.coords
[1] = filler
;
1513 } else if (target
== TGSI_TEXTURE_1D_ARRAY
||
1514 target
== TGSI_TEXTURE_SHADOW1D_ARRAY
) {
1515 args
.coords
[2] = args
.coords
[1];
1516 args
.coords
[1] = filler
;
1520 /* Pack LOD or sample index */
1521 if (opcode
== TGSI_OPCODE_TXL
)
1522 args
.lod
= args
.coords
[3];
1523 else if (opcode
== TGSI_OPCODE_TXL2
)
1524 args
.lod
= lp_build_emit_fetch(bld_base
, inst
, 1, TGSI_CHAN_X
);
1525 else if (opcode
== TGSI_OPCODE_TXF
) {
1526 if (target
== TGSI_TEXTURE_2D_MSAA
) {
1527 /* No LOD, but move sample index into the right place. */
1528 args
.coords
[2] = args
.coords
[3];
1529 } else if (target
!= TGSI_TEXTURE_2D_ARRAY_MSAA
) {
1530 args
.lod
= args
.coords
[3];
1534 if ((target
== TGSI_TEXTURE_2D_MSAA
||
1535 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
) &&
1536 !(ctx
->screen
->debug_flags
& DBG(NO_FMASK
))) {
1537 ac_apply_fmask_to_sample(&ctx
->ac
, fmask_ptr
, args
.coords
,
1538 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
);
1541 if (opcode
== TGSI_OPCODE_TXF
||
1542 opcode
== TGSI_OPCODE_TXF_LZ
) {
1543 /* add tex offsets */
1544 if (inst
->Texture
.NumOffsets
) {
1545 const struct tgsi_texture_offset
*off
= inst
->TexOffsets
;
1547 assert(inst
->Texture
.NumOffsets
== 1);
1550 case TGSI_TEXTURE_3D
:
1552 LLVMBuildAdd(ctx
->ac
.builder
, args
.coords
[2],
1553 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleZ
], "");
1555 case TGSI_TEXTURE_2D
:
1556 case TGSI_TEXTURE_SHADOW2D
:
1557 case TGSI_TEXTURE_RECT
:
1558 case TGSI_TEXTURE_SHADOWRECT
:
1559 case TGSI_TEXTURE_2D_ARRAY
:
1560 case TGSI_TEXTURE_SHADOW2D_ARRAY
:
1562 LLVMBuildAdd(ctx
->ac
.builder
, args
.coords
[1],
1563 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleY
], "");
1565 case TGSI_TEXTURE_1D
:
1566 case TGSI_TEXTURE_SHADOW1D
:
1567 case TGSI_TEXTURE_1D_ARRAY
:
1568 case TGSI_TEXTURE_SHADOW1D_ARRAY
:
1570 LLVMBuildAdd(ctx
->ac
.builder
, args
.coords
[0],
1571 ctx
->imms
[off
->Index
* TGSI_NUM_CHANNELS
+ off
->SwizzleX
], "");
1573 /* texture offsets do not apply to other texture targets */
1578 if (opcode
== TGSI_OPCODE_TG4
) {
1579 unsigned gather_comp
= 0;
1581 /* DMASK was repurposed for GATHER4. 4 components are always
1582 * returned and DMASK works like a swizzle - it selects
1583 * the component to fetch. The only valid DMASK values are
1584 * 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
1585 * (red,red,red,red) etc.) The ISA document doesn't mention
1589 /* Get the component index from src1.x for Gather4. */
1590 if (!tgsi_is_shadow_target(target
)) {
1591 LLVMValueRef comp_imm
;
1592 struct tgsi_src_register src1
= inst
->Src
[1].Register
;
1594 assert(src1
.File
== TGSI_FILE_IMMEDIATE
);
1596 comp_imm
= ctx
->imms
[src1
.Index
* TGSI_NUM_CHANNELS
+ src1
.SwizzleX
];
1597 gather_comp
= LLVMConstIntGetZExtValue(comp_imm
);
1598 gather_comp
= CLAMP(gather_comp
, 0, 3);
1601 args
.dmask
= 1 << gather_comp
;
1606 args
.dim
= ac_texture_dim_from_tgsi_target(ctx
->screen
, target
);
1607 args
.unorm
= target
== TGSI_TEXTURE_RECT
||
1608 target
== TGSI_TEXTURE_SHADOWRECT
;
1609 args
.opcode
= ac_image_sample
;
1612 case TGSI_OPCODE_TXF
:
1613 case TGSI_OPCODE_TXF_LZ
:
1614 args
.opcode
= opcode
== TGSI_OPCODE_TXF_LZ
||
1615 target
== TGSI_TEXTURE_2D_MSAA
||
1616 target
== TGSI_TEXTURE_2D_ARRAY_MSAA
?
1617 ac_image_load
: ac_image_load_mip
;
1619 case TGSI_OPCODE_LODQ
:
1620 args
.opcode
= ac_image_get_lod
;
1622 case TGSI_OPCODE_TEX
:
1623 case TGSI_OPCODE_TEX2
:
1624 case TGSI_OPCODE_TXP
:
1625 if (ctx
->type
!= PIPE_SHADER_FRAGMENT
)
1626 args
.level_zero
= true;
1628 case TGSI_OPCODE_TEX_LZ
:
1629 args
.level_zero
= true;
1631 case TGSI_OPCODE_TXB
:
1632 case TGSI_OPCODE_TXB2
:
1633 assert(ctx
->type
== PIPE_SHADER_FRAGMENT
);
1635 case TGSI_OPCODE_TXL
:
1636 case TGSI_OPCODE_TXL2
:
1638 case TGSI_OPCODE_TXD
:
1640 case TGSI_OPCODE_TG4
:
1641 args
.opcode
= ac_image_gather4
;
1642 args
.level_zero
= true;
1649 /* The hardware needs special lowering for Gather4 with integer formats. */
1650 LLVMValueRef gather4_int_result_workaround
= NULL
;
1652 if (ctx
->screen
->info
.chip_class
<= GFX8
&&
1653 opcode
== TGSI_OPCODE_TG4
) {
1654 assert(inst
->Texture
.ReturnType
!= TGSI_RETURN_TYPE_UNKNOWN
);
1656 if (inst
->Texture
.ReturnType
== TGSI_RETURN_TYPE_SINT
||
1657 inst
->Texture
.ReturnType
== TGSI_RETURN_TYPE_UINT
) {
1658 gather4_int_result_workaround
=
1659 si_lower_gather4_integer(ctx
, &args
, target
,
1660 inst
->Texture
.ReturnType
);
1664 args
.attributes
= AC_FUNC_ATTR_READNONE
;
1665 LLVMValueRef result
= ac_build_image_opcode(&ctx
->ac
, &args
);
1667 if (gather4_int_result_workaround
) {
1668 result
= si_fix_gather4_integer_result(ctx
, result
,
1669 inst
->Texture
.ReturnType
,
1670 gather4_int_result_workaround
);
1673 emit_data
->output
[emit_data
->chan
] = result
;
1676 static void si_llvm_emit_txqs(
1677 const struct lp_build_tgsi_action
*action
,
1678 struct lp_build_tgsi_context
*bld_base
,
1679 struct lp_build_emit_data
*emit_data
)
1681 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1682 LLVMValueRef res
, samples
;
1683 LLVMValueRef res_ptr
, samp_ptr
, fmask_ptr
= NULL
;
1685 tex_fetch_ptrs(bld_base
, emit_data
, &res_ptr
, &samp_ptr
, &fmask_ptr
);
1687 /* Read the samples from the descriptor directly. */
1688 res
= LLVMBuildBitCast(ctx
->ac
.builder
, res_ptr
, ctx
->v8i32
, "");
1689 samples
= LLVMBuildExtractElement(ctx
->ac
.builder
, res
,
1690 LLVMConstInt(ctx
->i32
, 3, 0), "");
1691 samples
= LLVMBuildLShr(ctx
->ac
.builder
, samples
,
1692 LLVMConstInt(ctx
->i32
, 16, 0), "");
1693 samples
= LLVMBuildAnd(ctx
->ac
.builder
, samples
,
1694 LLVMConstInt(ctx
->i32
, 0xf, 0), "");
1695 samples
= LLVMBuildShl(ctx
->ac
.builder
, ctx
->i32_1
,
1698 emit_data
->output
[emit_data
->chan
] = samples
;
1701 static void si_llvm_emit_fbfetch(const struct lp_build_tgsi_action
*action
,
1702 struct lp_build_tgsi_context
*bld_base
,
1703 struct lp_build_emit_data
*emit_data
)
1705 struct si_shader_context
*ctx
= si_shader_context(bld_base
);
1706 struct ac_image_args args
= {};
1707 LLVMValueRef ptr
, image
, fmask
;
1709 /* Ignore src0, because KHR_blend_func_extended disallows multiple render
1713 /* Load the image descriptor. */
1714 STATIC_ASSERT(SI_PS_IMAGE_COLORBUF0
% 2 == 0);
1715 ptr
= LLVMGetParam(ctx
->main_fn
, ctx
->param_rw_buffers
);
1716 ptr
= LLVMBuildPointerCast(ctx
->ac
.builder
, ptr
,
1717 ac_array_in_const32_addr_space(ctx
->v8i32
), "");
1718 image
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
,
1719 LLVMConstInt(ctx
->i32
, SI_PS_IMAGE_COLORBUF0
/ 2, 0));
1723 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_POS_FIXED_PT
, 0, 16);
1725 if (!ctx
->shader
->key
.mono
.u
.ps
.fbfetch_is_1D
)
1726 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_POS_FIXED_PT
, 16, 16);
1728 /* Get the current render target layer index. */
1729 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
)
1730 args
.coords
[chan
++] = si_unpack_param(ctx
, SI_PARAM_ANCILLARY
, 16, 11);
1732 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
)
1733 args
.coords
[chan
++] = si_get_sample_id(ctx
);
1735 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
&&
1736 !(ctx
->screen
->debug_flags
& DBG(NO_FMASK
))) {
1737 fmask
= ac_build_load_to_sgpr(&ctx
->ac
, ptr
,
1738 LLVMConstInt(ctx
->i32
, SI_PS_IMAGE_COLORBUF0_FMASK
/ 2, 0));
1740 ac_apply_fmask_to_sample(&ctx
->ac
, fmask
, args
.coords
,
1741 ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
);
1744 args
.opcode
= ac_image_load
;
1745 args
.resource
= image
;
1747 args
.attributes
= AC_FUNC_ATTR_READNONE
;
1749 if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_msaa
)
1750 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1751 ac_image_2darraymsaa
: ac_image_2dmsaa
;
1752 else if (ctx
->shader
->key
.mono
.u
.ps
.fbfetch_is_1D
)
1753 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1754 ac_image_1darray
: ac_image_1d
;
1756 args
.dim
= ctx
->shader
->key
.mono
.u
.ps
.fbfetch_layered
?
1757 ac_image_2darray
: ac_image_2d
;
1759 emit_data
->output
[emit_data
->chan
] =
1760 ac_build_image_opcode(&ctx
->ac
, &args
);
1764 * Setup actions for TGSI memory opcode, including texture opcodes.
1766 void si_shader_context_init_mem(struct si_shader_context
*ctx
)
1768 struct lp_build_tgsi_context
*bld_base
= &ctx
->bld_base
;
1770 bld_base
->op_actions
[TGSI_OPCODE_TEX
].emit
= build_tex_intrinsic
;
1771 bld_base
->op_actions
[TGSI_OPCODE_TEX_LZ
].emit
= build_tex_intrinsic
;
1772 bld_base
->op_actions
[TGSI_OPCODE_TEX2
].emit
= build_tex_intrinsic
;
1773 bld_base
->op_actions
[TGSI_OPCODE_TXB
].emit
= build_tex_intrinsic
;
1774 bld_base
->op_actions
[TGSI_OPCODE_TXB2
].emit
= build_tex_intrinsic
;
1775 bld_base
->op_actions
[TGSI_OPCODE_TXD
].emit
= build_tex_intrinsic
;
1776 bld_base
->op_actions
[TGSI_OPCODE_TXF
].emit
= build_tex_intrinsic
;
1777 bld_base
->op_actions
[TGSI_OPCODE_TXF_LZ
].emit
= build_tex_intrinsic
;
1778 bld_base
->op_actions
[TGSI_OPCODE_TXL
].emit
= build_tex_intrinsic
;
1779 bld_base
->op_actions
[TGSI_OPCODE_TXL2
].emit
= build_tex_intrinsic
;
1780 bld_base
->op_actions
[TGSI_OPCODE_TXP
].emit
= build_tex_intrinsic
;
1781 bld_base
->op_actions
[TGSI_OPCODE_TXQ
].emit
= resq_emit
;
1782 bld_base
->op_actions
[TGSI_OPCODE_TG4
].emit
= build_tex_intrinsic
;
1783 bld_base
->op_actions
[TGSI_OPCODE_LODQ
].emit
= build_tex_intrinsic
;
1784 bld_base
->op_actions
[TGSI_OPCODE_TXQS
].emit
= si_llvm_emit_txqs
;
1786 bld_base
->op_actions
[TGSI_OPCODE_FBFETCH
].emit
= si_llvm_emit_fbfetch
;
1788 bld_base
->op_actions
[TGSI_OPCODE_LOAD
].emit
= load_emit
;
1789 bld_base
->op_actions
[TGSI_OPCODE_STORE
].emit
= store_emit
;
1790 bld_base
->op_actions
[TGSI_OPCODE_RESQ
].emit
= resq_emit
;
1792 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
].emit
= atomic_emit
;
1793 bld_base
->op_actions
[TGSI_OPCODE_ATOMUADD
].intr_name
= "add";
1794 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
].emit
= atomic_emit
;
1795 bld_base
->op_actions
[TGSI_OPCODE_ATOMXCHG
].intr_name
= "swap";
1796 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
].emit
= atomic_emit
;
1797 bld_base
->op_actions
[TGSI_OPCODE_ATOMCAS
].intr_name
= "cmpswap";
1798 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
].emit
= atomic_emit
;
1799 bld_base
->op_actions
[TGSI_OPCODE_ATOMAND
].intr_name
= "and";
1800 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
].emit
= atomic_emit
;
1801 bld_base
->op_actions
[TGSI_OPCODE_ATOMOR
].intr_name
= "or";
1802 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
].emit
= atomic_emit
;
1803 bld_base
->op_actions
[TGSI_OPCODE_ATOMXOR
].intr_name
= "xor";
1804 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
].emit
= atomic_emit
;
1805 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMIN
].intr_name
= "umin";
1806 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
].emit
= atomic_emit
;
1807 bld_base
->op_actions
[TGSI_OPCODE_ATOMUMAX
].intr_name
= "umax";
1808 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
].emit
= atomic_emit
;
1809 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMIN
].intr_name
= "smin";
1810 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
].emit
= atomic_emit
;
1811 bld_base
->op_actions
[TGSI_OPCODE_ATOMIMAX
].intr_name
= "smax";