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[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
36
37 struct gfx10_format {
38 unsigned img_format:9;
39
40 /* Various formats are only supported with workarounds for vertex fetch,
41 * and some 32_32_32 formats are supported natively, but only for buffers
42 * (possibly with some image support, actually, but no filtering). */
43 bool buffers_only:1;
44 };
45
46 #include "gfx10_format_table.h"
47
48 static unsigned si_map_swizzle(unsigned swizzle)
49 {
50 switch (swizzle) {
51 case PIPE_SWIZZLE_Y:
52 return V_008F0C_SQ_SEL_Y;
53 case PIPE_SWIZZLE_Z:
54 return V_008F0C_SQ_SEL_Z;
55 case PIPE_SWIZZLE_W:
56 return V_008F0C_SQ_SEL_W;
57 case PIPE_SWIZZLE_0:
58 return V_008F0C_SQ_SEL_0;
59 case PIPE_SWIZZLE_1:
60 return V_008F0C_SQ_SEL_1;
61 default: /* PIPE_SWIZZLE_X */
62 return V_008F0C_SQ_SEL_X;
63 }
64 }
65
66 /* 12.4 fixed-point */
67 static unsigned si_pack_float_12p4(float x)
68 {
69 return x <= 0 ? 0 :
70 x >= 4096 ? 0xffff : x * 16;
71 }
72
73 /*
74 * Inferred framebuffer and blender state.
75 *
76 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
77 * if there is not enough PS outputs.
78 */
79 static void si_emit_cb_render_state(struct si_context *sctx)
80 {
81 struct radeon_cmdbuf *cs = sctx->gfx_cs;
82 struct si_state_blend *blend = sctx->queued.named.blend;
83 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
84 * but you never know. */
85 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
86 unsigned i;
87
88 if (blend)
89 cb_target_mask &= blend->cb_target_mask;
90
91 /* Avoid a hang that happens when dual source blending is enabled
92 * but there is not enough color outputs. This is undefined behavior,
93 * so disable color writes completely.
94 *
95 * Reproducible with Unigine Heaven 4.0 and drirc missing.
96 */
97 if (blend && blend->dual_src_blend &&
98 sctx->ps_shader.cso &&
99 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
100 cb_target_mask = 0;
101
102 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
103 * I think we don't have to do anything between IBs.
104 */
105 if (sctx->screen->dfsm_allowed &&
106 sctx->last_cb_target_mask != cb_target_mask) {
107 sctx->last_cb_target_mask = cb_target_mask;
108
109 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
110 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
111 }
112
113 unsigned initial_cdw = cs->current.cdw;
114 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
115 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
116
117 if (sctx->chip_class >= GFX8) {
118 /* DCC MSAA workaround for blending.
119 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
120 * COMBINER_DISABLE, but that would be more complicated.
121 */
122 bool oc_disable = blend &&
123 blend->blend_enable_4bit & cb_target_mask &&
124 sctx->framebuffer.nr_samples >= 2;
125 unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
126
127 radeon_opt_set_context_reg(
128 sctx, R_028424_CB_DCC_CONTROL,
129 SI_TRACKED_CB_DCC_CONTROL,
130 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx->chip_class <= GFX9) |
131 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
132 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
133 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->has_dcc_constant_encode));
134 }
135
136 /* RB+ register settings. */
137 if (sctx->screen->rbplus_allowed) {
138 unsigned spi_shader_col_format =
139 sctx->ps_shader.cso ?
140 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
141 unsigned sx_ps_downconvert = 0;
142 unsigned sx_blend_opt_epsilon = 0;
143 unsigned sx_blend_opt_control = 0;
144
145 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
146 struct si_surface *surf =
147 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
148 unsigned format, swap, spi_format, colormask;
149 bool has_alpha, has_rgb;
150
151 if (!surf) {
152 /* If the color buffer is not set, the driver sets 32_R
153 * as the SPI color format, because the hw doesn't allow
154 * holes between color outputs, so also set this to
155 * enable RB+.
156 */
157 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
158 continue;
159 }
160
161 format = G_028C70_FORMAT(surf->cb_color_info);
162 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
163 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
164 colormask = (cb_target_mask >> (i * 4)) & 0xf;
165
166 /* Set if RGB and A are present. */
167 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
168
169 if (format == V_028C70_COLOR_8 ||
170 format == V_028C70_COLOR_16 ||
171 format == V_028C70_COLOR_32)
172 has_rgb = !has_alpha;
173 else
174 has_rgb = true;
175
176 /* Check the colormask and export format. */
177 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
178 has_rgb = false;
179 if (!(colormask & PIPE_MASK_A))
180 has_alpha = false;
181
182 if (spi_format == V_028714_SPI_SHADER_ZERO) {
183 has_rgb = false;
184 has_alpha = false;
185 }
186
187 /* Disable value checking for disabled channels. */
188 if (!has_rgb)
189 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
190 if (!has_alpha)
191 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
192
193 /* Enable down-conversion for 32bpp and smaller formats. */
194 switch (format) {
195 case V_028C70_COLOR_8:
196 case V_028C70_COLOR_8_8:
197 case V_028C70_COLOR_8_8_8_8:
198 /* For 1 and 2-channel formats, use the superset thereof. */
199 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
200 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
201 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
202 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
203 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
204 }
205 break;
206
207 case V_028C70_COLOR_5_6_5:
208 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
209 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
210 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
211 }
212 break;
213
214 case V_028C70_COLOR_1_5_5_5:
215 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
216 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
217 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
218 }
219 break;
220
221 case V_028C70_COLOR_4_4_4_4:
222 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
223 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
224 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
225 }
226 break;
227
228 case V_028C70_COLOR_32:
229 if (swap == V_028C70_SWAP_STD &&
230 spi_format == V_028714_SPI_SHADER_32_R)
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
232 else if (swap == V_028C70_SWAP_ALT_REV &&
233 spi_format == V_028714_SPI_SHADER_32_AR)
234 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
235 break;
236
237 case V_028C70_COLOR_16:
238 case V_028C70_COLOR_16_16:
239 /* For 1-channel formats, use the superset thereof. */
240 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
241 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
242 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
243 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
244 if (swap == V_028C70_SWAP_STD ||
245 swap == V_028C70_SWAP_STD_REV)
246 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
247 else
248 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
249 }
250 break;
251
252 case V_028C70_COLOR_10_11_11:
253 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
254 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
255 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
256 }
257 break;
258
259 case V_028C70_COLOR_2_10_10_10:
260 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
261 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
262 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
263 }
264 break;
265 }
266 }
267
268 /* If there are no color outputs, the first color export is
269 * always enabled as 32_R, so also set this to enable RB+.
270 */
271 if (!sx_ps_downconvert)
272 sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_R;
273
274 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
275 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
276 SI_TRACKED_SX_PS_DOWNCONVERT,
277 sx_ps_downconvert, sx_blend_opt_epsilon,
278 sx_blend_opt_control);
279 }
280 if (initial_cdw != cs->current.cdw)
281 sctx->context_roll = true;
282 }
283
284 /*
285 * Blender functions
286 */
287
288 static uint32_t si_translate_blend_function(int blend_func)
289 {
290 switch (blend_func) {
291 case PIPE_BLEND_ADD:
292 return V_028780_COMB_DST_PLUS_SRC;
293 case PIPE_BLEND_SUBTRACT:
294 return V_028780_COMB_SRC_MINUS_DST;
295 case PIPE_BLEND_REVERSE_SUBTRACT:
296 return V_028780_COMB_DST_MINUS_SRC;
297 case PIPE_BLEND_MIN:
298 return V_028780_COMB_MIN_DST_SRC;
299 case PIPE_BLEND_MAX:
300 return V_028780_COMB_MAX_DST_SRC;
301 default:
302 PRINT_ERR("Unknown blend function %d\n", blend_func);
303 assert(0);
304 break;
305 }
306 return 0;
307 }
308
309 static uint32_t si_translate_blend_factor(int blend_fact)
310 {
311 switch (blend_fact) {
312 case PIPE_BLENDFACTOR_ONE:
313 return V_028780_BLEND_ONE;
314 case PIPE_BLENDFACTOR_SRC_COLOR:
315 return V_028780_BLEND_SRC_COLOR;
316 case PIPE_BLENDFACTOR_SRC_ALPHA:
317 return V_028780_BLEND_SRC_ALPHA;
318 case PIPE_BLENDFACTOR_DST_ALPHA:
319 return V_028780_BLEND_DST_ALPHA;
320 case PIPE_BLENDFACTOR_DST_COLOR:
321 return V_028780_BLEND_DST_COLOR;
322 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
323 return V_028780_BLEND_SRC_ALPHA_SATURATE;
324 case PIPE_BLENDFACTOR_CONST_COLOR:
325 return V_028780_BLEND_CONSTANT_COLOR;
326 case PIPE_BLENDFACTOR_CONST_ALPHA:
327 return V_028780_BLEND_CONSTANT_ALPHA;
328 case PIPE_BLENDFACTOR_ZERO:
329 return V_028780_BLEND_ZERO;
330 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
331 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
332 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
333 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
334 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
335 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
336 case PIPE_BLENDFACTOR_INV_DST_COLOR:
337 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
338 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
339 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
340 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
341 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
342 case PIPE_BLENDFACTOR_SRC1_COLOR:
343 return V_028780_BLEND_SRC1_COLOR;
344 case PIPE_BLENDFACTOR_SRC1_ALPHA:
345 return V_028780_BLEND_SRC1_ALPHA;
346 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
347 return V_028780_BLEND_INV_SRC1_COLOR;
348 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
349 return V_028780_BLEND_INV_SRC1_ALPHA;
350 default:
351 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
352 assert(0);
353 break;
354 }
355 return 0;
356 }
357
358 static uint32_t si_translate_blend_opt_function(int blend_func)
359 {
360 switch (blend_func) {
361 case PIPE_BLEND_ADD:
362 return V_028760_OPT_COMB_ADD;
363 case PIPE_BLEND_SUBTRACT:
364 return V_028760_OPT_COMB_SUBTRACT;
365 case PIPE_BLEND_REVERSE_SUBTRACT:
366 return V_028760_OPT_COMB_REVSUBTRACT;
367 case PIPE_BLEND_MIN:
368 return V_028760_OPT_COMB_MIN;
369 case PIPE_BLEND_MAX:
370 return V_028760_OPT_COMB_MAX;
371 default:
372 return V_028760_OPT_COMB_BLEND_DISABLED;
373 }
374 }
375
376 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
377 {
378 switch (blend_fact) {
379 case PIPE_BLENDFACTOR_ZERO:
380 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
381 case PIPE_BLENDFACTOR_ONE:
382 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
383 case PIPE_BLENDFACTOR_SRC_COLOR:
384 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
385 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
386 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
387 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
388 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
389 case PIPE_BLENDFACTOR_SRC_ALPHA:
390 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
391 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
392 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
393 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
394 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
395 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
396 default:
397 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
398 }
399 }
400
401 static void si_blend_check_commutativity(struct si_screen *sscreen,
402 struct si_state_blend *blend,
403 enum pipe_blend_func func,
404 enum pipe_blendfactor src,
405 enum pipe_blendfactor dst,
406 unsigned chanmask)
407 {
408 /* Src factor is allowed when it does not depend on Dst */
409 static const uint32_t src_allowed =
410 (1u << PIPE_BLENDFACTOR_ONE) |
411 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
412 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
413 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
414 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
415 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
416 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
417 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
418 (1u << PIPE_BLENDFACTOR_ZERO) |
419 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
420 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
421 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
422 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
423 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
424 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
425
426 if (dst == PIPE_BLENDFACTOR_ONE &&
427 (src_allowed & (1u << src))) {
428 /* Addition is commutative, but floating point addition isn't
429 * associative: subtle changes can be introduced via different
430 * rounding.
431 *
432 * Out-of-order is also non-deterministic, which means that
433 * this breaks OpenGL invariance requirements. So only enable
434 * out-of-order additive blending if explicitly allowed by a
435 * setting.
436 */
437 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
438 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
439 blend->commutative_4bit |= chanmask;
440 }
441 }
442
443 /**
444 * Get rid of DST in the blend factors by commuting the operands:
445 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
446 */
447 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
448 unsigned *dst_factor, unsigned expected_dst,
449 unsigned replacement_src)
450 {
451 if (*src_factor == expected_dst &&
452 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
453 *src_factor = PIPE_BLENDFACTOR_ZERO;
454 *dst_factor = replacement_src;
455
456 /* Commuting the operands requires reversing subtractions. */
457 if (*func == PIPE_BLEND_SUBTRACT)
458 *func = PIPE_BLEND_REVERSE_SUBTRACT;
459 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
460 *func = PIPE_BLEND_SUBTRACT;
461 }
462 }
463
464 static bool si_blend_factor_uses_dst(unsigned factor)
465 {
466 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
467 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
468 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
469 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
470 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
471 }
472
473 static void *si_create_blend_state_mode(struct pipe_context *ctx,
474 const struct pipe_blend_state *state,
475 unsigned mode)
476 {
477 struct si_context *sctx = (struct si_context*)ctx;
478 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
479 struct si_pm4_state *pm4 = &blend->pm4;
480 uint32_t sx_mrt_blend_opt[8] = {0};
481 uint32_t color_control = 0;
482
483 if (!blend)
484 return NULL;
485
486 blend->alpha_to_coverage = state->alpha_to_coverage;
487 blend->alpha_to_one = state->alpha_to_one;
488 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
489 blend->logicop_enable = state->logicop_enable;
490
491 if (state->logicop_enable) {
492 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
493 } else {
494 color_control |= S_028808_ROP3(0xcc);
495 }
496
497 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
498 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
499 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
500 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
501 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
502 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
503 S_028B70_OFFSET_ROUND(1));
504
505 if (state->alpha_to_coverage)
506 blend->need_src_alpha_4bit |= 0xf;
507
508 blend->cb_target_mask = 0;
509 blend->cb_target_enabled_4bit = 0;
510
511 for (int i = 0; i < 8; i++) {
512 /* state->rt entries > 0 only written if independent blending */
513 const int j = state->independent_blend_enable ? i : 0;
514
515 unsigned eqRGB = state->rt[j].rgb_func;
516 unsigned srcRGB = state->rt[j].rgb_src_factor;
517 unsigned dstRGB = state->rt[j].rgb_dst_factor;
518 unsigned eqA = state->rt[j].alpha_func;
519 unsigned srcA = state->rt[j].alpha_src_factor;
520 unsigned dstA = state->rt[j].alpha_dst_factor;
521
522 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
523 unsigned blend_cntl = 0;
524
525 sx_mrt_blend_opt[i] =
526 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
527 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
528
529 /* Only set dual source blending for MRT0 to avoid a hang. */
530 if (i >= 1 && blend->dual_src_blend) {
531 /* Vulkan does this for dual source blending. */
532 if (i == 1)
533 blend_cntl |= S_028780_ENABLE(1);
534
535 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
536 continue;
537 }
538
539 /* Only addition and subtraction equations are supported with
540 * dual source blending.
541 */
542 if (blend->dual_src_blend &&
543 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
544 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
545 assert(!"Unsupported equation for dual source blending");
546 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
547 continue;
548 }
549
550 /* cb_render_state will disable unused ones */
551 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
552 if (state->rt[j].colormask)
553 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
554
555 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
556 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
557 continue;
558 }
559
560 si_blend_check_commutativity(sctx->screen, blend,
561 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
562 si_blend_check_commutativity(sctx->screen, blend,
563 eqA, srcA, dstA, 0x8 << (4 * i));
564
565 /* Blending optimizations for RB+.
566 * These transformations don't change the behavior.
567 *
568 * First, get rid of DST in the blend factors:
569 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
570 */
571 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
572 PIPE_BLENDFACTOR_DST_COLOR,
573 PIPE_BLENDFACTOR_SRC_COLOR);
574 si_blend_remove_dst(&eqA, &srcA, &dstA,
575 PIPE_BLENDFACTOR_DST_COLOR,
576 PIPE_BLENDFACTOR_SRC_COLOR);
577 si_blend_remove_dst(&eqA, &srcA, &dstA,
578 PIPE_BLENDFACTOR_DST_ALPHA,
579 PIPE_BLENDFACTOR_SRC_ALPHA);
580
581 /* Look up the ideal settings from tables. */
582 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
583 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
584 srcA_opt = si_translate_blend_opt_factor(srcA, true);
585 dstA_opt = si_translate_blend_opt_factor(dstA, true);
586
587 /* Handle interdependencies. */
588 if (si_blend_factor_uses_dst(srcRGB))
589 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
590 if (si_blend_factor_uses_dst(srcA))
591 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
592
593 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
594 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
595 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
596 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
597 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
598
599 /* Set the final value. */
600 sx_mrt_blend_opt[i] =
601 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
602 S_028760_COLOR_DST_OPT(dstRGB_opt) |
603 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
604 S_028760_ALPHA_SRC_OPT(srcA_opt) |
605 S_028760_ALPHA_DST_OPT(dstA_opt) |
606 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
607
608 /* Set blend state. */
609 blend_cntl |= S_028780_ENABLE(1);
610 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
611 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
612 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
613
614 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
615 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
616 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
617 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
618 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
619 }
620 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
621
622 blend->blend_enable_4bit |= 0xfu << (i * 4);
623
624 /* This is only important for formats without alpha. */
625 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
626 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
627 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
628 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
629 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
630 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
631 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
632 }
633
634 if (blend->cb_target_mask) {
635 color_control |= S_028808_MODE(mode);
636 } else {
637 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
638 }
639
640 if (sctx->screen->rbplus_allowed) {
641 /* Disable RB+ blend optimizations for dual source blending.
642 * Vulkan does this.
643 */
644 if (blend->dual_src_blend) {
645 for (int i = 0; i < 8; i++) {
646 sx_mrt_blend_opt[i] =
647 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
648 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
649 }
650 }
651
652 for (int i = 0; i < 8; i++)
653 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
654 sx_mrt_blend_opt[i]);
655
656 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
657 if (blend->dual_src_blend || state->logicop_enable ||
658 mode == V_028808_CB_RESOLVE)
659 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
660 }
661
662 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
663 return blend;
664 }
665
666 static void *si_create_blend_state(struct pipe_context *ctx,
667 const struct pipe_blend_state *state)
668 {
669 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
670 }
671
672 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
673 {
674 struct si_context *sctx = (struct si_context *)ctx;
675 struct si_state_blend *old_blend = sctx->queued.named.blend;
676 struct si_state_blend *blend = (struct si_state_blend *)state;
677
678 if (!state)
679 return;
680
681 si_pm4_bind_state(sctx, blend, state);
682
683 if (!old_blend ||
684 old_blend->cb_target_mask != blend->cb_target_mask ||
685 old_blend->dual_src_blend != blend->dual_src_blend ||
686 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
687 sctx->framebuffer.nr_samples >= 2 &&
688 sctx->screen->dcc_msaa_allowed))
689 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
690
691 if (!old_blend ||
692 old_blend->cb_target_mask != blend->cb_target_mask ||
693 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
694 old_blend->alpha_to_one != blend->alpha_to_one ||
695 old_blend->dual_src_blend != blend->dual_src_blend ||
696 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
697 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
698 sctx->do_update_shaders = true;
699
700 if (sctx->screen->dpbb_allowed &&
701 (!old_blend ||
702 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
703 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
704 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
705 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
706
707 if (sctx->screen->has_out_of_order_rast &&
708 (!old_blend ||
709 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
710 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
711 old_blend->commutative_4bit != blend->commutative_4bit ||
712 old_blend->logicop_enable != blend->logicop_enable)))
713 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
714 }
715
716 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
717 {
718 struct si_context *sctx = (struct si_context *)ctx;
719 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
720 }
721
722 static void si_set_blend_color(struct pipe_context *ctx,
723 const struct pipe_blend_color *state)
724 {
725 struct si_context *sctx = (struct si_context *)ctx;
726 static const struct pipe_blend_color zeros;
727
728 sctx->blend_color.state = *state;
729 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
730 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
731 }
732
733 static void si_emit_blend_color(struct si_context *sctx)
734 {
735 struct radeon_cmdbuf *cs = sctx->gfx_cs;
736
737 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
738 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
739 }
740
741 /*
742 * Clipping
743 */
744
745 static void si_set_clip_state(struct pipe_context *ctx,
746 const struct pipe_clip_state *state)
747 {
748 struct si_context *sctx = (struct si_context *)ctx;
749 struct pipe_constant_buffer cb;
750 static const struct pipe_clip_state zeros;
751
752 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
753 return;
754
755 sctx->clip_state.state = *state;
756 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
757 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
758
759 cb.buffer = NULL;
760 cb.user_buffer = state->ucp;
761 cb.buffer_offset = 0;
762 cb.buffer_size = 4*4*8;
763 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
764 pipe_resource_reference(&cb.buffer, NULL);
765 }
766
767 static void si_emit_clip_state(struct si_context *sctx)
768 {
769 struct radeon_cmdbuf *cs = sctx->gfx_cs;
770
771 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
772 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
773 }
774
775 static void si_emit_clip_regs(struct si_context *sctx)
776 {
777 struct si_shader *vs = si_get_vs_state(sctx);
778 struct si_shader_selector *vs_sel = vs->selector;
779 struct tgsi_shader_info *info = &vs_sel->info;
780 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
781 unsigned window_space =
782 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
783 unsigned clipdist_mask = vs_sel->clipdist_mask;
784 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
785 unsigned culldist_mask = vs_sel->culldist_mask;
786 unsigned total_mask;
787
788 if (vs->key.opt.clip_disable) {
789 assert(!info->culldist_writemask);
790 clipdist_mask = 0;
791 culldist_mask = 0;
792 }
793 total_mask = clipdist_mask | culldist_mask;
794
795 /* Clip distances on points have no effect, so need to be implemented
796 * as cull distances. This applies for the clipvertex case as well.
797 *
798 * Setting this for primitives other than points should have no adverse
799 * effects.
800 */
801 clipdist_mask &= rs->clip_plane_enable;
802 culldist_mask |= clipdist_mask;
803
804 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
805 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
806 SI_TRACKED_PA_CL_VS_OUT_CNTL,
807 vs_sel->pa_cl_vs_out_cntl |
808 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
809 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
810 clipdist_mask | (culldist_mask << 8));
811 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
812 SI_TRACKED_PA_CL_CLIP_CNTL,
813 rs->pa_cl_clip_cntl |
814 ucp_mask |
815 S_028810_CLIP_DISABLE(window_space));
816
817 if (initial_cdw != sctx->gfx_cs->current.cdw)
818 sctx->context_roll = true;
819 }
820
821 /*
822 * inferred state between framebuffer and rasterizer
823 */
824 static void si_update_poly_offset_state(struct si_context *sctx)
825 {
826 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
827
828 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
829 si_pm4_bind_state(sctx, poly_offset, NULL);
830 return;
831 }
832
833 /* Use the user format, not db_render_format, so that the polygon
834 * offset behaves as expected by applications.
835 */
836 switch (sctx->framebuffer.state.zsbuf->texture->format) {
837 case PIPE_FORMAT_Z16_UNORM:
838 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
839 break;
840 default: /* 24-bit */
841 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
842 break;
843 case PIPE_FORMAT_Z32_FLOAT:
844 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
845 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
846 break;
847 }
848 }
849
850 /*
851 * Rasterizer
852 */
853
854 static uint32_t si_translate_fill(uint32_t func)
855 {
856 switch(func) {
857 case PIPE_POLYGON_MODE_FILL:
858 return V_028814_X_DRAW_TRIANGLES;
859 case PIPE_POLYGON_MODE_LINE:
860 return V_028814_X_DRAW_LINES;
861 case PIPE_POLYGON_MODE_POINT:
862 return V_028814_X_DRAW_POINTS;
863 default:
864 assert(0);
865 return V_028814_X_DRAW_POINTS;
866 }
867 }
868
869 static void *si_create_rs_state(struct pipe_context *ctx,
870 const struct pipe_rasterizer_state *state)
871 {
872 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
873 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
874 struct si_pm4_state *pm4 = &rs->pm4;
875 unsigned tmp, i;
876 float psize_min, psize_max;
877
878 if (!rs) {
879 return NULL;
880 }
881
882 if (!state->front_ccw) {
883 rs->cull_front = !!(state->cull_face & PIPE_FACE_FRONT);
884 rs->cull_back = !!(state->cull_face & PIPE_FACE_BACK);
885 } else {
886 rs->cull_back = !!(state->cull_face & PIPE_FACE_FRONT);
887 rs->cull_front = !!(state->cull_face & PIPE_FACE_BACK);
888 }
889 rs->depth_clamp_any = !state->depth_clip_near || !state->depth_clip_far;
890 rs->provoking_vertex_first = state->flatshade_first;
891 rs->scissor_enable = state->scissor;
892 rs->clip_halfz = state->clip_halfz;
893 rs->two_side = state->light_twoside;
894 rs->multisample_enable = state->multisample;
895 rs->force_persample_interp = state->force_persample_interp;
896 rs->clip_plane_enable = state->clip_plane_enable;
897 rs->half_pixel_center = state->half_pixel_center;
898 rs->line_stipple_enable = state->line_stipple_enable;
899 rs->poly_stipple_enable = state->poly_stipple_enable;
900 rs->line_smooth = state->line_smooth;
901 rs->line_width = state->line_width;
902 rs->poly_smooth = state->poly_smooth;
903 rs->uses_poly_offset = state->offset_point || state->offset_line ||
904 state->offset_tri;
905 rs->clamp_fragment_color = state->clamp_fragment_color;
906 rs->clamp_vertex_color = state->clamp_vertex_color;
907 rs->flatshade = state->flatshade;
908 rs->flatshade_first = state->flatshade_first;
909 rs->sprite_coord_enable = state->sprite_coord_enable;
910 rs->rasterizer_discard = state->rasterizer_discard;
911 rs->pa_sc_line_stipple = state->line_stipple_enable ?
912 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
913 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
914 rs->pa_cl_clip_cntl =
915 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
916 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
917 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
918 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
919 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
920
921 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
922 S_0286D4_FLAT_SHADE_ENA(1) |
923 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
924 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
925 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
926 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
927 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
928 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
929
930 /* point size 12.4 fixed point */
931 tmp = (unsigned)(state->point_size * 8.0);
932 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
933
934 if (state->point_size_per_vertex) {
935 psize_min = util_get_min_point_size(state);
936 psize_max = SI_MAX_POINT_SIZE;
937 } else {
938 /* Force the point size to be as if the vertex output was disabled. */
939 psize_min = state->point_size;
940 psize_max = state->point_size;
941 }
942 rs->max_point_size = psize_max;
943
944 /* Divide by two, because 0.5 = 1 pixel. */
945 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
946 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
947 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
948
949 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
950 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
951 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
952 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
953 S_028A48_MSAA_ENABLE(state->multisample ||
954 state->poly_smooth ||
955 state->line_smooth) |
956 S_028A48_VPORT_SCISSOR_ENABLE(1) |
957 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
958
959 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
960 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
961 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
962 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
963 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
964 S_028814_FACE(!state->front_ccw) |
965 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
966 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
967 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
968 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
969 state->fill_back != PIPE_POLYGON_MODE_FILL) |
970 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
971 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
972
973 if (!rs->uses_poly_offset)
974 return rs;
975
976 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
977 if (!rs->pm4_poly_offset) {
978 FREE(rs);
979 return NULL;
980 }
981
982 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
983 for (i = 0; i < 3; i++) {
984 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
985 float offset_units = state->offset_units;
986 float offset_scale = state->offset_scale * 16.0f;
987 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
988
989 if (!state->offset_units_unscaled) {
990 switch (i) {
991 case 0: /* 16-bit zbuffer */
992 offset_units *= 4.0f;
993 pa_su_poly_offset_db_fmt_cntl =
994 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
995 break;
996 case 1: /* 24-bit zbuffer */
997 offset_units *= 2.0f;
998 pa_su_poly_offset_db_fmt_cntl =
999 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1000 break;
1001 case 2: /* 32-bit zbuffer */
1002 offset_units *= 1.0f;
1003 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1004 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1005 break;
1006 }
1007 }
1008
1009 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
1010 fui(offset_scale));
1011 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1012 fui(offset_units));
1013 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1014 fui(offset_scale));
1015 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1016 fui(offset_units));
1017 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1018 pa_su_poly_offset_db_fmt_cntl);
1019 }
1020
1021 return rs;
1022 }
1023
1024 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1025 {
1026 struct si_context *sctx = (struct si_context *)ctx;
1027 struct si_state_rasterizer *old_rs =
1028 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1029 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1030
1031 if (!state)
1032 return;
1033
1034 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
1035 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1036
1037 /* Update the small primitive filter workaround if necessary. */
1038 if (sctx->screen->has_msaa_sample_loc_bug &&
1039 sctx->framebuffer.nr_samples > 1)
1040 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1041 }
1042
1043 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1044 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1045
1046 si_pm4_bind_state(sctx, rasterizer, rs);
1047 si_update_poly_offset_state(sctx);
1048
1049 if (!old_rs ||
1050 old_rs->scissor_enable != rs->scissor_enable)
1051 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1052
1053 if (!old_rs ||
1054 old_rs->line_width != rs->line_width ||
1055 old_rs->max_point_size != rs->max_point_size ||
1056 old_rs->half_pixel_center != rs->half_pixel_center)
1057 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1058
1059 if (!old_rs ||
1060 old_rs->clip_halfz != rs->clip_halfz)
1061 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1062
1063 if (!old_rs ||
1064 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1065 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1066 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1067
1068 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1069 rs->line_stipple_enable;
1070
1071 if (!old_rs ||
1072 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1073 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1074 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1075 old_rs->flatshade != rs->flatshade ||
1076 old_rs->two_side != rs->two_side ||
1077 old_rs->multisample_enable != rs->multisample_enable ||
1078 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1079 old_rs->poly_smooth != rs->poly_smooth ||
1080 old_rs->line_smooth != rs->line_smooth ||
1081 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1082 old_rs->force_persample_interp != rs->force_persample_interp)
1083 sctx->do_update_shaders = true;
1084 }
1085
1086 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1087 {
1088 struct si_context *sctx = (struct si_context *)ctx;
1089 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1090
1091 if (sctx->queued.named.rasterizer == state)
1092 si_pm4_bind_state(sctx, poly_offset, NULL);
1093
1094 FREE(rs->pm4_poly_offset);
1095 si_pm4_delete_state(sctx, rasterizer, rs);
1096 }
1097
1098 /*
1099 * infeered state between dsa and stencil ref
1100 */
1101 static void si_emit_stencil_ref(struct si_context *sctx)
1102 {
1103 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1104 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1105 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1106
1107 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1108 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1109 S_028430_STENCILMASK(dsa->valuemask[0]) |
1110 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1111 S_028430_STENCILOPVAL(1));
1112 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1113 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1114 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1115 S_028434_STENCILOPVAL_BF(1));
1116 }
1117
1118 static void si_set_stencil_ref(struct pipe_context *ctx,
1119 const struct pipe_stencil_ref *state)
1120 {
1121 struct si_context *sctx = (struct si_context *)ctx;
1122
1123 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1124 return;
1125
1126 sctx->stencil_ref.state = *state;
1127 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1128 }
1129
1130
1131 /*
1132 * DSA
1133 */
1134
1135 static uint32_t si_translate_stencil_op(int s_op)
1136 {
1137 switch (s_op) {
1138 case PIPE_STENCIL_OP_KEEP:
1139 return V_02842C_STENCIL_KEEP;
1140 case PIPE_STENCIL_OP_ZERO:
1141 return V_02842C_STENCIL_ZERO;
1142 case PIPE_STENCIL_OP_REPLACE:
1143 return V_02842C_STENCIL_REPLACE_TEST;
1144 case PIPE_STENCIL_OP_INCR:
1145 return V_02842C_STENCIL_ADD_CLAMP;
1146 case PIPE_STENCIL_OP_DECR:
1147 return V_02842C_STENCIL_SUB_CLAMP;
1148 case PIPE_STENCIL_OP_INCR_WRAP:
1149 return V_02842C_STENCIL_ADD_WRAP;
1150 case PIPE_STENCIL_OP_DECR_WRAP:
1151 return V_02842C_STENCIL_SUB_WRAP;
1152 case PIPE_STENCIL_OP_INVERT:
1153 return V_02842C_STENCIL_INVERT;
1154 default:
1155 PRINT_ERR("Unknown stencil op %d", s_op);
1156 assert(0);
1157 break;
1158 }
1159 return 0;
1160 }
1161
1162 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1163 {
1164 return s->enabled && s->writemask &&
1165 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1166 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1167 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1168 }
1169
1170 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1171 {
1172 /* REPLACE is normally order invariant, except when the stencil
1173 * reference value is written by the fragment shader. Tracking this
1174 * interaction does not seem worth the effort, so be conservative. */
1175 return op != PIPE_STENCIL_OP_INCR &&
1176 op != PIPE_STENCIL_OP_DECR &&
1177 op != PIPE_STENCIL_OP_REPLACE;
1178 }
1179
1180 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1181 * invariant in the sense that the set of passing fragments as well as the
1182 * final stencil buffer result does not depend on the order of fragments. */
1183 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1184 {
1185 return !state->enabled || !state->writemask ||
1186 /* The following assumes that Z writes are disabled. */
1187 (state->func == PIPE_FUNC_ALWAYS &&
1188 si_order_invariant_stencil_op(state->zpass_op) &&
1189 si_order_invariant_stencil_op(state->zfail_op)) ||
1190 (state->func == PIPE_FUNC_NEVER &&
1191 si_order_invariant_stencil_op(state->fail_op));
1192 }
1193
1194 static void *si_create_dsa_state(struct pipe_context *ctx,
1195 const struct pipe_depth_stencil_alpha_state *state)
1196 {
1197 struct si_context *sctx = (struct si_context *)ctx;
1198 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1199 struct si_pm4_state *pm4 = &dsa->pm4;
1200 unsigned db_depth_control;
1201 uint32_t db_stencil_control = 0;
1202
1203 if (!dsa) {
1204 return NULL;
1205 }
1206
1207 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1208 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1209 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1210 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1211
1212 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1213 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1214 S_028800_ZFUNC(state->depth.func) |
1215 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1216
1217 /* stencil */
1218 if (state->stencil[0].enabled) {
1219 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1220 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1221 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1222 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1223 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1224
1225 if (state->stencil[1].enabled) {
1226 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1227 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1228 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1229 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1230 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1231 }
1232 }
1233
1234 /* alpha */
1235 if (state->alpha.enabled) {
1236 dsa->alpha_func = state->alpha.func;
1237
1238 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1239 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1240 } else {
1241 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1242 }
1243
1244 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1245 if (state->stencil[0].enabled)
1246 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1247 if (state->depth.bounds_test) {
1248 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1249 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1250 }
1251
1252 dsa->depth_enabled = state->depth.enabled;
1253 dsa->depth_write_enabled = state->depth.enabled &&
1254 state->depth.writemask;
1255 dsa->stencil_enabled = state->stencil[0].enabled;
1256 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1257 (si_dsa_writes_stencil(&state->stencil[0]) ||
1258 si_dsa_writes_stencil(&state->stencil[1]));
1259 dsa->db_can_write = dsa->depth_write_enabled ||
1260 dsa->stencil_write_enabled;
1261
1262 bool zfunc_is_ordered =
1263 state->depth.func == PIPE_FUNC_NEVER ||
1264 state->depth.func == PIPE_FUNC_LESS ||
1265 state->depth.func == PIPE_FUNC_LEQUAL ||
1266 state->depth.func == PIPE_FUNC_GREATER ||
1267 state->depth.func == PIPE_FUNC_GEQUAL;
1268
1269 bool nozwrite_and_order_invariant_stencil =
1270 !dsa->db_can_write ||
1271 (!dsa->depth_write_enabled &&
1272 si_order_invariant_stencil_state(&state->stencil[0]) &&
1273 si_order_invariant_stencil_state(&state->stencil[1]));
1274
1275 dsa->order_invariance[1].zs =
1276 nozwrite_and_order_invariant_stencil ||
1277 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1278 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1279
1280 dsa->order_invariance[1].pass_set =
1281 nozwrite_and_order_invariant_stencil ||
1282 (!dsa->stencil_write_enabled &&
1283 (state->depth.func == PIPE_FUNC_ALWAYS ||
1284 state->depth.func == PIPE_FUNC_NEVER));
1285 dsa->order_invariance[0].pass_set =
1286 !dsa->depth_write_enabled ||
1287 (state->depth.func == PIPE_FUNC_ALWAYS ||
1288 state->depth.func == PIPE_FUNC_NEVER);
1289
1290 dsa->order_invariance[1].pass_last =
1291 sctx->screen->assume_no_z_fights &&
1292 !dsa->stencil_write_enabled &&
1293 dsa->depth_write_enabled && zfunc_is_ordered;
1294 dsa->order_invariance[0].pass_last =
1295 sctx->screen->assume_no_z_fights &&
1296 dsa->depth_write_enabled && zfunc_is_ordered;
1297
1298 return dsa;
1299 }
1300
1301 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1302 {
1303 struct si_context *sctx = (struct si_context *)ctx;
1304 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1305 struct si_state_dsa *dsa = state;
1306
1307 if (!state)
1308 return;
1309
1310 si_pm4_bind_state(sctx, dsa, dsa);
1311
1312 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1313 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1314 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1315 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1316 }
1317
1318 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1319 sctx->do_update_shaders = true;
1320
1321 if (sctx->screen->dpbb_allowed &&
1322 (!old_dsa ||
1323 (old_dsa->depth_enabled != dsa->depth_enabled ||
1324 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1325 old_dsa->db_can_write != dsa->db_can_write)))
1326 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1327
1328 if (sctx->screen->has_out_of_order_rast &&
1329 (!old_dsa ||
1330 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1331 sizeof(old_dsa->order_invariance))))
1332 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1333 }
1334
1335 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1336 {
1337 struct si_context *sctx = (struct si_context *)ctx;
1338 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1339 }
1340
1341 static void *si_create_db_flush_dsa(struct si_context *sctx)
1342 {
1343 struct pipe_depth_stencil_alpha_state dsa = {};
1344
1345 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1346 }
1347
1348 /* DB RENDER STATE */
1349
1350 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1351 {
1352 struct si_context *sctx = (struct si_context*)ctx;
1353
1354 /* Pipeline stat & streamout queries. */
1355 if (enable) {
1356 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1357 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1358 } else {
1359 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1360 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1361 }
1362
1363 /* Occlusion queries. */
1364 if (sctx->occlusion_queries_disabled != !enable) {
1365 sctx->occlusion_queries_disabled = !enable;
1366 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1367 }
1368 }
1369
1370 void si_set_occlusion_query_state(struct si_context *sctx,
1371 bool old_perfect_enable)
1372 {
1373 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1374
1375 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1376
1377 if (perfect_enable != old_perfect_enable)
1378 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1379 }
1380
1381 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1382 {
1383 st->saved_compute = sctx->cs_shader_state.program;
1384
1385 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1386 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1387
1388 st->saved_ssbo_writable_mask = 0;
1389
1390 for (unsigned i = 0; i < 3; i++) {
1391 if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
1392 (1u << si_get_shaderbuf_slot(i)))
1393 st->saved_ssbo_writable_mask |= 1 << i;
1394 }
1395 }
1396
1397 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1398 {
1399 sctx->b.bind_compute_state(&sctx->b, st->saved_compute);
1400
1401 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1402 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1403
1404 sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo,
1405 st->saved_ssbo_writable_mask);
1406 for (unsigned i = 0; i < 3; ++i)
1407 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1408 }
1409
1410 static void si_emit_db_render_state(struct si_context *sctx)
1411 {
1412 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1413 unsigned db_shader_control, db_render_control, db_count_control;
1414 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1415
1416 /* DB_RENDER_CONTROL */
1417 if (sctx->dbcb_depth_copy_enabled ||
1418 sctx->dbcb_stencil_copy_enabled) {
1419 db_render_control =
1420 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1421 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1422 S_028000_COPY_CENTROID(1) |
1423 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1424 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1425 db_render_control =
1426 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1427 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1428 } else {
1429 db_render_control =
1430 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1431 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1432 }
1433
1434 /* DB_COUNT_CONTROL (occlusion queries) */
1435 if (sctx->num_occlusion_queries > 0 &&
1436 !sctx->occlusion_queries_disabled) {
1437 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1438
1439 if (sctx->chip_class >= GFX7) {
1440 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1441
1442 /* Stoney doesn't increment occlusion query counters
1443 * if the sample rate is 16x. Use 8x sample rate instead.
1444 */
1445 if (sctx->family == CHIP_STONEY)
1446 log_sample_rate = MIN2(log_sample_rate, 3);
1447
1448 db_count_control =
1449 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1450 S_028004_SAMPLE_RATE(log_sample_rate) |
1451 S_028004_ZPASS_ENABLE(1) |
1452 S_028004_SLICE_EVEN_ENABLE(1) |
1453 S_028004_SLICE_ODD_ENABLE(1);
1454 } else {
1455 db_count_control =
1456 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1457 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1458 }
1459 } else {
1460 /* Disable occlusion queries. */
1461 if (sctx->chip_class >= GFX7) {
1462 db_count_control = 0;
1463 } else {
1464 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1465 }
1466 }
1467
1468 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1469 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1470 db_count_control);
1471
1472 /* DB_RENDER_OVERRIDE2 */
1473 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1474 SI_TRACKED_DB_RENDER_OVERRIDE2,
1475 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1476 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1477 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1478
1479 db_shader_control = sctx->ps_db_shader_control;
1480
1481 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1482 if (sctx->chip_class == GFX6 && sctx->smoothing_enabled) {
1483 db_shader_control &= C_02880C_Z_ORDER;
1484 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1485 }
1486
1487 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1488 if (!rs->multisample_enable)
1489 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1490
1491 if (sctx->screen->has_rbplus &&
1492 !sctx->screen->rbplus_allowed)
1493 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1494
1495 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1496 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1497
1498 if (initial_cdw != sctx->gfx_cs->current.cdw)
1499 sctx->context_roll = true;
1500 }
1501
1502 /*
1503 * format translation
1504 */
1505 static uint32_t si_translate_colorformat(enum pipe_format format)
1506 {
1507 const struct util_format_description *desc = util_format_description(format);
1508 if (!desc)
1509 return V_028C70_COLOR_INVALID;
1510
1511 #define HAS_SIZE(x,y,z,w) \
1512 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1513 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1514
1515 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1516 return V_028C70_COLOR_10_11_11;
1517
1518 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1519 return V_028C70_COLOR_INVALID;
1520
1521 /* hw cannot support mixed formats (except depth/stencil, since
1522 * stencil is not written to). */
1523 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1524 return V_028C70_COLOR_INVALID;
1525
1526 switch (desc->nr_channels) {
1527 case 1:
1528 switch (desc->channel[0].size) {
1529 case 8:
1530 return V_028C70_COLOR_8;
1531 case 16:
1532 return V_028C70_COLOR_16;
1533 case 32:
1534 return V_028C70_COLOR_32;
1535 }
1536 break;
1537 case 2:
1538 if (desc->channel[0].size == desc->channel[1].size) {
1539 switch (desc->channel[0].size) {
1540 case 8:
1541 return V_028C70_COLOR_8_8;
1542 case 16:
1543 return V_028C70_COLOR_16_16;
1544 case 32:
1545 return V_028C70_COLOR_32_32;
1546 }
1547 } else if (HAS_SIZE(8,24,0,0)) {
1548 return V_028C70_COLOR_24_8;
1549 } else if (HAS_SIZE(24,8,0,0)) {
1550 return V_028C70_COLOR_8_24;
1551 }
1552 break;
1553 case 3:
1554 if (HAS_SIZE(5,6,5,0)) {
1555 return V_028C70_COLOR_5_6_5;
1556 } else if (HAS_SIZE(32,8,24,0)) {
1557 return V_028C70_COLOR_X24_8_32_FLOAT;
1558 }
1559 break;
1560 case 4:
1561 if (desc->channel[0].size == desc->channel[1].size &&
1562 desc->channel[0].size == desc->channel[2].size &&
1563 desc->channel[0].size == desc->channel[3].size) {
1564 switch (desc->channel[0].size) {
1565 case 4:
1566 return V_028C70_COLOR_4_4_4_4;
1567 case 8:
1568 return V_028C70_COLOR_8_8_8_8;
1569 case 16:
1570 return V_028C70_COLOR_16_16_16_16;
1571 case 32:
1572 return V_028C70_COLOR_32_32_32_32;
1573 }
1574 } else if (HAS_SIZE(5,5,5,1)) {
1575 return V_028C70_COLOR_1_5_5_5;
1576 } else if (HAS_SIZE(1,5,5,5)) {
1577 return V_028C70_COLOR_5_5_5_1;
1578 } else if (HAS_SIZE(10,10,10,2)) {
1579 return V_028C70_COLOR_2_10_10_10;
1580 }
1581 break;
1582 }
1583 return V_028C70_COLOR_INVALID;
1584 }
1585
1586 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1587 {
1588 if (SI_BIG_ENDIAN) {
1589 switch(colorformat) {
1590 /* 8-bit buffers. */
1591 case V_028C70_COLOR_8:
1592 return V_028C70_ENDIAN_NONE;
1593
1594 /* 16-bit buffers. */
1595 case V_028C70_COLOR_5_6_5:
1596 case V_028C70_COLOR_1_5_5_5:
1597 case V_028C70_COLOR_4_4_4_4:
1598 case V_028C70_COLOR_16:
1599 case V_028C70_COLOR_8_8:
1600 return V_028C70_ENDIAN_8IN16;
1601
1602 /* 32-bit buffers. */
1603 case V_028C70_COLOR_8_8_8_8:
1604 case V_028C70_COLOR_2_10_10_10:
1605 case V_028C70_COLOR_8_24:
1606 case V_028C70_COLOR_24_8:
1607 case V_028C70_COLOR_16_16:
1608 return V_028C70_ENDIAN_8IN32;
1609
1610 /* 64-bit buffers. */
1611 case V_028C70_COLOR_16_16_16_16:
1612 return V_028C70_ENDIAN_8IN16;
1613
1614 case V_028C70_COLOR_32_32:
1615 return V_028C70_ENDIAN_8IN32;
1616
1617 /* 128-bit buffers. */
1618 case V_028C70_COLOR_32_32_32_32:
1619 return V_028C70_ENDIAN_8IN32;
1620 default:
1621 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1622 }
1623 } else {
1624 return V_028C70_ENDIAN_NONE;
1625 }
1626 }
1627
1628 static uint32_t si_translate_dbformat(enum pipe_format format)
1629 {
1630 switch (format) {
1631 case PIPE_FORMAT_Z16_UNORM:
1632 return V_028040_Z_16;
1633 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1634 case PIPE_FORMAT_X8Z24_UNORM:
1635 case PIPE_FORMAT_Z24X8_UNORM:
1636 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1637 return V_028040_Z_24; /* deprecated on AMD GCN */
1638 case PIPE_FORMAT_Z32_FLOAT:
1639 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1640 return V_028040_Z_32_FLOAT;
1641 default:
1642 return V_028040_Z_INVALID;
1643 }
1644 }
1645
1646 /*
1647 * Texture translation
1648 */
1649
1650 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1651 enum pipe_format format,
1652 const struct util_format_description *desc,
1653 int first_non_void)
1654 {
1655 struct si_screen *sscreen = (struct si_screen*)screen;
1656 bool uniform = true;
1657 int i;
1658
1659 assert(sscreen->info.chip_class <= GFX9);
1660
1661 /* Colorspace (return non-RGB formats directly). */
1662 switch (desc->colorspace) {
1663 /* Depth stencil formats */
1664 case UTIL_FORMAT_COLORSPACE_ZS:
1665 switch (format) {
1666 case PIPE_FORMAT_Z16_UNORM:
1667 return V_008F14_IMG_DATA_FORMAT_16;
1668 case PIPE_FORMAT_X24S8_UINT:
1669 case PIPE_FORMAT_S8X24_UINT:
1670 /*
1671 * Implemented as an 8_8_8_8 data format to fix texture
1672 * gathers in stencil sampling. This affects at least
1673 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1674 */
1675 if (sscreen->info.chip_class <= GFX8)
1676 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1677
1678 if (format == PIPE_FORMAT_X24S8_UINT)
1679 return V_008F14_IMG_DATA_FORMAT_8_24;
1680 else
1681 return V_008F14_IMG_DATA_FORMAT_24_8;
1682 case PIPE_FORMAT_Z24X8_UNORM:
1683 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1684 return V_008F14_IMG_DATA_FORMAT_8_24;
1685 case PIPE_FORMAT_X8Z24_UNORM:
1686 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1687 return V_008F14_IMG_DATA_FORMAT_24_8;
1688 case PIPE_FORMAT_S8_UINT:
1689 return V_008F14_IMG_DATA_FORMAT_8;
1690 case PIPE_FORMAT_Z32_FLOAT:
1691 return V_008F14_IMG_DATA_FORMAT_32;
1692 case PIPE_FORMAT_X32_S8X24_UINT:
1693 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1694 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1695 default:
1696 goto out_unknown;
1697 }
1698
1699 case UTIL_FORMAT_COLORSPACE_YUV:
1700 goto out_unknown; /* TODO */
1701
1702 case UTIL_FORMAT_COLORSPACE_SRGB:
1703 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1704 goto out_unknown;
1705 break;
1706
1707 default:
1708 break;
1709 }
1710
1711 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1712 if (!sscreen->info.has_format_bc1_through_bc7)
1713 goto out_unknown;
1714
1715 switch (format) {
1716 case PIPE_FORMAT_RGTC1_SNORM:
1717 case PIPE_FORMAT_LATC1_SNORM:
1718 case PIPE_FORMAT_RGTC1_UNORM:
1719 case PIPE_FORMAT_LATC1_UNORM:
1720 return V_008F14_IMG_DATA_FORMAT_BC4;
1721 case PIPE_FORMAT_RGTC2_SNORM:
1722 case PIPE_FORMAT_LATC2_SNORM:
1723 case PIPE_FORMAT_RGTC2_UNORM:
1724 case PIPE_FORMAT_LATC2_UNORM:
1725 return V_008F14_IMG_DATA_FORMAT_BC5;
1726 default:
1727 goto out_unknown;
1728 }
1729 }
1730
1731 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1732 (sscreen->info.family == CHIP_STONEY ||
1733 sscreen->info.family == CHIP_VEGA10 ||
1734 sscreen->info.family == CHIP_RAVEN)) {
1735 switch (format) {
1736 case PIPE_FORMAT_ETC1_RGB8:
1737 case PIPE_FORMAT_ETC2_RGB8:
1738 case PIPE_FORMAT_ETC2_SRGB8:
1739 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1740 case PIPE_FORMAT_ETC2_RGB8A1:
1741 case PIPE_FORMAT_ETC2_SRGB8A1:
1742 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1743 case PIPE_FORMAT_ETC2_RGBA8:
1744 case PIPE_FORMAT_ETC2_SRGBA8:
1745 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1746 case PIPE_FORMAT_ETC2_R11_UNORM:
1747 case PIPE_FORMAT_ETC2_R11_SNORM:
1748 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1749 case PIPE_FORMAT_ETC2_RG11_UNORM:
1750 case PIPE_FORMAT_ETC2_RG11_SNORM:
1751 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1752 default:
1753 goto out_unknown;
1754 }
1755 }
1756
1757 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1758 if (!sscreen->info.has_format_bc1_through_bc7)
1759 goto out_unknown;
1760
1761 switch (format) {
1762 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1763 case PIPE_FORMAT_BPTC_SRGBA:
1764 return V_008F14_IMG_DATA_FORMAT_BC7;
1765 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1766 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1767 return V_008F14_IMG_DATA_FORMAT_BC6;
1768 default:
1769 goto out_unknown;
1770 }
1771 }
1772
1773 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1774 switch (format) {
1775 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1776 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1777 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1778 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1779 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1780 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1781 default:
1782 goto out_unknown;
1783 }
1784 }
1785
1786 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1787 if (!sscreen->info.has_format_bc1_through_bc7)
1788 goto out_unknown;
1789
1790 switch (format) {
1791 case PIPE_FORMAT_DXT1_RGB:
1792 case PIPE_FORMAT_DXT1_RGBA:
1793 case PIPE_FORMAT_DXT1_SRGB:
1794 case PIPE_FORMAT_DXT1_SRGBA:
1795 return V_008F14_IMG_DATA_FORMAT_BC1;
1796 case PIPE_FORMAT_DXT3_RGBA:
1797 case PIPE_FORMAT_DXT3_SRGBA:
1798 return V_008F14_IMG_DATA_FORMAT_BC2;
1799 case PIPE_FORMAT_DXT5_RGBA:
1800 case PIPE_FORMAT_DXT5_SRGBA:
1801 return V_008F14_IMG_DATA_FORMAT_BC3;
1802 default:
1803 goto out_unknown;
1804 }
1805 }
1806
1807 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1808 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1809 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1810 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1811 }
1812
1813 /* R8G8Bx_SNORM - TODO CxV8U8 */
1814
1815 /* hw cannot support mixed formats (except depth/stencil, since only
1816 * depth is read).*/
1817 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1818 goto out_unknown;
1819
1820 /* See whether the components are of the same size. */
1821 for (i = 1; i < desc->nr_channels; i++) {
1822 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1823 }
1824
1825 /* Non-uniform formats. */
1826 if (!uniform) {
1827 switch(desc->nr_channels) {
1828 case 3:
1829 if (desc->channel[0].size == 5 &&
1830 desc->channel[1].size == 6 &&
1831 desc->channel[2].size == 5) {
1832 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1833 }
1834 goto out_unknown;
1835 case 4:
1836 if (desc->channel[0].size == 5 &&
1837 desc->channel[1].size == 5 &&
1838 desc->channel[2].size == 5 &&
1839 desc->channel[3].size == 1) {
1840 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1841 }
1842 if (desc->channel[0].size == 1 &&
1843 desc->channel[1].size == 5 &&
1844 desc->channel[2].size == 5 &&
1845 desc->channel[3].size == 5) {
1846 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1847 }
1848 if (desc->channel[0].size == 10 &&
1849 desc->channel[1].size == 10 &&
1850 desc->channel[2].size == 10 &&
1851 desc->channel[3].size == 2) {
1852 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1853 }
1854 goto out_unknown;
1855 }
1856 goto out_unknown;
1857 }
1858
1859 if (first_non_void < 0 || first_non_void > 3)
1860 goto out_unknown;
1861
1862 /* uniform formats */
1863 switch (desc->channel[first_non_void].size) {
1864 case 4:
1865 switch (desc->nr_channels) {
1866 #if 0 /* Not supported for render targets */
1867 case 2:
1868 return V_008F14_IMG_DATA_FORMAT_4_4;
1869 #endif
1870 case 4:
1871 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1872 }
1873 break;
1874 case 8:
1875 switch (desc->nr_channels) {
1876 case 1:
1877 return V_008F14_IMG_DATA_FORMAT_8;
1878 case 2:
1879 return V_008F14_IMG_DATA_FORMAT_8_8;
1880 case 4:
1881 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1882 }
1883 break;
1884 case 16:
1885 switch (desc->nr_channels) {
1886 case 1:
1887 return V_008F14_IMG_DATA_FORMAT_16;
1888 case 2:
1889 return V_008F14_IMG_DATA_FORMAT_16_16;
1890 case 4:
1891 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1892 }
1893 break;
1894 case 32:
1895 switch (desc->nr_channels) {
1896 case 1:
1897 return V_008F14_IMG_DATA_FORMAT_32;
1898 case 2:
1899 return V_008F14_IMG_DATA_FORMAT_32_32;
1900 #if 0 /* Not supported for render targets */
1901 case 3:
1902 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1903 #endif
1904 case 4:
1905 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1906 }
1907 }
1908
1909 out_unknown:
1910 return ~0;
1911 }
1912
1913 static unsigned si_tex_wrap(unsigned wrap)
1914 {
1915 switch (wrap) {
1916 default:
1917 case PIPE_TEX_WRAP_REPEAT:
1918 return V_008F30_SQ_TEX_WRAP;
1919 case PIPE_TEX_WRAP_CLAMP:
1920 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1921 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1922 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1923 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1924 return V_008F30_SQ_TEX_CLAMP_BORDER;
1925 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1926 return V_008F30_SQ_TEX_MIRROR;
1927 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1928 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1929 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1930 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1931 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1932 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1933 }
1934 }
1935
1936 static unsigned si_tex_mipfilter(unsigned filter)
1937 {
1938 switch (filter) {
1939 case PIPE_TEX_MIPFILTER_NEAREST:
1940 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1941 case PIPE_TEX_MIPFILTER_LINEAR:
1942 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1943 default:
1944 case PIPE_TEX_MIPFILTER_NONE:
1945 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1946 }
1947 }
1948
1949 static unsigned si_tex_compare(unsigned compare)
1950 {
1951 switch (compare) {
1952 default:
1953 case PIPE_FUNC_NEVER:
1954 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1955 case PIPE_FUNC_LESS:
1956 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1957 case PIPE_FUNC_EQUAL:
1958 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1959 case PIPE_FUNC_LEQUAL:
1960 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1961 case PIPE_FUNC_GREATER:
1962 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1963 case PIPE_FUNC_NOTEQUAL:
1964 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1965 case PIPE_FUNC_GEQUAL:
1966 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1967 case PIPE_FUNC_ALWAYS:
1968 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1969 }
1970 }
1971
1972 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1973 unsigned view_target, unsigned nr_samples)
1974 {
1975 unsigned res_target = tex->buffer.b.b.target;
1976
1977 if (view_target == PIPE_TEXTURE_CUBE ||
1978 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1979 res_target = view_target;
1980 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1981 else if (res_target == PIPE_TEXTURE_CUBE ||
1982 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1983 res_target = PIPE_TEXTURE_2D_ARRAY;
1984
1985 /* GFX9 allocates 1D textures as 2D. */
1986 if ((res_target == PIPE_TEXTURE_1D ||
1987 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1988 sscreen->info.chip_class == GFX9 &&
1989 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1990 if (res_target == PIPE_TEXTURE_1D)
1991 res_target = PIPE_TEXTURE_2D;
1992 else
1993 res_target = PIPE_TEXTURE_2D_ARRAY;
1994 }
1995
1996 switch (res_target) {
1997 default:
1998 case PIPE_TEXTURE_1D:
1999 return V_008F1C_SQ_RSRC_IMG_1D;
2000 case PIPE_TEXTURE_1D_ARRAY:
2001 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
2002 case PIPE_TEXTURE_2D:
2003 case PIPE_TEXTURE_RECT:
2004 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
2005 V_008F1C_SQ_RSRC_IMG_2D;
2006 case PIPE_TEXTURE_2D_ARRAY:
2007 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
2008 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2009 case PIPE_TEXTURE_3D:
2010 return V_008F1C_SQ_RSRC_IMG_3D;
2011 case PIPE_TEXTURE_CUBE:
2012 case PIPE_TEXTURE_CUBE_ARRAY:
2013 return V_008F1C_SQ_RSRC_IMG_CUBE;
2014 }
2015 }
2016
2017 /*
2018 * Format support testing
2019 */
2020
2021 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
2022 {
2023 struct si_screen *sscreen = (struct si_screen *)screen;
2024
2025 if (sscreen->info.chip_class >= GFX10) {
2026 const struct gfx10_format *fmt = &gfx10_format_table[format];
2027 if (!fmt->img_format || fmt->buffers_only)
2028 return false;
2029 return true;
2030 }
2031
2032 const struct util_format_description *desc = util_format_description(format);
2033 if (!desc)
2034 return false;
2035
2036 return si_translate_texformat(screen, format, desc,
2037 util_format_get_first_non_void_channel(format)) != ~0U;
2038 }
2039
2040 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
2041 const struct util_format_description *desc,
2042 int first_non_void)
2043 {
2044 int i;
2045
2046 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2047
2048 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2049 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
2050
2051 assert(first_non_void >= 0);
2052
2053 if (desc->nr_channels == 4 &&
2054 desc->channel[0].size == 10 &&
2055 desc->channel[1].size == 10 &&
2056 desc->channel[2].size == 10 &&
2057 desc->channel[3].size == 2)
2058 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
2059
2060 /* See whether the components are of the same size. */
2061 for (i = 0; i < desc->nr_channels; i++) {
2062 if (desc->channel[first_non_void].size != desc->channel[i].size)
2063 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2064 }
2065
2066 switch (desc->channel[first_non_void].size) {
2067 case 8:
2068 switch (desc->nr_channels) {
2069 case 1:
2070 case 3: /* 3 loads */
2071 return V_008F0C_BUF_DATA_FORMAT_8;
2072 case 2:
2073 return V_008F0C_BUF_DATA_FORMAT_8_8;
2074 case 4:
2075 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2076 }
2077 break;
2078 case 16:
2079 switch (desc->nr_channels) {
2080 case 1:
2081 case 3: /* 3 loads */
2082 return V_008F0C_BUF_DATA_FORMAT_16;
2083 case 2:
2084 return V_008F0C_BUF_DATA_FORMAT_16_16;
2085 case 4:
2086 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2087 }
2088 break;
2089 case 32:
2090 switch (desc->nr_channels) {
2091 case 1:
2092 return V_008F0C_BUF_DATA_FORMAT_32;
2093 case 2:
2094 return V_008F0C_BUF_DATA_FORMAT_32_32;
2095 case 3:
2096 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2097 case 4:
2098 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2099 }
2100 break;
2101 case 64:
2102 /* Legacy double formats. */
2103 switch (desc->nr_channels) {
2104 case 1: /* 1 load */
2105 return V_008F0C_BUF_DATA_FORMAT_32_32;
2106 case 2: /* 1 load */
2107 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2108 case 3: /* 3 loads */
2109 return V_008F0C_BUF_DATA_FORMAT_32_32;
2110 case 4: /* 2 loads */
2111 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2112 }
2113 break;
2114 }
2115
2116 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2117 }
2118
2119 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2120 const struct util_format_description *desc,
2121 int first_non_void)
2122 {
2123 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2124
2125 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2126 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2127
2128 assert(first_non_void >= 0);
2129
2130 switch (desc->channel[first_non_void].type) {
2131 case UTIL_FORMAT_TYPE_SIGNED:
2132 case UTIL_FORMAT_TYPE_FIXED:
2133 if (desc->channel[first_non_void].size >= 32 ||
2134 desc->channel[first_non_void].pure_integer)
2135 return V_008F0C_BUF_NUM_FORMAT_SINT;
2136 else if (desc->channel[first_non_void].normalized)
2137 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2138 else
2139 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2140 break;
2141 case UTIL_FORMAT_TYPE_UNSIGNED:
2142 if (desc->channel[first_non_void].size >= 32 ||
2143 desc->channel[first_non_void].pure_integer)
2144 return V_008F0C_BUF_NUM_FORMAT_UINT;
2145 else if (desc->channel[first_non_void].normalized)
2146 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2147 else
2148 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2149 break;
2150 case UTIL_FORMAT_TYPE_FLOAT:
2151 default:
2152 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2153 }
2154 }
2155
2156 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2157 enum pipe_format format,
2158 unsigned usage)
2159 {
2160 struct si_screen *sscreen = (struct si_screen *)screen;
2161 const struct util_format_description *desc;
2162 int first_non_void;
2163 unsigned data_format;
2164
2165 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2166 PIPE_BIND_SAMPLER_VIEW |
2167 PIPE_BIND_VERTEX_BUFFER)) == 0);
2168
2169 desc = util_format_description(format);
2170 if (!desc)
2171 return 0;
2172
2173 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2174 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2175 * for read-only access (with caveats surrounding bounds checks), but
2176 * obviously fails for write access which we have to implement for
2177 * shader images. Luckily, OpenGL doesn't expect this to be supported
2178 * anyway, and so the only impact is on PBO uploads / downloads, which
2179 * shouldn't be expected to be fast for GL_RGB anyway.
2180 */
2181 if (desc->block.bits == 3 * 8 ||
2182 desc->block.bits == 3 * 16) {
2183 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2184 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2185 if (!usage)
2186 return 0;
2187 }
2188 }
2189
2190 if (sscreen->info.chip_class >= GFX10) {
2191 const struct gfx10_format *fmt = &gfx10_format_table[format];
2192 if (!fmt->img_format || fmt->img_format >= 128)
2193 return 0;
2194 return usage;
2195 }
2196
2197 first_non_void = util_format_get_first_non_void_channel(format);
2198 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2199 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2200 return 0;
2201
2202 return usage;
2203 }
2204
2205 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2206 {
2207 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2208 si_translate_colorswap(format, false) != ~0U;
2209 }
2210
2211 static bool si_is_zs_format_supported(enum pipe_format format)
2212 {
2213 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2214 }
2215
2216 static boolean si_is_format_supported(struct pipe_screen *screen,
2217 enum pipe_format format,
2218 enum pipe_texture_target target,
2219 unsigned sample_count,
2220 unsigned storage_sample_count,
2221 unsigned usage)
2222 {
2223 struct si_screen *sscreen = (struct si_screen *)screen;
2224 unsigned retval = 0;
2225
2226 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2227 PRINT_ERR("radeonsi: unsupported texture type %d\n", target);
2228 return false;
2229 }
2230
2231 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2232 return false;
2233
2234 if (sample_count > 1) {
2235 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2236 return false;
2237
2238 if (usage & PIPE_BIND_SHADER_IMAGE)
2239 return false;
2240
2241 /* Only power-of-two sample counts are supported. */
2242 if (!util_is_power_of_two_or_zero(sample_count) ||
2243 !util_is_power_of_two_or_zero(storage_sample_count))
2244 return false;
2245
2246 /* MSAA support without framebuffer attachments. */
2247 if (format == PIPE_FORMAT_NONE && sample_count <= 16)
2248 return true;
2249
2250 if (!sscreen->info.has_eqaa_surface_allocator ||
2251 util_format_is_depth_or_stencil(format)) {
2252 /* Color without EQAA or depth/stencil. */
2253 if (sample_count > 8 ||
2254 sample_count != storage_sample_count)
2255 return false;
2256 } else {
2257 /* Color with EQAA. */
2258 if (sample_count > 16 ||
2259 storage_sample_count > 8)
2260 return false;
2261 }
2262 }
2263
2264 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2265 PIPE_BIND_SHADER_IMAGE)) {
2266 if (target == PIPE_BUFFER) {
2267 retval |= si_is_vertex_format_supported(
2268 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2269 PIPE_BIND_SHADER_IMAGE));
2270 } else {
2271 if (si_is_sampler_format_supported(screen, format))
2272 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2273 PIPE_BIND_SHADER_IMAGE);
2274 }
2275 }
2276
2277 if ((usage & (PIPE_BIND_RENDER_TARGET |
2278 PIPE_BIND_DISPLAY_TARGET |
2279 PIPE_BIND_SCANOUT |
2280 PIPE_BIND_SHARED |
2281 PIPE_BIND_BLENDABLE)) &&
2282 si_is_colorbuffer_format_supported(format)) {
2283 retval |= usage &
2284 (PIPE_BIND_RENDER_TARGET |
2285 PIPE_BIND_DISPLAY_TARGET |
2286 PIPE_BIND_SCANOUT |
2287 PIPE_BIND_SHARED);
2288 if (!util_format_is_pure_integer(format) &&
2289 !util_format_is_depth_or_stencil(format))
2290 retval |= usage & PIPE_BIND_BLENDABLE;
2291 }
2292
2293 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2294 si_is_zs_format_supported(format)) {
2295 retval |= PIPE_BIND_DEPTH_STENCIL;
2296 }
2297
2298 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2299 retval |= si_is_vertex_format_supported(screen, format,
2300 PIPE_BIND_VERTEX_BUFFER);
2301 }
2302
2303 if ((usage & PIPE_BIND_LINEAR) &&
2304 !util_format_is_compressed(format) &&
2305 !(usage & PIPE_BIND_DEPTH_STENCIL))
2306 retval |= PIPE_BIND_LINEAR;
2307
2308 return retval == usage;
2309 }
2310
2311 /*
2312 * framebuffer handling
2313 */
2314
2315 static void si_choose_spi_color_formats(struct si_surface *surf,
2316 unsigned format, unsigned swap,
2317 unsigned ntype, bool is_depth)
2318 {
2319 /* Alpha is needed for alpha-to-coverage.
2320 * Blending may be with or without alpha.
2321 */
2322 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2323 unsigned alpha = 0; /* exports alpha, but may not support blending */
2324 unsigned blend = 0; /* supports blending, but may not export alpha */
2325 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2326
2327 /* Choose the SPI color formats. These are required values for RB+.
2328 * Other chips have multiple choices, though they are not necessarily better.
2329 */
2330 switch (format) {
2331 case V_028C70_COLOR_5_6_5:
2332 case V_028C70_COLOR_1_5_5_5:
2333 case V_028C70_COLOR_5_5_5_1:
2334 case V_028C70_COLOR_4_4_4_4:
2335 case V_028C70_COLOR_10_11_11:
2336 case V_028C70_COLOR_11_11_10:
2337 case V_028C70_COLOR_8:
2338 case V_028C70_COLOR_8_8:
2339 case V_028C70_COLOR_8_8_8_8:
2340 case V_028C70_COLOR_10_10_10_2:
2341 case V_028C70_COLOR_2_10_10_10:
2342 if (ntype == V_028C70_NUMBER_UINT)
2343 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2344 else if (ntype == V_028C70_NUMBER_SINT)
2345 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2346 else
2347 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2348 break;
2349
2350 case V_028C70_COLOR_16:
2351 case V_028C70_COLOR_16_16:
2352 case V_028C70_COLOR_16_16_16_16:
2353 if (ntype == V_028C70_NUMBER_UNORM ||
2354 ntype == V_028C70_NUMBER_SNORM) {
2355 /* UNORM16 and SNORM16 don't support blending */
2356 if (ntype == V_028C70_NUMBER_UNORM)
2357 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2358 else
2359 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2360
2361 /* Use 32 bits per channel for blending. */
2362 if (format == V_028C70_COLOR_16) {
2363 if (swap == V_028C70_SWAP_STD) { /* R */
2364 blend = V_028714_SPI_SHADER_32_R;
2365 blend_alpha = V_028714_SPI_SHADER_32_AR;
2366 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2367 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2368 else
2369 assert(0);
2370 } else if (format == V_028C70_COLOR_16_16) {
2371 if (swap == V_028C70_SWAP_STD) { /* RG */
2372 blend = V_028714_SPI_SHADER_32_GR;
2373 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2374 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2375 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2376 else
2377 assert(0);
2378 } else /* 16_16_16_16 */
2379 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2380 } else if (ntype == V_028C70_NUMBER_UINT)
2381 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2382 else if (ntype == V_028C70_NUMBER_SINT)
2383 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2384 else if (ntype == V_028C70_NUMBER_FLOAT)
2385 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2386 else
2387 assert(0);
2388 break;
2389
2390 case V_028C70_COLOR_32:
2391 if (swap == V_028C70_SWAP_STD) { /* R */
2392 blend = normal = V_028714_SPI_SHADER_32_R;
2393 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2394 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2395 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2396 else
2397 assert(0);
2398 break;
2399
2400 case V_028C70_COLOR_32_32:
2401 if (swap == V_028C70_SWAP_STD) { /* RG */
2402 blend = normal = V_028714_SPI_SHADER_32_GR;
2403 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2404 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2405 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2406 else
2407 assert(0);
2408 break;
2409
2410 case V_028C70_COLOR_32_32_32_32:
2411 case V_028C70_COLOR_8_24:
2412 case V_028C70_COLOR_24_8:
2413 case V_028C70_COLOR_X24_8_32_FLOAT:
2414 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2415 break;
2416
2417 default:
2418 assert(0);
2419 return;
2420 }
2421
2422 /* The DB->CB copy needs 32_ABGR. */
2423 if (is_depth)
2424 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2425
2426 surf->spi_shader_col_format = normal;
2427 surf->spi_shader_col_format_alpha = alpha;
2428 surf->spi_shader_col_format_blend = blend;
2429 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2430 }
2431
2432 static void si_initialize_color_surface(struct si_context *sctx,
2433 struct si_surface *surf)
2434 {
2435 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2436 unsigned color_info, color_attrib;
2437 unsigned format, swap, ntype, endian;
2438 const struct util_format_description *desc;
2439 int firstchan;
2440 unsigned blend_clamp = 0, blend_bypass = 0;
2441
2442 desc = util_format_description(surf->base.format);
2443 for (firstchan = 0; firstchan < 4; firstchan++) {
2444 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2445 break;
2446 }
2447 }
2448 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2449 ntype = V_028C70_NUMBER_FLOAT;
2450 } else {
2451 ntype = V_028C70_NUMBER_UNORM;
2452 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2453 ntype = V_028C70_NUMBER_SRGB;
2454 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2455 if (desc->channel[firstchan].pure_integer) {
2456 ntype = V_028C70_NUMBER_SINT;
2457 } else {
2458 assert(desc->channel[firstchan].normalized);
2459 ntype = V_028C70_NUMBER_SNORM;
2460 }
2461 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2462 if (desc->channel[firstchan].pure_integer) {
2463 ntype = V_028C70_NUMBER_UINT;
2464 } else {
2465 assert(desc->channel[firstchan].normalized);
2466 ntype = V_028C70_NUMBER_UNORM;
2467 }
2468 }
2469 }
2470
2471 format = si_translate_colorformat(surf->base.format);
2472 if (format == V_028C70_COLOR_INVALID) {
2473 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2474 }
2475 assert(format != V_028C70_COLOR_INVALID);
2476 swap = si_translate_colorswap(surf->base.format, false);
2477 endian = si_colorformat_endian_swap(format);
2478
2479 /* blend clamp should be set for all NORM/SRGB types */
2480 if (ntype == V_028C70_NUMBER_UNORM ||
2481 ntype == V_028C70_NUMBER_SNORM ||
2482 ntype == V_028C70_NUMBER_SRGB)
2483 blend_clamp = 1;
2484
2485 /* set blend bypass according to docs if SINT/UINT or
2486 8/24 COLOR variants */
2487 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2488 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2489 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2490 blend_clamp = 0;
2491 blend_bypass = 1;
2492 }
2493
2494 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2495 if (format == V_028C70_COLOR_8 ||
2496 format == V_028C70_COLOR_8_8 ||
2497 format == V_028C70_COLOR_8_8_8_8)
2498 surf->color_is_int8 = true;
2499 else if (format == V_028C70_COLOR_10_10_10_2 ||
2500 format == V_028C70_COLOR_2_10_10_10)
2501 surf->color_is_int10 = true;
2502 }
2503
2504 color_info = S_028C70_FORMAT(format) |
2505 S_028C70_COMP_SWAP(swap) |
2506 S_028C70_BLEND_CLAMP(blend_clamp) |
2507 S_028C70_BLEND_BYPASS(blend_bypass) |
2508 S_028C70_SIMPLE_FLOAT(1) |
2509 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2510 ntype != V_028C70_NUMBER_SNORM &&
2511 ntype != V_028C70_NUMBER_SRGB &&
2512 format != V_028C70_COLOR_8_24 &&
2513 format != V_028C70_COLOR_24_8) |
2514 S_028C70_NUMBER_TYPE(ntype) |
2515 S_028C70_ENDIAN(endian);
2516
2517 /* Intensity is implemented as Red, so treat it that way. */
2518 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2519 util_format_is_intensity(surf->base.format));
2520
2521 if (tex->buffer.b.b.nr_samples > 1) {
2522 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2523 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2524
2525 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2526 S_028C74_NUM_FRAGMENTS(log_fragments);
2527
2528 if (tex->fmask_offset) {
2529 color_info |= S_028C70_COMPRESSION(1);
2530 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2531
2532 if (sctx->chip_class == GFX6) {
2533 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2534 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2535 }
2536 }
2537 }
2538
2539 if (sctx->chip_class >= GFX10) {
2540 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2541
2542 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2543 64 for APU because all of our APUs to date use DIMMs which have
2544 a request granularity size of 64B while all other chips have a
2545 32B request size */
2546 if (!sctx->screen->info.has_dedicated_vram)
2547 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2548
2549 surf->cb_dcc_control =
2550 S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
2551 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
2552 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2553 S_028C78_INDEPENDENT_64B_BLOCKS(0) |
2554 S_028C78_INDEPENDENT_128B_BLOCKS(1);
2555 } else if (sctx->chip_class >= GFX8) {
2556 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2557 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2558
2559 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2560 64 for APU because all of our APUs to date use DIMMs which have
2561 a request granularity size of 64B while all other chips have a
2562 32B request size */
2563 if (!sctx->screen->info.has_dedicated_vram)
2564 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2565
2566 if (tex->buffer.b.b.nr_storage_samples > 1) {
2567 if (tex->surface.bpe == 1)
2568 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2569 else if (tex->surface.bpe == 2)
2570 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2571 }
2572
2573 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2574 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2575 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2576 }
2577
2578 /* This must be set for fast clear to work without FMASK. */
2579 if (!tex->surface.fmask_size && sctx->chip_class == GFX6) {
2580 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2581 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2582 }
2583
2584 /* GFX10 field has the same base shift as the GFX6 field */
2585 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2586 S_028C6C_SLICE_MAX_GFX10(surf->base.u.tex.last_layer);
2587 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2588
2589 if (sctx->chip_class >= GFX10) {
2590 color_view |= S_028C6C_MIP_LEVEL_GFX10(surf->base.u.tex.level);
2591
2592 surf->cb_color_attrib3 = S_028EE0_MIP0_DEPTH(mip0_depth) |
2593 S_028EE0_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type) |
2594 S_028EE0_RESOURCE_LEVEL(1);
2595 } else if (sctx->chip_class == GFX9) {
2596 color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level);
2597 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2598 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2599 }
2600
2601 if (sctx->chip_class >= GFX9) {
2602 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2603 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2604 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2605 }
2606
2607 surf->cb_color_view = color_view;
2608 surf->cb_color_info = color_info;
2609 surf->cb_color_attrib = color_attrib;
2610
2611 /* Determine pixel shader export format */
2612 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2613
2614 surf->color_initialized = true;
2615 }
2616
2617 static void si_init_depth_surface(struct si_context *sctx,
2618 struct si_surface *surf)
2619 {
2620 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2621 unsigned level = surf->base.u.tex.level;
2622 unsigned format, stencil_format;
2623 uint32_t z_info, s_info;
2624
2625 format = si_translate_dbformat(tex->db_render_format);
2626 stencil_format = tex->surface.has_stencil ?
2627 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2628
2629 assert(format != V_028040_Z_INVALID);
2630 if (format == V_028040_Z_INVALID)
2631 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2632
2633 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2634 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2635 surf->db_htile_data_base = 0;
2636 surf->db_htile_surface = 0;
2637
2638 if (sctx->chip_class >= GFX10) {
2639 surf->db_depth_view |= S_028008_SLICE_START_HI(surf->base.u.tex.first_layer >> 11) |
2640 S_028008_SLICE_MAX_HI(surf->base.u.tex.last_layer >> 11);
2641 }
2642
2643 if (sctx->chip_class >= GFX9) {
2644 assert(tex->surface.u.gfx9.surf_offset == 0);
2645 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2646 surf->db_stencil_base = (tex->buffer.gpu_address +
2647 tex->surface.u.gfx9.stencil_offset) >> 8;
2648 z_info = S_028038_FORMAT(format) |
2649 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2650 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2651 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2652 s_info = S_02803C_FORMAT(stencil_format) |
2653 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2654
2655 if (sctx->chip_class == GFX9) {
2656 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2657 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2658 }
2659 surf->db_depth_view |= S_028008_MIPID(level);
2660 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2661 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2662
2663 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2664 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2665 S_028038_ALLOW_EXPCLEAR(1);
2666
2667 if (tex->tc_compatible_htile) {
2668 unsigned max_zplanes = 4;
2669
2670 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2671 tex->buffer.b.b.nr_samples > 1)
2672 max_zplanes = 2;
2673
2674 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1);
2675
2676 if (sctx->chip_class >= GFX10) {
2677 z_info |= S_028040_ITERATE_FLUSH(1);
2678 s_info |= S_028044_ITERATE_FLUSH(!tex->htile_stencil_disabled);
2679 } else {
2680 z_info |= S_028038_ITERATE_FLUSH(1);
2681 s_info |= S_02803C_ITERATE_FLUSH(1);
2682 }
2683 }
2684
2685 if (tex->surface.has_stencil && !tex->htile_stencil_disabled) {
2686 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2687 * See that for explanation.
2688 */
2689 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2690 } else {
2691 /* Use all HTILE for depth if there's no stencil. */
2692 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2693 }
2694
2695 surf->db_htile_data_base = (tex->buffer.gpu_address +
2696 tex->htile_offset) >> 8;
2697 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2698 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned);
2699 if (sctx->chip_class == GFX9) {
2700 surf->db_htile_surface |=
2701 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2702 }
2703 }
2704 } else {
2705 /* GFX6-GFX8 */
2706 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2707
2708 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2709
2710 surf->db_depth_base = (tex->buffer.gpu_address +
2711 tex->surface.u.legacy.level[level].offset) >> 8;
2712 surf->db_stencil_base = (tex->buffer.gpu_address +
2713 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2714
2715 z_info = S_028040_FORMAT(format) |
2716 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2717 s_info = S_028044_FORMAT(stencil_format);
2718 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2719
2720 if (sctx->chip_class >= GFX7) {
2721 struct radeon_info *info = &sctx->screen->info;
2722 unsigned index = tex->surface.u.legacy.tiling_index[level];
2723 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2724 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2725 unsigned tile_mode = info->si_tile_mode_array[index];
2726 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2727 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2728
2729 surf->db_depth_info |=
2730 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2731 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2732 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2733 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2734 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2735 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2736 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2737 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2738 } else {
2739 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2740 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2741 tile_mode_index = si_tile_mode_index(tex, level, true);
2742 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2743 }
2744
2745 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2746 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2747 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2748 levelinfo->nblk_y) / 64 - 1);
2749
2750 if (si_htile_enabled(tex, level, PIPE_MASK_ZS)) {
2751 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2752 S_028040_ALLOW_EXPCLEAR(1);
2753
2754 if (tex->surface.has_stencil) {
2755 /* Workaround: For a not yet understood reason, the
2756 * combination of MSAA, fast stencil clear and stencil
2757 * decompress messes with subsequent stencil buffer
2758 * uses. Problem was reproduced on Verde, Bonaire,
2759 * Tonga, and Carrizo.
2760 *
2761 * Disabling EXPCLEAR works around the problem.
2762 *
2763 * Check piglit's arb_texture_multisample-stencil-clear
2764 * test if you want to try changing this.
2765 */
2766 if (tex->buffer.b.b.nr_samples <= 1)
2767 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2768 } else if (!tex->tc_compatible_htile) {
2769 /* Use all of the htile_buffer for depth if there's no stencil.
2770 * This must not be set when TC-compatible HTILE is enabled
2771 * due to a hw bug.
2772 */
2773 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2774 }
2775
2776 surf->db_htile_data_base = (tex->buffer.gpu_address +
2777 tex->htile_offset) >> 8;
2778 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2779
2780 if (tex->tc_compatible_htile) {
2781 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2782
2783 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2784 if (tex->buffer.b.b.nr_samples <= 1)
2785 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2786 else if (tex->buffer.b.b.nr_samples <= 4)
2787 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2788 else
2789 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2790 }
2791 }
2792 }
2793
2794 surf->db_z_info = z_info;
2795 surf->db_stencil_info = s_info;
2796
2797 surf->depth_initialized = true;
2798 }
2799
2800 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2801 {
2802 if (sctx->decompression_enabled)
2803 return;
2804
2805 if (sctx->framebuffer.state.zsbuf) {
2806 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2807 struct si_texture *tex = (struct si_texture *)surf->texture;
2808
2809 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2810
2811 if (tex->surface.has_stencil)
2812 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2813 }
2814
2815 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2816 while (compressed_cb_mask) {
2817 unsigned i = u_bit_scan(&compressed_cb_mask);
2818 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2819 struct si_texture *tex = (struct si_texture*)surf->texture;
2820
2821 if (tex->fmask_offset)
2822 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2823 if (tex->dcc_gather_statistics)
2824 tex->separate_dcc_dirty = true;
2825 }
2826 }
2827
2828 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2829 {
2830 for (int i = 0; i < state->nr_cbufs; ++i) {
2831 struct si_surface *surf = NULL;
2832 struct si_texture *tex;
2833
2834 if (!state->cbufs[i])
2835 continue;
2836 surf = (struct si_surface*)state->cbufs[i];
2837 tex = (struct si_texture*)surf->base.texture;
2838
2839 p_atomic_dec(&tex->framebuffers_bound);
2840 }
2841 }
2842
2843 static void si_set_framebuffer_state(struct pipe_context *ctx,
2844 const struct pipe_framebuffer_state *state)
2845 {
2846 struct si_context *sctx = (struct si_context *)ctx;
2847 struct si_surface *surf = NULL;
2848 struct si_texture *tex;
2849 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2850 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2851 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2852 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2853 bool old_has_stencil =
2854 old_has_zsbuf &&
2855 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2856 bool unbound = false;
2857 int i;
2858
2859 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2860 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2861 * We could implement the full workaround here, but it's a useless case.
2862 */
2863 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2864 unreachable("the framebuffer shouldn't have zero area");
2865 return;
2866 }
2867
2868 si_update_fb_dirtiness_after_rendering(sctx);
2869
2870 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2871 if (!sctx->framebuffer.state.cbufs[i])
2872 continue;
2873
2874 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2875 if (tex->dcc_gather_statistics)
2876 vi_separate_dcc_stop_query(sctx, tex);
2877 }
2878
2879 /* Disable DCC if the formats are incompatible. */
2880 for (i = 0; i < state->nr_cbufs; i++) {
2881 if (!state->cbufs[i])
2882 continue;
2883
2884 surf = (struct si_surface*)state->cbufs[i];
2885 tex = (struct si_texture*)surf->base.texture;
2886
2887 if (!surf->dcc_incompatible)
2888 continue;
2889
2890 /* Since the DCC decompression calls back into set_framebuffer-
2891 * _state, we need to unbind the framebuffer, so that
2892 * vi_separate_dcc_stop_query isn't called twice with the same
2893 * color buffer.
2894 */
2895 if (!unbound) {
2896 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2897 unbound = true;
2898 }
2899
2900 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2901 if (!si_texture_disable_dcc(sctx, tex))
2902 si_decompress_dcc(sctx, tex);
2903
2904 surf->dcc_incompatible = false;
2905 }
2906
2907 /* Only flush TC when changing the framebuffer state, because
2908 * the only client not using TC that can change textures is
2909 * the framebuffer.
2910 *
2911 * Wait for compute shaders because of possible transitions:
2912 * - FB write -> shader read
2913 * - shader write -> FB read
2914 *
2915 * DB caches are flushed on demand (using si_decompress_textures).
2916 *
2917 * When MSAA is enabled, CB and TC caches are flushed on demand
2918 * (after FMASK decompression). Shader write -> FB read transitions
2919 * cannot happen for MSAA textures, because MSAA shader images are
2920 * not supported.
2921 *
2922 * Only flush and wait for CB if there is actually a bound color buffer.
2923 */
2924 if (sctx->framebuffer.uncompressed_cb_mask) {
2925 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2926 sctx->framebuffer.CB_has_shader_readable_metadata,
2927 sctx->framebuffer.all_DCC_pipe_aligned);
2928 }
2929
2930 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2931
2932 /* u_blitter doesn't invoke depth decompression when it does multiple
2933 * blits in a row, but the only case when it matters for DB is when
2934 * doing generate_mipmap. So here we flush DB manually between
2935 * individual generate_mipmap blits.
2936 * Note that lower mipmap levels aren't compressed.
2937 */
2938 if (sctx->generate_mipmap_for_depth) {
2939 si_make_DB_shader_coherent(sctx, 1, false,
2940 sctx->framebuffer.DB_has_shader_readable_metadata);
2941 } else if (sctx->chip_class == GFX9) {
2942 /* It appears that DB metadata "leaks" in a sequence of:
2943 * - depth clear
2944 * - DCC decompress for shader image writes (with DB disabled)
2945 * - render with DEPTH_BEFORE_SHADER=1
2946 * Flushing DB metadata works around the problem.
2947 */
2948 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2949 }
2950
2951 /* Take the maximum of the old and new count. If the new count is lower,
2952 * dirtying is needed to disable the unbound colorbuffers.
2953 */
2954 sctx->framebuffer.dirty_cbufs |=
2955 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2956 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2957
2958 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2959 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2960
2961 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2962 sctx->framebuffer.spi_shader_col_format = 0;
2963 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2964 sctx->framebuffer.spi_shader_col_format_blend = 0;
2965 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2966 sctx->framebuffer.color_is_int8 = 0;
2967 sctx->framebuffer.color_is_int10 = 0;
2968
2969 sctx->framebuffer.compressed_cb_mask = 0;
2970 sctx->framebuffer.uncompressed_cb_mask = 0;
2971 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2972 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2973 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2974 sctx->framebuffer.any_dst_linear = false;
2975 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2976 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2977 sctx->framebuffer.all_DCC_pipe_aligned = true;
2978
2979 for (i = 0; i < state->nr_cbufs; i++) {
2980 if (!state->cbufs[i])
2981 continue;
2982
2983 surf = (struct si_surface*)state->cbufs[i];
2984 tex = (struct si_texture*)surf->base.texture;
2985
2986 if (!surf->color_initialized) {
2987 si_initialize_color_surface(sctx, surf);
2988 }
2989
2990 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2991 sctx->framebuffer.spi_shader_col_format |=
2992 surf->spi_shader_col_format << (i * 4);
2993 sctx->framebuffer.spi_shader_col_format_alpha |=
2994 surf->spi_shader_col_format_alpha << (i * 4);
2995 sctx->framebuffer.spi_shader_col_format_blend |=
2996 surf->spi_shader_col_format_blend << (i * 4);
2997 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2998 surf->spi_shader_col_format_blend_alpha << (i * 4);
2999
3000 if (surf->color_is_int8)
3001 sctx->framebuffer.color_is_int8 |= 1 << i;
3002 if (surf->color_is_int10)
3003 sctx->framebuffer.color_is_int10 |= 1 << i;
3004
3005 if (tex->fmask_offset)
3006 sctx->framebuffer.compressed_cb_mask |= 1 << i;
3007 else
3008 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
3009
3010 /* Don't update nr_color_samples for non-AA buffers.
3011 * (e.g. destination of MSAA resolve)
3012 */
3013 if (tex->buffer.b.b.nr_samples >= 2 &&
3014 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
3015 sctx->framebuffer.nr_color_samples =
3016 MIN2(sctx->framebuffer.nr_color_samples,
3017 tex->buffer.b.b.nr_storage_samples);
3018 sctx->framebuffer.nr_color_samples =
3019 MAX2(1, sctx->framebuffer.nr_color_samples);
3020 }
3021
3022 if (tex->surface.is_linear)
3023 sctx->framebuffer.any_dst_linear = true;
3024
3025 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
3026 sctx->framebuffer.CB_has_shader_readable_metadata = true;
3027
3028 if (sctx->chip_class >= GFX9 &&
3029 !tex->surface.u.gfx9.dcc.pipe_aligned)
3030 sctx->framebuffer.all_DCC_pipe_aligned = false;
3031 }
3032
3033 si_context_add_resource_size(sctx, surf->base.texture);
3034
3035 p_atomic_inc(&tex->framebuffers_bound);
3036
3037 if (tex->dcc_gather_statistics) {
3038 /* Dirty tracking must be enabled for DCC usage analysis. */
3039 sctx->framebuffer.compressed_cb_mask |= 1 << i;
3040 vi_separate_dcc_start_query(sctx, tex);
3041 }
3042 }
3043
3044 /* For optimal DCC performance. */
3045 if (sctx->chip_class >= GFX10)
3046 sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
3047 else
3048 sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
3049
3050 struct si_texture *zstex = NULL;
3051
3052 if (state->zsbuf) {
3053 surf = (struct si_surface*)state->zsbuf;
3054 zstex = (struct si_texture*)surf->base.texture;
3055
3056 if (!surf->depth_initialized) {
3057 si_init_depth_surface(sctx, surf);
3058 }
3059
3060 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level,
3061 PIPE_MASK_ZS))
3062 sctx->framebuffer.DB_has_shader_readable_metadata = true;
3063
3064 si_context_add_resource_size(sctx, surf->base.texture);
3065 }
3066
3067 si_update_ps_colorbuf0_slot(sctx);
3068 si_update_poly_offset_state(sctx);
3069 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3070 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
3071
3072 if (sctx->screen->dpbb_allowed)
3073 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3074
3075 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
3076 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3077
3078 if (sctx->screen->has_out_of_order_rast &&
3079 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
3080 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
3081 (zstex && zstex->surface.has_stencil != old_has_stencil)))
3082 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3083
3084 if (sctx->framebuffer.nr_samples != old_nr_samples) {
3085 struct pipe_constant_buffer constbuf = {0};
3086
3087 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3088 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3089
3090 constbuf.buffer = sctx->sample_pos_buffer;
3091
3092 /* Set sample locations as fragment shader constants. */
3093 switch (sctx->framebuffer.nr_samples) {
3094 case 1:
3095 constbuf.buffer_offset = 0;
3096 break;
3097 case 2:
3098 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x2 -
3099 (ubyte*)sctx->sample_positions.x1;
3100 break;
3101 case 4:
3102 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x4 -
3103 (ubyte*)sctx->sample_positions.x1;
3104 break;
3105 case 8:
3106 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x8 -
3107 (ubyte*)sctx->sample_positions.x1;
3108 break;
3109 case 16:
3110 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x16 -
3111 (ubyte*)sctx->sample_positions.x1;
3112 break;
3113 default:
3114 PRINT_ERR("Requested an invalid number of samples %i.\n",
3115 sctx->framebuffer.nr_samples);
3116 assert(0);
3117 }
3118 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
3119 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
3120
3121 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3122 }
3123
3124 sctx->do_update_shaders = true;
3125
3126 if (!sctx->decompression_enabled) {
3127 /* Prevent textures decompression when the framebuffer state
3128 * changes come from the decompression passes themselves.
3129 */
3130 sctx->need_check_render_feedback = true;
3131 }
3132 }
3133
3134 static void si_emit_framebuffer_state(struct si_context *sctx)
3135 {
3136 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3137 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3138 unsigned i, nr_cbufs = state->nr_cbufs;
3139 struct si_texture *tex = NULL;
3140 struct si_surface *cb = NULL;
3141 unsigned cb_color_info = 0;
3142
3143 /* Colorbuffers. */
3144 for (i = 0; i < nr_cbufs; i++) {
3145 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3146 unsigned cb_color_attrib;
3147
3148 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3149 continue;
3150
3151 cb = (struct si_surface*)state->cbufs[i];
3152 if (!cb) {
3153 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
3154 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3155 continue;
3156 }
3157
3158 tex = (struct si_texture *)cb->base.texture;
3159 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3160 &tex->buffer, RADEON_USAGE_READWRITE,
3161 tex->buffer.b.b.nr_samples > 1 ?
3162 RADEON_PRIO_COLOR_BUFFER_MSAA :
3163 RADEON_PRIO_COLOR_BUFFER);
3164
3165 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3166 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3167 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3168 RADEON_PRIO_SEPARATE_META);
3169 }
3170
3171 if (tex->dcc_separate_buffer)
3172 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3173 tex->dcc_separate_buffer,
3174 RADEON_USAGE_READWRITE,
3175 RADEON_PRIO_SEPARATE_META);
3176
3177 /* Compute mutable surface parameters. */
3178 cb_color_base = tex->buffer.gpu_address >> 8;
3179 cb_color_fmask = 0;
3180 cb_color_cmask = tex->cmask_base_address_reg;
3181 cb_dcc_base = 0;
3182 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3183 cb_color_attrib = cb->cb_color_attrib;
3184
3185 if (cb->base.u.tex.level > 0)
3186 cb_color_info &= C_028C70_FAST_CLEAR;
3187
3188 if (tex->fmask_offset) {
3189 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3190 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3191 }
3192
3193 /* Set up DCC. */
3194 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3195 bool is_msaa_resolve_dst = state->cbufs[0] &&
3196 state->cbufs[0]->texture->nr_samples > 1 &&
3197 state->cbufs[1] == &cb->base &&
3198 state->cbufs[1]->texture->nr_samples <= 1;
3199
3200 if (!is_msaa_resolve_dst)
3201 cb_color_info |= S_028C70_DCC_ENABLE(1);
3202
3203 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3204 tex->dcc_offset) >> 8;
3205
3206 unsigned dcc_tile_swizzle = tex->surface.tile_swizzle;
3207 dcc_tile_swizzle &= (tex->surface.dcc_alignment - 1) >> 8;
3208 cb_dcc_base |= dcc_tile_swizzle;
3209 }
3210
3211 if (sctx->chip_class >= GFX10) {
3212 unsigned cb_color_attrib3;
3213
3214 /* Set mutable surface parameters. */
3215 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3216 cb_color_base |= tex->surface.tile_swizzle;
3217 if (!tex->fmask_offset)
3218 cb_color_fmask = cb_color_base;
3219 if (cb->base.u.tex.level > 0)
3220 cb_color_cmask = cb_color_base;
3221
3222 cb_color_attrib3 = cb->cb_color_attrib3 |
3223 S_028EE0_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3224 S_028EE0_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3225 S_028EE0_CMASK_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3226 S_028EE0_DCC_PIPE_ALIGNED(tex->surface.u.gfx9.dcc.pipe_aligned);
3227
3228 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 14);
3229 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3230 radeon_emit(cs, 0); /* hole */
3231 radeon_emit(cs, 0); /* hole */
3232 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3233 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3234 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3235 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3236 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3237 radeon_emit(cs, 0); /* hole */
3238 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3239 radeon_emit(cs, 0); /* hole */
3240 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3241 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3242 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3243
3244 radeon_set_context_reg(cs, R_028E40_CB_COLOR0_BASE_EXT + i * 4,
3245 cb_color_base >> 32);
3246 radeon_set_context_reg(cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + i * 4,
3247 cb_color_cmask >> 32);
3248 radeon_set_context_reg(cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + i * 4,
3249 cb_color_fmask >> 32);
3250 radeon_set_context_reg(cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + i * 4,
3251 cb_dcc_base >> 32);
3252 radeon_set_context_reg(cs, R_028EC0_CB_COLOR0_ATTRIB2 + i * 4,
3253 cb->cb_color_attrib2);
3254 radeon_set_context_reg(cs, R_028EE0_CB_COLOR0_ATTRIB3 + i * 4,
3255 cb_color_attrib3);
3256 } else if (sctx->chip_class == GFX9) {
3257 struct gfx9_surf_meta_flags meta;
3258
3259 if (tex->dcc_offset)
3260 meta = tex->surface.u.gfx9.dcc;
3261 else
3262 meta = tex->surface.u.gfx9.cmask;
3263
3264 /* Set mutable surface parameters. */
3265 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3266 cb_color_base |= tex->surface.tile_swizzle;
3267 if (!tex->fmask_offset)
3268 cb_color_fmask = cb_color_base;
3269 if (cb->base.u.tex.level > 0)
3270 cb_color_cmask = cb_color_base;
3271 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3272 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3273 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3274 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3275
3276 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3277 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3278 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3279 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3280 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3281 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3282 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3283 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3284 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3285 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3286 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3287 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3288 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3289 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3290 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3291 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3292
3293 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3294 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3295 } else {
3296 /* Compute mutable surface parameters (GFX6-GFX8). */
3297 const struct legacy_surf_level *level_info =
3298 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3299 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3300 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3301
3302 cb_color_base += level_info->offset >> 8;
3303 /* Only macrotiled modes can set tile swizzle. */
3304 if (level_info->mode == RADEON_SURF_MODE_2D)
3305 cb_color_base |= tex->surface.tile_swizzle;
3306
3307 if (!tex->fmask_offset)
3308 cb_color_fmask = cb_color_base;
3309 if (cb->base.u.tex.level > 0)
3310 cb_color_cmask = cb_color_base;
3311 if (cb_dcc_base)
3312 cb_dcc_base += level_info->dcc_offset >> 8;
3313
3314 pitch_tile_max = level_info->nblk_x / 8 - 1;
3315 slice_tile_max = level_info->nblk_x *
3316 level_info->nblk_y / 64 - 1;
3317 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3318
3319 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3320 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3321 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3322
3323 if (tex->fmask_offset) {
3324 if (sctx->chip_class >= GFX7)
3325 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3326 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3327 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3328 } else {
3329 /* This must be set for fast clear to work without FMASK. */
3330 if (sctx->chip_class >= GFX7)
3331 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3332 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3333 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3334 }
3335
3336 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3337 sctx->chip_class >= GFX8 ? 14 : 13);
3338 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3339 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3340 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3341 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3342 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3343 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3344 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3345 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3346 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3347 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3348 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3349 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3350 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3351
3352 if (sctx->chip_class >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */
3353 radeon_emit(cs, cb_dcc_base);
3354 }
3355 }
3356 for (; i < 8 ; i++)
3357 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3358 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3359
3360 /* ZS buffer. */
3361 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3362 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3363 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3364
3365 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3366 &tex->buffer, RADEON_USAGE_READWRITE,
3367 zb->base.texture->nr_samples > 1 ?
3368 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3369 RADEON_PRIO_DEPTH_BUFFER);
3370
3371 if (sctx->chip_class >= GFX10) {
3372 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3373 radeon_set_context_reg(cs, R_02801C_DB_DEPTH_SIZE_XY, zb->db_depth_size);
3374
3375 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 7);
3376 radeon_emit(cs, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3377 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3378 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3379 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3380 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3381 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3382 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3383 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3384
3385 radeon_set_context_reg_seq(cs, R_028068_DB_Z_READ_BASE_HI, 5);
3386 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
3387 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
3388 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
3389 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
3390 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
3391 } else if (sctx->chip_class == GFX9) {
3392 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3393 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3394 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3395 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3396
3397 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3398 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3399 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3400 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3401 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3402 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3403 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3404 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3405 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3406 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3407 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3408 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3409
3410 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3411 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3412 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3413 } else {
3414 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3415
3416 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3417 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3418 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3419 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3420 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3421 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3422 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3423 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3424 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3425 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3426 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3427 }
3428
3429 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3430 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3431 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3432
3433 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3434 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3435 } else if (sctx->framebuffer.dirty_zsbuf) {
3436 if (sctx->chip_class == GFX9)
3437 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3438 else
3439 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3440
3441 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3442 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3443 }
3444
3445 /* Framebuffer dimensions. */
3446 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3447 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3448 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3449
3450 if (sctx->screen->dfsm_allowed) {
3451 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3452 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3453 }
3454
3455 sctx->framebuffer.dirty_cbufs = 0;
3456 sctx->framebuffer.dirty_zsbuf = false;
3457 }
3458
3459 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3460 {
3461 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3462 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3463 unsigned nr_samples = sctx->framebuffer.nr_samples;
3464 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3465
3466 /* Smoothing (only possible with nr_samples == 1) uses the same
3467 * sample locations as the MSAA it simulates.
3468 */
3469 if (nr_samples <= 1 && sctx->smoothing_enabled)
3470 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3471
3472 /* On Polaris, the small primitive filter uses the sample locations
3473 * even when MSAA is off, so we need to make sure they're set to 0.
3474 *
3475 * GFX10 uses sample locations unconditionally, so they always need
3476 * to be set up.
3477 */
3478 if ((nr_samples >= 2 || has_msaa_sample_loc_bug ||
3479 sctx->chip_class >= GFX10) &&
3480 nr_samples != sctx->sample_locs_num_samples) {
3481 sctx->sample_locs_num_samples = nr_samples;
3482 si_emit_sample_locations(cs, nr_samples);
3483 }
3484
3485 if (sctx->family >= CHIP_POLARIS10) {
3486 unsigned small_prim_filter_cntl =
3487 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3488 /* line bug */
3489 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3490
3491 /* The alternative of setting sample locations to 0 would
3492 * require a DB flush to avoid Z errors, see
3493 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3494 */
3495 if (has_msaa_sample_loc_bug &&
3496 sctx->framebuffer.nr_samples > 1 &&
3497 !rs->multisample_enable)
3498 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3499
3500 radeon_opt_set_context_reg(sctx,
3501 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3502 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3503 small_prim_filter_cntl);
3504 }
3505
3506 /* The exclusion bits can be set to improve rasterization efficiency
3507 * if no sample lies on the pixel boundary (-8 sample offset).
3508 */
3509 bool exclusion = sctx->chip_class >= GFX7 &&
3510 (!rs->multisample_enable || nr_samples != 16);
3511 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3512 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3513 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3514 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3515 }
3516
3517 static bool si_out_of_order_rasterization(struct si_context *sctx)
3518 {
3519 struct si_state_blend *blend = sctx->queued.named.blend;
3520 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3521
3522 if (!sctx->screen->has_out_of_order_rast)
3523 return false;
3524
3525 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3526
3527 if (blend) {
3528 colormask &= blend->cb_target_enabled_4bit;
3529 } else {
3530 colormask = 0;
3531 }
3532
3533 /* Conservative: No logic op. */
3534 if (colormask && blend->logicop_enable)
3535 return false;
3536
3537 struct si_dsa_order_invariance dsa_order_invariant = {
3538 .zs = true, .pass_set = true, .pass_last = false
3539 };
3540
3541 if (sctx->framebuffer.state.zsbuf) {
3542 struct si_texture *zstex =
3543 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3544 bool has_stencil = zstex->surface.has_stencil;
3545 dsa_order_invariant = dsa->order_invariance[has_stencil];
3546 if (!dsa_order_invariant.zs)
3547 return false;
3548
3549 /* The set of PS invocations is always order invariant,
3550 * except when early Z/S tests are requested. */
3551 if (sctx->ps_shader.cso &&
3552 sctx->ps_shader.cso->info.writes_memory &&
3553 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3554 !dsa_order_invariant.pass_set)
3555 return false;
3556
3557 if (sctx->num_perfect_occlusion_queries != 0 &&
3558 !dsa_order_invariant.pass_set)
3559 return false;
3560 }
3561
3562 if (!colormask)
3563 return true;
3564
3565 unsigned blendmask = colormask & blend->blend_enable_4bit;
3566
3567 if (blendmask) {
3568 /* Only commutative blending. */
3569 if (blendmask & ~blend->commutative_4bit)
3570 return false;
3571
3572 if (!dsa_order_invariant.pass_set)
3573 return false;
3574 }
3575
3576 if (colormask & ~blendmask) {
3577 if (!dsa_order_invariant.pass_last)
3578 return false;
3579 }
3580
3581 return true;
3582 }
3583
3584 static void si_emit_msaa_config(struct si_context *sctx)
3585 {
3586 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3587 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3588 /* 33% faster rendering to linear color buffers */
3589 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3590 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3591 unsigned sc_mode_cntl_1 =
3592 S_028A4C_WALK_SIZE(dst_is_linear) |
3593 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3594 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3595 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3596 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3597 /* always 1: */
3598 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3599 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3600 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3601 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3602 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3603 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3604 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3605 S_028804_INCOHERENT_EQAA_READS(1) |
3606 S_028804_INTERPOLATE_COMP_Z(1) |
3607 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3608 unsigned coverage_samples, color_samples, z_samples;
3609 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3610
3611 /* S: Coverage samples (up to 16x):
3612 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3613 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3614 *
3615 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3616 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3617 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3618 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3619 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3620 * # Z samples).
3621 *
3622 * F: Color samples (up to 8x, must be <= coverage samples):
3623 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3624 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3625 *
3626 * Can be anything between coverage and color samples:
3627 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3628 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3629 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3630 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3631 * # All are currently set the same as coverage samples.
3632 *
3633 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3634 * flag for undefined color samples. A shader-based resolve must handle unknowns
3635 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3636 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3637 * useful. The CB resolve always drops unknowns.
3638 *
3639 * Sensible AA configurations:
3640 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3641 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3642 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3643 * EQAA 8s 8z 8f = 8x MSAA
3644 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3645 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3646 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3647 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3648 * EQAA 4s 4z 4f = 4x MSAA
3649 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3650 * EQAA 2s 2z 2f = 2x MSAA
3651 */
3652 if (sctx->framebuffer.nr_samples > 1 && rs->multisample_enable) {
3653 coverage_samples = sctx->framebuffer.nr_samples;
3654 color_samples = sctx->framebuffer.nr_color_samples;
3655
3656 if (sctx->framebuffer.state.zsbuf) {
3657 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3658 z_samples = MAX2(1, z_samples);
3659 } else {
3660 z_samples = coverage_samples;
3661 }
3662 } else if (sctx->smoothing_enabled) {
3663 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3664 } else {
3665 coverage_samples = color_samples = z_samples = 1;
3666 }
3667
3668 /* Required by OpenGL line rasterization.
3669 *
3670 * TODO: We should also enable perpendicular endcaps for AA lines,
3671 * but that requires implementing line stippling in the pixel
3672 * shader. SC can only do line stippling with axis-aligned
3673 * endcaps.
3674 */
3675 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3676 unsigned sc_aa_config = 0;
3677
3678 if (coverage_samples > 1) {
3679 /* distance from the pixel center, indexed by log2(nr_samples) */
3680 static unsigned max_dist[] = {
3681 0, /* unused */
3682 4, /* 2x MSAA */
3683 6, /* 4x MSAA */
3684 7, /* 8x MSAA */
3685 8, /* 16x MSAA */
3686 };
3687 unsigned log_samples = util_logbase2(coverage_samples);
3688 unsigned log_z_samples = util_logbase2(z_samples);
3689 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3690 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3691
3692 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3693 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3694 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3695 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3696
3697 if (sctx->framebuffer.nr_samples > 1) {
3698 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3699 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3700 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3701 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3702 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3703 } else if (sctx->smoothing_enabled) {
3704 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3705 }
3706 }
3707
3708 unsigned initial_cdw = cs->current.cdw;
3709
3710 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3711 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3712 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3713 sc_aa_config);
3714 /* R_028804_DB_EQAA */
3715 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3716 db_eqaa);
3717 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3718 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3719 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3720
3721 if (initial_cdw != cs->current.cdw) {
3722 sctx->context_roll = true;
3723
3724 /* GFX9: Flush DFSM when the AA mode changes. */
3725 if (sctx->screen->dfsm_allowed) {
3726 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3727 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3728 }
3729 }
3730 }
3731
3732 void si_update_ps_iter_samples(struct si_context *sctx)
3733 {
3734 if (sctx->framebuffer.nr_samples > 1)
3735 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3736 if (sctx->screen->dpbb_allowed)
3737 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3738 }
3739
3740 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3741 {
3742 struct si_context *sctx = (struct si_context *)ctx;
3743
3744 /* The hardware can only do sample shading with 2^n samples. */
3745 min_samples = util_next_power_of_two(min_samples);
3746
3747 if (sctx->ps_iter_samples == min_samples)
3748 return;
3749
3750 sctx->ps_iter_samples = min_samples;
3751 sctx->do_update_shaders = true;
3752
3753 si_update_ps_iter_samples(sctx);
3754 }
3755
3756 /*
3757 * Samplers
3758 */
3759
3760 /**
3761 * Build the sampler view descriptor for a buffer texture.
3762 * @param state 256-bit descriptor; only the high 128 bits are filled in
3763 */
3764 void
3765 si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
3766 enum pipe_format format,
3767 unsigned offset, unsigned size,
3768 uint32_t *state)
3769 {
3770 const struct util_format_description *desc;
3771 unsigned stride;
3772 unsigned num_records;
3773
3774 desc = util_format_description(format);
3775 stride = desc->block.bits / 8;
3776
3777 num_records = size / stride;
3778 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3779
3780 /* The NUM_RECORDS field has a different meaning depending on the chip,
3781 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3782 *
3783 * GFX6-7,10:
3784 * - If STRIDE == 0, it's in byte units.
3785 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3786 *
3787 * GFX8:
3788 * - For SMEM and STRIDE == 0, it's in byte units.
3789 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3790 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3791 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3792 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3793 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3794 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3795 * That way the same descriptor can be used by both SMEM and VMEM.
3796 *
3797 * GFX9:
3798 * - For SMEM and STRIDE == 0, it's in byte units.
3799 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3800 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3801 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3802 */
3803 if (screen->info.chip_class == GFX9 && HAVE_LLVM < 0x0800)
3804 /* When vindex == 0, LLVM < 8.0 sets IDXEN = 0, thus changing units
3805 * from STRIDE to bytes. This works around it by setting
3806 * NUM_RECORDS to at least the size of one element, so that
3807 * the first element is readable when IDXEN == 0.
3808 */
3809 num_records = num_records ? MAX2(num_records, stride) : 0;
3810 else if (screen->info.chip_class == GFX8)
3811 num_records *= stride;
3812
3813 state[4] = 0;
3814 state[5] = S_008F04_STRIDE(stride);
3815 state[6] = num_records;
3816 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3817 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3818 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3819 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
3820
3821 if (screen->info.chip_class >= GFX10) {
3822 const struct gfx10_format *fmt = &gfx10_format_table[format];
3823
3824 /* OOB_SELECT chooses the out-of-bounds check:
3825 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3826 * - 1: index >= NUM_RECORDS
3827 * - 2: NUM_RECORDS == 0
3828 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3829 * else: swizzle_address >= NUM_RECORDS
3830 */
3831 state[7] |= S_008F0C_FORMAT(fmt->img_format) |
3832 S_008F0C_OOB_SELECT(0) |
3833 S_008F0C_RESOURCE_LEVEL(1);
3834 } else {
3835 int first_non_void;
3836 unsigned num_format, data_format;
3837
3838 first_non_void = util_format_get_first_non_void_channel(format);
3839 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3840 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3841
3842 state[7] |= S_008F0C_NUM_FORMAT(num_format) |
3843 S_008F0C_DATA_FORMAT(data_format);
3844 }
3845 }
3846
3847 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3848 {
3849 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3850
3851 if (swizzle[3] == PIPE_SWIZZLE_X) {
3852 /* For the pre-defined border color values (white, opaque
3853 * black, transparent black), the only thing that matters is
3854 * that the alpha channel winds up in the correct place
3855 * (because the RGB channels are all the same) so either of
3856 * these enumerations will work.
3857 */
3858 if (swizzle[2] == PIPE_SWIZZLE_Y)
3859 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3860 else
3861 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3862 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3863 if (swizzle[1] == PIPE_SWIZZLE_Y)
3864 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3865 else
3866 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3867 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3868 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3869 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3870 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3871 }
3872
3873 return bc_swizzle;
3874 }
3875
3876 /**
3877 * Build the sampler view descriptor for a texture.
3878 */
3879 static void
3880 gfx10_make_texture_descriptor(struct si_screen *screen,
3881 struct si_texture *tex,
3882 bool sampler,
3883 enum pipe_texture_target target,
3884 enum pipe_format pipe_format,
3885 const unsigned char state_swizzle[4],
3886 unsigned first_level, unsigned last_level,
3887 unsigned first_layer, unsigned last_layer,
3888 unsigned width, unsigned height, unsigned depth,
3889 uint32_t *state,
3890 uint32_t *fmask_state)
3891 {
3892 struct pipe_resource *res = &tex->buffer.b.b;
3893 const struct util_format_description *desc;
3894 unsigned img_format;
3895 unsigned char swizzle[4];
3896 unsigned type;
3897 uint64_t va;
3898
3899 desc = util_format_description(pipe_format);
3900 img_format = gfx10_format_table[pipe_format].img_format;
3901
3902 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3903 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3904 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3905 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3906 bool is_stencil = false;
3907
3908 switch (pipe_format) {
3909 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3910 case PIPE_FORMAT_X32_S8X24_UINT:
3911 case PIPE_FORMAT_X8Z24_UNORM:
3912 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3913 is_stencil = true;
3914 break;
3915 case PIPE_FORMAT_X24S8_UINT:
3916 /*
3917 * X24S8 is implemented as an 8_8_8_8 data format, to
3918 * fix texture gathers. This affects at least
3919 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3920 */
3921 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3922 is_stencil = true;
3923 break;
3924 default:
3925 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3926 is_stencil = pipe_format == PIPE_FORMAT_S8_UINT;
3927 }
3928
3929 if (tex->upgraded_depth && !is_stencil) {
3930 assert(img_format == V_008F0C_IMG_FORMAT_32_FLOAT);
3931 img_format = V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP;
3932 }
3933 } else {
3934 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3935 }
3936
3937 if (!sampler &&
3938 (res->target == PIPE_TEXTURE_CUBE ||
3939 res->target == PIPE_TEXTURE_CUBE_ARRAY)) {
3940 /* For the purpose of shader images, treat cube maps as 2D
3941 * arrays.
3942 */
3943 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3944 } else {
3945 type = si_tex_dim(screen, tex, target, res->nr_samples);
3946 }
3947
3948 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3949 height = 1;
3950 depth = res->array_size;
3951 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3952 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3953 if (sampler || res->target != PIPE_TEXTURE_3D)
3954 depth = res->array_size;
3955 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3956 depth = res->array_size / 6;
3957
3958 state[0] = 0;
3959 state[1] = S_00A004_FORMAT(img_format) |
3960 S_00A004_WIDTH_LO(width - 1);
3961 state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
3962 S_00A008_HEIGHT(height - 1) |
3963 S_00A008_RESOURCE_LEVEL(1);
3964 state[3] = S_00A00C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3965 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3966 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3967 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3968 S_00A00C_BASE_LEVEL(res->nr_samples > 1 ?
3969 0 : first_level) |
3970 S_00A00C_LAST_LEVEL(res->nr_samples > 1 ?
3971 util_logbase2(res->nr_samples) :
3972 last_level) |
3973 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc->swizzle)) |
3974 S_00A00C_TYPE(type);
3975 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3976 * to know the total number of layers.
3977 */
3978 state[4] = S_00A010_DEPTH((type == V_008F1C_SQ_RSRC_IMG_3D && sampler)
3979 ? depth - 1 : last_layer) |
3980 S_00A010_BASE_ARRAY(first_layer);
3981 state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D && !sampler)) |
3982 S_00A014_MAX_MIP(res->nr_samples > 1 ?
3983 util_logbase2(res->nr_samples) :
3984 tex->buffer.b.b.last_level) |
3985 S_00A014_PERF_MOD(4);
3986 state[6] = 0;
3987 state[7] = 0;
3988
3989 if (tex->dcc_offset) {
3990 state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
3991 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
3992 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
3993 }
3994
3995 /* Initialize the sampler view for FMASK. */
3996 if (tex->fmask_offset) {
3997 uint32_t format;
3998
3999 va = tex->buffer.gpu_address + tex->fmask_offset;
4000
4001 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4002 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4003 case FMASK(2,1):
4004 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F1;
4005 break;
4006 case FMASK(2,2):
4007 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
4008 break;
4009 case FMASK(4,1):
4010 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F1;
4011 break;
4012 case FMASK(4,2):
4013 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F2;
4014 break;
4015 case FMASK(4,4):
4016 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
4017 break;
4018 case FMASK(8,1):
4019 format = V_008F0C_IMG_FORMAT_FMASK8_S8_F1;
4020 break;
4021 case FMASK(8,2):
4022 format = V_008F0C_IMG_FORMAT_FMASK16_S8_F2;
4023 break;
4024 case FMASK(8,4):
4025 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F4;
4026 break;
4027 case FMASK(8,8):
4028 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
4029 break;
4030 case FMASK(16,1):
4031 format = V_008F0C_IMG_FORMAT_FMASK16_S16_F1;
4032 break;
4033 case FMASK(16,2):
4034 format = V_008F0C_IMG_FORMAT_FMASK32_S16_F2;
4035 break;
4036 case FMASK(16,4):
4037 format = V_008F0C_IMG_FORMAT_FMASK64_S16_F4;
4038 break;
4039 case FMASK(16,8):
4040 format = V_008F0C_IMG_FORMAT_FMASK64_S16_F8;
4041 break;
4042 default:
4043 unreachable("invalid nr_samples");
4044 }
4045 #undef FMASK
4046 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4047 fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
4048 S_00A004_FORMAT(format) |
4049 S_00A004_WIDTH_LO(width - 1);
4050 fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
4051 S_00A008_HEIGHT(height - 1) |
4052 S_00A008_RESOURCE_LEVEL(1);
4053 fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4054 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4055 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4056 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4057 S_00A00C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
4058 S_00A00C_TYPE(si_tex_dim(screen, tex, target, 0));
4059 fmask_state[4] = S_00A010_DEPTH(last_layer) |
4060 S_00A010_BASE_ARRAY(first_layer);
4061 fmask_state[5] = 0;
4062 fmask_state[6] = S_00A018_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned);
4063 fmask_state[7] = 0;
4064 }
4065 }
4066
4067 /**
4068 * Build the sampler view descriptor for a texture (SI-GFX9).
4069 */
4070 static void
4071 si_make_texture_descriptor(struct si_screen *screen,
4072 struct si_texture *tex,
4073 bool sampler,
4074 enum pipe_texture_target target,
4075 enum pipe_format pipe_format,
4076 const unsigned char state_swizzle[4],
4077 unsigned first_level, unsigned last_level,
4078 unsigned first_layer, unsigned last_layer,
4079 unsigned width, unsigned height, unsigned depth,
4080 uint32_t *state,
4081 uint32_t *fmask_state)
4082 {
4083 struct pipe_resource *res = &tex->buffer.b.b;
4084 const struct util_format_description *desc;
4085 unsigned char swizzle[4];
4086 int first_non_void;
4087 unsigned num_format, data_format, type, num_samples;
4088 uint64_t va;
4089
4090 desc = util_format_description(pipe_format);
4091
4092 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
4093 MAX2(1, res->nr_samples) :
4094 MAX2(1, res->nr_storage_samples);
4095
4096 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
4097 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
4098 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
4099 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
4100
4101 switch (pipe_format) {
4102 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4103 case PIPE_FORMAT_X32_S8X24_UINT:
4104 case PIPE_FORMAT_X8Z24_UNORM:
4105 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
4106 break;
4107 case PIPE_FORMAT_X24S8_UINT:
4108 /*
4109 * X24S8 is implemented as an 8_8_8_8 data format, to
4110 * fix texture gathers. This affects at least
4111 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
4112 */
4113 if (screen->info.chip_class <= GFX8)
4114 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
4115 else
4116 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
4117 break;
4118 default:
4119 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
4120 }
4121 } else {
4122 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
4123 }
4124
4125 first_non_void = util_format_get_first_non_void_channel(pipe_format);
4126
4127 switch (pipe_format) {
4128 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4129 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4130 break;
4131 default:
4132 if (first_non_void < 0) {
4133 if (util_format_is_compressed(pipe_format)) {
4134 switch (pipe_format) {
4135 case PIPE_FORMAT_DXT1_SRGB:
4136 case PIPE_FORMAT_DXT1_SRGBA:
4137 case PIPE_FORMAT_DXT3_SRGBA:
4138 case PIPE_FORMAT_DXT5_SRGBA:
4139 case PIPE_FORMAT_BPTC_SRGBA:
4140 case PIPE_FORMAT_ETC2_SRGB8:
4141 case PIPE_FORMAT_ETC2_SRGB8A1:
4142 case PIPE_FORMAT_ETC2_SRGBA8:
4143 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
4144 break;
4145 case PIPE_FORMAT_RGTC1_SNORM:
4146 case PIPE_FORMAT_LATC1_SNORM:
4147 case PIPE_FORMAT_RGTC2_SNORM:
4148 case PIPE_FORMAT_LATC2_SNORM:
4149 case PIPE_FORMAT_ETC2_R11_SNORM:
4150 case PIPE_FORMAT_ETC2_RG11_SNORM:
4151 /* implies float, so use SNORM/UNORM to determine
4152 whether data is signed or not */
4153 case PIPE_FORMAT_BPTC_RGB_FLOAT:
4154 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
4155 break;
4156 default:
4157 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4158 break;
4159 }
4160 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
4161 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4162 } else {
4163 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
4164 }
4165 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
4166 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
4167 } else {
4168 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4169
4170 switch (desc->channel[first_non_void].type) {
4171 case UTIL_FORMAT_TYPE_FLOAT:
4172 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
4173 break;
4174 case UTIL_FORMAT_TYPE_SIGNED:
4175 if (desc->channel[first_non_void].normalized)
4176 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
4177 else if (desc->channel[first_non_void].pure_integer)
4178 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
4179 else
4180 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
4181 break;
4182 case UTIL_FORMAT_TYPE_UNSIGNED:
4183 if (desc->channel[first_non_void].normalized)
4184 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
4185 else if (desc->channel[first_non_void].pure_integer)
4186 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4187 else
4188 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
4189 }
4190 }
4191 }
4192
4193 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
4194 if (data_format == ~0) {
4195 data_format = 0;
4196 }
4197
4198 /* S8 with Z32 HTILE needs a special format. */
4199 if (screen->info.chip_class == GFX9 &&
4200 pipe_format == PIPE_FORMAT_S8_UINT &&
4201 tex->tc_compatible_htile)
4202 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
4203
4204 if (!sampler &&
4205 (res->target == PIPE_TEXTURE_CUBE ||
4206 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
4207 (screen->info.chip_class <= GFX8 &&
4208 res->target == PIPE_TEXTURE_3D))) {
4209 /* For the purpose of shader images, treat cube maps and 3D
4210 * textures as 2D arrays. For 3D textures, the address
4211 * calculations for mipmaps are different, so we rely on the
4212 * caller to effectively disable mipmaps.
4213 */
4214 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
4215
4216 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
4217 } else {
4218 type = si_tex_dim(screen, tex, target, num_samples);
4219 }
4220
4221 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
4222 height = 1;
4223 depth = res->array_size;
4224 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
4225 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
4226 if (sampler || res->target != PIPE_TEXTURE_3D)
4227 depth = res->array_size;
4228 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
4229 depth = res->array_size / 6;
4230
4231 state[0] = 0;
4232 state[1] = (S_008F14_DATA_FORMAT(data_format) |
4233 S_008F14_NUM_FORMAT(num_format));
4234 state[2] = (S_008F18_WIDTH(width - 1) |
4235 S_008F18_HEIGHT(height - 1) |
4236 S_008F18_PERF_MOD(4));
4237 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4238 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4239 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4240 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4241 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
4242 S_008F1C_LAST_LEVEL(num_samples > 1 ?
4243 util_logbase2(num_samples) :
4244 last_level) |
4245 S_008F1C_TYPE(type));
4246 state[4] = 0;
4247 state[5] = S_008F24_BASE_ARRAY(first_layer);
4248 state[6] = 0;
4249 state[7] = 0;
4250
4251 if (screen->info.chip_class == GFX9) {
4252 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
4253
4254 /* Depth is the the last accessible layer on Gfx9.
4255 * The hw doesn't need to know the total number of layers.
4256 */
4257 if (type == V_008F1C_SQ_RSRC_IMG_3D)
4258 state[4] |= S_008F20_DEPTH(depth - 1);
4259 else
4260 state[4] |= S_008F20_DEPTH(last_layer);
4261
4262 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
4263 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
4264 util_logbase2(num_samples) :
4265 tex->buffer.b.b.last_level);
4266 } else {
4267 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
4268 state[4] |= S_008F20_DEPTH(depth - 1);
4269 state[5] |= S_008F24_LAST_ARRAY(last_layer);
4270 }
4271
4272 if (tex->dcc_offset) {
4273 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
4274 } else {
4275 /* The last dword is unused by hw. The shader uses it to clear
4276 * bits in the first dword of sampler state.
4277 */
4278 if (screen->info.chip_class <= GFX7 && res->nr_samples <= 1) {
4279 if (first_level == last_level)
4280 state[7] = C_008F30_MAX_ANISO_RATIO;
4281 else
4282 state[7] = 0xffffffff;
4283 }
4284 }
4285
4286 /* Initialize the sampler view for FMASK. */
4287 if (tex->fmask_offset) {
4288 uint32_t data_format, num_format;
4289
4290 va = tex->buffer.gpu_address + tex->fmask_offset;
4291
4292 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4293 if (screen->info.chip_class == GFX9) {
4294 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
4295 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4296 case FMASK(2,1):
4297 num_format = V_008F14_IMG_FMASK_8_2_1;
4298 break;
4299 case FMASK(2,2):
4300 num_format = V_008F14_IMG_FMASK_8_2_2;
4301 break;
4302 case FMASK(4,1):
4303 num_format = V_008F14_IMG_FMASK_8_4_1;
4304 break;
4305 case FMASK(4,2):
4306 num_format = V_008F14_IMG_FMASK_8_4_2;
4307 break;
4308 case FMASK(4,4):
4309 num_format = V_008F14_IMG_FMASK_8_4_4;
4310 break;
4311 case FMASK(8,1):
4312 num_format = V_008F14_IMG_FMASK_8_8_1;
4313 break;
4314 case FMASK(8,2):
4315 num_format = V_008F14_IMG_FMASK_16_8_2;
4316 break;
4317 case FMASK(8,4):
4318 num_format = V_008F14_IMG_FMASK_32_8_4;
4319 break;
4320 case FMASK(8,8):
4321 num_format = V_008F14_IMG_FMASK_32_8_8;
4322 break;
4323 case FMASK(16,1):
4324 num_format = V_008F14_IMG_FMASK_16_16_1;
4325 break;
4326 case FMASK(16,2):
4327 num_format = V_008F14_IMG_FMASK_32_16_2;
4328 break;
4329 case FMASK(16,4):
4330 num_format = V_008F14_IMG_FMASK_64_16_4;
4331 break;
4332 case FMASK(16,8):
4333 num_format = V_008F14_IMG_FMASK_64_16_8;
4334 break;
4335 default:
4336 unreachable("invalid nr_samples");
4337 }
4338 } else {
4339 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
4340 case FMASK(2,1):
4341 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
4342 break;
4343 case FMASK(2,2):
4344 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
4345 break;
4346 case FMASK(4,1):
4347 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
4348 break;
4349 case FMASK(4,2):
4350 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
4351 break;
4352 case FMASK(4,4):
4353 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
4354 break;
4355 case FMASK(8,1):
4356 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
4357 break;
4358 case FMASK(8,2):
4359 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
4360 break;
4361 case FMASK(8,4):
4362 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
4363 break;
4364 case FMASK(8,8):
4365 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
4366 break;
4367 case FMASK(16,1):
4368 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
4369 break;
4370 case FMASK(16,2):
4371 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
4372 break;
4373 case FMASK(16,4):
4374 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
4375 break;
4376 case FMASK(16,8):
4377 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
4378 break;
4379 default:
4380 unreachable("invalid nr_samples");
4381 }
4382 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4383 }
4384 #undef FMASK
4385
4386 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4387 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
4388 S_008F14_DATA_FORMAT(data_format) |
4389 S_008F14_NUM_FORMAT(num_format);
4390 fmask_state[2] = S_008F18_WIDTH(width - 1) |
4391 S_008F18_HEIGHT(height - 1);
4392 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4393 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4394 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4395 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4396 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
4397 fmask_state[4] = 0;
4398 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
4399 fmask_state[6] = 0;
4400 fmask_state[7] = 0;
4401
4402 if (screen->info.chip_class == GFX9) {
4403 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
4404 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
4405 S_008F20_PITCH(tex->surface.u.gfx9.fmask.epitch);
4406 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
4407 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
4408 } else {
4409 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
4410 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
4411 S_008F20_PITCH(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
4412 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
4413 }
4414 }
4415 }
4416
4417 /**
4418 * Create a sampler view.
4419 *
4420 * @param ctx context
4421 * @param texture texture
4422 * @param state sampler view template
4423 * @param width0 width0 override (for compressed textures as int)
4424 * @param height0 height0 override (for compressed textures as int)
4425 * @param force_level set the base address to the level (for compressed textures)
4426 */
4427 struct pipe_sampler_view *
4428 si_create_sampler_view_custom(struct pipe_context *ctx,
4429 struct pipe_resource *texture,
4430 const struct pipe_sampler_view *state,
4431 unsigned width0, unsigned height0,
4432 unsigned force_level)
4433 {
4434 struct si_context *sctx = (struct si_context*)ctx;
4435 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
4436 struct si_texture *tex = (struct si_texture*)texture;
4437 unsigned base_level, first_level, last_level;
4438 unsigned char state_swizzle[4];
4439 unsigned height, depth, width;
4440 unsigned last_layer = state->u.tex.last_layer;
4441 enum pipe_format pipe_format;
4442 const struct legacy_surf_level *surflevel;
4443
4444 if (!view)
4445 return NULL;
4446
4447 /* initialize base object */
4448 view->base = *state;
4449 view->base.texture = NULL;
4450 view->base.reference.count = 1;
4451 view->base.context = ctx;
4452
4453 assert(texture);
4454 pipe_resource_reference(&view->base.texture, texture);
4455
4456 if (state->format == PIPE_FORMAT_X24S8_UINT ||
4457 state->format == PIPE_FORMAT_S8X24_UINT ||
4458 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4459 state->format == PIPE_FORMAT_S8_UINT)
4460 view->is_stencil_sampler = true;
4461
4462 /* Buffer resource. */
4463 if (texture->target == PIPE_BUFFER) {
4464 si_make_buffer_descriptor(sctx->screen,
4465 si_resource(texture),
4466 state->format,
4467 state->u.buf.offset,
4468 state->u.buf.size,
4469 view->state);
4470 return &view->base;
4471 }
4472
4473 state_swizzle[0] = state->swizzle_r;
4474 state_swizzle[1] = state->swizzle_g;
4475 state_swizzle[2] = state->swizzle_b;
4476 state_swizzle[3] = state->swizzle_a;
4477
4478 base_level = 0;
4479 first_level = state->u.tex.first_level;
4480 last_level = state->u.tex.last_level;
4481 width = width0;
4482 height = height0;
4483 depth = texture->depth0;
4484
4485 if (sctx->chip_class <= GFX8 && force_level) {
4486 assert(force_level == first_level &&
4487 force_level == last_level);
4488 base_level = force_level;
4489 first_level = 0;
4490 last_level = 0;
4491 width = u_minify(width, force_level);
4492 height = u_minify(height, force_level);
4493 depth = u_minify(depth, force_level);
4494 }
4495
4496 /* This is not needed if state trackers set last_layer correctly. */
4497 if (state->target == PIPE_TEXTURE_1D ||
4498 state->target == PIPE_TEXTURE_2D ||
4499 state->target == PIPE_TEXTURE_RECT ||
4500 state->target == PIPE_TEXTURE_CUBE)
4501 last_layer = state->u.tex.first_layer;
4502
4503 /* Texturing with separate depth and stencil. */
4504 pipe_format = state->format;
4505
4506 /* Depth/stencil texturing sometimes needs separate texture. */
4507 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4508 if (!tex->flushed_depth_texture &&
4509 !si_init_flushed_depth_texture(ctx, texture)) {
4510 pipe_resource_reference(&view->base.texture, NULL);
4511 FREE(view);
4512 return NULL;
4513 }
4514
4515 assert(tex->flushed_depth_texture);
4516
4517 /* Override format for the case where the flushed texture
4518 * contains only Z or only S.
4519 */
4520 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4521 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4522
4523 tex = tex->flushed_depth_texture;
4524 }
4525
4526 surflevel = tex->surface.u.legacy.level;
4527
4528 if (tex->db_compatible) {
4529 if (!view->is_stencil_sampler)
4530 pipe_format = tex->db_render_format;
4531
4532 switch (pipe_format) {
4533 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4534 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4535 break;
4536 case PIPE_FORMAT_X8Z24_UNORM:
4537 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4538 /* Z24 is always stored like this for DB
4539 * compatibility.
4540 */
4541 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4542 break;
4543 case PIPE_FORMAT_X24S8_UINT:
4544 case PIPE_FORMAT_S8X24_UINT:
4545 case PIPE_FORMAT_X32_S8X24_UINT:
4546 pipe_format = PIPE_FORMAT_S8_UINT;
4547 surflevel = tex->surface.u.legacy.stencil_level;
4548 break;
4549 default:;
4550 }
4551 }
4552
4553 view->dcc_incompatible =
4554 vi_dcc_formats_are_incompatible(texture,
4555 state->u.tex.first_level,
4556 state->format);
4557
4558 sctx->screen->make_texture_descriptor(sctx->screen, tex, true,
4559 state->target, pipe_format, state_swizzle,
4560 first_level, last_level,
4561 state->u.tex.first_layer, last_layer,
4562 width, height, depth,
4563 view->state, view->fmask_state);
4564
4565 const struct util_format_description *desc = util_format_description(pipe_format);
4566 view->is_integer = false;
4567
4568 for (unsigned i = 0; i < desc->nr_channels; ++i) {
4569 if (desc->channel[i].type == UTIL_FORMAT_TYPE_VOID)
4570 continue;
4571
4572 /* Whether the number format is {U,S}{SCALED,INT} */
4573 view->is_integer =
4574 (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED ||
4575 desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) &&
4576 (desc->channel[i].pure_integer || !desc->channel[i].normalized);
4577 break;
4578 }
4579
4580 view->base_level_info = &surflevel[base_level];
4581 view->base_level = base_level;
4582 view->block_width = util_format_get_blockwidth(pipe_format);
4583 return &view->base;
4584 }
4585
4586 static struct pipe_sampler_view *
4587 si_create_sampler_view(struct pipe_context *ctx,
4588 struct pipe_resource *texture,
4589 const struct pipe_sampler_view *state)
4590 {
4591 return si_create_sampler_view_custom(ctx, texture, state,
4592 texture ? texture->width0 : 0,
4593 texture ? texture->height0 : 0, 0);
4594 }
4595
4596 static void si_sampler_view_destroy(struct pipe_context *ctx,
4597 struct pipe_sampler_view *state)
4598 {
4599 struct si_sampler_view *view = (struct si_sampler_view *)state;
4600
4601 pipe_resource_reference(&state->texture, NULL);
4602 FREE(view);
4603 }
4604
4605 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4606 {
4607 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4608 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4609 (linear_filter &&
4610 (wrap == PIPE_TEX_WRAP_CLAMP ||
4611 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4612 }
4613
4614 static uint32_t si_translate_border_color(struct si_context *sctx,
4615 const struct pipe_sampler_state *state,
4616 const union pipe_color_union *color,
4617 bool is_integer)
4618 {
4619 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4620 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4621
4622 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4623 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4624 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4625 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4626
4627 #define simple_border_types(elt) \
4628 do { \
4629 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4630 color->elt[2] == 0 && color->elt[3] == 0) \
4631 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4632 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4633 color->elt[2] == 0 && color->elt[3] == 1) \
4634 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4635 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4636 color->elt[2] == 1 && color->elt[3] == 1) \
4637 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4638 } while (false)
4639
4640 if (is_integer)
4641 simple_border_types(ui);
4642 else
4643 simple_border_types(f);
4644
4645 #undef simple_border_types
4646
4647 int i;
4648
4649 /* Check if the border has been uploaded already. */
4650 for (i = 0; i < sctx->border_color_count; i++)
4651 if (memcmp(&sctx->border_color_table[i], color,
4652 sizeof(*color)) == 0)
4653 break;
4654
4655 if (i >= SI_MAX_BORDER_COLORS) {
4656 /* Getting 4096 unique border colors is very unlikely. */
4657 fprintf(stderr, "radeonsi: The border color table is full. "
4658 "Any new border colors will be just black. "
4659 "Please file a bug.\n");
4660 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4661 }
4662
4663 if (i == sctx->border_color_count) {
4664 /* Upload a new border color. */
4665 memcpy(&sctx->border_color_table[i], color,
4666 sizeof(*color));
4667 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4668 color, sizeof(*color));
4669 sctx->border_color_count++;
4670 }
4671
4672 return S_008F3C_BORDER_COLOR_PTR(i) |
4673 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4674 }
4675
4676 static inline int S_FIXED(float value, unsigned frac_bits)
4677 {
4678 return value * (1 << frac_bits);
4679 }
4680
4681 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4682 {
4683 if (filter == PIPE_TEX_FILTER_LINEAR)
4684 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4685 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4686 else
4687 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4688 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4689 }
4690
4691 static inline unsigned si_tex_aniso_filter(unsigned filter)
4692 {
4693 if (filter < 2)
4694 return 0;
4695 if (filter < 4)
4696 return 1;
4697 if (filter < 8)
4698 return 2;
4699 if (filter < 16)
4700 return 3;
4701 return 4;
4702 }
4703
4704 static void *si_create_sampler_state(struct pipe_context *ctx,
4705 const struct pipe_sampler_state *state)
4706 {
4707 struct si_context *sctx = (struct si_context *)ctx;
4708 struct si_screen *sscreen = sctx->screen;
4709 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4710 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4711 : state->max_anisotropy;
4712 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4713 union pipe_color_union clamped_border_color;
4714
4715 if (!rstate) {
4716 return NULL;
4717 }
4718
4719 #ifndef NDEBUG
4720 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4721 #endif
4722 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4723 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4724 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4725 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4726 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4727 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4728 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4729 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4730 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4731 S_008F30_COMPAT_MODE(sctx->chip_class == GFX8 || sctx->chip_class == GFX9));
4732 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4733 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4734 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4735 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4736 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4737 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4738 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4739 S_008F38_MIP_POINT_PRECLAMP(0));
4740 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4741
4742 if (sscreen->info.chip_class >= GFX10) {
4743 rstate->val[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4744 } else {
4745 rstate->val[2] |= S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= GFX8) |
4746 S_008F38_FILTER_PREC_FIX(1) |
4747 S_008F38_ANISO_OVERRIDE_GFX6(sctx->chip_class >= GFX8);
4748 }
4749
4750 /* Create sampler resource for integer textures. */
4751 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4752 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4753
4754 /* Create sampler resource for upgraded depth textures. */
4755 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4756
4757 for (unsigned i = 0; i < 4; ++i) {
4758 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4759 * when the border color is 1.0. */
4760 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4761 }
4762
4763 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0) {
4764 if (sscreen->info.chip_class <= GFX9)
4765 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4766 } else {
4767 rstate->upgraded_depth_val[3] =
4768 si_translate_border_color(sctx, state, &clamped_border_color, false);
4769 }
4770
4771 return rstate;
4772 }
4773
4774 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4775 {
4776 struct si_context *sctx = (struct si_context *)ctx;
4777
4778 if (sctx->sample_mask == (uint16_t)sample_mask)
4779 return;
4780
4781 sctx->sample_mask = sample_mask;
4782 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4783 }
4784
4785 static void si_emit_sample_mask(struct si_context *sctx)
4786 {
4787 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4788 unsigned mask = sctx->sample_mask;
4789
4790 /* Needed for line and polygon smoothing as well as for the Polaris
4791 * small primitive filter. We expect the state tracker to take care of
4792 * this for us.
4793 */
4794 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4795 (mask & 1 && sctx->blitter->running));
4796
4797 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4798 radeon_emit(cs, mask | (mask << 16));
4799 radeon_emit(cs, mask | (mask << 16));
4800 }
4801
4802 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4803 {
4804 #ifndef NDEBUG
4805 struct si_sampler_state *s = state;
4806
4807 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4808 s->magic = 0;
4809 #endif
4810 free(state);
4811 }
4812
4813 /*
4814 * Vertex elements & buffers
4815 */
4816
4817 struct si_fast_udiv_info32
4818 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4819 {
4820 struct util_fast_udiv_info info =
4821 util_compute_fast_udiv_info(D, num_bits, 32);
4822
4823 struct si_fast_udiv_info32 result = {
4824 info.multiplier,
4825 info.pre_shift,
4826 info.post_shift,
4827 info.increment,
4828 };
4829 return result;
4830 }
4831
4832 static void *si_create_vertex_elements(struct pipe_context *ctx,
4833 unsigned count,
4834 const struct pipe_vertex_element *elements)
4835 {
4836 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4837 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4838 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4839 struct si_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4840 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32) == 16);
4841 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4842 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4843 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4844 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4845 int i;
4846
4847 assert(count <= SI_MAX_ATTRIBS);
4848 if (!v)
4849 return NULL;
4850
4851 v->count = count;
4852 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4853
4854 for (i = 0; i < count; ++i) {
4855 const struct util_format_description *desc;
4856 const struct util_format_channel_description *channel;
4857 int first_non_void;
4858 unsigned vbo_index = elements[i].vertex_buffer_index;
4859
4860 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4861 FREE(v);
4862 return NULL;
4863 }
4864
4865 unsigned instance_divisor = elements[i].instance_divisor;
4866 if (instance_divisor) {
4867 v->uses_instance_divisors = true;
4868
4869 if (instance_divisor == 1) {
4870 v->instance_divisor_is_one |= 1u << i;
4871 } else {
4872 v->instance_divisor_is_fetched |= 1u << i;
4873 divisor_factors[i] =
4874 si_compute_fast_udiv_info32(instance_divisor, 32);
4875 }
4876 }
4877
4878 if (!used[vbo_index]) {
4879 v->first_vb_use_mask |= 1 << i;
4880 used[vbo_index] = true;
4881 }
4882
4883 desc = util_format_description(elements[i].src_format);
4884 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4885 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4886
4887 v->format_size[i] = desc->block.bits / 8;
4888 v->src_offset[i] = elements[i].src_offset;
4889 v->vertex_buffer_index[i] = vbo_index;
4890
4891 bool always_fix = false;
4892 union si_vs_fix_fetch fix_fetch;
4893 unsigned log_hw_load_size; /* the load element size as seen by the hardware */
4894
4895 fix_fetch.bits = 0;
4896 log_hw_load_size = MIN2(2, util_logbase2(desc->block.bits) - 3);
4897
4898 if (channel) {
4899 switch (channel->type) {
4900 case UTIL_FORMAT_TYPE_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4901 case UTIL_FORMAT_TYPE_FIXED: fix_fetch.u.format = AC_FETCH_FORMAT_FIXED; break;
4902 case UTIL_FORMAT_TYPE_SIGNED: {
4903 if (channel->pure_integer)
4904 fix_fetch.u.format = AC_FETCH_FORMAT_SINT;
4905 else if (channel->normalized)
4906 fix_fetch.u.format = AC_FETCH_FORMAT_SNORM;
4907 else
4908 fix_fetch.u.format = AC_FETCH_FORMAT_SSCALED;
4909 break;
4910 }
4911 case UTIL_FORMAT_TYPE_UNSIGNED: {
4912 if (channel->pure_integer)
4913 fix_fetch.u.format = AC_FETCH_FORMAT_UINT;
4914 else if (channel->normalized)
4915 fix_fetch.u.format = AC_FETCH_FORMAT_UNORM;
4916 else
4917 fix_fetch.u.format = AC_FETCH_FORMAT_USCALED;
4918 break;
4919 }
4920 default: unreachable("bad format type");
4921 }
4922 } else {
4923 switch (elements[i].src_format) {
4924 case PIPE_FORMAT_R11G11B10_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4925 default: unreachable("bad other format");
4926 }
4927 }
4928
4929 if (desc->channel[0].size == 10) {
4930 fix_fetch.u.log_size = 3; /* special encoding for 2_10_10_10 */
4931 log_hw_load_size = 2;
4932
4933 /* The hardware always treats the 2-bit alpha channel as
4934 * unsigned, so a shader workaround is needed. The affected
4935 * chips are GFX8 and older except Stoney (GFX8.1).
4936 */
4937 always_fix = sscreen->info.chip_class <= GFX8 &&
4938 sscreen->info.family != CHIP_STONEY &&
4939 channel->type == UTIL_FORMAT_TYPE_SIGNED;
4940 } else if (elements[i].src_format == PIPE_FORMAT_R11G11B10_FLOAT) {
4941 fix_fetch.u.log_size = 3; /* special encoding */
4942 fix_fetch.u.format = AC_FETCH_FORMAT_FIXED;
4943 log_hw_load_size = 2;
4944 } else {
4945 fix_fetch.u.log_size = util_logbase2(channel->size) - 3;
4946 fix_fetch.u.num_channels_m1 = desc->nr_channels - 1;
4947
4948 /* Always fix up:
4949 * - doubles (multiple loads + truncate to float)
4950 * - 32-bit requiring a conversion
4951 */
4952 always_fix =
4953 (fix_fetch.u.log_size == 3) ||
4954 (fix_fetch.u.log_size == 2 &&
4955 fix_fetch.u.format != AC_FETCH_FORMAT_FLOAT &&
4956 fix_fetch.u.format != AC_FETCH_FORMAT_UINT &&
4957 fix_fetch.u.format != AC_FETCH_FORMAT_SINT);
4958
4959 /* Also fixup 8_8_8 and 16_16_16. */
4960 if (desc->nr_channels == 3 && fix_fetch.u.log_size <= 1) {
4961 always_fix = true;
4962 log_hw_load_size = fix_fetch.u.log_size;
4963 }
4964 }
4965
4966 if (desc->swizzle[0] != PIPE_SWIZZLE_X) {
4967 assert(desc->swizzle[0] == PIPE_SWIZZLE_Z &&
4968 (desc->swizzle[2] == PIPE_SWIZZLE_X || desc->swizzle[2] == PIPE_SWIZZLE_0));
4969 fix_fetch.u.reverse = 1;
4970 }
4971
4972 /* Force the workaround for unaligned access here already if the
4973 * offset relative to the vertex buffer base is unaligned.
4974 *
4975 * There is a theoretical case in which this is too conservative:
4976 * if the vertex buffer's offset is also unaligned in just the
4977 * right way, we end up with an aligned address after all.
4978 * However, this case should be extremely rare in practice (it
4979 * won't happen in well-behaved applications), and taking it
4980 * into account would complicate the fast path (where everything
4981 * is nicely aligned).
4982 */
4983 bool check_alignment =
4984 log_hw_load_size >= 1 &&
4985 (sscreen->info.chip_class == GFX6 || sscreen->info.chip_class == GFX10);
4986 bool opencode = sscreen->options.vs_fetch_always_opencode;
4987
4988 if (check_alignment &&
4989 (elements[i].src_offset & ((1 << log_hw_load_size) - 1)) != 0)
4990 opencode = true;
4991
4992 if (always_fix || check_alignment || opencode)
4993 v->fix_fetch[i] = fix_fetch.bits;
4994
4995 if (opencode)
4996 v->fix_fetch_opencode |= 1 << i;
4997 if (opencode || always_fix)
4998 v->fix_fetch_always |= 1 << i;
4999
5000 if (check_alignment && !opencode) {
5001 assert(log_hw_load_size == 1 || log_hw_load_size == 2);
5002
5003 v->fix_fetch_unaligned |= 1 << i;
5004 v->hw_load_is_dword |= (log_hw_load_size - 1) << i;
5005 v->vb_alignment_check_mask |= 1 << vbo_index;
5006 }
5007
5008 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
5009 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
5010 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
5011 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
5012
5013 if (sscreen->info.chip_class >= GFX10) {
5014 const struct gfx10_format *fmt =
5015 &gfx10_format_table[elements[i].src_format];
5016 assert(fmt->img_format != 0 && fmt->img_format < 128);
5017 v->rsrc_word3[i] |= S_008F0C_FORMAT(fmt->img_format) |
5018 S_008F0C_RESOURCE_LEVEL(1);
5019 } else {
5020 unsigned data_format, num_format;
5021 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
5022 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
5023 v->rsrc_word3[i] |= S_008F0C_NUM_FORMAT(num_format) |
5024 S_008F0C_DATA_FORMAT(data_format);
5025 }
5026 }
5027
5028 if (v->instance_divisor_is_fetched) {
5029 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
5030
5031 v->instance_divisor_factor_buffer =
5032 (struct si_resource*)
5033 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
5034 num_divisors * sizeof(divisor_factors[0]));
5035 if (!v->instance_divisor_factor_buffer) {
5036 FREE(v);
5037 return NULL;
5038 }
5039 void *map = sscreen->ws->buffer_map(v->instance_divisor_factor_buffer->buf,
5040 NULL, PIPE_TRANSFER_WRITE);
5041 memcpy(map , divisor_factors, num_divisors * sizeof(divisor_factors[0]));
5042 }
5043 return v;
5044 }
5045
5046 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
5047 {
5048 struct si_context *sctx = (struct si_context *)ctx;
5049 struct si_vertex_elements *old = sctx->vertex_elements;
5050 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
5051
5052 sctx->vertex_elements = v;
5053 sctx->vertex_buffers_dirty = true;
5054
5055 if (v &&
5056 (!old ||
5057 old->count != v->count ||
5058 old->uses_instance_divisors != v->uses_instance_divisors ||
5059 /* we don't check which divisors changed */
5060 v->uses_instance_divisors ||
5061 (old->vb_alignment_check_mask ^ v->vb_alignment_check_mask) & sctx->vertex_buffer_unaligned ||
5062 ((v->vb_alignment_check_mask & sctx->vertex_buffer_unaligned) &&
5063 memcmp(old->vertex_buffer_index, v->vertex_buffer_index,
5064 sizeof(v->vertex_buffer_index[0]) * v->count)) ||
5065 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
5066 * functions of fix_fetch and the src_offset alignment.
5067 * If they change and fix_fetch doesn't, it must be due to different
5068 * src_offset alignment, which is reflected in fix_fetch_opencode. */
5069 old->fix_fetch_opencode != v->fix_fetch_opencode ||
5070 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
5071 sctx->do_update_shaders = true;
5072
5073 if (v && v->instance_divisor_is_fetched) {
5074 struct pipe_constant_buffer cb;
5075
5076 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
5077 cb.user_buffer = NULL;
5078 cb.buffer_offset = 0;
5079 cb.buffer_size = 0xffffffff;
5080 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
5081 }
5082 }
5083
5084 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
5085 {
5086 struct si_context *sctx = (struct si_context *)ctx;
5087 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
5088
5089 if (sctx->vertex_elements == state)
5090 sctx->vertex_elements = NULL;
5091 si_resource_reference(&v->instance_divisor_factor_buffer, NULL);
5092 FREE(state);
5093 }
5094
5095 static void si_set_vertex_buffers(struct pipe_context *ctx,
5096 unsigned start_slot, unsigned count,
5097 const struct pipe_vertex_buffer *buffers)
5098 {
5099 struct si_context *sctx = (struct si_context *)ctx;
5100 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
5101 uint32_t orig_unaligned = sctx->vertex_buffer_unaligned;
5102 uint32_t unaligned = orig_unaligned;
5103 int i;
5104
5105 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
5106
5107 if (buffers) {
5108 for (i = 0; i < count; i++) {
5109 const struct pipe_vertex_buffer *src = buffers + i;
5110 struct pipe_vertex_buffer *dsti = dst + i;
5111 struct pipe_resource *buf = src->buffer.resource;
5112
5113 pipe_resource_reference(&dsti->buffer.resource, buf);
5114 dsti->buffer_offset = src->buffer_offset;
5115 dsti->stride = src->stride;
5116 if (dsti->buffer_offset & 3 || dsti->stride & 3)
5117 unaligned |= 1 << (start_slot + i);
5118 else
5119 unaligned &= ~(1 << (start_slot + i));
5120
5121 si_context_add_resource_size(sctx, buf);
5122 if (buf)
5123 si_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
5124 }
5125 } else {
5126 for (i = 0; i < count; i++) {
5127 pipe_resource_reference(&dst[i].buffer.resource, NULL);
5128 }
5129 unaligned &= ~u_bit_consecutive(start_slot, count);
5130 }
5131 sctx->vertex_buffers_dirty = true;
5132 sctx->vertex_buffer_unaligned = unaligned;
5133
5134 /* Check whether alignment may have changed in a way that requires
5135 * shader changes. This check is conservative: a vertex buffer can only
5136 * trigger a shader change if the misalignment amount changes (e.g.
5137 * from byte-aligned to short-aligned), but we only keep track of
5138 * whether buffers are at least dword-aligned, since that should always
5139 * be the case in well-behaved applications anyway.
5140 */
5141 if (sctx->vertex_elements &&
5142 (sctx->vertex_elements->vb_alignment_check_mask &
5143 (unaligned | orig_unaligned) & u_bit_consecutive(start_slot, count)))
5144 sctx->do_update_shaders = true;
5145 }
5146
5147 /*
5148 * Misc
5149 */
5150
5151 static void si_set_tess_state(struct pipe_context *ctx,
5152 const float default_outer_level[4],
5153 const float default_inner_level[2])
5154 {
5155 struct si_context *sctx = (struct si_context *)ctx;
5156 struct pipe_constant_buffer cb;
5157 float array[8];
5158
5159 memcpy(array, default_outer_level, sizeof(float) * 4);
5160 memcpy(array+4, default_inner_level, sizeof(float) * 2);
5161
5162 cb.buffer = NULL;
5163 cb.user_buffer = NULL;
5164 cb.buffer_size = sizeof(array);
5165
5166 si_upload_const_buffer(sctx, (struct si_resource**)&cb.buffer,
5167 (void*)array, sizeof(array),
5168 &cb.buffer_offset);
5169
5170 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
5171 pipe_resource_reference(&cb.buffer, NULL);
5172 }
5173
5174 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
5175 {
5176 struct si_context *sctx = (struct si_context *)ctx;
5177
5178 si_update_fb_dirtiness_after_rendering(sctx);
5179
5180 /* Multisample surfaces are flushed in si_decompress_textures. */
5181 if (sctx->framebuffer.uncompressed_cb_mask) {
5182 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
5183 sctx->framebuffer.CB_has_shader_readable_metadata,
5184 sctx->framebuffer.all_DCC_pipe_aligned);
5185 }
5186 }
5187
5188 /* This only ensures coherency for shader image/buffer stores. */
5189 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
5190 {
5191 struct si_context *sctx = (struct si_context *)ctx;
5192
5193 if (!(flags & ~PIPE_BARRIER_UPDATE))
5194 return;
5195
5196 /* Subsequent commands must wait for all shader invocations to
5197 * complete. */
5198 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
5199 SI_CONTEXT_CS_PARTIAL_FLUSH;
5200
5201 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
5202 sctx->flags |= SI_CONTEXT_INV_SCACHE |
5203 SI_CONTEXT_INV_VCACHE;
5204
5205 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
5206 PIPE_BARRIER_SHADER_BUFFER |
5207 PIPE_BARRIER_TEXTURE |
5208 PIPE_BARRIER_IMAGE |
5209 PIPE_BARRIER_STREAMOUT_BUFFER |
5210 PIPE_BARRIER_GLOBAL_BUFFER)) {
5211 /* As far as I can tell, L1 contents are written back to L2
5212 * automatically at end of shader, but the contents of other
5213 * L1 caches might still be stale. */
5214 sctx->flags |= SI_CONTEXT_INV_VCACHE;
5215 }
5216
5217 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
5218 /* Indices are read through TC L2 since GFX8.
5219 * L1 isn't used.
5220 */
5221 if (sctx->screen->info.chip_class <= GFX7)
5222 sctx->flags |= SI_CONTEXT_WB_L2;
5223 }
5224
5225 /* MSAA color, any depth and any stencil are flushed in
5226 * si_decompress_textures when needed.
5227 */
5228 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
5229 sctx->framebuffer.uncompressed_cb_mask) {
5230 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
5231
5232 if (sctx->chip_class <= GFX8)
5233 sctx->flags |= SI_CONTEXT_WB_L2;
5234 }
5235
5236 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
5237 if (sctx->screen->info.chip_class <= GFX8 &&
5238 flags & PIPE_BARRIER_INDIRECT_BUFFER)
5239 sctx->flags |= SI_CONTEXT_WB_L2;
5240 }
5241
5242 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
5243 {
5244 struct pipe_blend_state blend;
5245
5246 memset(&blend, 0, sizeof(blend));
5247 blend.independent_blend_enable = true;
5248 blend.rt[0].colormask = 0xf;
5249 return si_create_blend_state_mode(&sctx->b, &blend, mode);
5250 }
5251
5252 static void si_init_config(struct si_context *sctx);
5253
5254 void si_init_state_compute_functions(struct si_context *sctx)
5255 {
5256 sctx->b.create_sampler_state = si_create_sampler_state;
5257 sctx->b.delete_sampler_state = si_delete_sampler_state;
5258 sctx->b.create_sampler_view = si_create_sampler_view;
5259 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
5260 sctx->b.memory_barrier = si_memory_barrier;
5261 }
5262
5263 void si_init_state_functions(struct si_context *sctx)
5264 {
5265 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
5266 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
5267 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
5268 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
5269 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
5270 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
5271 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
5272 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
5273 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
5274 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
5275 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
5276
5277 sctx->b.create_blend_state = si_create_blend_state;
5278 sctx->b.bind_blend_state = si_bind_blend_state;
5279 sctx->b.delete_blend_state = si_delete_blend_state;
5280 sctx->b.set_blend_color = si_set_blend_color;
5281
5282 sctx->b.create_rasterizer_state = si_create_rs_state;
5283 sctx->b.bind_rasterizer_state = si_bind_rs_state;
5284 sctx->b.delete_rasterizer_state = si_delete_rs_state;
5285
5286 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
5287 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
5288 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
5289
5290 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
5291 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
5292 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
5293 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
5294 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
5295
5296 sctx->b.set_clip_state = si_set_clip_state;
5297 sctx->b.set_stencil_ref = si_set_stencil_ref;
5298
5299 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
5300
5301 sctx->b.set_sample_mask = si_set_sample_mask;
5302
5303 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
5304 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
5305 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
5306 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
5307
5308 sctx->b.texture_barrier = si_texture_barrier;
5309 sctx->b.set_min_samples = si_set_min_samples;
5310 sctx->b.set_tess_state = si_set_tess_state;
5311
5312 sctx->b.set_active_query_state = si_set_active_query_state;
5313
5314 si_init_config(sctx);
5315 }
5316
5317 void si_init_screen_state_functions(struct si_screen *sscreen)
5318 {
5319 sscreen->b.is_format_supported = si_is_format_supported;
5320
5321 if (sscreen->info.chip_class >= GFX10) {
5322 sscreen->make_texture_descriptor = gfx10_make_texture_descriptor;
5323 } else {
5324 sscreen->make_texture_descriptor = si_make_texture_descriptor;
5325 }
5326 }
5327
5328 static void si_set_grbm_gfx_index(struct si_context *sctx,
5329 struct si_pm4_state *pm4, unsigned value)
5330 {
5331 unsigned reg = sctx->chip_class >= GFX7 ? R_030800_GRBM_GFX_INDEX :
5332 R_00802C_GRBM_GFX_INDEX;
5333 si_pm4_set_reg(pm4, reg, value);
5334 }
5335
5336 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
5337 struct si_pm4_state *pm4, unsigned se)
5338 {
5339 assert(se == ~0 || se < sctx->screen->info.max_se);
5340 si_set_grbm_gfx_index(sctx, pm4,
5341 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
5342 S_030800_SE_INDEX(se)) |
5343 S_030800_SH_BROADCAST_WRITES(1) |
5344 S_030800_INSTANCE_BROADCAST_WRITES(1));
5345 }
5346
5347 static void
5348 si_write_harvested_raster_configs(struct si_context *sctx,
5349 struct si_pm4_state *pm4,
5350 unsigned raster_config,
5351 unsigned raster_config_1)
5352 {
5353 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
5354 unsigned raster_config_se[4];
5355 unsigned se;
5356
5357 ac_get_harvested_configs(&sctx->screen->info,
5358 raster_config,
5359 &raster_config_1,
5360 raster_config_se);
5361
5362 for (se = 0; se < num_se; se++) {
5363 si_set_grbm_gfx_index_se(sctx, pm4, se);
5364 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
5365 }
5366 si_set_grbm_gfx_index(sctx, pm4, ~0);
5367
5368 if (sctx->chip_class >= GFX7) {
5369 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
5370 }
5371 }
5372
5373 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
5374 {
5375 struct si_screen *sscreen = sctx->screen;
5376 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
5377 unsigned rb_mask = sscreen->info.enabled_rb_mask;
5378 unsigned raster_config = sscreen->pa_sc_raster_config;
5379 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
5380
5381 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
5382 /* Always use the default config when all backends are enabled
5383 * (or when we failed to determine the enabled backends).
5384 */
5385 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
5386 raster_config);
5387 if (sctx->chip_class >= GFX7)
5388 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
5389 raster_config_1);
5390 } else {
5391 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
5392 }
5393 }
5394
5395 static void si_init_config(struct si_context *sctx)
5396 {
5397 struct si_screen *sscreen = sctx->screen;
5398 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
5399 bool has_clear_state = sscreen->has_clear_state;
5400 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
5401
5402 if (!pm4)
5403 return;
5404
5405 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
5406 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
5407 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5408 si_pm4_cmd_end(pm4, false);
5409
5410 if (has_clear_state) {
5411 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
5412 si_pm4_cmd_add(pm4, 0);
5413 si_pm4_cmd_end(pm4, false);
5414 }
5415
5416 if (sctx->chip_class <= GFX8)
5417 si_set_raster_config(sctx, pm4);
5418
5419 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
5420 if (!has_clear_state)
5421 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
5422
5423 /* FIXME calculate these values somehow ??? */
5424 if (sctx->chip_class <= GFX8) {
5425 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
5426 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
5427 }
5428
5429 if (!has_clear_state) {
5430 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
5431 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
5432 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
5433 }
5434
5435 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
5436 if (!has_clear_state)
5437 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
5438 if (sctx->chip_class < GFX7)
5439 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
5440 S_008A14_CLIP_VTX_REORDER_ENA(1));
5441
5442 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5443 * I don't know why. Deduced by trial and error.
5444 */
5445 if (sctx->chip_class <= GFX7) {
5446 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
5447 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
5448 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
5449 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
5450 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5451 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
5452 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
5453 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5454 }
5455
5456 if (!has_clear_state) {
5457 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
5458 S_028230_ER_TRI(0xA) |
5459 S_028230_ER_POINT(0xA) |
5460 S_028230_ER_RECT(0xA) |
5461 /* Required by DX10_DIAMOND_TEST_ENA: */
5462 S_028230_ER_LINE_LR(0x1A) |
5463 S_028230_ER_LINE_RL(0x26) |
5464 S_028230_ER_LINE_TB(0xA) |
5465 S_028230_ER_LINE_BT(0xA));
5466 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
5467 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
5468 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
5469 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
5470 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
5471 }
5472
5473 if (sctx->chip_class >= GFX10) {
5474 si_pm4_set_reg(pm4, R_030964_GE_MAX_VTX_INDX, ~0);
5475 si_pm4_set_reg(pm4, R_030924_GE_MIN_VTX_INDX, 0);
5476 si_pm4_set_reg(pm4, R_030928_GE_INDX_OFFSET, 0);
5477 } else if (sctx->chip_class == GFX9) {
5478 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
5479 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
5480 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
5481 } else {
5482 /* These registers, when written, also overwrite the CLEAR_STATE
5483 * context, so we can't rely on CLEAR_STATE setting them.
5484 * It would be an issue if there was another UMD changing them.
5485 */
5486 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
5487 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
5488 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
5489 }
5490
5491 if (sctx->chip_class >= GFX7) {
5492 if (sctx->chip_class >= GFX10) {
5493 /* Logical CUs 16 - 31 */
5494 si_pm4_set_reg(pm4, R_00B404_SPI_SHADER_PGM_RSRC4_HS,
5495 S_00B404_CU_EN(0xffff));
5496 si_pm4_set_reg(pm4, R_00B104_SPI_SHADER_PGM_RSRC4_VS,
5497 S_00B104_CU_EN(0xffff));
5498 si_pm4_set_reg(pm4, R_00B004_SPI_SHADER_PGM_RSRC4_PS,
5499 S_00B004_CU_EN(0xffff));
5500 }
5501
5502 if (sctx->chip_class >= GFX9) {
5503 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5504 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5505 } else {
5506 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
5507 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5508 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5509 S_00B41C_WAVE_LIMIT(0x3F));
5510 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5511 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5512
5513 /* If this is 0, Bonaire can hang even if GS isn't being used.
5514 * Other chips are unaffected. These are suboptimal values,
5515 * but we don't use on-chip GS.
5516 */
5517 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5518 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5519 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5520 }
5521
5522 /* Compute LATE_ALLOC_VS.LIMIT. */
5523 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
5524 unsigned late_alloc_limit; /* The limit is per SH. */
5525
5526 if (sctx->family == CHIP_KABINI) {
5527 late_alloc_limit = 0; /* Potential hang on Kabini. */
5528 } else if (num_cu_per_sh <= 4) {
5529 /* Too few available compute units per SH. Disallowing
5530 * VS to run on one CU could hurt us more than late VS
5531 * allocation would help.
5532 *
5533 * 2 is the highest safe number that allows us to keep
5534 * all CUs enabled.
5535 */
5536 late_alloc_limit = 2;
5537 } else {
5538 /* This is a good initial value, allowing 1 late_alloc
5539 * wave per SIMD on num_cu - 2.
5540 */
5541 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5542 }
5543
5544 unsigned cu_mask_vs = 0xffff;
5545 unsigned cu_mask_gs = 0xffff;
5546
5547 if (late_alloc_limit > 2) {
5548 if (sctx->chip_class >= GFX10) {
5549 /* CU2 & CU3 disabled because of the dual CU design */
5550 cu_mask_vs = 0xfff3;
5551 cu_mask_gs = 0xfff3; /* NGG only */
5552 } else {
5553 cu_mask_vs = 0xfffe; /* 1 CU disabled */
5554 }
5555 }
5556
5557 /* VS can't execute on one CU if the limit is > 2. */
5558 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5559 S_00B118_CU_EN(cu_mask_vs) |
5560 S_00B118_WAVE_LIMIT(0x3F));
5561 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5562 S_00B11C_LIMIT(late_alloc_limit));
5563
5564 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
5565 S_00B21C_CU_EN(cu_mask_gs) | S_00B21C_WAVE_LIMIT(0x3F));
5566
5567 if (sctx->chip_class >= GFX10) {
5568 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
5569 S_00B204_CU_EN(0xffff) |
5570 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_limit));
5571 }
5572
5573 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5574 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5575 }
5576
5577 if (sctx->chip_class >= GFX10) {
5578 /* Break up a pixel wave if it contains deallocs for more than
5579 * half the parameter cache.
5580 *
5581 * To avoid a deadlock where pixel waves aren't launched
5582 * because they're waiting for more pixels while the frontend
5583 * is stuck waiting for PC space, the maximum allowed value is
5584 * the size of the PC minus the largest possible allocation for
5585 * a single primitive shader subgroup.
5586 */
5587 si_pm4_set_reg(pm4, R_028C50_PA_SC_NGG_MODE_CNTL,
5588 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5589 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5590 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE,
5591 sscreen->info.pa_sc_tile_steering_override);
5592
5593 si_pm4_set_reg(pm4, R_02807C_DB_RMI_L2_CACHE_CONTROL,
5594 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5595 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5596 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5597 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR) |
5598 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD) |
5599 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD) |
5600 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD));
5601
5602 si_pm4_set_reg(pm4, R_028410_CB_RMI_GL2_CACHE_CONTROL,
5603 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5604 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5605 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5606 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR) |
5607 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
5608 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD) |
5609 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD) |
5610 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD));
5611 }
5612
5613 if (sctx->chip_class >= GFX8) {
5614 unsigned vgt_tess_distribution;
5615
5616 vgt_tess_distribution =
5617 S_028B50_ACCUM_ISOLINE(32) |
5618 S_028B50_ACCUM_TRI(11) |
5619 S_028B50_ACCUM_QUAD(11) |
5620 S_028B50_DONUT_SPLIT(16);
5621
5622 /* Testing with Unigine Heaven extreme tesselation yielded best results
5623 * with TRAP_SPLIT = 3.
5624 */
5625 if (sctx->family == CHIP_FIJI ||
5626 sctx->family >= CHIP_POLARIS10)
5627 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5628
5629 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5630 } else if (!has_clear_state) {
5631 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5632 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5633 }
5634
5635 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5636 if (sctx->chip_class >= GFX7) {
5637 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5638 S_028084_ADDRESS(border_color_va >> 40));
5639 }
5640 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5641 RADEON_PRIO_BORDER_COLORS);
5642
5643 if (sctx->chip_class >= GFX9) {
5644 unsigned num_se = sscreen->info.max_se;
5645 unsigned pc_lines = 0;
5646 unsigned max_alloc_count = 0;
5647
5648 switch (sctx->family) {
5649 case CHIP_VEGA10:
5650 case CHIP_VEGA12:
5651 case CHIP_VEGA20:
5652 pc_lines = 2048;
5653 break;
5654 case CHIP_RAVEN:
5655 case CHIP_RAVEN2:
5656 case CHIP_NAVI10:
5657 case CHIP_NAVI12:
5658 pc_lines = 1024;
5659 break;
5660 case CHIP_NAVI14:
5661 pc_lines = 512;
5662 break;
5663 default:
5664 assert(0);
5665 }
5666
5667 if (sctx->chip_class >= GFX10) {
5668 max_alloc_count = pc_lines / 3;
5669 } else {
5670 max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
5671 }
5672
5673 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5674 S_028C48_MAX_ALLOC_COUNT(max_alloc_count) |
5675 S_028C48_MAX_PRIM_PER_BATCH(1023));
5676 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5677 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5678 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5679 }
5680
5681 si_pm4_upload_indirect_buffer(sctx, pm4);
5682 sctx->init_config = pm4;
5683 }